Samsung S3C4510B Datasheet

S3C4510B PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

OVERVIEW

Samsung's S3C4510B 16/32-bit RISC microcontroller is a cost-effective, high-performance microcontroller
solution for Ethernet-based systems. An integrated Ethernet controller, the S3C4510B, is designed for use in
managed communication hubs and routers.

The S3C4510B is built around an outstanding CPU core: the 16/32-bit ARM7TDMI RISC processor designed by
Advanced RISC Machines, Ltd. The ARM7TDMI core is a low-power, general purpose microprocessor macro-cell
that was developed for use in application-specific and custom-specific integrated circuits. Its simple, elegant, and
fully static design is particularly suitable for cost-sensitive and power-sensitive applications.

The S3C4510B offers a configurable 8K-byte unified cache/SRAM and Ethernet controller which reduces total
system cost. Most of the on-chip function blocks have been designed using an HDL synthesizer and the
S3C4510B has been fully verified in Samsung's state-of-the-art ASIC test environment.

Important peripheral functions include two HDLC channels with buffer descriptor, two UART channels, 2-channel
GDMA, two 32-bit timers, and 18 programmable I/O ports. On-board logic includes an interrupt controller, DRAM/
SDRAM controller, and a controller for ROM/SRAM and flash memory. The System Manager includes an internal
32-bit system bus arbiter and an external memory controller.

The following integrated on-chip functions are described in detail in this user's manual:
— 8K-byte unified cache/SRAM

— I2C interface
— Ethernet controller
— HDLC
— GDMA
— UART
— Timers
— Programmable I/O ports
— Interrupt controller

1-1

PRODUCT OVERVIEW S3C4510B

FEATURES

Architecture

• Integrated system for embedded ethernet
applications

• Fully 16/32-bit RISC architecture

• Little/Big-Endian mode supported basically, the

internal architecture is big-endian.
So, the little-endian mode only support for
external memory.

• Efficient and powerful ARM7TDMI core

• Cost-effective JTAG-based debug solution

• Boundary scan

System Manager

• 8/16/32-bit external bus support for
ROM/SRAM, flash memory, DRAM, and
external I/O

• One external bus master with bus request/
acknowledge pins

• Support for EDO/normal or SDRAM

• Programmable access cycle (0-7 wait cycles)

• Four-word depth write buffer

• Cost-effective memory-to-peripheral DMA

interface

Unified Instruction/Data Cache

• Two-way, set-associative, unified 8K-byte cache

• Support for LRU (least recently used) protocol

• Cache is configurable as an internal SRAM

• Data alignment logic

• Endian translation

• 100/10-Mbit per second operation

• Full compliance with IEEE standard 802.3

• MII and 7-wire 10-Mbps interface

• Station management signaling

• On-chip CAM (up to 21 destination addresses)

• Full-duplex mode with PAUSE feature

• Long/short packet modes

• PAD generation

HDLCs

• HDLC protocol features:
— Flag detection and synchronization

— Zero insertion and deletion
— Idle detection and transmission
— FCS generation and detection (16-bit)
— Abort detection and transmission

• Address search mode (expandable to 4 bytes)

• Selectable CRC or No CRC mode

• Automatic CRC generator preset

• Digital PLL block for clock recovery

• Baud rate generator

• NRZ/NRZI/FM/Manchester data formats for

Tx/Rx

• Loop-back and auto-echo modes

I2C Serial Interface

• Master mode operation only

• Baud rate generator for serial clock generation

Ethernet Controller

• DMA engine with burst mode

• DMA Tx/Rx buffers (256 bytes Tx, 256 bytes

Rx)

• MAC Tx/Rx FIFO buffers (80 bytes Tx, 16 bytes
Rx)

1-2

• Tx/Rx FIFOs have 8-word (8 × 32-bit) depth

• Selectable 1-word or 4-word data transfer mode

• Data alignment logic

• Endian translation

• Programmable interrupts

• Modem interface

• Up to 10 Mbps operation

• HDLC frame length based on octets

• 2-channel DMA buffer descriptor for Tx/Rx on

each HDLC

S3C4510B PRODUCT OVERVIEW

DMA Controller

• 2-channel General DMA for memory-to­memory, memory-to-UART, UART-to-memory
data transfers without CPU intervention

• Initiated by a software or external DMA request

• Increments or decrements a source or

destination address in 8-bit, 16-bit or 32-bit data
transfers

• 4-data burst mode

UARTs

• Two UART (serial I/O) blocks with DMA-based
or interrupt-based operation

• Support for 5-bit, 6-bit, 7-bit, or 8-bit serial data
transmit and receive

• Programmable baud rates

• 1 or 2 stop bits

• Odd or even parity

• Break generation and detection

• Parity, overrun, and framing error detection

• ×16 clock mode

Programmable I/O

• 18 programmable I/O ports

• Pins individually configurable to input, output, or

I/O mode for dedicated signals

Interrupt Controller

• 21 interrupt sources, including 4 external
interrupt sources

• Normal or fast interrupt mode (IRQ, FIQ)

• Prioritized interrupt handling

PLL

• The external clock can be multiplied by on-chip
PLL to provide high frequency system clock

• The input frequency range is 10–40 MHz

• The output frequency is 5 times of input clock.

To get 50 MHz, input clock frequency should be
10 MHz.

Operating Voltage Range

• 3.3 V ± 5 %

• Infra-red (IR) Tx/Rx support (IrDA)

Timers

• Two programmable 32-bit timers

• Interval mode or toggle mode operation

Operating Temperature Range

• 0 °C to + 70 °C

Operating Frequency

• Up to 50 MHz

Package Type

• 208-Pin QFP

1-3

PRODUCT OVERVIEW S3C4510B

SCL

SDA

18 I/O Ports including
4: Ext INT req.
2: Timer out (0,1)
2: Ext DMA REQ.
2: Ext DMA ACK

Console

ARM7TDMI

32-bit RISE CPU

CPU Interface

8-Kbyte

Unified

Cache

4-Word

Write

Buffer

Bus Rounter

I2C

18 General I/O ports

Interruput Controller

UART 0,1

32-bit Timer 0,1

ICE-

Breaker

32-Bit
Sytem
Bus

Memory

Controller

with

Refresh

Control

System

Bus

Arbiter

2-Channel HDLCs

with DMAs

Ethernet Controller

2-channel BDMA

BDMA RAMs

Tx Buffer (256 bytes)

Rx Buffer (256 bytes)

CAM (128 bytes)

REQ/ACK

Ext Bus

6-bank

ROM

SRAM

FLASH

4-bank
DRAM

4-bank

External

I/O

Device

External

Bus

Master

Remote
port A,B

1-4

Xtal OSC

GDMA 0,1

PLL

Tx FIFO (80 bytes)

Rx FIFO (16 bytes)

TAP Controller for JTAG

Figure 1-1. S3C4510B Block Diagram

MAC

MII or
7-wire

S3C4510B PRODUCT OVERVIEW

VSS

VDD

UARXD1

uUADSR0

UATXD0

uUADTR0

UARXD0

SDA

SCL

P<17>/TOUT1

VSS

VDD

P<16>/TOUT0

P<15>/nXDACK<1>

P<14>/nXDACK<0>

P<13>/nXDREQ<1>

P<12>/nXDREQ<0>

P<11>/xINREQ<3>

P<10>/xINREQ<2>

P<9>/xINREQ<1>

VSS

VDD

P<8>/xINREG<0>

P<7>

P<6>

P<5>

P<4>

P<3>

P<2>

P<1>

VSS

VDD

P<0>

XDATA<31>

XDATA<30>

XDATA<29>

XDATA<28>

XDATA<27>

XDATA<26>

XDATA<25>

VSS

VDD

XDATA<24>

XDATA<23>

XDATA<22>

XDATA<21>

XDATA<20>

XDATA<19>

XDATA<18>

XDATA<17>

VSS

VDD

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158
VDD
VSS

nUADTR1

UATXD1

nUADSR1

nDTRA

RXDA

nRTSA

TXDA

nCTSA

VDD
VSS

nDCDA

RXCA

nSYNCA

TXCA

nDTRB

RTDB

nRTSB

TXDB

VDD
VSS

nCTSB

nDCDB

RXCB

nSYNCB

TXCB

CRS/CRS_ 10M

RX DV/LINK_10M

RXD<0>/RXD_10M

RX_CLK/RXCLK_10M

TXD<0>/TXD_10M

TXD<1>/LOOP_10M

TX_ERR/POCMP_10M

TX_CLK/TXCLK_10M

TX_EN/TXEN_10M

VDD
VSS

RXD<1>
RXD<2>
RXD<3>
RX ERR

COL/COL_10M

VDD
VSS

TXD<2>
TXD<3>

MDIO

LITTLE

MDC

VDD
VSS

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

5354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899

S3C4510B

208-QFP

100

101

102

103

157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109

108
107
106
105

104

VDD
VSS
XDATA<16>
XDATA<15>
XDATA<14>
XDATA<13>
XDATA<12>
XDATA<11>
XDATA<10>
XDATA<9>
XDATA<8>
XDATA<7>
XDATA<6>
VSS
VDD
XDATA<5>
XDATA<4>
XDATA<3>
XDATA<2>
XDATA<1>
XDATA<0>
XDATA<21>
XDATA<20>
XDATA<19>
XDATA<18>
VSS
VDD
ADDR<17>
ADDR<16>
ADDR<15>
ADDR<14>
ADDR<13>
ADDR<12>
ADDR<11>
ADDR<10>/AP
ADDR<9>
ADDR<8>
VSS
VDD
ADDR<7>
ADDR<6>
ADDR<5>
ADDR<4>
ADDR<3>
ADDR<2>
ADDR<1>
ADDR<0>
ExtMACK
ExtMREQ
nWBE<3>/DQM<3>
VSS
VDD

VDDa

VSSa

FILTER

TDI

TD0

VDD

VSS

TCK

TMS

nTRST

TMODE

VDD

UCLK

VSS

nECS<0>

nECS<1>

nECS<2>

nECS<3>

nOE

nEWAIT

CLKOEN

nRCS<0>

BOSIZE<0>

BOSIZE<1>

VSS

VSS

VDD

XCLK

SDCLK/MCLKO

nRESET

CLKSEL

nRCS<1>

nRCS<2>

nRCS<3>

nRCS<4>

Figure 1-2. S3C4510B Pin Assignment Diagram

VSS

VDD

nRCS<5>

nSDCS<0>/nRAS<0>

nSDCS<1>/nRAS<1>

nSDCS<2>/nRAS<2>

nSDCS<3>/nRAS<3>

nDWE

nCAS<3>

CKE/nCAS<2>

DQM0/nWBE<0>

nSDRAS/nCAS<0>

nSDCAS/nCAS<2>

DQM1/nWBE<1>

VSS

VDD

DQM2/nWBE<2>

1-5

PRODUCT OVERVIEW S3C4510B

SIGNAL DESCRIPTIONS

Table 1-1. S3C4510B Signal Descriptions

Signal Pin No. Type Description

XCLK 80 I S3C4510B system clock source. If CLKSEL is Low, PLL output

clock is used as the S3C4510B internal system clock. If
CLKSEL is High, XCLK is used as the S3C4510B internal
system clock.

MCLKO/SDCLK

(note)

CLKSEL 83 I Clock select. When CLKSEL is '0'(low level), PLL output clock

nRESET 82 I Not reset. nRESET is the global reset input for the S3C4510B.

CLKOEN
TMODE 63 I Test Mode. The TMODE bit settings are interpreted as follows:

FILTER 55 AI If the PLL is used, 820pF ceramic capacitor should be

TCK 58 I JTAG Test Clock. The JTAG test clock shifts state information

TMS 59 I JTAG Test Mode Select. This pin controls JTAG test operations

TDI 60 I JTAG Test Data In. The TDI level is used to serially shift test

TDO 61 O JTAG Test Data Out. The TDO level is used to serially shift test

nTRST 62 I JTAG Not Reset. Asynchronous reset of the JTAG logic.

77 O System clock out. MCLKO is monitored with some delay as the

same phase of internal system clock, MCLK(SCLK).
SDCLK is system clock for SDRAM.

can be used as the master clock. When CLKSEL is '1'(high
level), the XCLK is used as the master clock.

To allow a system reset, and for internal digital filtering,
nRESET must be held to low level for at least 64 master clock
cycles. Refer to "Figure 3. S3C4510B reset timing diagram" for
more details about reset timing.

76 I Clock out enable/disable. (see the pin description for MCLKO.)

'0' = normal operating mode, '1' = chip test mode.
This TMODE pin also can be used to change MF of PLL.
To get 5 times internal system clock from external clock, '0'(low
level) should be assigned to TMODE. If '1'(high level), MF will
be changed to 6.6

connected between the pin and analog ground(pin # 54).

and test data into, and out of, the S3C4510B during JTAG test
operations. This pin is internally connected pull-down.

in the S3C4510B. This pin is internally connected pull-up.

data and instructions into the S3C4510B during JTAG test
operations. This pin is internally connected pull-up.

data and instructions out of the S3C4510B during JTAG test
operations.

This pin is internally connected pull-up.

1-6

S3C4510B PRODUCT OVERVIEW

Table 1-1. S3C4510B Signal Descriptions (Continued)

Signal Pin No. Type Description

ADDR[21:0]/
ADDR[10]/AP

(note)

117–110,
129–120,

135–132

O Address Bus. The 22-bit address bus, ADDR[21:0], covers the full

4M word address range of each ROM/SRAM, flash memory,
DRAM, and the external I/O banks.
The 23-bit internal address bus used to generate DRAM address.
The number of column address bits in DRAM bank can be
programmed 8bits to 11bits use by DRAMCON registers.
ADDR[10]/AP is the auto precharge control pin. The auto
precharge command is issued at the same time as burst read or
burst write by asserting high on ADDR[10]/AP.

XDATA[31:0] 141–136,

154–144,

I/O External (bi-directional, 32-bit) Data Bus. The S3C4510B data

bus supports external 8-bit, 16-bit, and 32-bit bus sizes.

166–159,

175–169

nRAS[3:0]/
nSDCS[3:0]

(note)

94, 91, 90,

89

O Not Row Address Strobe for DRAM. The S3C4510B supports up

to four DRAM banks. One nRAS output is provided for each
bank. nSDCS[3:0] are chip select pins for SDRAM.

nCAS[3:0]
nCAS[0]/nSDRAS
nCAS[1]/nSDCAS

nCAS[2]/CKE

(note)

98, 97, 96,

95

O Not column address strobe for DRAM. The four nCAS outputs

indicate the byte selections whenenver a DRAM bank is
accessed. nSDRAS is row address strobe signal for SDRAM.
Latches row addresses on the positive going edge of the SDCLK
with nSDRAS low. Enable row access and precharge. nSDCAS is
column address strobe for SDRAM. Latches column addresses
on the positive going edge of the SDCLK with nSDCAS low.
Enables column access. CKE is clock enable signal for SDRAM.
Masks SDRAM system clock, SDCLK to freeze operation from
the next clock cycle. SDCLK should be enabled at least one cycle
prior to new command. Disable input buffers of SDRAM for
power down in standby.

nDWE 99 O DRAM Not Write Enable. This pin is provided for DRAM bank

write operations. (nWBE[3:0] is used for write operations to the
ROM/ SRAM/flash memory banks.) .

nECS[3:0] 70, 69, 68,

67

O Not External I/O Chip Select. Four external I/O banks are

provided for external memory-mapped I/O operations. Each I/O
bank stores up to 16 Kbytes. nECS signals indicate which of the
four external I/O banks is selected.

nEWAIT 71 I Not External Wait. This signal is activated when an external I/O

device or ROM/SRAM/flash bank 5 needs more access cycles
than those defined in the corresponding control register.
When de-assert the nEWAIT, you must synchronize the nEWAIT
with MCLKO rising edge. If not, memory state machine can get
into the Wrong State.

1-7

PRODUCT OVERVIEW S3C4510B

Table 1-1. S3C4510B Signal Descriptions (Continued)

Signal Pin No. Type Description

nRCS[5:0] 88-84, 75 O Not ROM/SRAM/Flash Chip Select. The S3C4510B can access

up to six external ROM/SRAM/Flash banks. By controlling the
nRCS signals, you can map CPU addresses into the physical
memory banks.

B0SIZE[1:0] 74, 73 I Bank 0 Data Bus Access Size. Bank 0 is used for the boot

program. You use these pins to set the size of the bank 0 data
bus as follows: '01' = one byte, '10' = half-word, '11' = one word,
and '00' = reserved.

nOE 72 O Not Output Enable. Whenever a memory access occurs, the nOE

output controls the output enable port of the specific memory
device.

nWBE[3:0]/
DQM[3:0]

(note)

107,

102–100

O Not Write Byte Enable. Whenever a memory write access

occurs, the nWBE output controls the write enable port of the
specific memory device (except for DRAM). For DRAM banks,
CAS[3:0] and nDWE are used for the write operation.
DQM is data input/output mask signal for SDRAM.

ExtMREQ 108 I External Bus Master Request. An external bus master uses this

pin to request the external bus. When it activates the ExtMREQ
signal, the S3C4510B drives the state of external bus pins to high
impedance. This lets the external bus master take control of the
external bus. When it has the control, the external bus master
assumes responsibility for DRAM refresh operations. The
ExtMREQ signal is deactivated when the external bus master
releases the external bus. When this occurs, ExtMACK goes Low

level and the S3C4510B assumes the control of the bus.
ExtMACK 109 O External Bus Acknowledge. (See the ExtMREQ pin description.)
MDC 50 O Management Data Clock. The signal level at the MDC pin is used

as a timing reference for data transfers that are controlled by the

MDIO signal.
MDIO 48 I/O Management Data I/O. When a read command is being

executed, data that is clocked out of the PHY is presented on this

pin. When a write command is being executed, data that is

clocked out of the controller is presented on this pin for the

Physical Layer Entity, PHY.
LITTLE 49 I Little endian mode select pin. If LITTLE is High, S3C4510B

operate in little endian mode. If Low, then in Big endian mode.

Default value is low because this pin is pull-downed internally.
COL/COL_10M 38 I Collision Detected/Collision Detected for 10M. COL is asserted

asynchronously with minimum delay from the start of a collision

on the medium in MII mode. COL_10M is asserted when a 10-

Mbit/s PHY detects a collision.
TX_CLK/

TXCLK_10M

46 I Transmit Clock/Transmit Clock for 10M. The controller drives

TXD[3:0] and TX_EN from the rising edge of TX_CLK. In MII

mode, the PHY samples TXD[3:0] and TX_EN on the rising edge

of TX_CLK. For data transfers, TXCLK_10M is provided by the

10-Mbit/s PHY.

1-8

S3C4510B PRODUCT OVERVIEW

Table 1-1. S3C4510B Signal Descriptions (Continued)

Signal Pin No. Type Description

TXD[3:0]
LOOP_10M
TXD_10M

44, 43, 40,

39

O Transmit Data/Transmit Data for 10 M/Loop-back for 10M.

Transmit data is aligned on nibble boundaries. TXD[0]
corresponds to the first bit to be transmitted on the physical
medium, which is the LSB of the first byte and the fifth bit of that
byte during the next clock. TXD_10M is shared with TXD[0] and
is a data line for transmitting to the 10-Mbit/s PHY. LOOP_10M is
shared with TXD[1] and is driven by the loop-back bit in the
control register.

TX_EN/
TXEN_10M

47 O Transmit Enable/Transmit Enable for 10M. TX_EN provides

precise framing for the data carried on TXD[3:0]. This pin is
active during the clock periods in which TXD[3:0] contains valid
data to be transmitted from the preamble stage through CRC.
When the controller is ready to transfer data, it asserts
TXEN_10M.

TX_ERR/
PCOMP_10M

45 O Transmit Error/Packet Compression Enable for 10M. TX_ERR is

driven synchronously to TX_CLK and sampled continuously by
the Physical Layer Entity, PHY. If asserted for one or more
TX_CLK periods, TX_ERR causes the PHY to emit one or more
symbols which are not part of the valid data, or delimiter set
located somewhere in the frame that is being transmitted.
PCOMP_10M is asserted immediately after the packet's DA field
is received. PCOMP_10M is used with the Management Bus of
the DP83950 Repeater Interface Controller (from National
Semiconductor). The MAC can be programmed to assert
PCOMP if there is a CAM match, or if there is not a match. The
RIC (Repeater Interface Controller) uses this signal to compress
(shorten) the packet received for management purposes and to
reduce memory usage. (See the DP83950 Data Sheet, published
by National Semiconductor, for details on the RIC Management
Bus.). This pin is controlled by a special register, with which you
can define the polarity and assertion method (CAM match active
or not match active) of the PCOMP signal.

CRS/CRS_10M 28 I Carrier Sense/Carrier Sense for 10M. CRS is asserted

asynchronously with minimum delay from the detection of a non­idle medium in MII mode. CRS_10M is asserted when a 10­Mbit/s PHY has data to transfer. A 10-Mbit/s transmission also
uses this signal.

RX_CLK/
RXCLK_10M

37 I Receive Clock/Receive Clock for 10M. RX_CLK is a continuous

clock signal. Its frequency is 25 MHz for 100-Mbit/s operation,
and 2.5 MHz for 10-Mbit/s. RXD[3:0], RX_DV, and RX_ERR are
driven by the PHY off the falling edge of RX_CLK, and sampled
on the rising edge of RX_CLK. To receive data, the TXCLK_10 M
clock comes from the 10-Mbit/s PHY.

RXD[3:0]/
RXD_10M

35, 34, 33,

30

I Receive Data/Receive Data for 10M. RXD is aligned on nibble

boundaries. RXD[0] corresponds to the first bit received on the
physical medium, which is the LSB of the byte in one clock
period and the fifth bit of that byte in the next clock. RXD_10M is
shared with RXD[0] and it is a line for receiving data from the 10­Mbit/s PHY.

1-9

PRODUCT OVERVIEW S3C4510B

Table 1-1. S3C4510B Signal Descriptions (Continued)

Signal Pin No. Type Description

RX_DV/LINK_10M 29 I Receive Data Valid/Link Status for 10M. PHY asserts RX_DV

synchronously, holding it active during the clock periods in which

RXD[3:0] contains valid data received. PHY asserts RX_DV no

later than the clock period when it places the first nibble of the

start frame delimiter (SFD) on RXD[3:0]. If PHY asserts RX_DV

prior to the first nibble of the SFD, then RXD[3:0] carries valid

preamble symbols. LINK_10M is shared with RX_DV and used to

convey the link status of the 10-Mbit/s endec. The value is stored

in a status register.
RX_ERR 36 I Receive Error. PHY asserts RX_ERR synchronously whenever it

detects a physical medium error (e.g., a coding violation). PHY

asserts RX_ERR only when it asserts RX_DV.
TXDA 9 O HDLC Ch-A Transmit Data. The serial output data from the

transmitter is coded in NRZ/NRZI/FM/Manchester data format.
RXDA 7 I HDLC Ch-A Receive Data. The serial input data received by the

device should be coded in NRZ/NRZI/FM/Manchester data

format. The data rate should not exceed the rate of the

S3C4510B internal master clock.
nDTRA 6 O HDLC Ch-A Data Terminal Ready. nDTRA output indicates that

the data terminal device is ready for transmission and reception.
nRTSA 8 O HDLC Ch-A Request To Send. The nRTSA output goes low when

there is exist data to be sent in TxFIFO. The data to be sent is

transmitted when the nCTS is active(Low) state.
nCTSA 10 I HDLC Ch-A Clear To Send. The S3C4510B stores each

transition of nCTS to ensure that its occurrence would be

acknowledged by the system.
nDCDA 13 I HDLC Ch-A Data Carrier Detected. A High level on this pin resets

and inhibits the receiver register. Data from a previous frame that

may remain in the RxFIFO is retained. The S3C4510B stores

each transition of nDCD.
nSYNCA 15 O HDLC Ch-A Sync is detected. This indicates the reception of a

flag. The nSYNC output goes low for one bit time beginning at

the last bit of the flag.
RXCA 14 I HDLC Ch-A Receiver Clock. When this clock input is used as the

receiver clock, the receiver samples the data on the positive

edge of RXCA clock. This clock can be the source clock of the

receiver, the baud rate generator, or the DPLL.
TXCA 16 I/O HDLC Ch-A Transmitter Clock. When this clock input is used as

the transmitter clock, the transmitter shifts data on the negative

transition of the TXCA clock . If you do not use TXCA as the

transmitter clock, you can use it as an output pin for monitoring

internal clocks such as the transmitter clock, receiver clock, and

baud rate generator output clocks.
TXDB 20 O
RXDB 18 I

HDLC Ch-B transmit data. See the TXDA pin description.

HDLC Ch-B receive data. See the RXDA pin description.

1-10

S3C4510B PRODUCT OVERVIEW

Table 1-1. S3C4510B Signal Descriptions (Continued)

Signal Pin No. Type Description

nDTRB 17 O HDLC Ch-B data terminal ready. See the nDTRA pin description.
nRTSB 19 O HDLC Ch-B request to send. See the nRTSA pin description.
nCTSB 23 I HDLC Ch-B clear to send. See the nCTSA pin description.
nDCDB 24 I HDLC Ch-B data carrier detected. See the nDCDA pin

description.
nSYNCB 26 O HDLC Ch-B sync is detected. See the nSYNCA pin description.
RXCB 25 I HDLC Ch-B receiver clock. See the RXCA pin description.
TXCB 27 I/O HDLC Ch-B transmitter clock. See the TXCA pin description.
UCLK 64 I The external UART clock input. MCLK or PLL generated clock

can be used as the UART clock. You can use UCLK, with an

appropriate divided by factor, if a very precious baud rate clock is

required.
UARXD0 202 I UART0 receive data. RXD0 is the UART 0 input signal for

receiving serial data.
UATXD0 204 O UART0 transmit data. TXD0 is the UART 0 output signal for

transmitting serial data.
nUADTR0 203 I Not UART0 data terminal ready. This input signals the S3C4510B

that the peripheral (or host) is ready to transmit or receive serial

data.
nUADSR0 205 O Not UART0 data set ready. This output signals the host

(or peripheral) that UART 0 is ready to transmit or receive serial

data.
UARXD1 206 I UART1 receive data. See the RXD0 pin description.
UATXD1 4 O UART1 transmit data. See the TXD0 pin description.
nUADTR1 3 I Not UART1 data terminal ready. See the DTR0 pin description.
nUADSR1 5 O Not UART1 data set ready. See the DSR0 pin description.
P[7:0] 185–179,

I/O General I/O ports. See the I/O ports, chapter 12.

176

XINTREQ[3:0]
P[11:8]

nXDREQ[1:0]/
P[13:12]

nXDACK[1:0]
P[15:14]

191–189,

186

I/O External interrupt request lines or general I/O ports.

See the I/O ports, chapter 12.

193, 192 I/O Not external DMA requests for GDMA or general I/O ports.

See the I/O ports, chapter 12.

195, 194 I/O Not external DMA acknowledge from GDMA or general I/O ports.

See the I/O ports, chapter 12.
TOUT0/P[16] 196 I/O Timer 0 out or general I/O port. See the I/O ports, chapter 12.
TOUT1/P[17] 199 I/O Timer 1 out or general I/O port. See the I/O ports, chapter 12.
SCL 200 I/O I2C serial clock.
SDA 201 I/O I2C serial data.

1-11

PRODUCT OVERVIEW S3C4510B

Table 1-1. S3C4510B Signal Descriptions (Continued)

Signal Pin No. Type Description

VDDP 1, 21, 41, 56, 78,

Power I/O pad power

92, 105, 118, 130,

155, 167, 177, 197

VDDI 11, 31, 51, 65,

Power Internal core power

103, 142, 157,

187, 207

VSSP 2, 22, 42, 57, 79,

GND I/O pad ground

81, 93, 106, 119,

131, 156, 168,

178, 198

VSSI 12, 32, 52, 66,

GND Internal core ground

104, 143, 158,

188, 208
VDDA 53 Power Analog power for PLL
VSSA/VBBA 54 GND Analog/bulk ground for PLL

NOTE: SDRAM or EDO/normal DRAM interface signal pins are shared functions. It's functions will be configured by
SYSCFG[31].

1-12

S3C4510B PRODUCT OVERVIEW

Table 1-2. S3C4510B Pin List and PAD Type

Group Pin Name Pin Counts I/O Type Pad Type Description

System XCLK 1 I ptic S3C4510B system source clock.
Configuration MCLKO 1 O pob4 System clock out.
(8) CLKSEL 1 I ptic Clock select.

nRESET 1 I ptis Not reset
CLKOEN 1 I ptic Clock out enable/disable.
TMODE 1 I ptic Test mode.
LITTLE 1 I pticd Little endian mode select pin

FILTER 1 I pia_bb PLL filter pin
TAP Control TCK 1 I ptic JTAG test clock.
(5) TMS 1 I pticu JTAG test mode select.

TDI 1 I pticu JTAG test data in.

TDO 1 O ptot2 JTAG test data out.

nTRST 1 I pticu JTAG not reset.
Memory ADDR[21:0] 22 O ptot6 Address bus.
Interface XDATA[31:0] 32 I/O ptbsut6 External, bi-directional, 32-bit data bus.
(83) nRAS[3:0] 4 O ptot4 Not row address strobe for DRAM.

nCAS[3:0] 4 O ptot4 Not column address strobe for DRAM.

nDWE 1 O ptot4 Not write enable

nECS[3:0] 4 O ptot4 Not external I/O chip select.

nEWAIT 1 I ptic Not external wait signal.

nRCS[5:0] 6 O ptot4 Not ROM/SRAM/flash chip select.

B0SIZE[1:0] 2 I ptic Bank 0 data bus access size.

nOE 1 O ptot4 Not output enable.

nWBE[3:0] 4 O ptot4 Not write byte enable.

ExtMREQ 1 I ptic External master bus request.

ExtMACK 1 O pob1 External bus acknowledge.

1-13

PRODUCT OVERVIEW S3C4510B

Table 1-2. S3C4510B Pin List and PAD Type (Continued)

Group Pin Name Pin Counts I/O Type Pad Type Description

Ethernet MDC 1 O pob4 Management data clock.
Controller MDIO 1 I/O ptbcut4 Management data I/O.
(18) COL/

COL_10M
TX_CLK/

1 I ptis Collision detected/collision detected for

10 M.

1 I ptis Transmit data/transmit data for 10 M.

TXCLK_10M
TXD[3:0]/

4 O pob4 Transmit data/transmit data for 10 M.
TXD_10M
LOOP_10M

TX_EN/
TXEN_10M

TX_ERR/

PCOMP_10M

CRS/

I O pob4 Transmit enable or transmit enable for 10

M.

1 O pob4 Transmit error/packet compression

enable for 10 M.

1 I ptis Carrier sense/carrier sense for 10 M.
CRS_10M

RX_CLK/

1 I ptis Receive clock/receive clock for 10 M.
RXCLK_10M

RXD[3:0]/

4 1 ptis Receive data/receive data for 10 M.
RXD_10M

RX_DV/

1 I ptis Receive data valid.
LINK_10M

RX_ERR 1 I ptis Receive error.

HDLC TXDA 1 O pob4 HDLC channel A transmit data.
Channel A RXDA 1 I ptis HDLC channel A receive data.
(9) nDTRA 1 O pob4 HDLC channel A data terminal ready.

nRTSA 1 O pob4 HDLC channel A request to send.
nCTSA 1 I ptis HDLC channel A clear to send.
nDCDA 1 I ptis HDLC channel A data carrier detected.
nSYNCA 1 O pob4 HDLC channel A sync is detected.
RXCA 1 I ptis HDLC channel A receiver clock.
TXCA 1 I/O ptbsut1 HDLC channel A transmitter clock.

HDLC TXDB 1 O pob4 HDLC channel B transmit data.
Channel B RXDB 1 I ptis HDLC channel B receive data.
(9) nDTRB 1 O pob4 HDLC channel B data terminal ready.

nRTSB 1 O pob4 HDLC channel B request to send.
nCTSB 1 I ptis HDLC channel B clear to send.
nDCDB 1 I ptis HDLC channel B data carrier detected.
nSYNCB 1 O pob4 HDLC channel B sync is detected.
RXCB 1 I ptis HDLC channel B receiver clock.
TXCB 1 I/O ptbsut1

HDLC channel B transmitter clock.

1-14

S3C4510B PRODUCT OVERVIEW

Table 1-2. S3C4510B Pin List and PAD Type (Continued)

Group Pin Name Pin Counts I/O Type Pad Type Description

UART 0 UCLK 1 I ptis UART External Clock for UART0/UART1
(5) UARXD0 1 I ptic UART 0 receive data.

UATXD0 1 O pob4 UART 0 transmit data.
nUADTR0 1 I ptic Not UART 0 data terminal ready.

nUADSR0 1 O pob4 Not UART 0 data set ready.
UART 1 UARXD1 1 I ptic UART 1 receive data.
(4) UATXD1 1 O pob4 UART 1 transmit data.

nUADTR1 1 I ptic Not UART 1 data terminal ready.

NUADSR1 1 O pob4 Not UART 1 data set ready.
General- P[7:0] 8 I/O ptbst4sm General I/O ports.
Purpose I/O

(xINTREQ,
nXDREQ,

nXDACK
Timer 0, 1)

(18)

xINTREQ

[3:0]/P[11:8]

xXDREQ

[1:0]/P[13:12]

nXDACK[1:0]

/ P[15:14]

TIMER0/P

4 I/O ptbst4sm External interrupt requests or general I/O

ports.

2 I/O ptbst4sm External DMA requests for GDMA or

general I/O ports.

2 I/O ptbst4sm External DMA acknowledge from GDMA

or general I/O ports.

1 I/O ptbst4sm Timer 0 out or general I/O port.

[16]

TIMER1/P

1 I/O ptbst4sm Timer 1 out or general I/O port.

[17]
I2C SCL 1 I/O ptbcd4 I2C serial clock.
(2) SDA 1 I/O ptbcd4 I2C serial data.

1-15

PRODUCT OVERVIEW S3C4510B

Table 1-3. S3C4510B PAD Type

Pad Type I/O Type Current

Drive

Cell Type Feature Slew-Rate

Control

ptic I – LVCMOS level 5 V-tolerant –
ptis I – LVCMOS schmit trigger level 5 V-tolerant –
pticu I – LVCMOS level 5 V-tolerant

–

Pull-up register

pticd I – LVCMOS level 5 V-tolerant

–

Pull-down register
pia_bb I – Analog input with seperate bulk bias – –
pob1 O 1 mA Normal buffer – –
ptot2 O 2 mA Tri-state buffer 5 V-tolerant –
pob4 O 4 mA Normal buffer – –
ptot4 O 4 mA Tri-state buffer 5 V-tolerant –
ptot6 O 6 mA Tri-state buffer 5 V-tolerant –
ptbsut1 I/O 1 mA LVCMOS schmit trigger level

Tri-state buffer

5 V-tolerant

Pull-up register

–

ptbcut4 I/O 4 mA LVCMOS level Tri-state buffer 5 V-tolerant Medium
ptbcd4 I/O 4 mA LVCMOS level open drain buffer 5 V-tolerant –
ptbst4sm I/O 4 mA LVCMOS schmit trigger level 5 V-tolerant Medium
Ptbsut6 I/O 6 mA LVCMOS schmit trigger level 5 V-tolerant

–

Pull-up register

NOTE: pticu and pticd provides 100K Ohm Pull-up(down) register. For detail information about the pad type, see Chapter 4.

Input/Output Cells of the "STD90/MDL90 0.35 um 3.3 V Standard Cell Library Data Book", produced by Samsung
Electrionic Co., Ltd, ASIC Team.

nRESET

64*f

MCLK

nRSCO

NOTE: After the falling edge of nRESET, the S3C4510B count 64 cycles for a system reset

and needs further 512 cycles for a TAG RAM clear of cache.
After these cycles, the S3C4510B asserts nRCS0 when the nRESET is released.

512*f

MCLK

Figure 1-3. Reset Timing Diagram

1-16

S3C4510B PRODUCT OVERVIEW

CPU CORE OVERVIEW

The S3C4510B CPU core is a general purpose 32-bit ARM7TDMI microprocessor, developed by Advanced RISC
Machines, Ltd. (ARM). The core architecture is based on Reduced Instruction Set Computer (RISC) principles.
The RISC architecture makes the instruction set and its related decoding mechanism simpler and more efficient
than those with microprogrammed Complex Instruction Set Computer (CISC) systems. High instruction
throughput and impressive real-time interrupt response are among the major beneifts of the architecture.
Pipelining is also employed so that all components of the processing and memory systems can operate
continuously. The ARM7TDMI has a 32-bit address bus.

An important feature of the ARM7TDMI processor that makes itself distinct from the ARM7 processor is a unique
architectural strategy called THUMB. The THUMB strategy is an extension of the basic ARM architecture
consisting of 36 instruction formats. These formats are based on the standard 32-bit ARM instruction set, while
having been re-coded using 16-bit wide opcodes.

As THUMB instructions are one-half the bit width of normal ARM instructions, they produce very high-density
codes. When a THUMB instruction is executed, its 16-bit opcode is decoded by the processor into its equivalent
instruction in the standard ARM instruction set. The ARM core then processes the 16-bit instruction as it would a
normal 32-bit instruction. In other words, the THUMB architecture gives 16-bit systems a way to access the 32-bit
performance of the ARM core without requiring the full overhead of 32-bit processing.

As the ARM7TDMI core can execute both standard 32-bit ARM instructions and 16-bit THUMB instructions, it
allows you to mix the routines of THUMB instructions and ARM code in the same address space. In this way, you
can adjust code size and performance, routine by routine, to find the best programming solution for a specific
application.

Address
Register

Address

Incrementer

Instruction

Register Bank

Multiplier

Barrel

Shifter

32-Bit ALU

Write Data

Register

Decoder and

Logic Controll

Instruction

Pipeline and Read

Data Register

Figure 1-4. ARM7TDMI Core Block Diagram

1-17

PRODUCT OVERVIEW S3C4510B

INSTRUCTION SET

The S3C4510B instruction set is divided into two subsets: a standard 32-bit ARM instruction set and a 16-bit
THUMB instruction set.

The 32-bit ARM instruction set is comprised of thirteen basic instruction types, which can, in turn, be divided into
four broad classes:

• Four types of branch instructions which control program execution flow, instruction privilege levels, and
switching between an ARM code and a THUMB code.

• Three types of data processing instructions which use the on-chip ALU, barrel shifter, and multiplier to
perform high-speed data operations in a bank of 31 registers (all with 32-bit register widths).

• Three types of load and store instructions which control data transfer between memory locations and the
registers. One type is optimized for flexible addressing, another for rapid context switching, and the third for
swapping data.

• Three types of co-processor instructions which are dedicated to controlling external co-processors. These
instructions extend the off-chip functionality of the instruction set in an open and uniform way.

NOTE

All 32-bit ARM instructions can be executed conditionally.

The 16-bit THUMB instruction set contains 36 instruction formats drawn from the standard 32-bit ARM instruction
set. The THUMB instructions can be divided into four functional groups:

• Four branch instructions.

• Twelve data processing instructions, which are a subset of the standard ARM data processing instructions.

• Eight load and store register instructions.

• Four load and store multiple instructions.

NOTE

Each 16-bit THUMB instruction has a corresponding 32-bit ARM instruction with an identical
processing model.

The 32-bit ARM instruction set and the 16-bit THUMB instruction set are good targets for compilers of many
different high-level languages. When an assembly code is required for critical code segments, the ARM
programming technique is straightforward, unlike that of some RISC processors which depend on sophisticated
compiler technology to manage complicated instruction interdependencies.

Pipelining is employed so that all parts of the processor and memory systems can operate continuously.
Typically, while one instruction is being executed, its successor is being decoded, and the third instruction is
being fetched from memory.

1-18

S3C4510B PRODUCT OVERVIEW

MEMORY INTERFACE

The CPU memory interface has been designed to help the highest performance potential to be realized without
incurring high costs in the memory system. Speed-critical control signals are pipelined so that system control
functions can be implemented in standard low-power logic. These pipelined control signals allow you to fully
exploit the fast local access modes, offered by industry standard dynamic RAMs.

OPERATING STATES

From a programmer′s point of view, the ARM7TDMI core is always in one of two operating states. These states,
which can be switched by software or by exception processing, are:

• ARM state (when executing 32-bit, word-aligned, ARM instructions), and

• THUMB state (when executing 16-bit, half-word aligned THUMB instructions).

OPERATING MODES

The ARM7TDMI core supports seven operating modes:

• User mode: a normal program execution state

• FIQ (Fast Interrupt Request) mode: for supporting a specific data transfer or channel processing

• IRQ (Interrupt ReQuest) mode: for general purpose interrupt handling

• Supervisor mode: a protected mode for the operating system

• Abort mode: entered when a data or instruction pre-fetch is aborted

• System mode: a privileged user mode for the operating system

• Undefined mode: entered when an undefined instruction is executed

Operating mode changes can be controlled by software. They can also be caused by external interrupts or
exception processing. Most application programs execute in user mode. Privileged modes (that is, all modes
other than User mode) are entered to service interrupts or exceptions, or to access protected resources.

1-19

PRODUCT OVERVIEW S3C4510B

REGISTERS

The S3C4510B CPU core has a total of 37 registers: 31 general-purpose 32-bit registers, and 6 status registers.
Not all of these registers are always available. Whether a registers is available to the programmer at any given
time depends on the current processor operating state and mode.

NOTE

When the S3C4510B is operating in ARM state, 16 general registers and one or two status registers can
be accessed at any time. In privileged mode, mode-specific banked registers are switched in.

Two register sets, or banks, can also be accessed, depending on the core′s current state, the ARM state register
set and the THUMB state register set:

• The ARM state register set contains 16 directly accessible registers: R0-R15. All of these registers, except for
R15, are for general-purpose use, and can hold either data or address values. An additional (17th) register,
the CPSR (Current Program Status Register), is used to store status information.

• The THUMB state register set is a subset of the ARM state set. You can access 8 general registers, R0-R7,
as well as the program counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR. Each
privileged mode has a corresponding banked stack pointer, link register, and saved process status register
(SPSR).

The THUMB state registers are related to the ARM state registers as follows:

• THUMB state R0-R7 registers and ARM state R0–R7 registers are identical

• THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical

• THUMB state SP, LR, and PC are mapped directly to ARM state registers R13, R14, and R15, respectively

In THUMB state, registers R8-R15 are not part of the standard register set. However, you can access them for
assembly language programming and use them for fast temporary storage, if necessary.

1-20

S3C4510B PRODUCT OVERVIEW

EXCEPTIONS

An exception arises when the normal flow of program execution is interrupted, e.g., when processing is diverted
to handle an interrupt from a peripheral. The processor state just prior to handling the exception must be
preserved so that the program flow can be resumed when the exception routine is completed. Multiple exceptions
may arise simultaneously.

To process exceptions, the S3C4510B uses the banked core registers to save the current state. The old PC value
and the CPSR contents are copied into the appropriate R14 (LR) and SPSR registers. The PC and mode bits in
the CPSR are adjusted to the value corresponding to the type of exception being processed.

The S3C4510B core supports seven types of exceptions. Each exception has a fixed priority and a corresponding
privileged processor mode, as shown in Table 1-4.

Table 1-4. S3C4510B CPU Exceptions

Exception Mode on Entry Priority

Reset Supervisor mode 1 (highest)
Data abort Abort mode 2
FIQ FIQ mode 3
IRQ IRQ mode 4
Prefetch abort Abort mode 5
Undefined instruction Undefined mode 6
SWI Supervisor mode 6 (lowest)

1-21

PRODUCT OVERVIEW S3C4510B

SPECIAL REGISTERS

Table 1-5. S3C4510B Special Registers

Group Registers Offset R/W Description Reset/Value

System SYSCFG 0x0000 R/W System configuration register 0x37FFFF91
Manager CLKCON 0x3000 R/W Clock control register 0x00000000

EXTACON0 0x3008 R/W External I/O timing register 1 0x00000000
EXTACON1 0x300C R/W External I/O timing register 2 0x00000000
EXTDBWTH 0x3010 R/W Data bus width for each memory bank 0x00000000
ROMCON0 0x3014 R/W ROM/SRAM/Flash bank 0 control register 0x20000060
ROMCON1 0x3018 R/W ROM/SRAM/Flash bank 1 control register 0x00000060
ROMCON2 0x301C R/W ROM/SRAM/Flash bank 2 control register 0x00000060
ROMCON3 0x3020 R/W ROM/SRAM/Flash bank 3 control register 0x00000060
ROMCON4 0x3024 R/W ROM/SRAM/Flash bank 4 control register 0x00000060
ROMCON5 0x3028 R/W ROM/SRAM/Flash bank 5 control register 0x00000060
DRAMCON0 0x302C R/W DRAM bank 0 control register 0x00000000
DRAMCON1 0x3030 R/W DRAM bank 1 control register 0x00000000
DRAMCON2 0x3034 R/W DRAM bank 2 control register 0x00000000
DRAMCON3 0x3038 R/W DRAM bank 3 control register 0x00000000

REFEXTCON 0x303C R/W Refresh and external I/O control register 0x000083FD
Ethernet BDMATXCON 0x9000 R/W Buffered DMA receive control register 0x00000000
(BDMA) BDMARXCO

N

BDMATXPTR 0x9008 R/W Transmit frame descriptor start address 0x00000000

BDMARXPTR 0x900C R/W Receive frame descriptor start address 0x00000000

BDMARXLSZ 0x9010 R/W Receive frame maximum size Undefined

BDMASTAT 0x9014 R/W Buffered DMA status 0x00000000

CAM 0x9100–

BDMATXBUF 0x9200–

BDMARXBUF 0x9800–

0x9004 R/W Buffered DMA transmit control register 0x00000000

W CAM content (32 words) Undefined

0x917C

0x92FC

0x99FC

R/W BDMA Tx buffer (64 words) for test mode

addressing

R/W BDMA Rx buffer (64 words) for test mode

addressing

Undefined

Undefined

1-22

S3C4510B PRODUCT OVERVIEW

Table 1-5. S3C4510B Special Registers (Continued)

Group Registers Offset R/W Description Reset/Value

Ethernet MACON 0xA000 R/W
(MAC) CAMCON 0xA004 R/W

MACTXCON 0xA008 R/W
MACTXSTAT 0xA00C R/W
MACRXCON 0xA010 R/W
MACRXSTAT 0xA014 R/W

Ethernet MAC control register
CAM control register
MAC transmit control register
MAC transmit status register
MAC receive control register
MAC receive status register

0x00000000
0x00000000
0x00000000
0x00000000
0x00000000

0x00000000
STADATA 0xA018 R/W Station management data 0x00000000
STACON 0xA01C R/W Station management control and address 0x00006000
CAMEN 0xA028 R/W CAM enable register 0x00000000
EMISSCNT 0xA03C R/W Missed error count register 0x00000000
EPZCNT 0xA040 R Pause count register 0x00000000
ERMPZCNT 0xA044 R Remote pause count register 0x00000000
ETXSTAT 0x9040 R Transmit control frame status 0x00000000

HDLC HMODE 0x7000 R/W HDLC mode register 0x00000000
Channel A HCON 0x7004 R/W HDLC control register 0x00000000

HSTAT 0x7008 R/W HDLC status register 0x00010400
HINTEN 0x700C R/W HDLC interrupt enable register 0x00000000
HTXFIFOC 0x7010 W TxFIFO frame continue register –
HTXFIFOT 0x7014 W TxFIFO frame terminate register –
HRXFIFO 0x7018 R HDLC RxFIFO entry register 0x00000000
HBRGTC 0x701C R/W HDLC baud rate generate time constant 0x00000000
HPRMB 0x7020 R/W HDLC preamble constant 0x00000000
HSAR0 0x7024 R/W HDLC station address 0 0x00000000
HSAR1 0x7028 R/W HDLC station address 1 0x00000000
HSAR2 0x702C R/W HDLC station address 2 0x00000000
HSAR3 0x7030 R/W HDLC station address 3 0x00000000
HMASK 0x7034 R/W HDLC mask register 0x00000000
DMATxPTR 0x7038 R/W DMA Tx buffer descriptor pointer 0xFFFFFFFF
DMARxPTR 0x703C R/W DMA Rx buffer descriptor pointer 0xFFFFFFFF
HMFLR 0x7040 R/W Maximum frame length register 0xXXXX0000
HRBSR 0x7040 R/W DMA receive buffer size register 0xXXXX0000

1-23

PRODUCT OVERVIEW S3C4510B

Table 1-5. S3C4510B Special Registers (Continued)

Group Registers Offset R/W Description Reset/Value

HDLC HMODE 0x8000 R/W HDLC mode register 0x00000000
Channel B HCON 0x8004 R/W HDLC control register 0x00000000

HSTAT 0x8008 R/W HDLC status register 0x00010400
HINTEN 0x800C R/W HDLC interrupt enable register 0x00000000
HTXFIFOC 0x8010 W TxFIFO frame continue register –
HTXFIFOT 0x8014 W TxFIFO frame terminate register –
HRXFIFO 0x8018 R HDLC RxFIFO entry register 0x00000000
HBRGTC 0x801C R/W HDLC baud rate generate time constant 0x00000000
HPRMB 0xA020 R/W HDLC preamble constant 0x00000000
HSAR0 0x8024 R/W HDLC station address 0 0x00006000
HSAR1 0x8028 R/W HDLC station address 1 0x00000000
HSAR2 0x802C R/W HDLC station address 2 0x00000000
HSAR3 0x8030 R HDLC station address 3 0x00000000
HMASK 0x8034 R HDLC mask register 0x00000000
DMATxPTR 0x8038 R DMA Tx buffer descriptor pointer 0xFFFFFFFF
DMARxPTR 0x803C R/W DMA Rx buffer descriptor pointer 0xFFFFFFFF
HMFLR 0x8040 R/W Maximum frame length register 0xXXXX0000
HRBSR 0x8044 R/W DMA receive buffer size register 0xXXXX0000

I/O Ports IOPMOD 0x5000 R/W I/O port mode register 0x00000000

IOPCON 0x5004 R/W I/O port control register 0x00000000

IOPDATA 0x5008 R/W Input port data register Undefined
Interrupt INTMOD 0x4000 R/W Interrupt mode register 0x00000000
Controller INTPND 0x4004 R/W Interrupt pending register 0x00000000

INTMSK 0x4008 R/W Interrupt mask register 0x003FFFFF

INTPRI0 0x400C R/W Interrupt priority register 0 0x03020100

INTPRI1 0x4010 R/W Interrupt priority register 1 0x07060504

INTPRI2 0x4014 R/W Interrupt priority register 2 0x0B0A0908

INTPRI3 0x4018 R/W Interrupt priority register 3 0x0F0E0D0C

INTPRI4 0x401C R/W Interrupt priority register 4 0x13121110

INTPRI5 0x4020 R/W Interrupt priority register 5 0x00000014

INTOFFSET 0x4024 R Interrupt offset address register 0x00000054

INTOSET_FIQ 0x4030 R FIQ interrupt offset register 0x00000054

INTOSET_IRQ 0x4034 R IRQ interrupt offset register 0x00000054
I2C Bus IICCON 0XF000 R/W I2C bus control status register 0x00000054

IICBUF 0xF004 R/W I2C bus shift buffer register Undefined

IICPS 0xF008 R/W I2C bus prescaler register 0x00000000

IICCOUNT 0xF00C R I2C bus prescaler counter register 0x00000000

1-24

S3C4510B PRODUCT OVERVIEW

Table 1-5. S3C4510BC Special Registers (Continued)

Group Registers Offset R/W Description Reset/Value

GDMA GDMACON0 0xB000 R/W GDMA channel 0 control register 0x00000000

GDMACON1 0xC000 R/W GDMA channel 1 control register 0x00000000
GDMASRC0 0xB004 R/W GDMA source address register 0 Undefined
GDMADST0 0xB008 R/W GDMA destination address register 0 Undefined
GDMASRC1 0xC004 R/W GDMA source address register 1 Undefined
GDMADST1 0xC008 R/W GDMA destination address register 1 Undefined
GDMACNT0 0xB00C R/W GDMA channel 0 transfer count register Undefined
GDMACNT1 0xC00C R/W GDMA channel 1 transfer count register Undefined

UART ULCON0 0xD000 R/W UART channel 0 line control register 0x00

ULCON1 0xE000 R/W UART channel 1 line control register 0x00
UCON0 0xD004 R/W UART channel 0 control register 0x00
UCON1 0xE004 R/W UART channel 1 control register 0x00
USTAT0 0xD008 R UART channel 0 status register 0xC0
USTAT1 0xE008 R UART channel 1 status register 0xC0
UTXBUF0 0xD00C W UART channel 0 transmit holding register Undefined
UTXBUF1 0xE00C W UART channel 1 transmit holding register Undefined
URXBUF0 0xD010 R UART channel 0 receive buffer register Undefined
URXBUF1 0xE010 R UART channel 1 receive buffer register Undefined
UBRDIV0 0xD014 R/W Baud rate divisor register 0 0x00
UBRDIV1 0xE014 R/W Baud rate divisor register 1 0x00

Timers TMOD 0x6000 R/W Timer mode register 0x00000000

TDATA0 0x6004 R/W Timer 0 data register 0x00000000
TDATA1 0x6008 R/W Timer 1 data register 0x00000000
TCNT0 0x600C R/W Timer 0 count register 0xFFFFFFFF
TCNT1 0x6010 R/W Timer 1 count register 0xFFFFFFFF

1-25

PRODUCT OVERVIEW S3C4510B

NOTES

1-26

S3C4510B PROGRAMMER'S MODEL

2 PROGRAMMER′′S MODEL

OVERVIEW

S3C4510B was developed using the advanced ARM7TDMI core designed by advanced RISC machines, Ltd.
Processor Operating States
From the programmer′s point of view, the ARM7TDMI can be in one of two states:
— ARM state which executes 32-bit, word-aligned ARM instructions.

— THUMB state which operates with 16-bit, half-word-aligned THUMB instructions. In this state, the PC uses bit

1 to select between alternate half-words.

NOTE

Transition between these two states does not affect the processor mode or the contents of the registers.

SWITCHING STATE
Entering THUMB State

Entry into THUMB state can be achieved by executing a BX instruction with the state bit (bit 0) set in the operand
register.

Transition to THUMB state will also occur automatically on return from an exception (IRQ, FIQ, UNDEF, ABORT,
SWI etc.), if the exception was entered with the processor in THUMB state.

Entering ARM State

Entry into ARM state happens:

1. On execution of the BX instruction with the state bit clear in the operand register.

2. On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI etc.). In this case, the PC is
placed in the exception mode′s link register, and execution commences at the exception′s vector address.

MEMORY FORMATS

ARM7TDMI views memory as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first
stored word, bytes 4 to 7 the second and so on. ARM7TDMI can treat words in memory as being stored either in
Big-Endian or Little-Endian format.

2-1

PROGRAMMER'S MODEL S3C4510B

BIG-ENDIAN FORMAT

In Big-Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least
significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines
31 through 24.

Higher address

Lower address

31
24

8

4

0

w Most significant byte is at lowest address
w Word is addressed by byte address of most signficant byte

9 15 8 7 0 Word address
5

9

5

1

10

11

6

2

7

3

8

4

0

Figure 2-1. Big-Endian Addresses of Bytes within Words

NOTE

The data locations in the external memory are different with Figure 2-1 in the S3C4620. Please refer to
the chapter 4, system manager.

LITTLE-ENDIAN FORMAT

In Little-Endian format, the lowest numbered byte in a word is considered the word′s least significant byte, and
the highest numbered byte the most significant. Byte 0 of the memory system is therefore connected to data lines
7 through 0.

2-2

Higher address

Lower address

31
24

11

7

3

w Most significant byte is at lowest address
w Word is addressed by byte address of least signficant byte

23 15 8 7 0
16

10

6

2

9

5

1

8

4

0

Figure 2-2. Little-Endian Addresses of Bytes Words

Word address

8

4

0

S3C4510B PROGRAMMER'S MODEL

INSTRUCTION LENGTH

Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state).
Data Types

ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four­byte boundaries and half words to two-byte boundaries.

OPERATING MODES

ARM7TDMI supports seven modes of operation:
— User (usr): The normal ARM program execution state
— FIQ (fiq): Designed to support a data transfer or channel process
— IRQ (irq): Used for general-purpose interrupt handling
— Supervisor (svc): Protected mode for the operating system
— Abort mode (abt): Entered after a data or instruction prefetch abort
— System (sys): A privileged user mode for the operating system
— Undefined (und): Entered when an undefined instruction is executed

Mode changes may be made under software control, or may be brought about by external interrupts or exception
processing. Most application programs will execute in User mode. The non-user modes known as privileged
modes-are entered in order to service interrupts or exceptions, or to access protected resources.

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PROGRAMMER'S MODEL S3C4510B

REGISTERS

ARM7TDMI has a total of 37 registers-31 general-purpose 32-bit registers and six status registers - but these
cannot all be seen at once. The processor state and operating mode dictate which registers are available to the
programmer.

The ARM State Register Set

In ARM state, 16 general registers and one or two status registers are visible at any one time. In privileged (non­User) modes, mode-specific banked registers are switched in. Figure 2-3 shows which registers are available in
each mode: the banked registers are marked with a shaded triangle.

The ARM state register set contains 16 directly accessible registers: R0 to R15. All of these except R15 are
general-purpose, and may be used to hold either data or address values. In addition to these, there is a
seventeenth register used to store status information.

Register 14 is used as the subroutine link register. This receives a copy of R15 when a branch

and link (BL) instruction is executed. At all other times it may be treated as a
general-purpose register. The corresponding banked registers R14_svc, R14_irq,
R14_fiq, R14_abt and R14_und are similarly used to hold the return values of
R15 when interrupts and exceptions arise, or when branch and link instructions are
executed within interrupt or exception routines.

Register 15

holds the Program Counter (PC). In ARM state, bits [1:0] of R15 are zero and bits
[31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1] contain the PC.

Register 16

is the CPSR (Current Program Status Register). This contains condition code flags
and the current mode bits.

FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). In ARM state, many FIQ handlers do
not need to save any registers. User, IRQ, Supervisor, Abort and Undefined each have two banked registers
mapped to R13 and R14, allowing each of these modes to have a private stack pointer and link registers.

2-4