SAMSUNG S3C2800 Technical data
现货库存、技术资料、百科信息、热点资讯，精彩尽在鼎好!
S3C2800
32-BIT RISC MICROPROCESSOR
DATA SHEET
Revision 1.0
Important Notice
The information in this publication has been carefully
checked and is believed to be entirely accurate at the
time of publication. Samsung assumes no
responsibility, however, for possible errors or
omissions, or for any consequences resulting from the
use of the information contained herein.
Samsung reserves the right to make changes in its
products or product specifications with the intent to
improve function or design at any time and without
notice and is not required to update this documentation
to reflect such changes.
This publication does not convey to a purchaser of
semiconductor devices described herein any license
under the patent rights of Samsung or others.
Samsung makes no warranty, representation, or
guarantee regarding the suitability of its products for
any particular purpose, nor does Samsung assume
any liability arising out of the application or use of any
product or circuit and specifically disclaims any and all
liability, including without limitation any consequential
or incidental damages.
S3C2800 32-Bit Microprocessor
Data Sheet, Revision 1.0
Publication Number: 11.0-S3-C2800-072002
"Typical" parameters can and do vary in different
applications. All operating parameters, including
"Typicals" must be validated for each customer
application by the customer's technical experts.
Samsung products are not designed, intended, or
authorized for use as components in systems
intended for surgical implant into the body, for
other applications intended to support or sustain
life, or for any other application in which the failure
of the Samsung product could create a situation
where personal injury or death may occur.
Should the Buyer purchase or use a Samsung
product for any such unintended or unauthorized
application, the Buyer shall indemnify and hold
Samsung and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all
claims, costs, damages, expenses, and
reasonable attorney fees arising out of, either
directly or indirectly, any claim of personal injury or
death that may be associated with such
unintended or unauthorized use, even if such
claim alleges that Samsung was negligent
regarding the design or manufacture of said
product.
© 2002 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior
written consent of Samsung Electronics.
Samsung Electronics' microcontroller business has been awarded full ISO-14001
certification (BSI Certificate No. FM24653). All semiconductor products are designed
and manufactured in accordance with the highest quality standards and objectives.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Lee, Giheung-Eup
Yongin-City, Gyeonggi-Do, Korea
C.P.O. Box #37, Suwon 449-900
TEL: (82)-(31)-209-6530
FAX: (82)-(31)-209-6547
Home-Page URL: Http://www.samsungsemi.com
Printed in the Republic of Korea
Microprocessor
S3C2800
32-Bit RISC
Data Sheet
OVERVIEW
SAMSUNG's S3C2800 32-bit RISC microprocessor is designed to provide a cost-effective and high-performance
micro-controller solution for general applications. The S3C2800 features the following integrated on-chip support
to help design a system a low cost: 16KB I/D caches, 2-ch UART with handshake, 4-ch DMA, memory controller,
3-ch timer, GPIO (General-Purpose Input/Output) ports, RTC (Real Time Clock), 2-ch IIC-BUS interface, and a
built-in PLL for system clock.
Based on ARM920T core, the S3C2800 is developed using 0.18 um CMOS standard cells and a memory
compiler. Its simple, elegant, and fully static low-power design is particularly suitable for both cost-sensitive and
power-sensitive applications. The 32-bit ARM920T RISC processor core (220Mips @200MHz), designed by
Advanced RISC Machines, Ltd., provides architectural enhancements such as the Thumb de-compressor, a 32bit hardware multiplier, and an on-chip ICE debug support. Also, the S3C2800 features the Harvard BUS
architecture for efficient data/instruction transfers.
By integrating various common system peripherals, the S3C2800 minimizes the overall system cost and
eliminates the need to configure additional components. The integrated on-chip functions are summarized as
follows :
• PCI BUS interface (32-bit, up to 66MHz).
1.8V static ARM920T CPU core with 16KB I/D (Instruction/Data) cache. (Harvard bus architecture up to
•
200MHz).
• External memory controller. (FP/EDO/SDRAM control, Chip select logic).
• 4-ch general DMAs with external request pins.
2-ch UART with handshake (IRDA1.0, 16-byte FIFO), Modem Interface.
•
• 2-ch multi-master IIC-BUS controller.
• 3-ch 16-bit timer.
16-bit Watchdog timer.
•
• 44 general-purpose GPIO ports including 8 external interrupt source.
• Power management: Normal, Slow, and Idle modes.
• RTC with calendar function.
• On-chip PLL clock generator.
S3C2800 MICROCONTROLLER DATA SHEET
FEATURES
Architecture
· Little-/Big-endian support for external memory.
Address space: 32Mbytes per each bank (Total
•
256Mbyte)
• Supports programmable 8/16/32-bit data bus
width for each memory bank
Fixed bank start address for all (static memory
•
and dynamic memory banks)
8 memory banks
•
– 4 memory banks for static memory (ROM,
SRAM, FLASH etc)
– 4 memory banks for dynamic memory (Fast
Page, EDO, and Synchronous DRAM)
Fully programmable access cycles for all static
•
memory banks
• Supports external wait signal to extend the bus
cycle
Supports self-refresh mode in DRAM/SDRAM.
•
Supports asymmetric/symmetric address of
•
DRAM
I/D (Instruction/Data) Cache Memory
64-way set-associative ICache (16KB) and
•
DCache (16KB)
• 8 words per line with one valid bit and 2 dirty
bits per line
Pseudo-random or round-robin replacement
•
algorithm
Write-through and Write-back cache operation.
•
The write buffer can hold 16 words of data and 4
•
addresses
• Low voltage cache for reduced power
consumption
Clock & Power Manager
• The on-chip PLL generates the necessary clock
for the operation of MCU at maximum of
200MHz@1.8V
Input frequency range: (Fin) = 6MHz – 10MHz.
•
Output frequency range: (F
•
) = 20MHz –
CLK
200MHz
Clock can be selectively provided to each
•
function block by software
Power Down Mode: NORMAL, SLOW, and IDLE
•
mode
– NORMAL mode: Normal operating mode
– SLOW mode: Low frequency clock without
PLL
– IDLE mode: Clock to CPU is disabled
PCI Bus Interface
• Embedded PCI Host Bridge
32-bit data bus at 66MHz
•
2
DATA SHEET S3C2800 MICROCONTROLLER
FEATURES (Continued)
Interrupt Controller
34 Interrupt sources.
•
(3 for Timers, 6 for UART, 8 for External
interrupts, 4 for DMA, 2 for RTC, 2 for IIC, 2 for
RCSR (Remote Control Signal Receiver), and 7
for PCI))
Software polling Interrupt mode
•
• Selectable level- or edge-triggered external
interrupts source
Programmable IRQ/FIQ for each interrupt
•
request
Supports FIQ (Fast Interrupt Request) for very
•
urgent interrupt request
Timer
3-ch 16-bit Timer with DMA-based or interrupt-
•
based operation
Watchdog Timer
16-bit Watchdog Timer
•
RCSR (Remote Control Signal Receiver)
8-step FIFO
•
• FIFO interrupt is generated on full (8) step
overflow
RTC (Real Time Clock)
• Full clock feature: sec, min, hour, date, day,
week, month, and year
32.768 kHz input clock
•
Alarm interrupt
•
Time tick interrupt
•
GPIO (General-Purpose Input/Output) Ports
8 external interrupt ports
•
• 44 multiplexed input/output ports.
UART
2-channel UART with DMA-based or interrupt
•
based operation
Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data
•
transmit/receive
• Supports hardware handshaking during
transmit/receive operation
Programmable baud rates (up to 230.4Kbps).
•
Supports IrDA 1.0 (up to 115.2Kbps)
•
Loop back mode for testing
•
• Program accessible 16-byte FIFO (2x16 byte
FIFO for transmit/receive data)
DMA Controller
• 4-channel general-purpose Direct Memory
Access controller without CPU intervention.
Support memory to memory, memory to I/O and
•
I/O to I/O DMA operations of the following 6
types:
Software, 3 internal function blocks (UART0,
UART1, Timer), and 2 External requests
• Burst transfer mode to enhance the transfer rate
on the FPDRAM, EDODRAM and SDRAM
IIC-BUS Interface
• 2-ch Multi-Master IIC-Bus with interrupt-based
operation
Serial, 8-bit oriented, bi-directional data
•
transfers at up to 100 Kbit/s in the standard
mode or up to 400 Kbit/s in the fast mode
Operating Voltage Range
Core: 1.8 V -0.1 V/+0.15 V
•
I/O: 3.3 V ± 0.3 V
•
Operating Frequency
Up to 200 MHz.
•
Package
208-pin LQFP
•
3
S3C2800 MICROCONTROLLER DATA SHEET
IPA[31:0]
BLOCK DIAGRAM
JTAG
Data MMU
DPA[31:0]
Data cache
Write back
PA tag
RAM
4ch-GDMA
Arbiter/Decode
PCI Bridge
Memory
Controller
WBPA[31:0]
C13
Processor core
(Integral
ARM9TDMI
EmbeddedICE)
DVA[31:0]
DD[31:0]
CP15
Write
buffer
AMBA bus
Interface
ASB
ASB to AHB bus Bridge
AHB BUS 32-bit
ID[31:0]
IV2A[31:0]DV2A[31:0]
C13
IVA[31:0]
Instruction
MMU
Instruction
cache
External
coproc
interface
BUS Controller
Arbiter/Decode
Interrupt
Controller
Clock(PLL) &
Power Manage
AHB to APB Bridge
AHB to APB Bridge
2ch-IIC
Watch-dog
APB BUS 32-bit
2ch-IIC
2ch-IIC
GPIO
RTC
2ch-IIC
2ch-UART
RMT Receive
2ch-IIC
2ch-IIC
3ch-Timers
Figure 1. S3C2800 Block Diagram
4
PRELIMINARY DATA SHEET S3C2800 MICROCONTROLLER
PIN DIAGRAM (208-LQFP)
ADDR5
DATA7
ADDR7
DATA8
ADDR8
DATA9
ADDR9
VDD
VSS
DATA10
ADDR10
DATA11
ADDR11
VSS3OP
ADDR13
ADDR12
VDD3OP
DATA12
DATA13
DATA14
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
S3C2800X
208-LQFP
VDD/VSS : Internal 1.8V power
AVDD/AVSS : Analog 1.8V Power
VDD3OP/VSS3OP : I/O 3.3V power
6564636261
686766
7473727170
69
7677787980
75
DATA6
ADDR6GPF2/EXTINT2
181
178
179
180
81
ADDR4
DATA5
176
177
VSS3OP
DATA4
174
175
8685848382
87
ADDR2
DATA3
ADDR3
VDD3OP
170
171
172
173
8889909192
DATA2
ADDR1
169
168
93
DATA1
ADDR0
166
167
PCI_nINTA
DATA0
164
165
PCI_AD2
PCI_AD1
PCI_AD0
161
162
163
9897969594
100
99
VSS3OP
PCI_AD4
PCI_AD3
158
159
160
101
102
103
PCI_AD5
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
PCI_AD6
PCI_AD7
PCI_C0/nBE0
VDD3OP
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
VSS3OP
PCI_AD15
PCI_C1/nBE1
PCI_PAR
PCI_nSERR
PCI_nPERR
PCI_nLOCK
PCI_nSTOP
PCI_nDEVSEL
PCI_nTRDY
VDD3OP
PCI_nIRDY
PCI_nFRAME
PCI_C2/nBE2
VSS3OP
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
VSS
VDD
PCI_AD22
PCI_AD23
PCI_IDSEL
PCI_C3/nBE3
VSS3OP
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
VDD3OP
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_nREQx3
PCI_nREQx2
VSS3OP
PCI_nREQ1
nSDCS3/nDRAS3/GPA5
nDCAS2/nSDCAS/GPB0
nDCAS3/nSDRAS/GPB1
nBE0/nWBE0/DQM0/GPB2
nBE1/nWBE1/DQM1/GPB3
nBE2/nWBE2/DQM2/GPB4
nBE3/nWBE3/DQM3/GPB5
VDD3OP
VSS3OP
nDCAS0/GPA6
nDCAS1/GPA7
SDCKE
SDCLK
DATA16
ADDR16
DATA17
ADDR17
DATA18
ADDR18
VDD3OP
VSS3OP
DATA19
ADDR19
DATA20
ADDR20
VDD
VSS
DATA21
ADDR21
DATA22
ADDR22
DATA23
ADDR23
DATA24
ADDR24
DATA25
DATA26
DATA27
DATA28
VDD3OP
VSS3OP
DATA29
DATA30
DATA31
nOE
nWE
GPB6/nWAIT
GPB7/CLKout
GPC0
GPC1
GPC2
nSDCS1/nDRAS1/GPA3
nSDCS0/nDRAS0
207
208
1nSDCS2/nDRAS2/GPA4
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53545556575860
nSCS3/GPA2
nSCS2/GPA1
nSCS0
nSCS1/GPA0
203
204
205
206
DATA15
ADDR15
201
202
59
ADDR14
200
TDI
TCK
IRIN
TMS
nTRST
GPC3/ENDIAN
TDO
GPD0/IICSDA0
GPD5/TxD0
GPD4/RxD0
GPD2/IICSDA1
GPD1/IICSCLK0
GPD3/IICSCLK1
GPD6/nCTS0
GPD7/nRTS0
nRESET_OUT
GPE1/TxD1
GPE0/RxD1
GPE2/nCTS1
GPE3/nRTS1
VSS
VDD
GPE5/nXDACK0
GPE4/nXDREQ0
GPF0/EXTINT0
GPF1/EXTINT1
GPF3/EXTINT3
GPE7/nXDACK1
GPE6/nXDREQ1
VDD3OP
GPF4/EXTINT4
GPF5/EXTINT5
GPF6/EXTINT6
GPF7/EXTINT7
XTAL0
VSS3OP
TEST
EXTAL0
XTAL1
nRESET
OM0
EXTAL1
OM1
AVDD
AVSS
PLLCAP
PCI_CLK
PCI_nRST
PCI_nGNT1
PCI_nGNTx2
PCI_nGNTx3
Figure 2. S3C2800 Pin Assignment (208-LQFP)
5
Loading...