SAMSUNG S3C2510A User Manual

现货库存、技术资料、百科信息、热点资讯，精彩尽在鼎好!

S3C2510A PRODUCT OVERVIEW

1.1 OVERVIEW

Samsung's S3C2510A 16/32-bit RISC micro-controller is a cost-effective, high-performance micro-controller solution for Ethernet-based systems, for example, SOHO router, internet gateway, WLAN AP, etc.

To efficiently support those network applications, S3C2510A provides the followings: 16/32-bit ARM940T RISC embedded with 4K-byte I-cache and 4K-byte D-cache, memory controller with 24-bit external address pins, one external bus master with bus request/acknowledge pins, two 10/100 Mbps Ethernet controllers, PCI & PC Card host/agent controller, AAL5 SAR and UTOPIA L1/L2, two port full/low speed USB host with root hub, one port USB function device with transceiver, six general-purpose DMAs, two high-speed UARTs, one console UART, DES and 3DES for IP security, IIC serial interface, interrupt controller, six 32-bit programmable timers, 30-bit watchdog timer, 64 programmable I/O ports, and four PLLs for clock generation.

The S3C2510A is developed using an ARM940T core, 0.18um CMOS standard cells and a memory compiler. Its powerful, elegant and fully static design is suitable for various network applications. Also S3C2510A adopts a new bus architecture, AMBA (Advanced Microcontroller Bus Architecture).

PRODUCT OVERVIEW

1-1

PRODUCT OVERVIEW S3C2510A

1.2 FEATURES

The following integrated on-chip functions are described in detail in this user's manual:

• 16/32-bit ARM940T RISC Embedded

• 4K-byte I-Cache and 4K-byte D-Cache

• Memory Controller with 24-bit External Address

Pins — 2 Banks of SDRAM for 16/32-bit Bus — 8 Banks of Flash/ROM/SRAM/External I/O for 8/16/32-bit Bus — One External Bus Master with Bus Request/Acknowledge Pins

• Two 10/100 Mbps Ethernet Controllers

• PCI Host/Agent Controller or CardBus (PCMCIA)

Host/Agent Controller — PCI Host mode: 5 (or more) PCI Slots Interface for PCI Cards — PC Card Host mode: 1 PC Card Socket Interface for 16-bit PC Card or CardBus PC Card

• AAL5 SAR and UTOPIA L1/L2

• 2 Port Full/Low Speed USB HOST with Root

Hub.

• 1 Port Full Speed USB Function with Transceiver

Spec. 1.1

• Six General-Purpose DMAs

• IIC Serial Interface

• Interrupt Controller

• Six 32-bit Programmable Timers

• 30-bit Watchdog Timer

• 64 Programmable I/O Ports

— 8 General-Purpose I/O — 6 External Interrupt Request — 6 Timer Output — 4 External DMA Request — 4 External DMA Acknowledge — 21 SAR Signals — 15 UART Signals

• Four PLLs for each ARM940T (166MHz),

System (133MHz), PCI & PC Card Controller Clock (33/66MHz), USB Host/Device Clock (48MHz), and Ethernet PHY (20/25MHz).

• CPU Operating Frequency: Up to 166MHz

• AHB Bus Operating Frequency: Up to 133MHz

• Package Type: 416 PBGA

• Core Operating at 1.8V ±5 %, -40~85

• I/O Operating at 3.3V ±5 %, -40~85

• 3.3V input/output levels, 5V tolerant only for PCI.

• Two High-Speed UARTs

• One Console UART

• DES and 3DES for IP Security

1-2

S3C2510A PRODUCT OVERVIEW

1.3 BLOCK DIAGRAM

2-bank

SDRAM

8-bank

Flash/ROM/

SRAM/ Ext I/O

10/100

Ethernet

MAC

10/100

Ethernet

MAC

AAL5 SAR

& Utopia L1/L2

USB Host Controller

PCI/PC Card

Host/Agent

Controller

Memory

Controller

DMA

133 MHz AHB BUS

A H B

I/F

APB

Bridge

Sys. Bus

Arbiter

Six

GDMA

4KB

D-Cache

ARM940T (166 MHz)

4KB

I-Cache

Interrupt

Controller

DES/

3DES

WDT

Six

Timers

133 MHz APB BUS

High Speed UART

Console

UART

I2C

GPIOs

USB 1.1

Function

External

Bus Master

REQ/ACK

Clock Gen.

Reset Drv.

with 4 PLLs

10 MHz

OSC.

20 MHz or

25 MHz

Figure 1-1. Block Diagram

1-3

PRODUCT OVERVIEW S3C2510A

ARM940T

The ARM940T cached processor is a member of the ARM9 Thumb family of high-performance 32-bit system-ona-chip processor solutions. It provides a complete high performance CPU subsystem, including ARM9TDMI RISC integer CPU, 4KB instruction/data caches, write buffer, and protection unit, with an AMBA bus interface. The ARM9TDMI core within the ARM940T executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing the user to trade off between high performance and high code density. It is binary compatible with ARM7TDMI, ARM10TDMI, and StrongARM processors, and is supported by a wide range of tools, operating systems, and application software.

Memory organization

Memory system is composed of 8 ROM/SRAM/Flash/Ext I/O banks and 2 SDRAM banks. Each ROM bank is fixed with 16M-byte address range and is supported with multiplexed and non-multiplexed address/data bus capability. Each SDRAM bank is supported with 128 MByte.

Two Ethernet Controllers

The S3C2510A includes two Ethernet controllers, which enables the user to configure SOHO router, internet gateway, etc. The main features are as follows.

— Buffered DMA (BDMA) engine using burst mode

— BDMA Tx/Rx buffers (256-byte/256-byte)

— MAC Tx/Rx FIFOs (80-byte/16-byte) to support re-transmit after collision without DMA request

— Data alignment logic

— Support for old and new media (compatible with existing 10M-bit/s networks)

— 10/100 Mbps operation to increase price/performance options and to support phased conversions

— Full IEEE 802.3 compatibility for existing applications

— Media Independent interface (MII) or 7-wire interface

— Station management (STA) signaling for external physical layer configuration and link negotiation

— On-chip CAM (21 addresses)

— Full-duplex mode for doubled bandwidth

— Pause operation hardware support for full-duplex flow control

— Long packet mode for specialized environments

— Short packet mode for fast testing

— PAD generation for ease of processing and reduced processing time

1-4

S3C2510A PRODUCT OVERVIEW

PCI & PC Card Host/Agent Controller

S3C2510A's PCI & PC Card Host/Agent Controller complies with the PCI Local Bus Specification rev. 2.2, PC Card Standard Release 7.2, and various design guides. PCI & PC Card Controller connects the ARM940T processor core and local system memory to the PCI bus or CardBus socket. The PCI bus or CardBus uses a 32bit multiplexed, address/data bus, and various control and error signals. Mis-aligned transfers are supported as well as burst transfers at the maximum data rate of 264MB/s @66MHz (132MB/s @33MHz). S3C2510A can function as a PCI(or CardBus) master(initiator) or target(slave), and function as PCI host bridge(or CardBus host bus adapter) referred to as "host mode" or PCI device(or CardBus PC Card) referred to as "agent mode". In host mode, it can be used as host/PCI bridge (or CardBus socket controller) on main board . But in agent mode, it can be used as PCI device on PCI card or CardBus device on CardBus PC Card. The PCI & PC Card Host Controller provides PCI bus arbitration for the S3C2510A and up to five other PCI bus masters (except PCI target-only devices). It can be disabled to allow for external PCI arbiter (if more than five PCI bus masters will be connected).

The PCI & PC Card Host Controller has one integrated block for PCI interface and CardBus interface (common silicon) and it supports only one interface as defined by PCI_PCCDM(PC Card Mode) pin. And PCI_HOSTM pin signal forces PCI & PC Card Controller to operate in host mode or agent mode. Each modes can be set as followings.

PCI Host Mode PCI_PCCDM = 0, PCI_HOSTM=1

PCI Agent Mode PCI_PCCDM = 0, PCI_HOSTM=0

CardBus PC Card Host Mode PCI_PCCDM = 1, PCI_HOSTM=1, CardBus PC Card is inserted

16-bit PC Card (PCMCIA) Host Mode PCI_PCCDM = 1, PCI_HOSTM=1, 16-bit PC Card is inserted

CardBus PC Card Agent Mode PCI_PCCDM = 1, PCI_HOSTM=0

NOTE:

Each mode is selected by PCI_PCCDM & PCI_HOSTM pin input and inserted card type

The PCI & PC Card Host/Agent Controller provides an address translation mechanism to map inbound PCI to local memory or peripherals and outbound processor core or peripherals to PCI. Four independent 8-word deep FIFOs are implemented for flow-through operation of PCI & PC Card read/write burst operation. And doorbell and mailbox registers, CLKRUN# central resource control logic, integrated pull-up resistors are also implemented.

As a CardBus host mode, it supports only single PC Card slot and generates interface signals to PC Card powerswitch. CardBus Host Controller supports 16-bit PC Card (PCMCIA card) or CardBus PC Card. CardBus Host Controller provides an address translation mechanism to map inbound PCI to local memory or peripherals and outbound processor core or peripherals to PCI. Four independent 8-word deep FIFOs are implemented.

As a PCI/CardBus agent mode, it supports independent three address decoders and provides address translation mechanism to map AHB local memory from PCI bus through three address bars and vice-versa. To support power management, it complies with PCI Bus Power Management Interface Specification Rev. 1.1 and PCI Mobile Design Guide Ver. 1.1. And also it supports DMA operation with two-channel dedicated DMA to enhance the performance.

1-5

PRODUCT OVERVIEW S3C2510A

PCI Host/Agent Controller Features are as Follows

— 32-bit, 33/66 MHz, 5V tolerant, Up to 264M-byte/sec @66MHz

— PCI Local Bus Specification Rev.2.2 compliant

— PCI Bus Power Management Interface Specification Rev.1.1 compliant

— PCI Mobile Design Guide Ver.1.1 compliant

— Mini PCI Specification Rev.1.0 compliant

— Advanced Configuration and Power Interface (ACPI) Specification Rev.2.0 compliant

— Supports PCI PME# pin and wake-up by software

— Round-robin PCI bus arbiter supports five external REQ#, GNT# pins

— Two-channel dedicated DMA

— Integrated pull-up resistors

CardBus PC Card Host/Agent Controller Features (Common Silicon with PCI) are as Follows

— 32-bit, 33 MHz, 3.3V, Up to 132M-byte/sec

— PC Card Standard Release 7.1 compliant

— PCI Bus Power Management Interface Specification Rev.1.1 compliant

— PCI Mobile Design Guide Ver.1.1 compliant

— Advanced Configuration and Power Interface (ACPI) Specification Rev.2.0 compliant

— Single PC Card slot interface with hot insertion and removal

— Interface to 16-bit PC Card (PCMCIA card) or CardBus PC Card

— Interface to PC Card power-switch like TI TPS2211A and MAXIM MAX1602

— Integrated slew-rate controlled buffers for the difference between PCI and CardBus

— Advanced filtering on card detect lines provide 60 microseconds of noise immunity

— Supports CardBus CSTSCHG pin and Socket Event (Status Changed registers) registers

— Two-channel dedicated DMA

— Integrated pull-up resistors

— Common memory, attribute memory and I/O interface supported for 16-bit PC Card

16-bit PC Card Host Controller Features (Common Silicon with PCI) are as Follows

— PC Card Standard Release 7.1 compliant

— Advanced filtering on card detect lines provide 60 microseconds of noise immunity

— Two-channel dedicated DMA

1-6

S3C2510A PRODUCT OVERVIEW

AAL5 SAR and UTOPIA L1/L2

The S3C2510A SAR is a powerful, cost-effective solution for providing packet-to-ATM connectivity. Once a data packet is given to the S3C2510A SAR, the packet is translated into cells using either the AAL5 protocol or the null AAL protocol. Then, without further host intervention, the cells are transmitted using selected scheduling algorithms. The host is notified upon completion of the packet transmission. The S3C2510A SAR also receives cells from the PHY devices, reassembles them into packets, and notifies the host when a packet has arrived.

All packets are queued in system memory. Misaligned transfers are supported for ease of implementing LANE and MPOA protocols without requiring any packet data movement. VP scheduling is supported, as well as the more common VC scheduling, allowing a mix of Permanent Virtual Path (PVP), Switched Virtual Path (SVP), Permanent Virtual Channel (PVC), and Switched Virtual Channel (SVC) connections.

Some key features are as follow:

— CBR, UBR, rt-VBR and nrt-VBR traffic with rates set on a per-VC or per-VP basis

— AAL0 (raw cells) and AAL5 segmentation and reassembly

— Segments and reassembles data up to about 70Mbps via UTOPIA interface

— Generates and verifies CRC-10 for OAM cells and AAL-3/4 cells

— Concurrent OAM cells and AAL5 cells on each active connection

— Simultaneous segmentation and reassembly of up to 32 connection with internal memory and up to 4K

connection with external memory

— On chip 8K-byte SRAM for internal connection memory

— CAM for connection number mapping (up to 32 connections)

— Packet sizes up to 64K-byte

— Scatter and gather packet capability for large packets

— Starts of Packet offset available for ease of implementing bridging and routing between different protocols

— Big/little endian mode for packet payload

— Glue-less UTOPIA level 2 interface (up to 7 PHYs).

USB Host Controller

S3C2510A supports 2 port USB host interface as follows; Open HCI Rev 1.0 compatible, USB Rev1.1 compatible, 2 down stream ports. Support for Full/Low Speed USB devices. The S3C2510A USB Host controller complies with OPEN HCI Rev 1.0. Please refer to Open Host Controller Interface Rev 1.0 specification for detail information. The main features are as follows

— USB specification 1.0 compliant

— Full/Low speed operation support.

— Root hub built in with 2 downstream ports.

1-7

PRODUCT OVERVIEW S3C2510A

Universal Serial Bus (USB) Function Device

The S3C2510A includes a USB controller that enables the customers to implement USB devices for telephony, audio, and other applications. The USB controller is intended for the full-speed signaling rate of 12Mbit/s. Additionally, the S3C2510A USB controller has following features:

— A total of 5 endpoints: 1 control endpoint and 4 data endpoints that can support control, interrupt, bulk

transaction.

— Two data endpoints have 32-byte FIFO, two data endpoints have 64-byte FIFO.

— General DMA supported

Universal Asynchronous Receiver Transmitter (UART)

The S3C2510A has one console-UART and two high-speed UART. Consol UART can be used as system configuration or debug port. Each high-speed UART can be used as modem interface or other high-speed applications.

The most important features of high-speed UART are as follows

— Programmable baud rates

— 32-byte Transmit FIFO and 32-byte Receive FIFO

— UART source clock selectable (Internal clock: MCLK2, External clock : EUCLK)

— Auto baud rate detection

— Infra-red (IR) transmit/receive

— Insertion of one or two Stop bits per frame

— Selectable 5-bit, 6-bit, 7-bit, or 8-bit data transfers

— Parity checking

DES/3DES Accelerator

The DES Accelerator is a hardware accelerator for execution of the Data Encryption Standard(DES) algorithms as defined in FIPS PUB 46-1, which is equivalent to the Data Encryption Algorithm(DEA) provided in ANSI x3.92-

1981. The main features are as follows

— DES or Triple DES mode

— ECB or CBC mode

— Encryption or decryption support

— General DMA support

Six General DMA Channels

The S3C2510A has six general DMA channels, which can be used for data transfer between memory and peripherals (memory to peripherals, peripherals to memory) or within memory space (memory to memory). On-chip peripherals with general DMA service are the two high-speed UART, the DES and the USB controller. General DMA can also support four external DMA requests from DMA request pins (xGDMA_Req0 – xGDMA_Req3). General DMA can also support the programmable cycle counts of the external DMA acknowledge signals (xGDMA_Ack0 – xGDMA_Ack3).

1-8

S3C2510A PRODUCT OVERVIEW

Six Programmable Timer

The S3C2510A has six programmable timers. Each timer has its related pin, which is shared with programmable I/O function. Each timer can be programmed two operation mode. One is interval mode and the other is toggle mode. In interval mode, the initial timer output is set to low and it is set to high for 1 cycle time when timeout is reached. therefore the timer output is shaped like pulse wave. In toggle mode, the timer output is toggled when timeout is reached.

Hardware Watchdog Timer

The S3C2510A includes a watchdog timer, which is capable of generating system reset when the timeout value is reached. The time value is ranged up to 2^30 system clock cycles. The watchdog timer is used to reset and restart the system when a system has failed due to software error or to wrong response of external device.

Programmable Interrupt Controller

The S3C2510A has one programmable interrupt controller, which arranges the 36 programmable interrupt sources by the programmable priority. The interrupt controller supports 36 maskable interrupt sources, where 30 interrupts are from internal interrupts and 6 interrupts are from external interrupts. The interrupt with the highest priority is reported to the CPU.

Programmable I/O Port Controller

The S3C2510A has 64 programmable I/O ports, which can be used for another function. If another function is enabled, its I/O functionality is disabled. Six external interrupt request, four external DMA request, four external DMA acknowledge, six timer outputs, 21 SAR signals, and 15 UART signals are multiplexed with I/O function. Each I/O port can be programmed as Input or Output.

C Controller

The S3C2510A has IIC controller, which enables the customer to implement a simple and cost effective inter-IC connection. The IIC bus is a two-wire synchronous serial interface consisting of one data (SDA) and one clock (SCL) line. The S3C2510A IIC controller operates in only single master mode.

1-9

PRODUCT OVERVIEW S3C2510A

1.4 S3C2510A PIN LIST AND PAD TYPE

Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type

Group Pin Name Pin No. I/O Type Pad

System

XCLK T3 I phic S3C2510A PLL Clock Source. If CLKSEL is

Configurations

(21)

HCLKO M23 O phbst24 System clock output. The internal system

CLKSEL U1 I phic Clock Select for CPU PLL.

FILTER R2 AO poar50_

PHY_FREQ Y2 I phic PHY clock frequency select for PHY PLL.

PHY_CLKSEL U3 I phic Clock Select for PHY PLL

PHY_FILTER T2 AO poar50_

PHY_CLKO AD12 O phob8 PHY clock Out

Type

abb

Description

Low, PLL output clock is used as the system clock. If CLKSEL is high, XCLK is used as the system clock.

clock is monitored via HCLKO. If SDRAM is used, this clock should be used SDRAM clock

If CLKSEL is low, CPU PLL clock is used as ARM940T source clock. If high, XCLK (External clock) is used.

PLL filter pin for System PLL. If the PLL is used, 320pF capacitor should be connected between the pin and ground.

0 = 20MHz 1 = 25MHz

If this pin is set to Low, the PHY PLL generates clock depending on PHY_FREQ state. The PHY PLL goes into power down mode with PHY_CLKSEL set to High.

PLL filter pin for PHY PLL. If the PLL is used, 320pF capacitor should be connected between the pin and ground.

PHY PLL clock output can be monitored by PHY_CLKO. This clock is used as the external PHY source clock.

1-10

S3C2510A PRODUCT OVERVIEW

Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued)

Group Pin Name Pin No. I/O Type Pad

System

Configurations

CLKMOD[1] CLKMOD[0]

AB4 AC2

I phic The CLKMOD pin determines internal

(21)

CPU_FREQ[2] CPU_FREQ[1] CPU_FREQ[0]

AE1

AD1

I phic CPU Clock Frequency Selection.

AC3

BUS_FREQ[2] BUS_FREQ[1] BUS_FREQ[0]

AD2

AB3

I phic System Bus Clock Frequency Selection.

AC1

nRESET AB2 I phis Not Reset. NRESET is the global reset

TMODE AF3 I phicd Test Mode. The TMODE pin setting is

BIG W3 I phicd BIG endian mode select pin.

PCI_PCCDM AA2 I phic PCI(1'b0) or PC Card(1'b1) Mode Select of

PCI_HOSTM Y3 I phic Host (1'b1) or Agent (1'b0) Mode Select of

Description

Type

clock scheme of S3C2510A. When CLKMOD is “00”, the nfast clock mode is defined. In this mode, the same clock is used as CPU clock and system clock. When CLKMOD is “01” or “10”, the sync mode is defined. In this mode, the system clock is half frequency of the CPU clock. When CLKMOD is "11", the async clock mode is defined. In this mode, the CPU clock and system clock can operate independently as long as the CPU clock is faster than system clock. In this case, BUS_FREQ[2:0] pins should be 3b’000 to select PCI PLL, 3b’001 to select USB PLL for programmable setting.

input for the S3C2510A and nRESET must be held to "low" for at least 64 clock cycles for digital filtering.

interpreted as follows: 0 = normal operating mode 1 = chip test mode.

When this pin is set to “0”, the S3C2510A operates in litte endian mode. When this pin is set to “1”, the S3C2510A operates in big endian mode.

PCI & PC Card Controller

1-11

PRODUCT OVERVIEW S3C2510A

Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued)

Group Pin Name Pin No. I/O Type Pad Type Description

Memory

Interface

(80)

ADDR[23:0]

ADDR[10]

B14 O phot20 Address bus.

The 24-bit address bus covers the full 16 M word address range of each ROM/SRAM /FLASH and external I/O bank. In the SDRAM interface, ADDR[14:13] is always used as bank address of SDRAM devices. If SDRAM devices with 2 internal bank is used, ADDR[13] should be connected to the BA of SDRAM. If SDRAM devices with 4 internal bank is used, ADDR[14:13] should be connected to the BA[1:0] of SDRAM. ADDR[10]/AP is the auto precharge control pin. The auto precharge command is issued at the same time as burst read or burst write by asserting high on ADDR[10]/AP.

XDATA[31:0]

B phbsut20 External bi-directional 32bit data bus.

The S3C2510A supports 8 bit, 16bit, 32bit bus with ROM/SRAM/Flash/Ext IO bank, but supports 16 bit or 32 bit bus with SDRAM bank.

nSDCS[1] nSDCS[0]

G24 F26

O phot20 Not chip select strobe for SDRAM.

Two SDRAM banks are supported.

nSDRAS E25 O phot20 Not row address strobe for SDRAM.

NSDRAS signal is used for both SDRAM banks.

nSDCAS E26 O phot20 Not column address strobe for SDRAM.

NSDCAS signal is used for both SDRAM banks.

CKE L24 O phob12 Clock Enable for SDRAM

CKE is clock enable signal for SDRAM.

nSDWE/nWE16 F23 O phot20 Not Write Enable for SDRAM or 16 bit

ROM/SRAM. This signal is always used as write enable of SDRAM and is used as write enable of only 16-bit ROM/SRAM/Flash. (That is, It is not enabled for 8 bit Memory)

1-12

S3C2510A PRODUCT OVERVIEW

Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued)

Group Pin Name Pin No. I/O Type Pad

Type

Memory

nEWAIT K25 I phicu Not External wait signal.

Interface

(80)

nMCS[7] nMCS[6] nMCS[5] nMCS[4] nMCS[3] nMCS[2] nMCS[1] nMCS[0]

B0SIZE[1] B0SIZE[0]

nOE G25 O phot20 Not output enable.

nWBE[3]/nBE/

DQM[3]

nWBE[2]/nBE/

DQM[2]

nWBE[1]/nBE/

DQM[1]

nWBE[0]/nBE/

J24 H26 H25

J26 K24

J25 K23 K26

AE3 AF2

F25

H24

G26

H23

O phot20 Not ROM/SRAM/Flash/ External I/O Chip

I phic Bank 0 Data Bus Access Size.

O phot20 Not write byte enable or DQM for SDRAM

DQM[0]

Description

This signal is activated when an external I/O device or ROM/SRAM/Flash banks need more access cycles than those defined in the corresponding control register.

select. The S3C2510A supports upt to 8 banks of ROM/SRAM/Flash/ External I/O. By controlling the nRCS signals, you can map CPU address into the physical memory banks.

Bank0 is used for the boot program. You use these pins to set the size of the bank 0 data bus as follows: “01” = Byte, “10” = Half word, “11” = Word, and “00” = reserved.

Whenever a memory read access occurs, the nOE output controls the output enable port of the specific memory device.

Whenever a memory write access occurs, the nWBE output controls the write enable port of the specific memory device. DQM is data input/output mask signal for SDRAM.

1-13

PRODUCT OVERVIEW S3C2510A

Table 1-1. S3C2510A Pin List and PAD Type S3C2510A Pin List and PAD Type (Continued)

Group Pin Name Pin No. I/O Type Pad

Type

Memory

XBMREQ M24 I phicd External Bus Master request.

Interface

(80)

TAP

XBMACK L26 O phob8 External bus Acknowledge.

TCK AC5 I phic JTAG Test Clock.

Control

(5)

TMS AE4 I phicu JTAG Test Mode Select.

TDI AF4 I phicu JTAG Test Data In.

TDO AD4 O phot12 JTAG Test Data Out.

nTRST AE5 I phicu JTAG Not Reset.

Description

An external bus master uses this pin to request the external bus. When it activates the XBMREQ, the S3C2510A drives the state of external bus pins to high impedance. This lets the external bus master take control of the external bus. When it has control, the external bus master assumes responsibity for SDRAM refresh operation. The XBMREQ is deactivated when the external bus master releases the external bus. When this occurs, the S3C2510A can get the control of the bus and the XBMACK goes “low”.

The JTAG test clock shifts state information and test data into, and out of, the S3C2510A during JTAG test operations.

This pin controls JTAG test operations in the S3C2510A. This pin is internally connected pull-up.

The TDI level is used to serially shift test data and instructions into the S3C2510A during JTAG test operations. This pin is internally connected pull-up.

The TDO level is used to serially shift test data and instructions out of the S3C2510A during JTAG test operations.

Asynchronous reset of the JTAG logic. This pin is internally connected pull-up.

1-14

+ 32 hidden pages