SAMSUNG S3C24A0A User Guide

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S3C24A0A
32-BIT RISC
MICROPROCESSOR
USER'S MANUAL
Revision 0.4
(Preliminary)
Important Notice
The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.
Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes.
This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others.
Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.
S3C24A0A 32-Bit RISC Microprocessor User's Manual, Revision 0.4 Publication Number: 20-S3-CS3C24A0A-112004
"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts.
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Table of Contents
Chapter 1 Product Overview
Architectural Overview ..................................................................................................................................1-1
Features................................................................................................................................................1-2
Microprocessor and Overall Architecture .............................................................................................1-2
Memory Subsystem ..............................................................................................................................1-2
General Peripherals..............................................................................................................................1-3
Serial Communication ..........................................................................................................................1-3
Parallel Communication........................................................................................................................1-4
Image and Video Processing................................................................................................................1-4
Display Control .....................................................................................................................................1-6
Input Devices ........................................................................................................................................1-6
Storage Devices ...................................................................................................................................1-7
System Management............................................................................................................................1-7
Electrical Characteristics ......................................................................................................................1-7
Package................................................................................................................................................1-7
Pin Assignment.....................................................................................................................................1-9
Pin Descriptions ............................................................................................................................................1-30
I/O Signal Descriptions .........................................................................................................................1-30
Address MAP ................................................................................................................................................1-38
Address Space Assignment Overview .................................................................................................1-38
Device Specific Address Space............................................................................................................1-39
Internal Registers..................................................................................................................................1-42
Important Notes About S3C24A0A Special Registers .........................................................................1-62
Chapter 2 SROM Controller
Overview........................................................................................................................................................2-1
Feature .................................................................................................................................................2-2
Block Diagram ......................................................................................................................................2-2
Function Description.............................................................................................................................2-3
Programmable Access Cycle Write to Read Waveform.......................................................................2-5
Special Function Registers ...........................................................................................................................2-6
Srom Bus Width & Wait Contrl Register(SROM_BW)..........................................................................2-6
Srom Bank Control Register (SROM_BC: XrCSn0 ~ XrCSn2)............................................................2-7
S3C24A0A MICROPROCESSOR iii
Table of Contents (Continued)
Chapter 3 SDRAM Controller
Overview....................................................................................................................................................... 3-1
Selection of SDRAM ..................................................................................................................................... 3-2
Selection of SDRAM ..................................................................................................................................... 3-2
SELF Refresh....................................................................................................................................... 3-2
SDRAM Initialization Sequence........................................................................................................... 3-3
SDRAM Configuration Register.................................................................................................................... 3-6
SDRAM Control Register ..................................................................................................................... 3-7
Refresh Control Register ..................................................................................................................... 3-8
Chapter 4 NAND Flash Controller
Overview....................................................................................................................................................... 4-1
Features ............................................................................................................................................... 4-1
Pin Configuration ................................................................................................................................. 4-2
Block Diagram .............................................................................................................................................. 4-3
Boot Loader Function ................................................................................................................................... 4-4
Auto Load Mode ........................................................................................................................................... 4-6
Auto Load Programming Guide ........................................................................................................... 4-6
Auto Store Mode........................................................................................................................................... 4-7
Auto Store Programming Guide........................................................................................................... 4-7
Software Mode.............................................................................................................................................. 4-8
Stepping Stone (4K-Byte SRAM) ................................................................................................................. 4-9
Error Correction Code .................................................................................................................................. 4-9
ECC Module Features ......................................................................................................................... 4-10
ECC Programming Guide .................................................................................................................... 4-10
NAND Flash Memory Configurations ........................................................................................................... 4-11
NAND Flash Controller Special Registers.................................................................................................... 4-13
Configuration Register ......................................................................................................................... 4-13
Control Register ................................................................................................................................... 4-14
Command Register .............................................................................................................................. 4-15
Address Register ................................................................................................................................. 4-15
Main Data Area ECC0 Register ........................................................................................................... 4-16
Main Data Area ECC1 Register ........................................................................................................... 4-16
Main Data Area ECC2 Register ........................................................................................................... 4-16
Main Data Area ECC3 Register ........................................................................................................... 4-17
Spare Area ECC0 Register................................................................................................................. 4-17
Spare Area ECC1 Register.................................................................................................................. 4-17
Control Status Register........................................................................................................................ 4-18
ECC0 Status Register.......................................................................................................................... 4-19
ECC1 Status Register.......................................................................................................................... 4-19
Main Data Area ECC0 Status Register................................................................................................ 4-20
Main Data Area ECC1 Status Register................................................................................................ 4-20
Spare Area ECC Status Register ........................................................................................................ 4-20
Start Block Address Register ............................................................................................................... 4-21
END Block Address Register ............................................................................................................... 4-21
iv S3C24A0A MICROPROCESSOR
Table of Contents (Continued)
Chapter 5 Bus Matrix
Overview........................................................................................................................................................5-1
Special Function Registers ...........................................................................................................................5-2
SROMC/NFLASHC Arbiter Priority Register (Priority 0) ......................................................................5-2
SDRAMC Arbiter Priority Register (Priority 1) ......................................................................................5-2
Chapter 6 Interrupt Controller
Overview........................................................................................................................................................6-1
Functional Description...................................................................................................................................6-2
F-Bit and I-Bit Of PSR (Program Status Register) ...............................................................................6-2
Interrupt Mode ......................................................................................................................................6-2
Interrupt Pending Register....................................................................................................................6-2
Interrupt Mask Register ........................................................................................................................6-2
Interrupt Sources ..................................................................................................................................6-3
Interrupt Priority Generating Block .......................................................................................................6-4
Vectored Interrupt Mode (Only for IRQ) ...............................................................................................6-5
Source Pending Register (SRCPND)...................................................................................................6-7
Interrupt Mode Register (INTMOD) ......................................................................................................6-9
Interrupt Mask Register (INTMSK) .......................................................................................................6-11
Priority Register (PRIORITY)................................................................................................................6-13
Interrupt Pending Register (INTIPND)..................................................................................................6-14
Interrupt Offset Register (INTOFFSET)................................................................................................6-16
Sub Source Pending Register (SUBSRCPND)....................................................................................6-17
Interrupt Sub Mask Register (INTSUBMSK) ........................................................................................6-18
Vectored Interrupt Mode Register (VECT_INT_MODE) ......................................................................6-19
Vector Address Register (VAR)............................................................................................................6-19
S3C24A0A MICROPROCESSOR v
Table of Contents (Continued)
Chapter 7 PWM Timer
Overview....................................................................................................................................................... 7-1
Feature................................................................................................................................................. 7-1
PWM Timer Operation .................................................................................................................................. 7-3
Prescaler & Divider .............................................................................................................................. 7-3
Basic Timer Operation ......................................................................................................................... 7-3
Auto-Reload & Double Buffering.......................................................................................................... 7-4
TIMER Initialization Using Manual Update Bit and Inverter Bit ........................................................... 7-4
Example of a Timer Operation ............................................................................................................. 7-5
PWM (Pulse Width Modulation)........................................................................................................... 7-6
Output Level Control ............................................................................................................................ 7-7
DEAD Zone Generator......................................................................................................................... 7-8
DMA Request Mode............................................................................................................................. 7-9
PWM Timer Control Registers...................................................................................................................... 7-10
Timer Configuration Register 0 (TCFG0)............................................................................................. 7-10
Timer Configuration Register 1 (TCFG1)............................................................................................. 7-11
Timer Control Register (TCON) ........................................................................................................... 7-12
Timer 0 Count Observation Register (TCNTO0) ................................................................................. 7-13
Timer 1 Count Buffer Register & Compare Buffer Register (TCNTB1, TCMPB1) .............................. 7-14
Timer 1 Count Observation Register(TCNTO1) .................................................................................. 7-14
Timer 2 Count Buffer Register & Compare Buffer Register (TCNTB2, TCMPB2) .............................. 7-15
Timer 2 Count Observation Register (TCNTO2) ................................................................................. 7-15
Timer 3 Count Buffer Register & Compare Buffer Register (TCNTB3, TCMPB3) .............................. 7-16
Timer 3 Count Observation Register (TCNTO3) ................................................................................. 7-16
Timer 4 Count Buffer Register (TCNTB4)............................................................................................ 7-17
Timer 4 Count Observation Register (TCNTO4) ................................................................................. 7-17
Chapter 8 Watchdog Timer
Overview....................................................................................................................................................... 8-1
Features ............................................................................................................................................... 8-1
Watchdog Timer Operation.................................................................................................................. 8-2
WTDAT & WTCNT............................................................................................................................... 8-2
Consideration of Debugging Environment ........................................................................................... 8-2
Watchdog Timer Special Registers .............................................................................................................. 8-3
Watchdog Timer Control Register (WTCON) ...................................................................................... 8-3
Watchdog Timer Data Register (WTDAT) ........................................................................................... 8-4
Watchdog Timer Count Register (WTCNT)......................................................................................... 8-4
vi S3C24A0A MICROPROCESSOR
Table of Contents (Continued)
Chapter 9 DMA
Overview........................................................................................................................................................9-1
DMA Request Sources .........................................................................................................................9-1
DMA Operation..............................................................................................................................................9-2
External DMA DREQ/DACK Protocol...................................................................................................9-2
Examples of Possible Cases ................................................................................................................9-5
DMA Special Registers.........................................................................................................................9-6
DMA Initial Source Register (DISRC)...................................................................................................9-6
DMA Initial Source Control Register (DISRCC) ...................................................................................9-6
DMA Initial Destination Register (DIDST) ............................................................................................9-7
DMA Initial Destination Control Register (DIDSTC) .............................................................................9-7
DMA Control Register (DCON).............................................................................................................9-8
DMA Status Register (DSTAT).............................................................................................................9-10
DMA Current Source Register (DCSRC) .............................................................................................9-10
Current Destination Register (DCDST) ................................................................................................9-11
DMA Mask Trigger Register (DMASKTRIG) ........................................................................................9-12
S3C24A0A MICROPROCESSOR vii
Table of Contents (Continued)
Chapter 10 RTC (Real Time Clock)
Overview....................................................................................................................................................... 10-1
Feature................................................................................................................................................. 10-1
Real Time Clock Operation.................................................................................................................. 10-2
Leap Year Generator ........................................................................................................................... 10-2
Read/Write Registers........................................................................................................................... 10-2
Backup Battery Operation.................................................................................................................... 10-2
ALARM Function.................................................................................................................................. 10-3
TICK Time Interrupt ............................................................................................................................. 10-3
Round Reset Function ......................................................................................................................... 10-3
32.768kHz X-Tal Connection Example............................................................................................... 10-3
Real Time Clock Special Registers .............................................................................................................. 10-4
Real Time Clock Control Register (RTCCON) .................................................................................... 10-4
TICK Time Count Register (TICNT)..................................................................................................... 10-4
RTC ALARM Control Register (RTCALM)........................................................................................... 10-5
ALARM Second Data Register (ALMSEC) .......................................................................................... 10-6
ALARM Min Data Register (ALMMIN) ................................................................................................. 10-6
ALARM Hour Data Register (ALMHOUR) ........................................................................................... 10-6
ALARM Date Data Register (ALMDATE) ............................................................................................ 10-7
ALARM Mon Data Register (ALMMON) .............................................................................................. 10-7
ALARM Year Data Register (ALMYEAR) ............................................................................................ 10-7
BCD Second Register (BCDSEC) ....................................................................................................... 10-8
BCD Minute Register (BCDMIN) ......................................................................................................... 10-8
BCD Hour Register (BCDHOUR) ........................................................................................................ 10-9
BCD Date Register (BCDDATE).......................................................................................................... 10-9
BCD Day Register (BCDDAY) ............................................................................................................. 10-9
BCD Month Register (BCDMON) ........................................................................................................ 10-10
BCD Year Register (BCDYEAR) ......................................................................................................... 10-10
viii S3C24A0A MICROPROCESSOR
Table of Contents (Continued)
Chapter 11 UART
Overview........................................................................................................................................................11-1
Features................................................................................................................................................11-1
Block Diagram ......................................................................................................................................11-2
Uart Operation ......................................................................................................................................11-3
Uart Special Registers...................................................................................................................................11-10
Uart Line Control Register ....................................................................................................................11-10
Uart Control Register............................................................................................................................11-11
Uart FIFO Control Register...................................................................................................................11-13
Uart Modem Control Register...............................................................................................................11-14
Uart Tx/Rx Status Register...................................................................................................................11-15
Uart Error Status Register ....................................................................................................................11-16
Uart FIFO Status Register ....................................................................................................................11-17
Uart Modem Status Register ................................................................................................................11-18
Uart Transmit Buffer Register(Holding Register & FIFO Register) ......................................................11-19
Uart Receive Buffer Register (Holding Register & FIFO Register) ......................................................11-19
Uart Baud Rate Divisor Register ..........................................................................................................11-20
Uart Baud Rate Divisor Register ..........................................................................................................11-20
Chapter 12 IrDA Controller
Overview........................................................................................................................................................12-1
Feature .................................................................................................................................................12-1
Block Diagram ......................................................................................................................................12-2
External Interface Signals.....................................................................................................................12-2
Function Description.............................................................................................................................12-3
Core Initialization Procedure ................................................................................................................12-9
Special Function Registers ...........................................................................................................................12-10
IrDA Control Register (IrDA_CNT) .......................................................................................................12-10
IrDA Mode Definition Register(IrDA_MDR) ..........................................................................................12-11
IrDA Interrupt / DMA Configuration Register (IrDA_CNF)....................................................................12-11
IrDA Interupt Enalble Register (IrDA_IER) ...........................................................................................12-12
IrDA Interupt Identification Register (IrDA_IIR) ....................................................................................12-13
IrDA Line Status Register (IrDA_LSR) .................................................................................................12-14
IrDA FIFO Control Register (IrDA_FCR) ..............................................................................................12-15
IrDA Preamble Length Register (IrDA_PLR)........................................................................................12-16
IrDA Total Number of Data Bytes Remained in Rx FIFO (IrDA_RXNO)..............................................12-17
IrDA Transmit Frame-Length Register Low (IrDA_TXFLL) .................................................................. 12-17
IrDA Transmit Frame-Length Register High (IrDA_TXFLH).................................................................12-17
IrDA Receiver Frame-Length Register Low (IrDA_RXFLL) .................................................................12-18
IrDA Receiver Frame-Length Register High (IrDA_RXFLH) ................................................................12-18
S3C24A0A MICROPROCESSOR ix
Table of Contents (Continued)
Chapter 13 IIC-Bus Interface
Overview....................................................................................................................................................... 13-1
The IIC-Bus Interface........................................................................................................................... 13-2
Start and Stop Conditions .................................................................................................................... 13-2
Data Transfer Format........................................................................................................................... 13-4
ACK Signal Transmission .................................................................................................................... 13-5
Read-Write Operation .......................................................................................................................... 13-6
Bus Arbitration Procedures.................................................................................................................. 13-6
Abort Conditions .................................................................................................................................. 13-6
Configuring the IIC-Bus........................................................................................................................ 13-6
Flowcharts of the Operations in Each Mode........................................................................................ 13-7
IIC-Bus Interface Special Registers.............................................................................................................. 13-11
Multi-Master IIC-Bus Control Register (IICCON)................................................................................. 13-11
Multi-Master IIC-Bus Control/Status Register (IICSTAT) .................................................................... 13-12
Multi-Master IIC-Bus Address Register (IICADD)................................................................................ 13-13
Multi-Master IIC-Bus Transmit/Receive Data Shift Register (IICDS) .................................................. 13-13
Multi-Master IIC-Bus Sdaout Delay Register (SDADLY) ..................................................................... 13-13
Chapter 14 IIS-Bus Interface
Overview....................................................................................................................................................... 14-1
Features ............................................................................................................................................... 14-1
Block Diagram...................................................................................................................................... 14-1
Functional Descriptions........................................................................................................................ 14-2
Transmit or Receive Only Mode .......................................................................................................... 14-2
Dma Transfer ....................................................................................................................................... 14-2
Transmit and Receive Mode................................................................................................................ 14-2
Audio Serial Interface Format....................................................................................................................... 14-3
IIS-Bus Format ..................................................................................................................................... 14-3
MSB(Left) Justified............................................................................................................................... 14-3
Sampling Frequency and Master Clock............................................................................................... 14-4
IIS-Bus Interface Special Registers.............................................................................................................. 14-5
IIS Control Register (IISCON).............................................................................................................. 14-5
IIS Mode Register (IISMOD) ................................................................................................................ 14-6
IIS Prescaler Register (IISPSR)........................................................................................................... 14-7
IIS FIFO Control Register (IISFCON) .................................................................................................. 14-7
IIS FIFO Register (IISFIFO) ................................................................................................................. 14-8
x S3C24A0A MICROPROCESSOR
Table of Contents (Continued)
Chapter 15 SPI Interface
Overview........................................................................................................................................................15-1
Features................................................................................................................................................15-1
Block Diagram ......................................................................................................................................15-2
SPI Operation................................................................................................................................................15-3
SPI Special Registers....................................................................................................................................15-6
SPI Control Register.............................................................................................................................15-6
SPI Status Register ..............................................................................................................................15-7
SPI Pin Control Register.......................................................................................................................15-8
SPI Baud Rate Prescaler Register .......................................................................................................15-9
SPI Tx Data Register ............................................................................................................................15-9
SPI Rx Data Register............................................................................................................................15-9
Chapter 16 AC97 Controller
Overview........................................................................................................................................................16-1
Feature .................................................................................................................................................16-1
AC97 Controller Operation............................................................................................................................16-2
Block Diagram ......................................................................................................................................16-2
Internal Data Path.................................................................................................................................16-3
Operation Flow Chart ....................................................................................................................................16-4
AC-link Digital Interface protocol...................................................................................................................16-5
AC-link Output Frame (SDATA_OUT)..................................................................................................16-6
AC-link Input Frame (SDATA_IN).........................................................................................................16-6
AC97 Powerdown..........................................................................................................................................16-7
AC97 Controller Special Registers................................................................................................................16-9
AC97 Global Control Register (AC_GLBCTRL)...................................................................................16-9
AC97 Global Status Register (AC_GLBSTAT).....................................................................................16-10
AC97 Codec Command Register (AC_CODEC_CMD) .......................................................................16-11
AC97 Codec Status Register (AC_CODEC_STAT).............................................................................16-11
AC97 PCM Out/In Channel FIFO Address Register (AC_PCMADDR) ...............................................16-11
AC97 MIC in Channel FIFO Address Register (AC_MICADDR) .........................................................16-12
AC97 PCM Out/In Channel FIFO Data Register (AC_PCMDATA)......................................................16-12
AC97 MIC in Channel FIFO Data Register (AC_MICDATA)................................................................16-12
S3C24A0A MICROPROCESSOR xi
Table of Contents (Continued)
Chapter 17 USB Host Controller
Overview....................................................................................................................................................... 17-1
USB Host Controller Special Registers ........................................................................................................ 17-2
OHCI Registers for USB Host Controller ............................................................................................. 17-2
Chapter 18 USB Device
Overview....................................................................................................................................................... 18-1
Feature................................................................................................................................................. 18-1
USB Device Special Registers ..................................................................................................................... 18-3
FUNC_ADDR_REG ............................................................................................................................. 18-5
Power Management Register (PWR_REG) ........................................................................................ 18-6
Interrupt Register (EP_INT_REG, USB_INT_REG) ............................................................................ 18-7
Interrupt Enable Register (EP_INT_EN_REG, USB_INT_REG)......................................................... 18-9
Frame Number Register (FPAME_NUM1_REG, FRAME_NUM2_REG) ........................................... 18-10
Index Register (INDEX_REG).............................................................................................................. 18-11
End Point0 Control Status Register (EP0_CSR) ................................................................................. 18-12
End Point in Control Status Register (IN_CSR1_REG, IN_CSR2_REG) ........................................... 18-13
End Point Out Control Status Register (OUT_CSR1_REG, OUT_CSR2_REG) ................................ 18-15
End Point FIFO Register (EPN_FIFO_REG)....................................................................................... 18-17
Max Packet Register (MAXP_REG) .................................................................................................... 18-17
End Point Out Write Count Register (OUT_FIFO_CNT1_REG, OUT_FIFO_CNT2_REG) ................ 18-18
DMA Interface Control Register (EPN_DMA_CON)............................................................................ 18-19
DMA Unit Counter Register (EPN_DMA_UNIT).................................................................................. 18-20
DMA FIFO Counter Register (EPN_DMA_FIFO) ................................................................................ 18-21
DMA Total Transfer Counter Register
(EPN_DMA_TTC_L, EPN_DMA_TTC_M, EPN_DMA_TTC_H) ......................................................... 18-22
xii S3C24A0A MICROPROCESSOR
Table of Contents (Continued)
Chapter 19 MODEM Interface
Overview........................................................................................................................................................19-1
Features................................................................................................................................................19-2
Hardware Interface ...............................................................................................................................19-2
Signal Description.................................................................................................................................19-2
Interrupt Ports .......................................................................................................................................19-2
Address Mapping..................................................................................................................................19-3
Timing Diagram ....................................................................................................................................19-4
Software Interface.................................................................................................................................19-5
Modem Interface Special Registers ..............................................................................................................19-6
Interrupt Request to AP Register (INT2AP) .........................................................................................19-6
Interrupt Request to Modem Register (INT2MDM) ..............................................................................19-6
Chapter 20 General Purpose I/O Ports
Overview........................................................................................................................................................20-1
Port Control Descriptions ..............................................................................................................................20-3
Gpio Port Configuration Register For Normal Mode (GPCON_U, GPCON_M, GPCON_L) ...............20-3
Gpio Port Data Register For Normal Mode (GPDAT) ..........................................................................20-3
Gpio Port Pull-Pu Control Register for Normal Mode (GPPU) ............................................................. 20-3
External Interrupt Control Register (Extintcn/ Eintfltn/ Eintmask/ Eintpend) ........................................20-3
Peripheral Port Pull-Up Control Register for Normal Mode (PERIPU).................................................20-3
Alive Control Register (ALIVECON) .....................................................................................................20-4
Gpio Output Control Register for Sleep Mode (GPOEN_SLEEP) .......................................................20-4
Gpio Pull-Up Control Register for Sleep Mode (GPPU_SLEEP) .........................................................20-4
Peripheral Port Output Data Register for Sleep Mode (PERIDAT_SLEEPN)......................................20-4
Peripheral Port Output Control Register for Sleep Mode (PERIOEN_SLEEPN) .................................20-4
Peripheral Port Pull-Up Control Register for Sleep Mode (PERIPU_SLEEP) .....................................20-4
Reset Count Compare Register (RstCnt).............................................................................................20-4
General Purpose RAM Array (GPRAMn) .............................................................................................20-4
I/O Port Control Register ...............................................................................................................................20-5
GPIO Upper Port Control Register (GPCON_U).................................................................................. 20-5
Gpio Middle Port Control Register (GPCON_M) ..................................................................................20-6
Gpio Lower Port Control Register (GPCON_L)....................................................................................20-7
Gpio Port Data Register (GPDAT)........................................................................................................20-8
Gpio Port Pull Up Resister Control Register (GPPU)........................................................................... 20-8
External Interrupt Control Register (EXTINTC0) ..................................................................................20-9
S3C24A0A MICROPROCESSOR xiii
Table of Contents (Continued)
Chapter 20 General Purpose I/O Ports (Continued)
External Interrupt Control Register (EXTINTC1) ................................................................................. 20-10
External Interrupt Control Register (EXTINTC2) ................................................................................. 20-11
External Interrupt Filter Control Register (EINTFLTN) ........................................................................ 20-12
External Interrupt Mask Register (EINTMASK)) .................................................................................. 20-13
External Interrupt Pending Register (EINTPEND)............................................................................... 20-14
Peripheral Port Pull up Control Register (PERIPU)............................................................................. 20-15
Alive Control Register (ALIVECON) .................................................................................................... 20-16
GPIO Output Data Register (GPDAT_SLEEP).................................................................................... 20-17
GPIO Output Control Register for Sleep Mode (GPOEN_SLEEP) ..................................................... 20-17
GPIO Pull up Control Register for Sleep Mode (GPPU_SLEEP)........................................................ 20-17
Peripheral Port Output Data Register for Sleep Mode (PERIDAT_SLEEP0)...................................... 20-18
Peripheral Port Output Data Register for Sleep Mode (PERIDAT_SLEEP1)...................................... 20-19
Peripheral Port Output Control Register for Sleep Mode (PERIOEN_SLEEP0) ................................. 20-20
Peripheral Port Output Control Register for Sleep Mode (PERIOEN_SLEEP1) ................................. 20-21
Peripheral Port Pull up Control Register for Sleep Mode (PERIPU_SLEEP)...................................... 20-22
Reset Count Compare Register (RstCnt) ............................................................................................ 20-23
General Purpose RAM Array (GPRAMn) ............................................................................................ 20-24
Chapter 21 Camera Interface
Overview....................................................................................................................................................... 21-1
Features ............................................................................................................................................... 21-2
External Interface ................................................................................................................................. 21-2
Signal Description ................................................................................................................................ 21-2
Timing Diagram.................................................................................................................................... 21-3
External Connection Guide .................................................................................................................. 21-5
8-Bit Mode............................................................................................................................................ 21-5
16-Bit Mode.......................................................................................................................................... 21-5
Camera Interface Operation ......................................................................................................................... 21-6
Two DMA Ports .................................................................................................................................... 21-6
Clock DOMAIN..................................................................................................................................... 21-7
Frame Memory Hirerarchy ................................................................................................................... 21-8
Memory Storing Method....................................................................................................................... 21-9
Timing Diagram for Register Setting.................................................................................................... 21-10
Timing Diagram for Last IRQ ............................................................................................................... 21-11
Software Interface......................................................................................................................................... 21-11
xiv S3C24A0A MICROPROCESSOR
Table of Contents (Continued)
Chapter 21 Camera Interface
Camera Interface Special Registers .............................................................................................................21-12
Source Format Register .......................................................................................................................21-12
Window Option Register.......................................................................................................................21-13
Global Control Register ........................................................................................................................21-14
Y1 Start Address Register ....................................................................................................................21-14
Y2 Start Address Register ....................................................................................................................21-14
Y3 Start Address Register ....................................................................................................................21-15
Y4 Start Address Register ....................................................................................................................21-15
CB1 Start Address Register .................................................................................................................21-15
CB2 Start Address Register .................................................................................................................21-15
CB3 Start Address Register .................................................................................................................21-16
CB4 Start Address Register .................................................................................................................21-16
CR1 Start Address Register .................................................................................................................21-16
CR2 Start Address Register .................................................................................................................21-16
CR3 Start Address Register .................................................................................................................21-17
CR4 Start Address Register .................................................................................................................21-17
Codec Target Format Register .............................................................................................................21-18
Codec DMA Control Register ...............................................................................................................21-19
Register Setting Guide for Codec Scaler and Preview Scaler .............................................................21-19
Codec Pre-Scaler Control Register 1 ...................................................................................................21-22
Codec Pre-Scaler Control Register 2 ...................................................................................................21-22
Codec Main-Scaler Control Register....................................................................................................21-22
Codec DMA Target Area Register........................................................................................................21-23
Codec Status Register..........................................................................................................................21-23
RGB1 Start Address Register...............................................................................................................21-24
RGB2 Start Address Register...............................................................................................................21-24
RGB3 Start Address Register...............................................................................................................21-24
RGB4 Start Address Register...............................................................................................................21-24
Preview Target Format Register...........................................................................................................21-25
Preview DMA Control Register.............................................................................................................21-25
Preview Pre-Scaler Control Register 1.................................................................................................21-26
Preview Pre-Scaler Control Register 2.................................................................................................21-26
Preview Main-Scaler Control Register .................................................................................................21-26
Preview DMA Target Area Register .....................................................................................................21-27
Preview Status Register .......................................................................................................................21-27
Image Capture Enable Register ...........................................................................................................21-27
(Continued)
S3C24A0A MICROPROCESSOR xv
Table of Contents (Continued)
Chapter 22 MPEG-4 Video Codec
Overview....................................................................................................................................................... 22-1
Feature................................................................................................................................................. 22-1
Block Diagram...................................................................................................................................... 22-2
Chapter 23 MPEG-4 Motion Estimation
Overview....................................................................................................................................................... 23-1
Feature................................................................................................................................................. 23-1
MPEG-4 Motion Estimation Operation ......................................................................................................... 23-2
Block Diagram...................................................................................................................................... 23-2
Operation Flow..................................................................................................................................... 23-3
Result Data .......................................................................................................................................... 23-4
MPEG-4 Motion Estimation Special Registers ............................................................................................. 23-5
Current Frame Start Address Register (ME_CFSA)............................................................................ 23-5
Previous Frame Start Address Register (ME_PFSA).......................................................................... 23-5
Motion Vector Start Address Register (ME_MVSA) ............................................................................ 23-5
Command Register (ME_CMND) ........................................................................................................ 23-6
Status & S/W Reset Register (ME_STAT_SWR) ................................................................................ 23-7
Configuration Register (ME_CNFG) .................................................................................................... 23-8
Image Format Register (ME_IMGFMT) ............................................................................................... 23-8
xvi S3C24A0A MICROPROCESSOR
Table of Contents (Continued)
Chapter 24 MPEG-4 Motion Compensation
Overview........................................................................................................................................................24-1
Feature .................................................................................................................................................24-1
MPEG-4 Motion Compensation Operation ...................................................................................................24-2
Block Diagram ......................................................................................................................................24-2
Operation Flow .....................................................................................................................................24-3
Configuration of QCIF/CIF Frame ........................................................................................................24-4
MPEG-4 Motion Compensation Special Registers .......................................................................................24-6
Previous Frame Y Start Address Register for the Encoder (MC_PFYSA_ENC) .................................24-6
MCED Frame Y Start Address Register for the Encoder (MC_MFYSA_ENC)....................................24-6
Previous Frame Y Start Address Register for the Decoder (MC_PFYSA_DEC).................................24-6
MCED Frame Y Start Address Register for the Decoder (MC_MFYSA_DEC)....................................24-6
Previous Frame Cb Start Address Register for the Encoder (MC_PFCbSA_ENC) ............................24-7
Previous Frame Cr Start Address Register for the Encoder (MC_PFCrSA_ENC) ..............................24-7
MCED Frame Cb Start Address Register for the Encoder (MC_MFCbSA_ENC) ...............................24-7
MCED Frame Cr Start Address Register for the Encoder (MC_MFCrSA_ENC).................................24-7
Previous Frame Cb Start Address Register for the Decoder (MC_PFCbSA_DEC) ............................24-8
Previous Frame Cr Start Address Register for the Decoder (MC_PFCrSA_DEC)..............................24-8
MCED Frame Cb Start Address Register for the Decoder (MC_MFCbSA_DEC) ...............................24-8
MCED Frame Cr Start Address Register for the Decoder (MC_MFCrSA_DEC).................................24-8
Motion Vector Start Address Register for the Encoder (MC_MVSA_ENC) .........................................24-9
Motion Vector Start Address Register for the Decoder (MC_MVSA_DEC) .........................................24-9
Command Register (MC_CMND).........................................................................................................24-10
Status & S/W Reset Register (MC_STAT_SWR).................................................................................24-11
Configuration Register (MC_CNFG) ....................................................................................................24-12
Image Format Register (MC_IMGFMT) ...............................................................................................24-12
S3C24A0A MICROPROCESSOR xvii
Table of Contents (Continued)
Chapter 25 MPEG-4 DCTQ
Overview....................................................................................................................................................... 25-1
Features ............................................................................................................................................... 25-2
Timing Diagram.................................................................................................................................... 25-2
Separated Clock Domain ..................................................................................................................... 25-3
DCT...................................................................................................................................................... 25-3
IDCT..................................................................................................................................................... 25-3
Quantisation ......................................................................................................................................... 25-4
DEQuantisation.................................................................................................................................... 25-4
Frame Memory Map............................................................................................................................. 25-5
Q-Information ....................................................................................................................................... 25-6
Bit Format............................................................................................................................................. 25-7
Transposed Coefficeint Output ............................................................................................................ 25-8
Software Interface......................................................................................................................................... 25-8
MPEG-4 DCTQ Special Registers................................................................................................................ 25-9
Current Frame Y Start Address Register............................................................................................. 25-9
Current Frame Cb Start Address Register........................................................................................... 25-9
Current Frame Cr Start Address Register ........................................................................................... 25-9
Reference Frame Y Start Address Register ........................................................................................ 25-10
Reference Frame Cb Start Address Register ...................................................................................... 25-10
Reference Frame Cr Start Address Register....................................................................................... 25-10
Dctqed Frame Y Start Address Register ............................................................................................. 25-10
Dctqed Frame Cb Start Address Register ........................................................................................... 25-11
Dctqed Frame Cr Start Address Register ............................................................................................ 25-11
Quantisation Factor Start Address Register ........................................................................................ 25-11
Image Size Register............................................................................................................................. 25-11
SHQ Register ....................................................................................................................................... 25-12
Control Register ................................................................................................................................... 25-13
Chapter 26 VLX
Overview....................................................................................................................................................... 26-1
Feature................................................................................................................................................. 26-1
MPEG-4 VLX (Variable Length Coding, Decoding) Operation..................................................................... 26-2
MPEG-4 VLX (Variable Length Coding, Decoding) Operation..................................................................... 26-2
VLC ...................................................................................................................................................... 26-2
Entropy Coder ...................................................................................................................................... 26-4
VLD ...................................................................................................................................................... 26-6
VLX (VLC and VLD) Special Registers ........................................................................................................ 26-10
VLX Common SFR .............................................................................................................................. 26-10
Frame Start Addr.................................................................................................................................. 26-11
VLX Control Register (VLX_CON)....................................................................................................... 26-12
VLD Control Register (VLD_CON) ...................................................................................................... 26-13
VLX Output Register 1 (VLX_CON 1) – Read Only ............................................................................ 26-14
VLX Output Register 2 (VLX_CON 2) – Read Only ............................................................................ 26-14
xviii S3C24A0A MICROPROCESSOR
Table of Contents (Continued)
Chapter 27 Post Processor
Overview........................................................................................................................................................27-1
Overall Features ...................................................................................................................................27-2
A Source and Destination Image Data Format .............................................................................................27-3
Image Size and Scale Ratio..........................................................................................................................27-6
DMA Operation of Source and Destination Image........................................................................................27-8
Starting and Terminating of Post Processor .................................................................................................27-11
Register File Lists..........................................................................................................................................27-12
Pre-Scale Image Size Register ............................................................................................................27-13
Source Image Size Register.................................................................................................................27-14
Destination Image Size Register ..........................................................................................................27-15
DMA Start Address Register ................................................................................................................27-15
DMA End Address Register..................................................................................................................27-16
Offset Register......................................................................................................................................27-16
Chapter 28 LCD Controller
Overview........................................................................................................................................................28-1
Features................................................................................................................................................28-1
External Interface Signal ......................................................................................................................28-2
Block Diagram ......................................................................................................................................28-3
Timing Controller Operation ..........................................................................................................................28-4
Video Operation ............................................................................................................................................28-5
OSD (On-Screen Display): Overlay......................................................................................................28-5
Color-Key Function...............................................................................................................................28-6
Dual Buffer............................................................................................................................................28-7
256 Palette Usage (TFT) ......................................................................................................................28-12
Virtual Display.......................................................................................................................................28-15
Register Description ......................................................................................................................................28-16
Memory Map.........................................................................................................................................28-16
S3C24A0A MICROPROCESSOR xix
Table of Contents (Continued)
Chapter 29 Key PAD I/F
Overview....................................................................................................................................................... 29-1
Keypad Control Register .............................................................................................................................. 29-2
Keypad Control Registers (KEYDAT, KEYPUP) ................................................................................. 29-2
Keypad Interrupt Control Register ....................................................................................................... 29-2
Debouncing Filter................................................................................................................................. 29-3
Keypad Filter Control Register ( KEYFLT ).......................................................................................... 29-3
Keypad Manual Scan Control Register (YMAN).................................................................................. 29-4
Chapter 30 ADC & Touch Screen Interface
Overview....................................................................................................................................................... 30-1
Features ............................................................................................................................................... 30-1
ADC & Touch Screen Interface Operation ................................................................................................... 30-2
Block Diagram...................................................................................................................................... 30-2
Example for Touch Screen .................................................................................................................. 30-3
Function Descriptions .......................................................................................................................... 30-4
Function Descriptions .......................................................................................................................... 30-4
ADC and Touch Screen Interface Special Registers ................................................................................... 30-7
ADC Control Register (ADCCON) ....................................................................................................... 30-7
ADC Touch Screen Control Register (ADCTSC) ................................................................................ 30-8
ADC Start Delay Register (ADCDLY) .................................................................................................. 30-9
ADC Conversion Data Register (ADCDAX) ........................................................................................ 30-10
ADC Conversion Data Register (ADCDAY) ........................................................................................ 30-11
xx S3C24A0A MICROPROCESSOR
Table of Contents (Continued)
Chapter 31 Secure Digital Interface
Overview........................................................................................................................................................31-1
Feature .................................................................................................................................................31-1
Block Diagram ......................................................................................................................................31-2
SDI Operation................................................................................................................................................31-3
SDIO Operation.............................................................................................................................................31-4
SDI Special Registers ...................................................................................................................................31-5
SDI Control Register (SDICON) ...........................................................................................................31-5
SDI Baud Rate Prescaler Register (SDIPRE) ......................................................................................31-6
SDI Command Argument Register (SDICARG) ...................................................................................31-6
SDI Command Control Register (SDICCON)....................................................................................... 31-6
SDI Command Status Register (SDICSTA) .........................................................................................31-7
SDI Response Register0 (SDIRSP0) ...................................................................................................31-7
SDI Response Register1 (SDIRSP1) ...................................................................................................31-7
SDI Response Register2 (SDIRSP2) ...................................................................................................31-8
SDI Response Register3 (SDIRSP3) ...................................................................................................31-8
SDI Data / Busy Timer Register (SDIDTIMER) .................................................................................... 31-8
SDI Block Size Register (SDIBSIZE)....................................................................................................31-8
SDI Data Control Register (SDIDCON)................................................................................................31-9
SDI Data Remain Counter Register (SDIDCNT)..................................................................................31-10
SDI Data Status Register (SDIDSTA) ..................................................................................................31-11
SDI FIFO Status Register (SDIFSTA) ..................................................................................................31-12
SDI Interrupt Mask Register (SDIIMSK)...............................................................................................31-13
SDI Data Register (SDIDATn) ..............................................................................................................31-14
Chapter 32 Memory Stick
Overview........................................................................................................................................................32-1
Features................................................................................................................................................32-1
Memory Stick Protocol..........................................................................................................................32-2
Mandatory Hardware Configuration .....................................................................................................32-2
Host Block Pin Description ...................................................................................................................32-3
Memory Stick Special Registers ...................................................................................................................32-4
Prescaler Control (MSPRE) Register ...................................................................................................32-4
FIFO Interrupt Control (MSFINTCON) Register ...................................................................................32-4
Transfer Protocol Command (TP_CMD) Register ...............................................................................32-5
Control and Status (CTRLSTA) Register .............................................................................................32-6
Data FIFO (DAT_FIFO) Register..........................................................................................................32-7
Interrupt Control and Status (INTCTRLSTA) Register .........................................................................32-7
INS Port Control (INSCON) Register ...................................................................................................32-8
Auto Command/POL Control (ACMD_CON) Register .........................................................................32-8
Auto Transfer Protocol Command (ATP_CMD) Register.....................................................................32-8
S3C24A0A MICROPROCESSOR xxi
Table of Contents (Continued)
Chapter 33 Clock & Power Management
Overview....................................................................................................................................................... 33-1
Function Description ............................................................................................................................ 33-2
Power Saving Modes ........................................................................................................................... 33-9
Clock Generator & Power Management Special Register ........................................................................... 33-13
Lock Time Count Register (LOCKTIME) ............................................................................................. 33-13
X-Tal Oscillation Wait Register (XTALWSET) ..................................................................................... 33-13
Pll Control Register (MPLLCON, UPLLCON)...................................................................................... 33-14
Clock Control Register (CLKCON) ...................................................................................................... 33-15
Clock Source Control Register (CLKSRC) .......................................................................................... 33-17
Clock Divider Control Register (CLKDIVN) ......................................................................................... 33-18
Power Management Control Register (PWRMAN).............................................................................. 33-18
Softreset Control Register (SOFTRESET) .......................................................................................... 33-19
Chapter 34 Mechanical Data
Package Dimensions.................................................................................................................................... 34-1
xxii S3C24A0A MICROPROCESSOR
List of Figures
Figure Title Page Number Number
1-1 An Overall Block Diagram of the S3C24A0A ..........................................................................1-8
1-2 337-Pin FBGA Pin Assignment ...............................................................................................1-9
1-3 Address map............................................................................................................................1-38
2-1 SROM Controller Address Mapping ........................................................................................2-1
2-2 SROM Controller Block Diagram.............................................................................................2-2
2-3 Memory Interface Block Diagram ............................................................................................2-3
2-4 XrWAITn Pin Operation ...........................................................................................................2-4
2-5 Programmable Access Cycle ..................................................................................................2-5
3-1 Memory Interface with 16-bit SDRAM (4Mx16, 4banks) ......................................................... 3-4
3-2 Memory Interface with 16-bit SDRAM (4Mx16 × 2ea, 4banks) ...............................................3-4
3-3 SDRAM Timing Diagram .........................................................................................................3-5
4-1 NAND Flash Controller Block Diagram ...................................................................................4-3
4-2 NAND Flash Controller Boot Loader Block Diagram...............................................................4-4
4-3 NAND Flash Controller Operation Mode Block Diagram ........................................................4-5
4-4 Auto Mode Timing Diagram (TACLS = 1, TWRPH0 = 0, TWRPH1 = 0) ................................4-5
4-5 NAND Flash Controller Auto Load Timing Diagram (TWRPH0 = 0, TWRPH1 = 0) ...............4-6
4-6 NAND Flash Controller Auto Store Timing Diagram (TWRPH0 = 0, TWRPH1 = 0)...............4-7
4-7 8-bit NAND Flash Memory Interface .......................................................................................4-11
4-8 Two 8-bit NAND Flash Memory Interface................................................................................4-11
4-9 16-bit NAND Flash Memory Interface .....................................................................................4-12
5-1 Configuration of MATRIX and Memory Sub-System...............................................................5-1
6-1 Priority Generating Block.........................................................................................................6-4
7-1 16-bit PWM Timer Block Diagram ...........................................................................................7-2
7-2 Timer operations......................................................................................................................7-3
7-3 Example of Double Buffering Feature .....................................................................................7-4
7-4 Example of a Timer Operation.................................................................................................7-5
7-5 Example of PWM .....................................................................................................................7-6
7-6 Inverter On/Off .........................................................................................................................7-7
7-7 The Wave Form When a Dead Zone Feature is Enabled .......................................................7-8
7-8 The Timer4 DMA Mode Operation ..........................................................................................7-9
S3C24A0A MICROPROCESSOR xxiii
List of Figures (Continued)
Figure Title Page Number Number
8-1 Watchdog Timer Block Diagram ............................................................................................. 8-2
9-1 Basic DMA Timing Diagram.................................................................................................... 9-3
9-2 Demand/Handshake Mode Comparison ................................................................................ 9-3
9-3 Burst 4 Transfer Size .............................................................................................................. 9-4
9-4 Single service, Demand Mode, Single Transfer Size ............................................................. 9-5
9-5 Single service, Handshake Mode, Single Transfer Size ........................................................ 9-5
9-6 Whole service, Handshake Mode, Single Transfer Size ........................................................ 9-5
10-1 Real Time Clock Block Diagram ............................................................................................. 10-2
11-1 UART Block Diagram (with FIFO)........................................................................................... 11-2
11-2 UART AFC Interface ............................................................................................................... 11-3
11-3 Example showing UART Receiving 5 Characters with 2 Errors............................................. 11-6
11-4 IrDA Function Block Diagram ................................................................................................. 11-8
11-5 Serial I/O Frame Timing Diagram (Normal UART) ................................................................. 11-9
11-6 Infrared Transmit Mode Frame Timing Diagram .................................................................... 11-9
11-7 Infrared Receive Mode Frame Timing Diagram ..................................................................... 11-9
11-8 nCTS and Delta CTS Timing Diagram.................................................................................... 11-18
12-1 Block Diagram......................................................................................................................... 12-2
12-2 Fir Modulation Process ........................................................................................................... 12-4
12-3 Fir Demodulation Process ...................................................................................................... 12-5
12-4 Pulse Modulation in MIR Mode............................................................................................... 12-6
12-5 Mir Modulation Process .......................................................................................................... 12-7
12-6 Mir Demodulation Process...................................................................................................... 12-8
12-7 General Program Flowchart.................................................................................................... 12-9
13-1 IIC-Bus Block Diagram............................................................................................................ 13-2
13-2 Start and Stop Condition......................................................................................................... 13-3
13-3 IIC-Bus Interface Data Format................................................................................................ 13-4
13-4 Data Transfer on the IIC-Bus.................................................................................................. 13-5
13-5 Acknowledge on the IIC-Bus .................................................................................................. 13-5
13-6 Operations for Master / Transmitter Mode.............................................................................. 13-7
13-7 Operations for Master / Receiver Mode.................................................................................. 13-8
13-8 Operations for Slave / Transmitter Mode................................................................................ 13-9
13-9 Operations for Slave / Receiver Mode.................................................................................... 13-10
xxiv S3C24A0A MICROPROCESSOR
List of Figures (Continued)
Figure Title Page Number Number
14-1 IIS-Bus Block Diagram ...........................................................................................................14-1
14-2 IIS-Bus and MSB(Left)-justified Data Interface Formats ........................................................14-4
15-1 SPI Block Diagram ..................................................................................................................15-2
15-2 SPI Transfer Format ................................................................................................................15-4
16-1 AC97 Block Diagram ...............................................................................................................16-2
16-2 Internal Data Path....................................................................................................................16-3
16-3 AC97 Operation Flow Chart ....................................................................................................16-4
16-4 Bi-directional AC-link Frame with Slot Assignments ...............................................................16-5
16-5 AC-link Output Frame..............................................................................................................16-6
16-6 AC-link Input Frame.................................................................................................................16-6
16-7 AC97 Powerdown Timing ........................................................................................................16-7
16-8 AC97 Power down/Power up Flow..........................................................................................16-8
17-1 USB Host Controller Block Diagram........................................................................................17-1
18-1 USB Device Block Diagram.....................................................................................................18-2
19-1 Modem Interface Overview......................................................................................................19-1
19-2 Modem Interface Address Mapping ........................................................................................19-3
19-3 Modem Interface Write Timing Diagram..................................................................................19-4
19-4 Modem Interface Read Timing Diagram .................................................................................19-5
21-1 Camera Interface Overview.....................................................................................................21-1
21-2 ITU-R BT 601 Input Timing Diagram.......................................................................................21-3
21-3 ITU-R BT 656 Input Timing Diagram.......................................................................................21-3
21-4 IO Connection Guide ...............................................................................................................21-5
21-5 Two DMA Ports........................................................................................................................21-6
21-6 Clock Generation.....................................................................................................................21-7
21-7 Ping-pong Memory Hierarchy..................................................................................................21-8
21-8 Memory Storing Style ..............................................................................................................21-9
21-9 Timing Diagram for Register Setting .......................................................................................21-10
21-10 Timing Diagram for Last IRQ...................................................................................................21-11
21-11 Window Offset Scheme ...........................................................................................................21-13
21-12 Image Mirror and Rotation.......................................................................................................21-18
21-13 Scaling scheme .......................................................................................................................21-20
S3C24A0A MICROPROCESSOR xxv
List of Figures (Continued)
Figure Title Page Number Number
22-1 MPEG-4 Video CODEC Block Diagram ................................................................................. 22-2
23-1 MPEG-4 Motion Estimation Block Diagram ............................................................................ 23-2
23-2 Memory Map of Y (Luminance) Image for Current and Previous Frames ............................. 23-3
23-3 Motion Estimation Result Data ............................................................................................... 23-4
24-1 MPEG-4 Motion Compensation Block Diagram ..................................................................... 24-2
24-2 Y/Cb/Cr Image Memory Map of Original and Padded Frames............................................... 24-3
24-3 Y/Cb/Cr Configuration for QCIF/CIF Original Frame .............................................................. 24-4
24-4 Y/Cb/Cr Configuration for QCIF/CIF Padded Frame .............................................................. 24-5
24-5 Motion Vector Configuration for QCIF/CIF Image .................................................................. 24-5
25-1 DCTQ Overview...................................................................................................................... 25-1
25-2 DCTQ Operation Timing Diagram .......................................................................................... 25-2
25-3 DCTQ clock domain................................................................................................................ 25-3
25-4 DCTQ Frame Memory Map in QCIF Case ............................................................................. 25-5
25-5 Q-Information Structure .......................................................................................................... 25-6
25-6 DCTQ Bit-Format .................................................................................................................... 25-7
25-7 Transposed Coefficient Output for MB ................................................................................... 25-8
26-1 VLX Top Interface Block Diagram .......................................................................................... 26-2
26-2 ZigZag Scanning Method........................................................................................................ 26-3
26-3 Previous Neighboring Blocks Used in DC Prediction ............................................................. 26-4
26-4 VLC output bit stream format .................................................................................................. 26-5
26-5 VLC Start, Busy, And Interrupt Signal Timing Diagram.......................................................... 26-6
26-6 VLD Bit Stream H/W and S/W Interface Format..................................................................... 26-6
26-7 External Memory Amount in VLD Mode. ................................................................................ 26-7
26-8 VLD Output Coefficient Format............................................................................................... 26-7
26-9 MSB is First Bit Value in Output Bit Stream............................................................................ 26-8
26-10 VLD Flow Chart and S/W and H/W Processing Partition ....................................................... 26-9
26-11 Start Signal, Busy Signal and Interrupt Signal in VLD Mode.................................................. 26-9
xxvi S3C24A0A MICROPROCESSOR
List of Figures (Continued)
Figure Title Page Number Number
27-1 Block Diagram of Post Processor............................................................................................27-1
27-2 Data Format Stored in External Memory.................................................................................27-4
27-3 Byte and Half-Word Organization............................................................................................27-4
27-4 Sampling Position of YCbCr420 and YCbCr422 Format
(X: Luma Sample and Ο: Chroma Sample).............................................................................27-5
27-5 Source Destination Image Size ...............................................................................................27-6
27-6 Start and End Address Set According to Memory Allocation Type.........................................27-8
27-7 Offset for (a) Source Image for Zoom In/Out Operation and
(b) Destination Image for PIP Applications..............................................................................27-10
27-8 Start and Termination of the Operation of Post Processor .....................................................27-11
28-1 LCD Controller Block Diagram ................................................................................................28-3
28-2 Clock Selection ........................................................................................................................28-4
28-3 OSD Procedure .......................................................................................................................28-6
28-4 Blending and Color Key Function of OSD ............................................................................... 28-7
28-5 16BPP Display Types..............................................................................................................28-13
28-6 TFT LCD Timing Example .......................................................................................................28-14
28-7 Example of Scrolling in Virtual Display....................................................................................28-15
29-1 Key Matrix Interface Guide ......................................................................................................29-1
30-1 ADC and Touch Screen Interface Functional Block Diagram .................................................30-2
30-2 Example of ADC and Touch Screen Interface ........................................................................30-3
31-1 SDI Block Diagram ..................................................................................................................31-2
32-1 Memory Stick Write Packet .....................................................................................................32-2
32-2 Memory Stick Read Packet .....................................................................................................32-2
33-1 Clock Generator Block Diagram..............................................................................................33-2
33-2 PLL (Phase-Locked Loop) Block Diagram ..............................................................................33-3
33-3 Power-On Reset Sequence.....................................................................................................33-5
33-4 The Case that Changes Slow Clock by Setting PMS Value ...................................................33-6
33-5 The Clock Distribution Block Diagram.....................................................................................33-8
33-6 Entering STOP Mode and Exiting STOP mode (Wake-up).....................................................33-10
33-7 Power mode state diagram......................................................................................................33-11
34-1 337-FBGA-1313 Package Dimension 1 (Top View)................................................................34-1
34-2 337-FBGA-1313 Package Dimension 2 (Bottom View) ..........................................................34-2
S3C24A0A MICROPROCESSOR xxvii
List of Tables
Table Title Page Number Number
1-1 337-Pin FBGA Pin Assignments – Pin Number Order ............................................................ 1-10
1-2 337-Pin FBGA Pin Assignments..............................................................................................1-14
3-1 Supported SDRAM Configuration ...........................................................................................3-2
4-1 Advance NAND Flash Controller Configuration (word means 16-bit in this table)..................4-2
4-2 2K Byte Main Area ECC Parity Code Assignment Table ........................................................4-9
4-3 16 Byte SPARE AREA ECC Parity Code Assignment Table..................................................4-9
9-1 DMA Request Sources for Each Channel...............................................................................9-1
11-1 Interrupts in Connection with FIFO..........................................................................................11-5
14-1 CODEC Clock (IISCDCLK = 256 or 384fs) .............................................................................14-4
14-2 Usable Serial Bit Clock Frequency (IISCLK = 16 or 32 or 48fs) .............................................14-4
16-1 AC97 Block Diagram ...............................................................................................................16-2
16-2 Internal Data Path....................................................................................................................16-3
16-3 AC97 Operation Flow Chart ....................................................................................................16-4
16-4 Bi-directional AC-link Frame with Slot Assignments ...............................................................16-5
16-5 AC-link Output Frame..............................................................................................................16-6
16-6 AC-link Input Frame.................................................................................................................16-6
16-7 AC97 Powerdown Timing ........................................................................................................16-7
16-8 AC97 Power down/Power up Flow..........................................................................................16-8
19-1 Modem Interface Signal Description .......................................................................................19-2
19-2 Interrupt Ports And Interrupt-Request/Clear Conditions .........................................................19-2
19-3 Modem Interface Write Timing ................................................................................................19-4
19-4 Modem Interface Read Timing ................................................................................................19-5
20-1 S3C24A0A Port Configuration Overview.................................................................................20-2
21-1 Camera Interface Signal Description.......................................................................................21-2
21-2 Video Timing Reference Codes of ITU-656 Format................................................................21-4
S3C24A0A MICROPROCESSOR xxix
List of Tables (Continued)
Table Title Page Number Number
23-1 Example of Sizes of Y Image and Offset for QCIF and CIF ................................................... 23-3
24-1 Sizes of Y/Cb/Cr Image and Offset for QCIF and CIF............................................................ 24-3
27-1 Mode Configuration for Video/Graphic Source Format and the
Corresponding Data Format ................................................................................................... 27-3
28-1 Relation Between XvVCLK and CLKVAL (TFT, Freq. of Video Clock Source = 60 MHz) ..... 28-5
28-2 6:6:6 Palette Data Format....................................................................................................... 28-12
28-3 5:6:5 Palette Data Format....................................................................................................... 28-12
28-4 5:5:5:1 Palette Data Format.................................................................................................... 28-12
30-1 Condition of Touch Screen Panel Pads in Separate X/Y Position Conversion Mode ............ 30-4
30-2 Condition of Touch Screen Panel Pads in Auto (Sequential) X/Y Position Conversion Mode 30-5
30-3 Condition of Touch Screen Panel Pads in Waiting for Interrupt Mode ................................... 30-5
33-1 Clock Source Selection for the Internal PLLs and Clock Generation Logic ........................... 33-2
33-2 Recommended operation conditions ...................................................................................... 33-4
33-3 DC Electrical Characteristics .................................................................................................. 33-4
33-4 AC Electrical Characteristics .................................................................................................. 33-4
33-5 The Status of PLL and ARMCLK After Wake-Up ................................................................... 33-11
33-6 Power Saving Mode Entering/Exiting condition...................................................................... 33-12
33-7 PLL value selection table ........................................................................................................ 33-14
xxx S3C24A0A MICROPROCESSOR
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
1 PRODUCT OVERVIEW
ARCHITECTURAL OVERVIEW
The S3C24A0A is a 16/32-bit RISC microprocessor, designed to provide a cost-effective, low power, and high performance micro-controller solution for mobile phones and general applications. To provide a sufficient H/W performance for the 2.5G & 3G communication services, the S3C24A0A adopts dual-32-bit bus architecture and includes many powerful hardware accelerators for the motion video processing, serial communications, and etc. For the real time video conferencing, an optimized MPEG4 H/W Encoder/Decoder is integrated.
To reduce total system cost and enhance overall functionality, the S3C24A0A also includes following components: separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD controller (TFT), Camera Interface, MPEG-4 ME, MC, DCTQ, NAND Flash Boot loader, System Manager (power management & etc.), SDRAM controller, 2-ch UART, 4-ch DMA, 4-ch Timers, General I/O Ports, IIC­BUS interface, USB Host, SD Host & Multi-Media Card Interface, Memory Stick Interface, PLL for clock generation & etc. The S3C24A0A can be used as a most powerful Application Processor for mobiles phones. For this application, the S3C24A0A has a Modem Interface to communicate with various Modem Chips.
The S3C24A0A is developed using an ARM926EJ-S core, advanced 0.13um CMOS standard cells and memory compliers. Its low-power, simple, elegant and fully static-design scheme is particularly suitable for cost-sensitive and power-sensitive applications. Also, the S3C24A0A adopts a de-facto standard bus architecture – the AMBA (Advanced Microcontroller Bus Architecture).
One of the outstanding features of the S3C24A0A is it’s CPU core, a 16/32-bit ARM926EJ-S RISC processor designed by ARM, Ltd. The ARM926EJ-S is a single chip MCU and Java enabled microprocessor. The ARM926EJ-S also implements the MMU, the AMBA BUS, and the Harvard cache architecture with separate 16KB instruction and 16KB data caches, each cache with an 8-word line length.
By providing a complete set of common system peripherals, the S3C24A0A minimizes overall system costs and eliminates the need to configure additional components.
Preliminary product information describe products that are in development, 1-1
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
FEATURES
This section will explain the features of the S3C24A0A. Figure 1-1 is an overall block diagram of the S3C24A0A.
MICROPROCESSOR AND OVERALL ARCHITECTURE
SoC (System-on-Chip) for mobile phones and general embedded applications.
16/32-Bit RISC architecture and powerful instruction set with ARM926EJ-S CPU core.
ARM’s Jazelle Java technology enhanced ARM architecture MMU to support WinCE, Symbian and Linux
Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main
memory bandwidth and latency on performance
4 way set-associative cache with I-Cache (16KB) and D-Cache (16KB).
8-words per line with one valid bit and two dirty bits per line
Pseudo random or round robin replacement algorithm.
Write through or write back cache operation to update the main memory.
The write buffer can hold 16 words of data and four addresses.
ARM926EJ-S core supports the ARM debug architecture
Internal AMBA (Advanced Microcontroller Bus Architecture) (AMBA2.0, AHB/APB)
Dual AHB bus for high-performance processing (AHB-I & AHB-S)
MEMORY SUBSYSTEM
High bandwidth Memory subsystem with two access channels (accesses from two AHB buses) and three- channel memory ports
Double the bandwidth with the simultaneous access capability
ROM/SRAM/NOR-Flash/NAND-Flash channel
One SDRAM channels
Up to 1GB Address space
Low-power SDRAM interface support : Mobile SDRAM function
– DS: Driver Strength Control – TCSR: Temperature Compensated Self-Refresh Control – PASR: Partial Array Self-Refresh Control
NAND Flash Boot Loader with the ECC circuitry to support booting from NAND Flash – 4KB Stepping Stone – Support 1G, 2G bit NAND Flash
1-2 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
GENERAL PERIPHERALS
Interrupt Controller – 61 Interrupt sources (1 Watch Dog Timer, 5 Timer, 6 UART, 18 External Interrupts, 4 DMA, 2 RTC, 3 ADC, 1 I2C, 1 AC97, 1 NAND Flash, 1 IrDA, 1 Memory Stick, 2 SPI, 1 SDI, 2 USB (Host and Device), 1 Keypad, 1 Modem Interface, 2 Camera Interface, 4 MPEG, 2 LCD, 1 Battery Fault, 1 Post) – Level/Edge mode on external interrupt source. – Programmable polarity of edge and level. – Supports FIQ (Fast Interrupt request) for very urgent interrupt request.
Timer with PWM (Pulse Width Modulation) – 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal timer with DMA-based or interrupt-based operation – Programmable duty cycle, frequency, and polarity – Dead-zone generation. – Support external clock source.
16-bit Watchdog Timer. – Interrupt request or system reset at time-out.
4-ch DMA controller. – Support memory to memory, IO to memory, memory to IO, and IO to IO – Burst transfer mode to enhance the transfer rate.
RTC (Real Time Clock) – Full clock feature: msec, sec, min, hour, day, date, week, month, year. – 32.768 KHz operation – Alarm interrupt – Time-tick interrupt
SERIAL COMMUNICATION
UART – 2-channel UART with DMA-based or interrupt-based operation – Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive – Supports external clock for the UART operation (XuCLK) – Programmable baud rate – Supports IrDA 1.0 – Loop back mode for testing – Each channel has internal 64-byte Tx FIFO and 64-byte Rx FIFO
IrDA – Support IrDA 1.1 (1.152Mbps and 4Mbps) – Support FIFO operation in the MIR and FIR mode – Configurable FIFO Size (16-byte or 64-byte) – Support Back-to-Back Transactions – Support Software Selection Temic-IBM or HP Transceiver – Support Little-endian access
IIC-Bus Interface – 1-ch Multi-Master IIC-Bus – Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in the standard mode
Preliminary product information describe products that are in development, 1-3
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
IIS-Bus Interface – 1-ch IIS-bus for the audio-codec interface with DMA-based operation – Serial, 8/16-bit per channel data transfers – 128 Bytes (64-Byte + 64-Byte) FIFO for receive/transmit – Supports IIS format and MSB-justified data format
SPI Interface – 2-ch Serial Peripheral Interface Protocol version 2.11 compatible – 2x8 bits Shift register for receive/transmit. – DMA-based or interrupt-based operation.
AC97 Audio-CODEC Interface – 48kHz 16-bit sampling – 1-ch stereo PCM inputs / 1-ch stereo PCM outputs / 1-ch MIC input
USB Host – 2-port USB Host – Complies with OHCI Rev. 1.0 – Compatible with the USB Specification version 1.1
USB Device – 1-port USB Device – 5 End-points for USB Device – Compatible with the USB Specification version 1.1
PARALLEL COMMUNICATION
Modem Chip Interface – 8-bit Asynchronous SRAM interface-style interface – On-chip 2KB dual-ported SRAM buffer – Interrupt Request for Data Exchange – Programmable Interrupt Port Address
32-bit GPIO – Fully configurable 32-bit GPIO
IMAGE AND VIDEO PROCESSING
Camera Inteface – ITU601/ITU656 YCbCr 4:2:2 8/16-bit mode – Image down scaling capability for variable applications – Digital Zoom-In – Image X, Y-flip, 180 rotation – Input Image Window Cut – Two master for dedicated DMA operation – Programmable burst length for DMA operation – Programmable polarity of video sync signals – Wide horizontal line buffer (maximum 2048 pixel) – Up to 4M pixel resolution support for scaled image (image preview or motion video capturing) and 16M pixel for unscaled image (JPEG) – Format conversion from YCrCb 4:2:2 to 4:2:0 for codec, and to RGB 4:4:4 for preview
1-4 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Hardware Accelerated MPEG4 Video Encoding/Decoding – A AHB Interface – Realtime MPEG-4 Video Encoding & Decoding – Up to Simple Profile at Level 3 (352x288 at 30fps) – Supports H.263 Base Line
MPEG-4 ME (Motion Estimation) – Highly optimized hard-wired engine – Unrestricted Mode and Advanced Prediction Mode (4MV) – Use the advanced MRMCS algorithm – Half-pel search – Programmable Image size up to 2048x2048 – Padding for Macro-block basis – Search Range: [-16, 15.5] – Intra/Inter Mode Decision MC (Motion Compensation)
MC (Motion Compensation) – Highly optimized hard-wired engine – Unrestricted Mode and Advanced Prediction Mode (4MV) – Half-pel search – Programmable Image size up to 2048x2048 – Dedicated DMA – Macroblock-based Pading – Search Range: [-64, 63.5]
DCTQ – DCT/IDCT/Q/IQ operations – AMBA AHB Interface – Support MPEG-4 Simple Profile Level 3 / H.263 Base-Line – Support programmable image size up to 4096x4096 – Macroblock-based processing – Rate Control by Qp Information – Local DMA – Support MPEG-4 Encoding / Decoding – Support JPEG DCT / IDCT Operation – Operation unit : 1MB(MacroBlock) ~ 1 Frame
VLX – VLC/VLD operations – AMBA AHB Interface – Support MPEG4 Simple Profile Level 3/ H.263. Baseline – Macro block-based processing – Dedicated DMA – Only DCTQ coefficient VLC/VLD operation – Only DC prediction operation in VLC
Preliminary product information describe products that are in development, 1-5
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Post Processor – Dedicate DMA with Offset Address – 3 Channel Scaling Pipelines for Video/Graphis Signal – Input Format: YCbCr4:2:0, YCbCr4:2:2, or RGB 16b/24b – Output Format: RGB 16b/24b – Programmable Image Size (Source up to 4096x4096, Destination up to 2048x2048) – Programmable Scale Ratio (Up-scale: up to Max. Destination Size, Down-scale: ~>1/64 in X & Y) – Format Conversion for Video Signal (YCbCr4:2:0 or YCbCr4:2:2) – Color Space Conversion (YCbCr2RGB) – Separate Processing Clock from AHB Interface Clock
DISPLAY CONTROL
TFT LCD Interface – 18-bit Parallel or 6bit*3 Interface – 1/2/4/8-bpp Palletized or 8/16/18-bpp Non-Palletized Color-TFF support – Supports 640x480, 320x240, 176x192 and others – Up to 16 Mbyte virtual screen size – Supports Multiple Virtual Display Screen (Supports Hardware Horizontal/Vertical Scrolling) – Programmable timing control for different display panels – Dual Buffer
OSD (On Screen Display) – Realtime overlay plane multiplexing – Programmable OSD window positioning – Per-pixel alpha blending for 18-bpp OSD images – Fixed alpha-value for 8-/16-/18-bpp OSD image – 56-level alpha blending – 24-bit color key support – Dual buffer
INPUT DEVICES
Keypad Interface – Provides internal debouncing filter – 5-input, 5-output pins for key scan in/out
A/D Converter and Touch Screen Interface – 8-ch multiplexed ADC – Max. 500K samples/sec and 10-bit resolution
1-6 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
STORAGE DEVICES
SD Host – Compatible with SD Memory Card Protocol version 1.0 – Compatible with SDIO Card Protocol version 1.0 – 64 Bytes FIFO for Tx/Rx – DMA based or Interrupt based operation – Compatible with Multimedia Card Protocol version 2.11
Memory Stick Host – Memory Stick version 1.3 compliant
SYSTEM MANAGEMENT
Little Endian format support
System operating clock generation
– Two on-chip PLLs, MPLL & UPLL – MPLL generates the system reference clock, 200MHz@1.3V – UPLL generates clocks for the USB Host/Device, IrDA and Camera
Power Management – Clock-off control for individual components – Various power-down modes are available such as IDLE, STOP and SLEEP – Wake-up by one of external interrupts or by the RTC alarm interrupt, etc.
ELECTRICAL CHARACTERISTICS
Operating Conditions – Supply Voltage for Logic Core: 1.3V ± 0.05V – External Memory Interface: 1.9V / 2.5V / 3.3V – External I/O Interface: 3.3V
Operational Frequency – Max. 200MHz@1.3V
PACKAGE
337-pin FBGA (0.5mm pitch, 13mm x 13mm)
Preliminary product information describe products that are in development, 1-7
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Timer x 5
Watchdog
Timer
USB1.1
Device
Memory
Stick Host
SD Host
UART x 2
I2C
I2S
SPI x 2
GPIO [31:0]
ADC & TSP
AC97
Keypad
RTC
Peripheral Bus
MPEG4
DCTQ/ VLX
ME/ MC
ARM926EJ
JTAG
Controller
LCD
C o ntro ller
Power
Managem ent
& Clock
Controller
Camera
Inte r fa c e
Post
Processor
Mutiple System Bus
Inte rru p t
Controller
NAND
Bootloader
DMA x 4
USB1.1
Host
Memory
C o ntro ller
NAND
FLASH
SDRAM
SROM
IrDA1 .1
Modem
Inte r fa c e
Figure 1-1. An Overall Block Diagram of the S3C24A0A
1-8 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
PIN ASSIGNMENT
#A1
12345678910111213141819 15161720212223
Index Mark
A B C D E F G H J K L M N P R T U V W Y AA AB AC
Bottom View
Figure 1-2. 337-Pin FBGA Pin Assignment
Preliminary product information describe products that are in development, 1-9
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Table 1-1. 337-Pin FBGA Pin Assignments – Pin Number Order
Pin
Number
Pin Name Pin
Number
Pin Name Pin
Number
Pin Name
A01 XCIYDATA[4] B11 XRDATA[1] C21 XRADDR [21] A02 VSSpadIO B12 XRDATA[3] C22 XFNFPS A03 XCICDATA[0] B13 XRDATA[7] C23 XFNFADV A04 XCIYDATA[7] B14 XRADDR[5] D01 XJTDO A05 XCIPCLK B15 XRNWBE[0] D02 XJTDI A06 XVVD[5] B16 XRWEN D03 XVVD[2] A07 XVVD[7] B17 XRCSN[2] D04 XCIRSTN A08 XVVCLK B18 XRDATA[14] D05 XCIYDATA[5] A09 XVDEN B19 XRADDR[11] D06 XCIVSYNC A10 XCICDATA[7] B20 XRADDR[15] D07 XVVD[13] A11 XRDATA[0] B21 XRADDR[22] D08 XVVD[14] A12 XRDATA[5] B22 XFALE D09 XCICDATA[5] A13 XRADDR [3] B23 XFNFACYC D10 XJRTCK A14 XRADDR [7] C01 XJTMS D11 XVVSYNC A15 XRNWBE[1] C02 XJTRSTN D12 XVVD[19] A16 XRDATA[8] C03 XCICLK D13 XVVD[22] A17 XRDATA[13] C04 XCICDATA[1] D14 XRADDR [4] A18 XRADDR [10] C05 XVVD[4] D15 XRADDR [2] A19 XRADDR [16] C06 XCIHREF D16 XRADDR [0] A20 XRADDR [17] C07 XCICDATA[4] D17 XRADDR [14] A21 XRADDR[20] C08 XCICDATA[6] D18 XRADDR [19] A22 XRADDR [23] C09 XVHSYNC D19 XFCLE A23 XFRNB[0] C10 XVVD[20] D20 XRADDR [8] B01 XJTCK C11 XVVD[23] D21 XRADDR [12] B02 XCIYDATA[0] C12 VDDarm D22 XFNFBW B03 XCIYDATA[2] C13 XRDATA[6] D23 XRADDR [25] B04 XCIYDATA[6] C14 XRADDR[1] E01 XGPIO[31] B05 XCICDATA[2] C15 XRADDR [6] E02 X2CSDA B06 XCICDATA[3] C16 XRWAITN E03 X2CSCL B07 XVVD[11] C17 XRCSN[1] E04 XCIYDATA[1] B08 XVVD[15] C18 XRDATA[10] E20 XFRNB[1] B09 XVVD[18] C19 XRDATA[12] E21 XRADDR [24] B10 XVVD[21] C20 XRADDR [9] E22 XPDATA[2]
1-10 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Table 1-1. 337-Pin FBGA Pin Assignments – Pin Number Order (Continued)
Pin
Number
Pin Name Pin
Number
Pin Name Pin
Number
Pin Name
E23 XPDATA[1] J21 VDDlogic M09 VSSpadIO F01 XGPIO[28] J22 XPDQM[3] M10 VDDalive F02 XGPIO[29] J23 XPDATA[8] M11 VSS F03 XGPIO[30] K01 XGPIO[11] M12 VSS F04 XCIYDATA[3] K02 XGPIO[14] M13 VSS F20 XRADDR [18] K03 XGPIO[16] M14 VDDlogic F21 XPDATA[0] K04 XVVD[12] M15 VSSpadSDRAM F22 XPDATA[6] K11 VDDpadIO M20 XPADDR[2] F23 XPDATA[3] K12 VSS M21 XPDATA[15] G01 XGPIO[24] K13 VSSpadFlash M22 XPADDR[1] G02 XGPIO[26] K20 XRDATA[11] M23 XPADDR[3] G03 XGPIO[27] K21 XPDATA[9] N01 X97SYNC G04 XVVD[3] K22 XPDATA[10] N02 X97RESETN G20 XRADDR [13] K23 XPDATA[11] N03 XGPIO[4] G21 XPDATA[5] L01 XGPIO[7] N04 XGPIO[8] G22 XPDQM[0] L02 XGPIO[10] N09 VDDlogic G23 XPDATA[7] L03 XGPIO[12] N10 VDDpadIO H01 XGPIO[20] L04 XGPIO[21] N11 VSS H02 XGPIO[23] L09 VDDarm N12 VSS H03 XGPIO[22] L10 VDDarm N13 VSS H04 XVVD[6] L11 VSS N14 VSSpadSDRAM H20 XPDATA[4] L12 VSS N15 VDDpadSDRAM H21 VDDpadSDRAM L13 VSS N20 XRDATA[9] H22 XPDQM[1] L14 VDDpadFlash N21 XPADDR[4] H23 XPDQM[2] L15 VSSpadSDRAM N22 XPADDR[5]
J01 XGPIO[17] L20 XPDATA[14] N23 XPADDR[6] J02 XGPIO[18] L21 XPDATA[12] P01 XURTSN J03 XGPIO[25] L22 XPDATA[13] P02 X97SDO J04 XVVD[10] L23 XPADDR[0] P03 X97BITCLK J11 VSSpadIO M01 XGPIO[0] P04 XGPIO[5] J12 VSSpadFlash M02 XGPIO[6] P11 VSSpadIO J13 VDDpadFlash M03 VDDpadIO P12 VDDalive
Preliminary product information describe products that are in development, 1-11
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Table 1-1. 337-Pin FBGA Pin Assignments – Pin Number Order (Continued)
Pin
Number
Pin Name Pin
Number
Pin Name Pin
Number
Pin Name
J20 XRDATA[15] M04 XGPIO[19] P13 VSSpadSDRAM P20 XRCSN[0] V03 XGTMODE[3] Y20 VDDpadSDRAM P21 XPDATA[16] V04 XUCLK Y21 XPDATA[25] P22 XPADDR[7] V20 XRDATA[2] Y22 XPDATA[27] P23 XPDATA[18] V21 XPDATA[29] Y23 XPDATA[26] R01 XGTMODE[2] V22 XPWEN AA01 XRTCXTI R02 XURXD V23 XPCASN AA02 XGREFCLKSEL[0] R03 XGPIO[2] W01 XGTMODE[1] AA03 XGPWROFFN R04 XGPIO[15] W02 XSPIMISO AA04 XADCAIN[5] R11 VDDlogic W03 XSPISSIN[0] AA05 XADCAVREF R12
VDDpadModem
W04 X2SCLK AA06 XADCAIN[2] R13 VSSpadSDRAM W20 VDDpadSDRAM AA07 VSSadc R20 XROEN W21 VDDlogic AA08 VDDMpll R21 XPDATA[17] W22 XPCSN[0] AA09 XSRESETN R22 XPDATA[19] W23 XPCSN[1] AA10 XSXTOUT R23 XPSCLK Y01 XSWRESETN AA11 XUSDP[0] T01 X2SCDCLK Y02 XGTMODE[0] AA12 XUSDN[0] T02 XUCTSN Y03 XSPICLK AA13 XMSBS T03 X97SDI Y04 X2SDI AA14 XMIWEN T04 XGPIO[13] Y05 XGBATFLTN AA15 XMIADR[8] T20 XPDATA[24] Y06 XGPIO[1] AA16 XMIADR[6] T21 XPDATA[20] Y07 XGPIO[3] AA17 XMIDATA[6] T22 XPDATA[21] Y08 VDD15 AA18 VDDlogic T23 XPDATA[23] Y09 XSRSTOUTN AA19 XMIDATA[2] U01 X2SDO Y10 XUDDP AA20 XMIADR[0] U02 X2SLRCK Y11 XSDDAT[3] AA21 VDDpadSDRAM U03 XUTXD Y12 VDD20(VDDpadUSB) AA22 XPDATA[31] U04 XGPIO[9] Y13 XMSSDIO AA23 XPDATA[28] U20 XRDATA[4] Y14 XMSPI AB01 VDDrtc U21 XPDATA[22] Y15 XMICSN AB02 XADCAIN[7] U22 XPCKE Y16 XMIADR[10] AB03 XRTCXTO U23 XPRASN Y17 XPADDR[13] AB04 XGREFCLKSEL[1]
1-12 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Table 1-1. 337-Pin FBGA Pin Assignments – Pin Number Order (Continued)
Pin
Number
Pin Name Pin
Number
Pin Name Pin
Number
Pin Name
V01 XSPIMOSI Y18 XMIADR[4] AB05 XADCAIN[0]
V02 XSPISSIN[1] Y19 XMIADR[2] AB06 VDDadc AB07 VSSMpll AB21 XPADDR[11] AC12 XSDDAT[2] AB08 XSUPLLCAP AB22 XPDATA[30] AC13 XSDDAT[0] AB09 XSEXTCLK AB23 XPADDR[8] AC14 XMIADR[9] AB10 XUSDP[1] AC01 VSSrtc AC15 XMIADR[5] AB11 XUDDN AC02 XADCAIN[6] AC16 XMIDATA[5] AB12 XSDDAT[1] AC03 XADCAIN[4] AC17 XMIDATA[3] AB13 VSSpadUSB AC04 XADCAIN[3] AC18 XMIDATA[1] AB14 XMIOEN AC05 XADCAIN[1] AC19 XMIADR[3] AB15 XMIADR[7] AC06 XSMPLLCAP AC20 XPADDR[14] AB16 XMIDATA[7] AC07 VSSUpll AC21 XPADDR[12] AB17 XMIDATA[4] AC08 XGMONHCLK AC22 XPADDR[10] AB18 XMIIRQN AC09 XSXTIN AC23 XPADDR[9] AB19 XMIDATA[0] AC10 XUSDN[1] AB20 XMIADR[1] AC11 XMSSCLKO
Preliminary product information describe products that are in development, 1-13
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Table 1-2. 337-Pin FBGA Pin Assignments
Pin
Number
AA7 VSSadc VSSadc P P P P P AB7 VSSMpll VSSMpll P P P P P AC7 VSSUpll VSSUpll P P P P P
AB13 VSSpadUSB VSSpadUSB P P P P P
AC1 VSSrtc VSSrtc P P P P P
AA18 VDDlogic VDDlogic P P P P P
J21 VDDlogic VDDlogic P P P P P
M14 VDDlogic VDDlogic P P P P P
N9 VDDlogic VDDlogic P P P P P
R11 VDDlogic VDDlogic P P P P P
W21 VDDlogic VDDlogic P P P P P
K11 VDDpadIO VDDpadIO P P P P P
M3 VDDpadIO VDDpadIO P P P P P N10 VDDpadIO VDDpadIO P P P P P R12 VDDpadModem VDDpadModem P P P P P C12 VDDarm VDDarm P P P P P
L10 VDDarm VDDarm P P P P P
L9 VDDarm VDDarm P P P P P
AA21 VDDpadSDRAM VDDpadSDRAM P P P P P
H21 VDDpadSDRAM VDDpadSDRAM P P P P P N14 VSSpadSDRAM VSSpadSDRAM P P P P P N15 VDDpadSDRAM VDDpadSDRAM P P P P P
W20 VDDpadSDRAM VDDpadSDRAM P P P P P
Y20 VDDpadSDRAM VDDpadSDRAM P P P P P
J13 VDDpadFlash VDDpadFlash P P P P P
L14 VDDpadFlash VDDpadFlash P P P P P M10 VDDalive VDDalive P P P P P P12 VDDalive VDDalive P P P P P AB1 VDDrtc VDDrtc P P P P P AB6 VDDadc VDDadc P P P P P AA8 VDDMpll VDDMpll P P P P P
Y8 VDDupll VDDupll P P P P P
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
1-14 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Table 1-2. 337-Pin FBGA Pin Assignments (Continued)
Pin
Number
Y12 VDDpadUSB VDDpadUSB P P P P P K12 VSS VSS P P P P P L11 VSS VSS P P P P P L12 VSS VSS P P P P P
L13 VSS VSS P P P P P M11 VSS VSS P P P P P M12 VSS VSS P P P P P M13 VSS VSS P P P P P N11 VSS VSS P P P P P N12 VSS VSS P P P P P N13 VSS VSS P P P P P
A2 VSSpadIO VSSpadIO P P P P P
J11 VSSpadIO VSSpadIO P P P P P
M9 VSSpadIO VSSpadIO P P P P P P11 VSSpadIO VSSpadIO P P P P P L15 VSSpadSDRAM VSSpadSDRAM P P P P P
M15 VSSpadSDRAM VSSpadSDRAM P P P P P
P13 VSSpadSDRAM VSSpadSDRAM P P P P P
R13 VSSpadSDRAM VSSpadSDRAM P P P P P
J12 VSSpadFlash VSSpadFlash P P P P P
K13 VSSpadFlash VSSpadFlash P P P P P
E3 X2cSCL X2cSCL I/O I/H L or I H phbsud8sm
E2 X2cSDA X2cSDA I/O I/H L or I H phbsud8sm
T1 X2sCDCLK X2sCDCLK O H or L/L Hi-z or H or L H phot8
W4 X2sCLK X2sCLK I/O L/L/L H or L or I L phbsu100ct8sm
Y4 X2sDI X2sDI I I – – phis
U1 X2sDO X2sDO O L/L Hi-z or H or L L phot8
U2 X2sLRCK X2sLRCK I/O H/L/L H or L or I Pre phbsu100ct8sm
P3 X97BITCLK X97BITCLK I I phis
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
Preliminary product information describe products that are in development, 1-15
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Table 1-2. 337-Pin FBGA Pin Assignments (Continued)
Pin
Number
N2 X97RESET n X97RESETn O L/L Hi-z or H or L H phot8 T3 X97SDI X97SDI I I – phis P2 X97SDO X97SDO O L/L Hi-z or H or L L phot8 N1 X97SYNC X97SYNC O L/L Hi-z or H or L L phot8
AB5 XadcAIN[0] XadcAIN[0] Ain I phiar10
AC5 XadcAIN[1] XadcAIN[1] Ain I phiar10
AA6 XadcAIN[2] XadcAIN[2] Ain I phiar10
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
_abb
_abb
_abb
1-16 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Table 1-2. 337-Pin FBGA Pin Assignments (Continued)
Pin
Number
AC4 XadcAIN[3] XadcAIN[3] Ain I phiar10_abb AC3 XadcAIN[4] XadcAIN[4] Ain I phiar10_abb AA4 XadcAIN[5] XadcAIN[5] Ain I phiar10_abb AC2 XadcAIN[6] XadcAIN[6] Ain I phiar10_abb AB2 XadcAIN[7] XadcAIN[7] Ain I phiar10_abb AA5 XadcAVREF XadcAVREF Ain I phia_abb
A3 XciCDATA[0] XciCDATA[0] I I/H/L – phbsu100ct8sm
C4 XciCDATA[1] XciCDATA[1] I I/H/L phbsu100ct8sm
B5 XciCDATA[2] XciCDATA[2] I I/H/L phbsu100ct8sm
B6 XciCDATA[3] XciCDATA[3] I I/H/L phbsu100ct8sm
C7 XciCDATA[4] XciCDATA[4] I I/H/L phbsu100ct8sm
D9 XciCDATA[5] XciCDATA[5] I I/H/L phbsu100ct8sm
C8 XciCDATA[6] XciCDATA[6] I I/H/L phbsu100ct8sm
A10 XciCDATA[7] XciCDATA[7] I I/H/L phbsu100ct8sm
C3 XciCLK XciCLK O L/L Hi-z or H or L L phot12sm
C6 XciHREF XciHREF I I phis
A5 XciPCLK XciPCLK I I – – phis
D4 XciRSTn XciRSTn O L/L Hi-z or H or L Pre phot8
D6 XciVSYNC XciVSYNC I I phis
B2 XciYDATA[0] XciYDATA[0] I I phis
E4 XciYDATA[1] XciYDATA[1] I I phis
B3 XciYDATA[2] XciYDATA[2] I I phis
F4 XciYDATA[3] XciYDATA[3] I I phis
A1 XciYDATA[4] XciYDATA[4] I I phis
D5 XciYDATA[5] XciYDATA[5] I I phis
B4 XciYDATA[6] XciYDATA[6] I I phis
A4 XciYDATA[7] XciYDATA[7] I I phis
B22 XfALE XfALE O L/L Hi-z or H or L L phot8 D19 XfCLE XfCLE O L/L Hi-z or H or L L phot8
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
Preliminary product information describe products that are in development, 1-17
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Table 1-2. 337-Pin FBGA Pin Assignments (Continued)
Pin
Number
B23 XfNFACYC XfNFACYC I I phis C23 XfNFADV XfNFADV I I phis D22 XfNFBW XfNFBW I I – phis C22 XfNFPS XfNFPS I I phis A23 XfRnB[0] XfRnB[0] I I phisu E20 XfRnB[1] XfRnB[1] I I phisu
Y5 XgBATFLT XgBATFLT I H phis
AC8 XgMONHCLK XgMONHCLK O L/L Hi-z or H or L L phot8
M1 XgpIO[0]/EINT0 XgpIO[0] I/O I/H/L H or L or I phbsu100ct8sm
Y6 XgpIO[1]/EINT1/
L2 XgpIO[10]/YMON XgpIO[10] I/O I/H/L H or L or I phbsu100ct8sm
K1 XgpIO[11]/EINT11
L3 XgpIO[12]/EINT12/
T4 XgpIO[13]/EINT13/
K2 XgpIO[14]/EINT14/
R4 XgpIO[15]/EINT15/
K3 XgpIO[16]/EINT16/
J1 XgpIO[17]/EINT17/
J2 XgpIO[18]/EINT18/
M4 XgpIO[19]/PWM_
R3 XgpIO[2]/EINT2/
H1 XgpIO[20]/PWM_
Name Default
Function
XgpIO[1] I/O I/H/L H or L or I phbsu100ct8sm
PWM_ECLK
XgpIO[11] I/O I/H/L H or L or I phbsu100ct8sm
/YPON
XgpIO[12] I/O I/H/L H or L or I phbsu100ct8sm
XMON
XgpIO[13] I/O I/H/L H or L or I phbsu100ct8sm
XPON
XgpIO[14] I/O I/H/L H or L or I phbsu100ct8sm
RTC_ALMINT
XgpIO[15] I/O I/H/L H or L or I phbsu100ct8sm
XspiMOSI
XgpIO[16] I/O I/H/L H or L or I phbsu100ct8sm
XspiMISO
XgpIO[17] I/O I/H/L H or L or I phbsu100ct8sm
XspiCLK
XgpIO[18] I/O I/H/L H or L or I phbsu100ct8sm
XkpROW0
XgpIO[19] I/O I/H/L H or L or I phbsu100ct8sm
ECLK/XkpROW1
XgpIO[2] I/O I/H/L H or L or I phbsu100ct8sm
PWM_TOUT0
XgpIO[20] I/O I/H/L H or L or I phbsu100ct8sm
TOUT0/ XkpROW2
I/O I/O state@
Reset mode
(Data/En/
PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
1-18 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Table 1-2. 337-Pin FBGA Pin Assignments (Continued)
Pin
Number
L4 XgpIO[21]/PWM_TO
H3 XgpIO[22]/PWM_TO
H2 XgpIO[23]/PWM_TO
G1 XgpIO[24]/
J3 XgpIO[25]/EXTDMA_
G2 XgpIO[26]/EXTDMA_
G3 XgpIO[27]/EXTDMA_
F1 XgpIO[28]/XuCTSn1/
F2 XgpIO[29]/XuRTSn1/
Y7 XgpIO[3]/EINT3/
F3 XgpIO[30]/
E1 XgpIO[31]/
N3 XgpIO[4]/EINT4/
P4 XgpIO[5]/EINT5/
M2 XgpIO[6]/EINT6 XgpIO[6] I/O I/H/L H or L or I phbsu100ct8sm
L1 XgpIO[7]/EINT7 XgpIO[7] I/O I/H/L H or L or I phbsu100ct8sm N4 XgpIO[8]/EINT8 XgpIO[8] I/O I/H/L H or L or I phbsu100ct8sm U4 XgpIO[9]/EINT9 XgpIO[9] I/O I/H/L H or L or I phbsu100ct8sm
AA3 XgPWROFFn XgPWROFFn O H L H phob8
Name Default
UT1/XkpROW3
UT2/XkpROW4
UT3/XkpCOL0
EXTDMA_REQ0/
XkpCOL1
REQ1/XkpCOL2
ACK0/ XkpCOL3
ACK1/XkpCOL4
RTC_ALMINT
IrDA_SDBW
PWM_TOUT1
XuTXD1/IrDA_TXD
XuRXD1/ IrDA_RXD
PWM_TOUT2
PWM_TOUT3
I/O I/O state@
Function
XgpIO[21] I/O I/H/L H or L or I phbsu100ct8sm
XgpIO[22] I/O I/H/L H or L or I phbsu100ct8sm
XgpIO[23] I/O I/H/L H or L or I phbsu100ct8sm
XgpIO[24] I/O I/H/L H or L or I phbsu100ct8sm
XgpIO[25] I/O I/H/L H or L or I phbsu100ct8sm
XgpIO[26] I/O I/H/L H or L or I phbsu100ct8sm
XgpIO[27] I/O I/H/L H or L or I phbsu100ct8sm
XgpIO[28] I/O I/H/L H or L or I phbsu100ct8sm
XgpIO[29] I/O I/H/L H or L or I phbsu100ct8sm
XgpIO[3] I/O I/H/L H or L or I phbsu100ct8sm
XgpIO[30] I/O I/H/L H or L or I phbsu100ct8sm
XgpIO[31] I/O I/H/L H or L or I phbsu100ct8sm
XgpIO[4] I/O I/H/L H or L or I phbsu100ct8sm
XgpIO[5] I/O I/H/L H or L or I phbsu100ct8sm
Reset mode
(Data/En/PullupEn)
En(L)=>output PullupEn(L)=>
PullUp
I/O State@
SLEEP
Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
Preliminary product information describe products that are in development, 1-19
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Table 1-2. 337-Pin FBGA Pin Assignments (Continued)
Pin
Number
AA2 XgREFCLKSEL[0] XgREFCLKSEL[0] I H phis AB4 XgREFCLKSEL[1] XgREFCLKSEL[1] I H phis
Y2 XgTMODE[0] XgTMODE[0] I I phis
W1 XgTMODE[1] XgTMODE[1] I I phis
R1 XgTMODE[2] XgTMODE[2] I I phis V3 XgTMODE[3] XgTMODE[3] I I phis
D10 XjRTCK XjRTCK O L – – phob8
B1 XjTCK XjTCK I I – – phis D2 XjTDI XjTDI I I – – phisu D1 XjTDO XjTDO O I/H Hi-z or H or L Hi-z phot8
C1 XjTMS XjTMS I I – – phisu
C2 XjTRSTn XjTRSTn I I – – phisu AA20 XmiADR[0] XmiADR[0] I I/H/L – phbsu100ct8sm AB20 XmiADR[1] XmiADR[1] I I/H/L – phbsu100ct8sm
Y16 XmiADR[10] XmiADR[10] I I/H/L – phbsu100ct8sm Y19 XmiADR[2] XmiADR[2] I I/H/L – phbsu100ct8sm
AC19 XmiADR[3] XmiADR[3] I I/H/L – phbsu100ct8sm
Y18 XmiADR[4] XmiADR[4] I I/H/L – phbsu100ct8sm AC15 XmiADR[5] XmiADR[5] I I/H/L – phbsu100ct8sm AA16 XmiADR[6] XmiADR[6] I I/H/L – phbsu100ct8sm AB15 XmiADR[7] XmiADR[7] I I/H/L – phbsu100ct8sm AA15 XmiADR[8] XmiADR[8] I I/H/L – phbsu100ct8sm AC14 XmiADR[9] XmiADR[9] I I/H/L – phbsu100ct8sm
Y15 XmiCSn XmiCSn I I – – phisu AB19 XmiDATA[0] XmiDATA[0] I/O I/H/L H or L or I phbsu100ct8sm AC18 XmiDATA[1] XmiDATA[1] I/O I/H/L H or L or I phbsu100ct8sm AA19 XmiDATA[2] XmiDATA[2] I/O I/H/L H or L or I phbsu100ct8sm AC17 XmiDATA[3] XmiDATA[3] I/O I/H/L H or L or I phbsu100ct8sm AB17 XmiDATA[4] XmiDATA[4] I/O I/H/L H or L or I phbsu100ct8sm AC16 XmiDATA[5] XmiDATA[5] I/O I/H/L H or L or I phbsu100ct8sm AA17 XmiDATA[6] XmiDATA[6] I/O I/H/L H or L or I phbsu100ct8sm AB16 XmiDATA[7] XmiDATA[7] I/O I/H/L H or L or I phbsu100ct8sm
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP
Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
1-20 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Table 1-2. 337-Pin FBGA Pin Assignments (Continued)
Pin
Number
AB18 XmiIRQn XmiIRQn O H/L Hi-z or H or L H phot8 AB14 XmiOEn XmiOEn I I phisu AA14 XmiWEn XmiWEn I I phisu AA13 XmsBS XmsBS O L/L Hi-z or H or L L phot8
Y14 XmsPI XmsPI I I phis
AC11 XmsSCLKO XmsSCLKO O H/L Hi-z or H or L H phot8
Y13 XmsSDIO XmsSDIO I/O I/H/L H or L or I phbsu100ct12sm L23 XpADDR[0] XpADDR[0] O L/L Hi-z or H or L Pre phot12sm
M22 XpADDR[1] XpADDR[1] O L/L Hi-z or H or L Pre phot12sm AC22 XpADDR[10] XpADDR[10] O L/L Hi-z or H or L Pre phot12sm AB21 XpADDR[11] XpADDR[11] O L/L Hi-z or H or L Pre phot12sm AC21 XpADDR[12] XpADDR[12] O L/L Hi-z or H or L Pre phot12sm
Y17 XpADDR[13] XpADDR[13] O L/L Hi-z or H or L Pre phot12sm
AC20 XpADDR[14] XpADDR[14] O L/L Hi-z or H or L Pre phot12sm
M20 XpADDR[2] XpADDR[2] O L/L Hi-z or H or L Pre phot12sm
M23 XpADDR[3] XpADDR[3] O L/L Hi-z or H or L Pre phot12sm
N21 XpADDR[4] XpADDR[4] O L/L Hi-z or H or L Pre phot12sm
N22 XpADDR[5] XpADDR[5] O L/L Hi-z or H or L Pre phot12sm
N23 XpADDR[6] XpADDR[6] O L/L Hi-z or H or L Pre phot12sm
P22 XpADDR[7] XpADDR[7] O L/L Hi-z or H or L Pre phot12sm AB23 XpADDR[8] XpADDR[8] O L/L Hi-z or H or L Pre phot12sm AC23 XpADDR[9] XpADDR[9] O L/L Hi-z or H or L Pre phot12sm
V23 XpCASn XpCASn O H/L Hi-z or H or L Pre phot12sm
U22 XpCKE XpCKE O L/L Hi-z or H or L L phot12sm
Name Default
Function
I/O I/O state@
Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
Preliminary product information describe products that are in development, 1-21
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Table 1-2. 337-Pin FBGA Pin Assignments (Continued)
Pin
Number
W22 XpCSN[0] XpCSN[0] O H/L Hi-z or H or L H phot12sm W23 XpCSN[1] XpCSN[1] O H/L Hi-z or H or L H phot12sm
F21 XpDATA[0] XpDATA[0] I/O I/H/L H or L or I phbsu100ct12sm E23 XpDATA[1] XpDATA[1] I/O I/H/L H or L or I phbsu100ct12sm K22 XpDATA[10] XpDATA[10] I/O I/H/L H or L or I phbsu100ct12sm K23 XpDATA[11] XpDATA[11] I/O I/H/L H or L or I phbsu100ct12sm
L21 XpDATA[12] XpDATA[12] I/O I/H/L H or L or I phbsu100ct12sm L22 XpDATA[13] XpDATA[13] I/O I/H/L H or L or I phbsu100ct12sm
L20 XpDATA[14] XpDATA[14] I/O I/H/L H or L or I phbsu100ct12sm M21 XpDATA[15] XpDATA[15] I/O I/H/L H or L or I phbsu100ct12sm P21 XpDATA[16] XpDATA[16] I/O I/H/L H or L or I phbsu100ct12sm R21 XpDATA[17] XpDATA[17] I/O I/H/L H or L or I phbsu100ct12sm P23 XpDATA[18] XpDATA[18] I/O I/H/L H or L or I phbsu100ct12sm R22 XpDATA[19] XpDATA[19] I/O I/H/L H or L or I phbsu100ct12sm E22 XpDATA[2] XpDATA[2] I/O I/H/L H or L or I phbsu100ct12sm T21 XpDATA[20] XpDATA[20] I/O I/H/L H or L or I phbsu100ct12sm T22 XpDATA[21] XpDATA[21] I/O I/H/L H or L or I phbsu100ct12sm U21 XpDATA[22] XpDATA[22] I/O I/H/L H or L or I phbsu100ct12sm T23 XpDATA[23] XpDATA[23] I/O I/H/L H or L or I phbsu100ct12sm T20 XpDATA[24] XpDATA[24] I/O I/H/L H or L or I phbsu100ct12sm Y21 XpDATA[25] XpDATA[25] I/O I/H/L H or L or I phbsu100ct12sm Y23 XpDATA[26] XpDATA[26] I/O I/H/L H or L or I phbsu100ct12sm Y22 XpDATA[27] XpDATA[27] I/O I/H/L H or L or I phbsu100ct12sm
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
1-22 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Table 1-2. 337-Pin FBGA Pin Assignments (Continued)
Pin
Number
AA23 XpDATA[28] XpDATA[28] I/O I/H/L H or L or I phbsu100ct12sm
V21 XpDATA[29] XpDATA[29] I/O I/H/L H or L or I phbsu100ct12sm
F23 XpDATA[3] XpDATA[3] I/O I/H/L H or L or I phbsu100ct12sm AB22 XpDATA[30] XpDATA[30] I/O I/H/L H or L or I phbsu100ct12sm AA22 XpDATA[31] XpDATA[31] I/O I/H/L H or L or I phbsu100ct12sm
H20 XpDATA[4] XpDATA[4] I/O I/H/L H or L or I phbsu100ct12sm G21 XpDATA[5] XpDATA[5] I/O I/H/L H or L or I phbsu100ct12sm
F22 XpDATA[6] XpDATA[6] I/O I/H/L H or L or I phbsu100ct12sm
G23 XpDATA[7] XpDATA[7] I/O I/H/L H or L or I phbsu100ct12sm
J23 XpDATA[8] XpDATA[8] I/O I/H/L H or L or I phbsu100ct12sm
K21 XpDATA[9] XpDATA[9] I/O I/H/L H or L or I phbsu100ct12sm
G22 XpDQM[0] XpDQM[0] O H/L Hi-z or H or L phot12sm H22 XpDQM[1] XpDQM[1] O H/L Hi-z or H or L phot12sm H23 XpDQM[2] XpDQM[2] O H/L Hi-z or H or L phot12sm
J22 XpDQM[3] XpDQM[3] O H/L Hi-z or H or L phot12sm U23 XpRASn XpRASn O H/L Hi-z or H or L phot12sm R23 XpSCLK XpSCLK I/O H or L /L H or L or I L phbst12sm
V22 XpWEn XpWEn O H/L Hi-z or H or L H phot12sm D16 XrADDR[0] XrADDR[0] O L/L Hi-z or H or L Pre phot8 C14 XrADDR[1] XrADDR[1] O L/L Hi-z or H or L Pre phot8
A18 XrADDR[10] XrADDR[10] O L/L Hi-z or H or L Pre phot8
B19 XrADDR[11] XrADDR[11] O L/L Hi-z or H or L Pre phot8 D21 XrADDR[12] XrADDR[12] O L/L Hi-z or H or L Pre phot8
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
Preliminary product information describe products that are in development, 1-23
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Table 1-2. 337-Pin FBGA Pin Assignments (Continued)
Pin
Number
G20 XrADDR[13] XrADDR[13] O L/L Hi-z or H or L Pre phot8 D17 XrADDR[14] XrADDR[14] O L/L Hi-z or H or L Pre phot8 B20 XrADDR[15] XrADDR[15] O L/L Hi-z or H or L Pre phot8 A19 XrADDR[16] XrADDR[16] O L/L Hi-z or H or L Pre phot8 A20 XrADDR[17] XrADDR[17] O L/L Hi-z or H or L Pre phot8 D15 XrADDR[2] XrADDR[2] O L/L Hi-z or H or L Pre phot8 A13 XrADDR[3] XrADDR[3] O L/L Hi-z or H or L Pre phot8 D14 XrADDR[4] XrADDR[4] O L/L Hi-z or H or L Pre phot8 B14 XrADDR[5] XrADDR[5] O L/L Hi-z or H or L Pre phot8 C15 XrADDR[6] XrADDR[6] O L/L Hi-z or H or L Pre phot8 A14 XrADDR[7] XrADDR[7] O L/L Hi-z or H or L Pre phot8 D20 XrADDR[8] XrADDR[8] O L/L Hi-z or H or L Pre phot8 C20 XrADDR [9] XrADDR [9] O L/L Hi-z or H or L Pre phot8 F20 XrADDR[18] XrADDR[18] O L/L/H Hi-z or H or L Pre phbsu100ct8sm D18 XrADDR[19] XrADDR[19] O L/L/H Hi-z or H or L Pre phbsu100ct8sm A21 XrADDR[20] XrADDR[20] O L/L/H Hi-z or H or L Pre phbsu100ct8sm C21 XrADDR[21] XrADDR[21] O L/L/H Hi-z or H or L Pre phbsu100ct8sm B21 XrADDR[22] XrADDR[22] O L/L/H Hi-z or H or L Pre phbsu100ct8sm A22 XrADDR[23] XrADDR[23] O L/L/H Hi-z or H or L Pre phbsu100ct8sm E21 XrADDR[24] XrADDR[24] O L/L/H Hi-z or H or L Pre phbsu100ct8sm D23 XrADDR[25] XrADDR[25] O L/L/H Hi-z or H or L Pre phbsu100ct8sm P20 XrCSn[0] XrCSn[0] O H/L Hi-z or H or L Pre phot8
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
1-24 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Table 1-2. 337-Pin FBGA Pin Assignments (Continued)
Pin
Number
C17 XrCSn[1] XrCSn[1] O H/L Hi-z or H or L Pre phot8
B17 XrCSn[2] XrCSn[2] O H/L Hi-z or H or L Pre phot8 A11 XrDATA[0] XrDATA[0] I/O I/H/L H or L or I phbsu100ct8sm B11 XrDATA[1] XrDATA[1] I/O I/H/L H or L or I phbsu100ct8sm
C18 XrDATA[10] XrDAT A[10] I/O I/H/L H or L or I phbsu100ct8sm
K20 XrDATA[11] XrDATA[11] I/O I/H/L H or L or I phbsu100ct8sm
C19 XrDATA[12] XrDAT A[12] I/O I/H/L H or L or I phbsu100ct8sm
A17 XrDATA[13] XrDATA[13] I/O I/H/L H or L or I phbsu100ct8sm B18 XrDATA[14] XrDATA[14] I/O I/H/L H or L or I phbsu100ct8sm J20 XrDAT A[15] XrDATA[15] I/O I/H/L H or L or I phbsu100ct8sm V20 XrDATA[2] XrDATA[2] I/O I/H/L H or L or I phbsu100ct8sm B12 XrDATA[3] XrDATA[3] I/O I/H/L H or L or I phbsu100ct8sm
U20 XrDATA[4] XrDATA[4] I/O I/H/L H or L or I phbsu100ct8sm
A12 XrDATA[5] XrDATA[5] I/O I/H/L H or L or I phbsu100ct8sm
C13 XrDATA[6] XrDATA[6] I/O I/H/L H or L or I phbsu100ct8sm
B13 XrDATA[7] XrDATA[7] I/O I/H/L H or L or I phbsu100ct8sm A16 XrDATA[8] XrDATA[8] I/O I/H/L H or L or I phbsu100ct8sm
N20 XrDATA[9] XrDATA[9] I/O I/H/L H or L or I phbsu100ct8sm
B15 XrnWBE[0] XrnWBE[0] O H/L Hi-z or H or L Pre phot8 A15 XrnWBE[1] XrnWBE[1] O H/L Hi-z or H or L Pre phot8
R20 XrOEn XrOEn O H/L Hi-z or H or L H phot8
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
Preliminary product information describe products that are in development, 1-25
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Table 1-2. 337-Pin FBGA Pin Assignments (Continued)
Pin
Number
AA1 XrtcXTI XrtcXTI Ain L rtc_osc AB3 XrtcXTO XrtcXTO Aout X rtc_osc C16 XrWAITn XrWAITn I I phis
B16 XrWEn XrWEn O H/L Hi-z or H or L H phot8 AC13 XsdDAT[0] XsdDAT[0] I/O I/H/L H or L or I phbsu100ct12sm AB12 XsdDAT[1] XsdDAT[1] I/O I/H/L H or L or I phbsu100ct12sm AC12 XsdDAT[2] XsdDAT[2] I/O I/H/L H or L or I phbsu100ct12sm
Y11 XsdDAT[3] XsdDAT[3] I/O I/H/L H or L or I phbsu100ct12sm
AB9 XsEXTCLK XsEXTCLK I I phis AC6 XsMPLLCAP XsMPLLCAP Aout X Phoar50_abb
Y3 XspiCLK XspiCLK I/O I/H/L H or L or I phtbsu100ct8sm
W2 XspiMISO XspiMISO I/O H/L/L H or L or I H phtbsu100ct8sm
V1 XspiMOSI XspiMOSI I/O I/H/L H or L or I phtbsu100ct8sm
W3 XspiSSIn[0] XspiSSIn[0] I I phisu
V2 XspiSSIn[1] XspiSSIn[1] I I phisu
AA9 XsRESETn XsRESETn I L phisu
Y9 XsRSTOUTn XsRSTOUTn O L Hi-z or H or L H phot8
AB8 XsUPLLCAP XsUPLLCAP Aout X Phoar50_abb
Y1 XsWRESETn XsWRESETn I L phisu
AC9 XsXTIN XsXTIN I H or L phsoscm26_schmitt
AA10 XsXTOUT XsXTOUT O H or L phsoscm26_schmitt
V4 XuCLK XuCLK I I – phis
T2 XuCTSn XuCTSn I I phis
AB11 XudDN XudDN I/O I H or L or I pbusb1
Y10 XudDP XudDP I/O I H or L or I pbusb1
P1 XuRTSn XuRTSn O H/L Hi-z or H or L H phot8 R2 XuRXD XuRXD I I – phisu
AA12 XusDN[0] XusDN[0] I/O X H or L or I pbusb1
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
1-26 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Table 1-2. 337-Pin FBGA Pin Assignments (Continued)
Pin
Number
AC10 XusDN[1] XusDN[1] I/O X H or L or I pbusb1 AA11 XusDP[0] XusDP[0] I/O X H or L or I pbusb1 AB10 XusDP[1] XusDP[1] I/O X H or L or I pbusb1
U3 XuTXD XuTXD O H/L Hi-z or H or L H phot8 A9 XvDEN XvDEN O L/L Hi-z or H or L L phot8 C9 XvHSYNC XvHSYNC O L/L Hi-z or H or L Pre phot8 A8 XvVCLK XvVCLK O H or L /L Hi-z or H or L L phot12sm
J4 XvVD[6] XvVD[6] O L/L H or L or I Pre phot12sm B7 XvVD[7] XvVD[7] O L/L H or L or I Pre phot12sm K4 XvVD[8] XvVD[8] O L/L H or L or I Pre phot12sm D7 XvVD[9] XvVD[9] O L/L H or L or I Pre phot12sm D8 XvVD[10] XvVD[10] O L/L H or L or I Pre phot12sm B8 XvVD[11] XvVD[11] O L/L H or L or I Pre phot12sm B9 XvVD[12] XvVD[12] O L/L H or L or I Pre phot12sm
D12 XvVD[13] XvVD[13] O L/L H or L or I Pre phot12sm
D3 XvVD[0] XvVD[0] O L/L H or L or I Pre phot12sm
C10 XvVD[14] XvVD[14] O L/L H or L or I Pre phot12sm
B10 XvVD[15] XvVD[15] O L/L H or L or I Pre phot12sm D13 XvVD[16] XvVD[16] O L/L H or L or I Pre phot12sm C11 XvVD[17] XvVD[17] O L/L H or L or I Pre phot12sm
G4 XvVD[1] XvVD[1] O L/L H or L or I Pre phot12sm
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
Preliminary product information describe products that are in development, 1-27
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Table 1-2. 337-Pin FBGA Pin Assignments (Continued)
Pin
Number
C5 XvVD[2] XvVD[2] O L/L H or L or I Pre phot12sm A6 XvVD[3] XvVD[3] O L/L H or L or I Pre phot12sm H4 XvVD[4] XvVD[4] O L/L H or L or I Pre phot12sm A7 XvVD[5] XvVD[5] O L/L H or L or I Pre phot12sm
D11 XvVSYNC XvVSYNC O L/L Hi-z or H or L L phot8
NOTES:
1. ‘–‘ mark indicates the unchanged pin state
2. Hi-z or Pre means Hi-z or Previous value
3. P, I and O mean power, input and output respectively
4. AI/AO means analog input/output
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
1-28 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
The table below shows I/O types and the descriptions.
I/O Type Descriptions
vdd12ih 1.2V Vdd for alive vdd12ih_core 1.2V Vdd for internal logic vdd33oph 3.3V Vdd for external logic vdd33th_abb 3.3V Vdd for analog circuit vdd30th_rtc 3.3V Vdd for rtc circuit vdd33th_abb 3.3V Vdd for pll circuit Vss Vss Phis Input pad, LVCMOS schmitt-trigger level Phisu Input pad, schmitt-trigger level, pull-up Phisd Input pad, schmitt-trigger level, pull-down Pbusb USB pad phot8 Output pad, tri-state, Io=8mA phob8 Output pad, Io=8mA phot12sm Output pad, tri-state, medium slew rate, Io=12mA phbst12sm Bi-directional pad, LVCMOS schmitt-trigger, pull-up resistor with
control, tri-state, Io=12mA pbusb1 USB pad Rtc-osc rtc X-tal phob1-abb Analog pad phiar10_abb Analog input pad with 10-ohm resistor phia_abb Analog input pad phsoscm26_shmitt Oscillator cell with enable and feedback resistor phbsu100ct8sm Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with
control, tri-state, Io=8mA phbsu100ct12sm Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with
control, tri-state, Io=12mA phbsud8sm Bi-directional pad, schmitt-trigger, pull-up resistor with, open-drain
control, Io=8mA
NOTE: phbsu100ct8sm means a bi-directional pad, but this means input pad so long as phbsu100ct8sm is used for
XciCDATA[7:0]
Preliminary product information describe products that are in development, 1-29
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
PIN DESCRIPTIONS
I/O SIGNAL DESCRIPTIONS External Memory Interface
Shared Memory Bus (ROM/SRAM/NOR Flash/NAND Flash/External Bus)
Signal I/O Description
XrADDR[25:0] O XrADDR[25:0] (Address Bus for shared memory) outputs the memory address of the
corresponding bank .
XrDATA[15:0] IO XrDATA[15:0] (Data Bus) inputs data during memory read and outputs data during
memory write. The bus width is programmable among 8/16-bit.
XrCSn[2:0] O XrCSn[2:0] (Chip Select) are activated when the address of a memory is within the
address region of each bank. The number of access cycles and the bank size can
be programmed. XrWEn O XrWEn (Write Enable) indicates that the current bus cycle is a write cycle. XrOEn O XrOEn (Output Enable) indicates that the current bus cycle is a read cycle. XrWAITn I XrWAITn requests to prolong a current bus cycle. As long as XrWAITn n is L, the
current bus cycle cannot be completed. XrnWBE[1:0] O Write Byte Enable XfCLE O Nand Flash Command Latch Enable XfALE O Nand Flash Address Latch Enable XfNFPS I Nand Flash Page Size (0:256HWord, 1:512Byte)
or Advanced Page size(0:1K Hword , 1:2K Byte) XfNFBW I Nand Flash Bus Width (0:8-bit, 1:16-bit) XfNFACYC I Nand Flash Address Step (0:3-step, 1:4-step)
or Advanced Address step(0:4-step, 1:5-step) XfNFADV I To Support advanced 2G Nand Flash XfRnB[1:0] I Nand Flash Ready and Busy
SDRAM BUS
Signal I/O Description
XpCSN[1:0] O SDRAM Chip Select XpCASn O SDRAM Column Address Strobe XpRASn O SDRAM Row Address Strobe XpWEn O SDRAM Write Enable XpCKE O SDRAM Clock Enable XpDQM[3:0] O SDRAM Data Mask XpSCLK IO SDRAM Clock XpADDR[14:0] O SDRAM Address bus XpDATA[31:0] O SDRAM Data bus
1-30 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Serial Communication
UART
Signal I/O Description
XuCLK I UART 0 clock signal XuRXD0 I UART 0 receives data input XuCTSn0 I UART 0 clear to send input signal XuTXD0 O UART 0 transmits data output XuRTSn0 O UART 0 request to send output signal
IIC Bus
Signal I/O Description
X2cSDA IO IIC-bus data X2cSCL IO IIC-bus clock
IIS Bus
Signal I/O Description
X2sLRCK IO IIS-bus channel select clock X2sDO O IIS-bus serial data output X2sDI I IIS-bus serial data input X2sCLK IO IIS-bus serial clock X2sCDCLK O CODEC system clock
SPI Bus
Signal I/O Description
XspiSSIn[1:0] I SPI chip select(only for slave mode) XspiCLK IO SPI clock for channel 0 XspiMISO IO XspiMISO is the master data input line, when SPI is configured as a master.
When SPI is configured as a slave, these pins reverse its role. For channel 0
XspiMOSI IO XspiMOSI is the master data output line, when SPI is configured as a master.
When SPI is configured as a slave, these pins reverse its role. For channel 0
Preliminary product information describe products that are in development, 1-31
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
AC97
Signal I/O Description
X97BITCLK I AC-Link bit clock(12.288MHz) from AC97 Codec X97SDI I AC-link Serial Data input from AC97 Codec X97RESETn O AC-link Reset to Codec X97SYNC O AC-link Frame Synchronization (Sampling Frequency 48kHz) from AC97 Controllor X97SDO O AC-link Serial Data output to AC97 Codec
USB Host
Signal I/O Description
XusDN[1:0] IO DATA(–) from USB host XusDP[1:0] IO DATA(+) from USB host
USB Device
Signal I/O Description
XudDN IO DATA(–) for USB peripheral device XudDP IO DATA(+) for USB peripheral device
Parallel Communzication
GPIO
Signal I/O Description
XgpIO[31:0] IO General input/output ports
Modem Interface (8-bit Parallel)
Signal I/O Description
XmiCSn I Chip select, driven by the Modem chip XmiWEn I Write enable, driven by the Modem chip XmiOEn I Read enable, driven by the Modem chip XmiADR[10:0] I Address bus, driven by the Modem chip XmiDATA[7:0] IO Data bus, driven by the Modem chip XmiIRQn O Interrupt request to the Modem chip
1-32 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Image/Video Processing
Camera Interface
Signal I/O Description
XciPCLK I Pixel Clock, driven by the Camera processor XciVSYNC I Vertical Sync, driven by the Camera processor XciHREF I Horizontal Sync, driven by the Camera processor XciCDATA[7:0] I Pixel Data for CbCr in 16-bit mode, driven by the Camera processor XciYDATA[7:0] I Pixel Data for YCbCr in 8-bit mode or for Y in 16-bit mode, driven by the Camera
processor XciCLK O Master Clock to the Camera processor XciRSTn O Software Reset to the Camera processor
Display Control
TFT LCD Display Interface
Signal I/O Description
XvVD[17:0] O LCD pixel data output ports XvVCLK O Pixel clock signal XvVSYNC O Vertical synchronous signal XvHSYNC O Horizontal synchronous signal XvDEN O Data enable signal
Input Devices
Analog-to-Digital Converter and Touch Screen Interface
Signal I/O Description
XadcAVREF AI ADC reference top XadcAIN[7:0] AI ADC analog input
Preliminary product information describe products that are in development, 1-33
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Storage Devices
Secure Digital (SD) and Memory Stick Interface
Signal I/O Description
XsdDAT[3:0] IO SD/MMC card receive/transmit Data XmsPI I Input port used for insertion/extraction detect of Memory stick XmsSDIO IO SD/MMC card command signal port (default). If MemoryStick card enable, Memory
stick Serial data in/out port XmsSCLKO O SD/MMC card Clock (default). If MemoryStick card enable, MemoryStick Clock XmsBS O MemoryStick Serial bus control signal
System Management
Reset
Signal I/O Description
XsRESETn I XsRESETn suspends any operation in progress and places S3C24A0A into a known
reset state. For a reset, XsRESETn must be held to L level for at least 4 External
clock after the processor power has been stabilized. XsWRESETn I System Warm Reset. Reset the whole system while preserves the SDRAM contents XsRSTOUTn O For external device reset control (XsRSTOUTn = XsRESETn & nWDTRST
& SW_RESET & XsWRESETn)
Clock
Signal I/O Description
XsMPLLCAP AO Loop filter capacitor for main clock. XsUPLLCAP AO Loop filter capacitor for USB clock. XrtcXTI AI 32.768KHz crystal input for RTC. XrtcXTO AO 32.768KHz crystal output for RTC. XsXTIN I Crystal Input for internal osc circuit. XsXTOUT O Crystal Input for internal osc circuit. XsEXTCLK I External clock source.
1-34 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
JTAG
Signal I/O Description
XjTRSTn I XjTRSTn (TAP Controller Reset) resets the TAP controller at start.
If debugger(black ICE) is not used, XjTRSTn pin must be issued by a low active pulse (Typically connected to XsRESETn)
XjTMS I XjTMS (TAP Controller Mode Select) controls the sequence of the TAP
controller’s states. XjTCK I XjTCK (TAP Controller Clock) provides the clock input for the JTAG logic. XjRTCK O XjRTCK (TAP Controller Returned Clock) provides the clock output for the
JTAG logic. XjTDI I XjTDI (TAP Controller Data Input) is the serial input for test instructions and
data. XjTDO O XjTDO (TAP Controller Data Output) is the serial output for test instructions
and data.
Misc
Signal I/O Description
XgREFCLKSEL[1:0] I Clock Source Selection
XgREFCLKSEL determines how the clock is made. XgREFCLKSEL[0] - ‘0’: Main clock source is from XsXTIN,
‘1’: Main clock source is from XsEXTCLK
XgREFCLKSEL[1] - ‘0’: USB clock source is from XsXTIN ‘1’: USB clock source is from XsEXTCLK
XgTMODE[3] I ‘0’ : PAD JTAG(Selection of S3C24A0A boundary scan)
‘1’ : ARM JTAG(Selection of ARM core boundary scan) XgTMODE[2:1] I These signals must be reserved ‘00’ XgTMODE[0] I ‘0’ : Normal Operation without NAND BOOT
‘1’ : Normal Operation with NAND BOOT XgBATFLTn I Probe for battery state
(Does not wake up at Stop and Sleep mode in case of low battery state) XgPWROFFn O 1.2V core power on-off control signal XgMONHCLK O HCLK clock monitoring. HCLK clock can be monitored through this pin when
the ClkMonOn bit in the CLKCON register is set.
Preliminary product information describe products that are in development, 1-35
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Power -Supply Groups
VDD
Signal I/O Description
XxVDDlogic P Core logic VDD (1.2V) for internal logic XxVDDalive P S3C24A0A reset block and port status register VDD (1.2V).
It should be always supplied whether in normal mode or in Stop and Sleep
mode. XxVDDarm P Core logic VDD (1.2V) for CPU XxVDDMpll P S3C24A0A MPLL analog and digital VDD (1.2 V). XxVDDUpll P S3C24A0A UPLL analog and digital VDD (1.2V) XxVDDpadIO P S3C24A0A I/O port VDD (3.3V) XxVDDpadSDRAM P S3C24A0A SDRAM memory IO VDD (3.3V) XxVDDpadFlash P S3C24A0A NFLASH memory IO VDD (3.3V) XxVDDpadUSB P S3C24A0A USB IO VDD (3.3V) XrtcVDD P RTC VDD (3.3V)
(Although RTC function is not used, this pin should be connected to power) XadcVDD P S3C24A0A ADC VDD(3.3V) XxVDDpadModem P S3C24A0A MODEM IO VDD (3.3V)
1-36 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
VSS
Signal I/O Description
VSS P Core logic VSS for internal logic VSS for S3C24A0A reset block and port status register Core logic VSS for CPU S3C24A0A I/O port VSS XxVSSpadSDRAM P S3C24A0A SDRAM memory IO VSS XxVSSpadFlash P S3C24A0A Flash memory IO VSS XxVSSpadUSB P S3C24A0A USB IO VSS XxVSSMpll P S3C24A0A MPLL analog and digital VSS. XxVSSUpll P S3C24A0A UPLL analog and digital VSS XrtcVSS P RTC VSS XadcVSS P S3C24A0A ADC VSS
NOTES:
1. I/O means input/output.
2. AI/AO means analog input/output.
3. P means power.
Preliminary product information describe products that are in development, 1-37
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
ADDRESS MAP
ADDRESS SPACE ASSIGNMENT OVERVIEW
0xFFFF_FFFF
0x5000_0000
0x4800_0000
0x4400_0000
0x4000_0000
0x2000_0000
0x1800_0000
0x1000_0000
0x0c00_0000
0x0800_0000
0x0400_0000
0x0000_0000
SROM_BW[9] = 0 TMODE[2:0] = 000
Reserved
AHB_I SFRs
APB SFRs
AHB_S SFRs
Reserved Reserved Reserved
SDRAM
(XpCSn1)
SDRAM
(XpCSn0)
Stepping stone
(4KB, No CS)
SROM
(XrCSn2)
SROM
(XrCSn1)
SROM
(XrCSn0)
[Not using NAND flash for boot ROM]
SROM_BW[9] = 1 TMODE[2:0] = 000
Reserved Reserved
AHB_I SFRs
APB SFRs
SDRAM
(XpCSn1)
SDRAM
(XpCSn0)
Reserved Reserved
Stepping stone
(4KBytes)
SROM
(XrCSn1)
SROM
(XrCSn0)
TMODE[2:0] = 001
[Using NAND flash for boot ROM]
AHB_I SFRs
APB SFRs
AHB_S SFRs
SDRAM
(XpCSn1)
SDRAM
(XpCSn0)
SROM
(XrCSn2)
SROM
(XrCSn1)
Stepping stone
(4KBytes)
128MB
64MB
64MBAHB_S SFRs
128MB
128MB
64MB
64MB
64MB
64MB
Assigned for Special Function Registers
Assigned for SDRAM Bank0/1 Accessible Region
Assigned for SROM Bank0/1/2 Accessible Region
NOTES:
1. SROM means ROM or SRAM type memory.
2. SFR means Special Function Register.
Figure 1-3. Address Map
1-38 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
DEVICE SPECIFIC ADDRESS SPACE
AHB_S (System-side AHB Bus) Devices: Base = 0x4000_0000 (just above 1GB), Size = 64MB – Physical Address = Base Address + Device Offset + Register Offset
Device Offset Size (MB) Group Device Note
0x00_0_0000 1 AHB_S SystemCtrl 0x01_0_0000 1 AHB_S Reserved 0x02_0_0000 1 AHB_S INTC 0x03_0_0000 1 AHB_S Reserved 0x04_0_0000 1 AHB_S DMA 0 0x05_0_0000 1 AHB_S DMA 1 0x06_0_0000 1 AHB_S DMA 2 0x07_0_0000 1 AHB_S DMA 3 0x08_0_0000 4 AHB_S Reserved
0x0C_0_0000 1 AHB_S MemCtrl 0x0D_0_0000 3 AHB_S Reserved
0x10_0_0000 1 AHB_S USB Host 0x11_0_0000 1 AHB_S Modem IF0 0x12_0_0000 6 AHB_S Reserved 0x18_0_0000 1 AHB_S IrDA 0x19_0_0000 7 AHB_S Reserved 0x20_0_0000 16 AHB_S EXT AHB 0x30_0_0000 16 AHB_S Reserved 0x40_0_0000 64 AHB_S APB devices Through AHB to APB Bridge 0x80_0_0000 128 AHB_S AHB_I devices Through AHB to AHB Bridge
Preliminary product information describe products that are in development, 1-39
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
APB Devices: Base = 0x4000_0000
Device Offset Size (MB) Group Device Note
0x40_0_0000 1 APB PWM Timer 0x41_0_0000 1 APB Watch Dog Timer 0x42_0_0000 1 APB RTC 0x43_0_0000 1 APB Reserved 0x44_0_0000 1 APB UART 0x45_0_0000 1 APB SPI 0x46_0_0000 1 APB I2C 0x47_0_0000 1 APB I2S 0x48_0_0000 1 APB GPIO
0x49_0_0000 1 APB KEYPAD Interface 0x4A_0_0000 1 APB USB Device 0x4B_0_0000 5 APB Reserved
0x50_0_0000 1 APB AC97
0x51_0_0000 7 APB Reserved
0x58_0_0000 1 APB ADC/Touch Screen
0x59_0_0000 7 APB Reserved
0x60_0_0000 1 APB SD/MMC
0x61_0_0000 1 APB Memory Stick
0x62_0_0000 14 APB Reserved
0x70_0_0000 16 APB Reserved
1-40 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
AHB_I (the AHB Bus for the Image Subsystem) Devices: Base = 0x4000_0000
Offset (Hex) Size (MB) Group Device Note
0x80_0_0000 4 AHB_I Camera Inteface 0x84_0_0000 4 AHB_I Reserved 0x88_0_0000 4 AHB_I ME
0x8C_0_0000 4 AHB_I MC
0x90_0_0000 4 AHB_I DCT/Q 0x94_0_0000 12 AHB_I Reserved 0xA0_0_0000 1 AHB_I Display Controller 0xA1_0_0000 1 AHB_I Video POST
Processor 0xA2_0_0000 4 AHB_I Reserved 0xA4_0_0000 10 AHB_I VLX 0xB0_0_0000 16 AHB_I Reserved
0xC0_0_0000 16 AHB_I Reserved 0xD0_0_0000 16 AHB_I Reserved
0xE0_0_0000 16 AHB_I Reserved 0xF0_0_0000 16 AHB_I Reserved
Preliminary product information describe products that are in development, 1-41
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
INTERNAL REGISTERS
The base of all devices internal registers = 0x4000_0000
External Memory Interface
NAND Flash Controller
Register
Name
Offset Acc.
Unit
Read/
Write
Function
NFCONF 0x0C0_0000 W R/W NAND flash configuration NFCONT 0x0C0_0004 NAND flash control NFCMMD 0x0C0_0008 NAND flash command NFADDR 0x0C0_000C NAND flash address NFDATA 0x0C0_0010 NAND flash data NFMECCDATA0 0x0C0_0014 NAND flash main area ECC data reg.0 NFMECCDATA1 0x0C0_0018 NAND flash main area ECC data reg.1 NFMECCDATA2 0x0C0_001C NAND flash main area ECC data reg.2 NFMECCDATA3 0x0C0_0020 NAND flash main area ECC data reg.3 NFSECCDATA0 0x0C0_0024 NAND flash spare area ECC data
reg.1
NFSECCDATA1 0x0C0_0028 NAND flash spare area ECC data
reg.2 NFSTAT 0x0C0_002C R NAND flash status NFESTAT0 0x0C0_0030 NAND flash ECC status 0 for I/O[7:0] NFESTAT1 0x0C0_0034 NAND flash ECC status 1 for
I/O[15:8] NFMECC0 0x0C0_0038 NAND flash main area ECC reg.0 NFMECC1 0x0C0_003C NAND flash main area ECC reg.1 NFSECC 0x0C0_0040 NAND flash spare area ECC reg. NFSBLK 0x0C0_0044 R/W NAND flash start block address NFEBLK 0x0C0_0048 NAND flash end block address
1-42 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
SROM Controller
Register
Name
Offset Acc.
Unit
Read/
Write
Function
SROM_BW 0x0C2_0000 W R/W SROM bus width & wait control SROM_BC0 0x0C2_0004 SROM bank0 Control register SROM_BC1 0x0C2_0008 SROM bank1 Control register SROM_BC2 0x0C2_000C SROM bank2 Control register
SDRAM Controller
Register
Name
Offset Acc.
Unit
Read/
Write
Function
SDRAM_BANKCFG 0x0C4_0000 W R/W SDRAM configuration SDRAM_BANKCON 0x0C4_0004 SDRAM control SDRAM_REFRESH 0x0C4_0008 SDRAM refresh control
BUS Matrix
Register
Name
Offset Acc.
Unit
Read/
Write
Function
PRIORITY0 0x0CE_0000 W R/W Priority control for SROMC/NFLASHC PRIORITY1 0x0CE_0004 Priority control for SDRAMC
General Peripherals
Interrupt Controller
Register
Name
Offset Acc.
Unit
Read/
Write
Function
SRCPND 0x020_0000 W R/W Interrupt request status INTMOD 0x020_0004 Interrupt mode control INTMSK 0x020_0008 Interrupt mask control PRIORITY 0x020_000C IRQ priority control INTPND 0x020_0010 Interrupt request status INTOFFSET 0x020_0014 R Interrupt request source offset SUBSRCPND 0x020_0018 R/W Sub source pending INTSUBMSK 0x020_001C Interrupt sub mask VECINTMOD 0x020_0020 Vectored interrupt mode VECADDR 0x020_0024 R Vectored mode address NVECADDR 0x020_0028 R/W Non-vectored mode address VAR 0x020_002C R Vector address register
Preliminary product information describe products that are in development, 1-43
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Timer with PWM (Pulse Width Modulation)
Register
Name
Offset Acc.
Unit
Read/
Write
Function
TCFG0 0x400_0000 W R/W Timer configuration TCFG1 0x400_0004 Timer configuration TCON 0x400_0008 Timer control TCNTB0 0x400_000C Timer count buffer 0 TCMPB0 0x400_0010 Timer compare buffer 0 TCNTO0 0x400_0014 R Timer count observation 0 TCNTB1 0x400_0018 R/W Timer count buffer 1 TCMPB1 0x400_001C Timer compare buffer 1 TCNTO1 0x400_0020 R Timer count observation 1 TCNTB2 0x400_0024 R/W Timer count buffer 2 TCMPB2 0x400_0028 Timer compare buffer 2 TCNTO2 0x400_002C R Timer count observation 2 TCNTB3 0x400_0030 R/W Timer count buffer 3 TCMPB3 0x400_0034 Timer compare buffer 3 TCNTO3 0x400_0038 R Timer count observation 3 TCNTB4 0x400_003C R/W Timer count buffer 4 TCNTO4 0x400_0040 R Timer count observation 4
16-bit Watchdog Timer.
Register
Name
Offset Acc.
Unit
Read/
Write
WTCON 0x410_0000 W R/W Watch-dog timer mode WTDAT 0x410_0004 Watch-dog timer data WTCNT 0x410_0008 Watch-dog timer count
Function
1-44 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
4-ch DMA controller.
Register
Name
Offset Acc.
Unit
Read/
Write
Function
DISRC0 0x040_0000 W R/W DMA 0 initial source DISRCC0 0x040_0004 DMA 0 initial source control DIDST0 0x040_0008 DMA 0 initial destination DIDSTC0 0x040_000C DMA 0 initial destination control DCON0 0x040_0010 DMA 0 control DSTAT0 0x040_0014 R DMA 0 count DCSRC0 0x040_0018 DMA 0 current source DCDST0 0x040_001C DMA 0 current destination DMASKTRIG0 0x040_0020 W R/W DMA 0 mask trigger DISRC1 0x050_0000 DMA 1 initial source DISRCC1 0x050_0004 DMA 1 initial source control DIDST1 0x050_0008 DMA 1 initial destination DIDSTC1 0x050_000C DMA 1 initial destination control DCON1 0x050_0010 DMA 1 control DSTAT1 0x050_0014 R DMA 1 count DCSRC1 0x050_0018 DMA 1 current source DCDST1 0x050_001C W DMA 1 current destination DMASKTRIG1 0x050_0020 R/W DMA 1 mask trigger DISRC2 0x060_0000 DMA 2 initial source DISRCC2 0x060_0004 DMA 2 initial source control DIDST2 0x060_0008 DMA 2 initial destination DIDSTC2 0x060_000C DMA 2 initial destination control DCON2 0x060_0010 DMA 2 control DSTAT2 0x060_0014 R DMA 2 count DCSRC2 0x060_0018 W DMA 2 current source DCDST2 0x060_001C DMA 2 current destination DMASKTRIG2 0x060_0020 R/W DMA 2 mask trigger DISRC3 0x070_0000 W R/W DMA 3 initial source DISRCC3 0x070_0004 DMA 3 initial source control DIDST3 0x070_0008 DMA 3 initial destination DIDSTC3 0x070_000C DMA 3 initial destination control DCON3 0x070_0010 DMA 3 control DSTAT3 0x070_0014 R DMA 3 count DCSRC3 0x070_0018 DMA 3 current source DCDST3 0x070_001C DMA 3 current destination DMASKTRIG3 0x070_0020 R/W DMA 3 mask trigger
Preliminary product information describe products that are in development, 1-45
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
RTC (Real Time Clock)
Register
Name
Offset Acc.
Unit
Read/
Write
RTCCON 0x420_0040 B R/W RTC control TICINT 0x420_0044 Tick time count RTCALM 0x420_0050 RTC alarm control ALMSEC 0x420_0054 Alarm second ALMMIN 0x420_0058 Alarm minute ALMHOUR 0x420_005C Alarm hour ALMDATE 0x420_0060 Alarm day ALMMON 0x420_0064 Alarm month ALMYEAR 0x420_0068 Alarm year RTCRST 0x420_006C RTC round reset BCDSEC 0x420_0070 BCD second BCDMIN 0x420_0074 BCD minute BCDHOUR 0x420_0078 BCD hour BCDDATE 0x420_007C BCD day BCDDAY 0x420_0080 BCD date BCDMON 0x420_0084 BCD month BCDYEAR 0x420_0088 BCD year
Function
1-46 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Serial Communication
UART
Register
Name
Offset Acc.
Unit
Read/
Write
Function
ULCON0 0x440_0000 W R/W UART 0 line control UCON0 0x440_0004 UART 0 control UFCON0 0x440_0008 UART 0 FIFO control UMCON0 0x440_000C UART 0 modem control UTRSTAT0 0x440_0010 R UART 0 Tx/Rx status UERSTAT0 0x440_0014 UART 0 Rx error status UFSTAT0 0x440_0018 UART 0 FIFO status UMSTAT0 0x440_001C UART 0 modem status UTXH0 0x440_0020 B W UART 0 transmission hold URXH0 0x440_0024 R UART 0 receive buffer UBRDIV0 0x440_0028 W R/W UART 0 baud rate divisor ULCON1 0x440_4000 W R/W UART 1 line control UCON1 0x440_4004 UART 1 control UFCON1 0x440_4008 UART 1 FIFO control UMCON1 0x440_400C UART 1 modem control UTRSTAT1 0x440_4010 R UART 1 Tx/Rx status UERSTAT1 0x440_4014 UART 1 Rx error status UFSTAT1 0x440_4018 UART 1 FIFO status UMSTAT1 0x440_401C UART 1 modem status UTXH1 0x440_4020 B W UART 1 transmission hold URXH1 0x440_4024 R UART 1 receive buffer UBRDIV1 0x440_4028 W R/W UART 1 baud rate divisor
Preliminary product information describe products that are in development, 1-47
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
IIC-Bus Interface
Register
Name
Offset Acc.
Unit
Read/
Write
IICCON 0x460_0000 W R/W IIC control IICSTAT 0x460_0004 IIC status IICADD 0x460_0008 IIC address IICDS 0x460_000C IIC data shift IICSDADLY 0x460_0010 1-bit SDA output delay
IIS-Bus Interface
Register
Name
Offset Acc.
Unit
Read/
Write
IISCON 0x470_0000 W R/W IIS control IISMOD 0x470_0004 W IIS mode IISPSR 0x470_0008 W IIS prescaler IISFCON 0x470_000C W IIS FIFO control IISFIFO 0x470_0010 HW IIS FIFO entry
SPI Interface
Function
Function
Register
Name
Offset Acc.
Unit
Read/
Write
Function
SPCON0 0x450_0000 W R/W SPI channel 0 control SPSTA0 0x450_0004 R SPI channel 0 status SPPIN0 0x450_0008 R/W SPI channel 0 pin control SPPRE0 0x450_000C SPI channel 0 baud rate prescaler SPTDAT0 0x450_0010 SPI channel 0 Tx data SPRDAT0 0x450_0014 R SPI channel 0 Rx data SPCON1 0x450_0020 R/W SPI channel 1 control SPSTA1 0x450_0024 R SPI channel 1 status SPPIN1 0x450_0028 R/W SPI channel 1 pin control SPPRE1 0x450_002C SPI channel 1 baud rate prescaler SPTDAT1 0x450_0030 SPI channel 1 Tx data SPRDAT1 0x450_0034 R SPI channel 1 Rx data
1-48 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
AC97 Audio-CODEC Interface
Register
Name
Offset Acc.
Unit
Read/
Write
Function
AC_GLBCTRL 0x500_0000 W R/W AC97 global control AC_GLBSTAT 0x500_0004 R AC97 global status AC_CODEC_CMD 0x500_0008 R/W AC97 codec command AC_CODEC_STAT 0x500_000C R AC97 codec status AC_PCM_ADDR 0x500_0010 R AC97 PCM out/in channel FIFO address AC_MICADDR 0x500_0014 R AC97 MIC in channel FIFO address AC_PCMDATA 0x500_0018 R/W AC97 PCM out/in channel FIFO data AC_MICDATA 0x500_001C R/W AC97 MIC in channel FIFO data
USB Host
Register
Name
Offset Acc.
Unit
Read/
Write
Function
HcRevision 0x100_0000 W Control and status group HcControl 0x100_0004 HcCommonStatus 0x100_0008 HcInterruptStatus 0x100_000C HcInterruptEnable 0x100_0010 HcInterruptDisable 0x100_0014 HcHCCA 0x100_0018 Memory pointer group HcPeriodCuttentED 0x100_001C HcControlHeadED 0x100_0020 HcControlCurrentED 0x100_0024 HcBulkHeadED 0x100_0028 HcBulkCurrentED 0x100_002C HcDoneHead 0x100_0030 HcRmInterval 0x100_0034 Frame counter group HcFmRemaining 0x100_0038 HcFmNumber 0x100_003C
HcPeriodicStart 0x100_0040 HcLSThreshold 0x100_0044 HcRhDescriptorA 0x100_0048 Root HUB group HcRhDescriptorB 0x100_004C HcRhStatus 0x100_0050 HcRhPortStatus1 0x100_0054 HcRhPortStatus2 0x100_0058
Preliminary product information describe products that are in development, 1-49
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
USB Device
Register
Name
Offset Acc.
Unit
Read/
Write
Function
FUNC_ADDR_REG 0x4A0_0140 B R/W Function address PWR_REG 0x4A0_0144 Power management EP_INT_REG 0x4A0_0148 EP interrupt pending and clear USB_INT_REG 0x4A0_0158 USB interrupt pending and clear EP_INT_EN_REG 0x4A0_015C Interrupt enable USB_INT_EN_REG 0x4A0_016C Interrupt enbale FRAME_NUM1_REG 0x4A0_0170 R Frame number lower byte INDEX_REG 0x4A0_0178 R/W Register index EP0_CSR 0x4A0_0184 Endpoint 0 status IN_CSR1_REG 0x4A0_0184 In endpoint control status IN_CSR2_REG 0x4A0_0188 In endpoint control status MAXP_REG 0x4A0_0180 Endpoint max packet OUT_CSR1_REG 0x4A0_0190 Out endpoint control status OUT_CSR2_REG 0x4A0_0194 Out endpoint control status OUT_FIFO_CNT1_REG 0x4A0_0198 R Endpoint out write count OUT_FIFO_CNT2_REG 0x4A0_019C Endpoint out write count EP0_FIFO 0x4A0_01C0 R/W Endpoint 0 FIFO EP1_FIFO 0x4A0_01C4 Endpoint 1 FIFO EP2_FIFO 0x4A0_01C8 Endpoint 2 FIFO EP3_FIFO 0x4A0_01CC Endpoint 3 FIFO EP4_FIFO 0x4A0_01D0 Endpoint 4 FIFO EP1_DMA_CON 0x4A0_0200 EP1 DMA interface control EP1_DMA_UNIT 0x4A0_0204 EP1 DMA Tx unit counter EP1_DMA_FIFO 0x4A0_0208 EP1 DMA Tx FIFO counter EP1_DMA_TTC_L 0x4A0_020C EP1 DMA total Tx counter EP1_DMA_TTC_M 0x4A0_0210 EP1 DMA total Tx counter EP1_DMA_TTC_H 0x4A0_0214 EP1 DMA total Tx counter EP2_DMA_CON 0x4A0_0218 B R/W EP2 DMA interface control EP2_DMA_UNIT 0x4A0_021C EP2 DMA Tx Unit counter EP2_DMA_FIFO 0x4A0_0220 EP2 DMA Tx FIFO counter EP2_DMA_TTC_L 0x4A0_0224 EP2 DMA total Tx counter EP2_DMA_TTC_M 0x4A0_0228 EP2 DMA total Tx counter EP2_DMA_TTC_H 0x4A0_022C EP2 DMA total Tx counter EP3_DMA_CON 0x4A0_0240 EP3 DMA interface control
1-50 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
USB Device (Continued)
Register
Name
Offset Acc.
Unit
Read/
Write
Function
EP3_DMA_UNIT 0x4A0_0244 EP3 DMA Tx unit counter EP3_DMA_FIFO 0x4A0_0248 EP3 DMA Tx FIFO counter EP3_DMA_TTC_L 0x4A0_024C EP3 DMA total Tx counter EP3_DMA_TTC_M 0x4A0_0250 EP3 DMA total Tx counter EP3_DMA_TTC_H 0x4A0_0254 EP3 DMA total Tx counter EP4_DMA_CON 0x4A0_0258 EP4 DMA interface control EP4_DMA_UNIT 0x4A0_025C EP4 DMA Tx Unit counter EP4_DMA_FIFO 0x4A0_0260 EP4 DMA Tx FIFO counter EP4_DMA_TTC_L 0x4A0_0264 EP4 DMA total Tx counter EP4_DMA_TTC_M 0x4A0_0268 EP4 DMA total Tx counter EP4_DMA_TTC_H 0x4A0_026C EP4 DMA total Tx counter
Preliminary product information describe products that are in development, 1-51
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
IrDA
Register
Name
Offset Acc.
Unit
Read/
Write
Function
IrDA _CNT 0x180_0000 W R/W IrDA control IrDA_MDR 0x180_0004 IrDA mode definition IrDA_CNF 0x180_0008 IrDA interrupt / DMA configuration IrDA _IER 0x180_000C IrDA interrupt enable IrDA _IIR 0x180_0010 R IrDA interrupt identification IrDA _LSR 0x180_0014 IrDA line status IrDA _FCR 0x180_0018 R/W IrDA FIFO control IrDA _PLR 0x180_001C IrDA preamble length IrDA_RBR 0x180_0020 IrDA receiver & transmitter buffer IrDA_TXNO 0x180_0024 R The total number of data bytes remained in Tx FIFO IrDA_RXNO 0x180_0028 The total number of data bytes remained in Rx FIFO IrDA _TXFLL 0x180_002C R/W IrDA transmit frame-length register low IrDA _TXFLH 0x180_0030 IrDA transmit frame-length register high IrDA _RXFLL 0x180_0034 IrDA receive frame-length register low
IrDA _RXFLH 0x180_0038 IrDA receive frame-length register high
1-52 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Parallel Communication
Modem Interface
Register
Name
Offset Acc.
Unit
Read/
Write
Function
INT2AP 0x118_0000 W R/W Interrupt request to AP register INT2MDM 0x118_0004 Interrupt request to modem register
GPIO
Register
Name
Offset Acc.
Unit
Read/
Write
Function
GPCON_U 0x480_0000 W R/W GPIO ports configuration register GPCON_M 0x480_0004 GPIO ports configuration register GPCON_L 0x480_0008 GPIO ports configuration register GPDAT 0x480_000C GPIO ports data register GPPU 0x480_0010 GPIO ports pull-up control register EXTINTC0 0x480_0018 External interrupt control register 0 EXTINTC1 0x480_001C External interrupt control register 1 EXTINTC2 0x480_0020 External interrupt control register 2 EINTFLT0 0x480_0024 External interrupt filter control register 0 EINTFLT1 0x480_0028 External interrupt filter control register 1 EINTMASK 0x480_0034 External interupt mask register EINTPEND 0x480_0038 External interupt pending register PERIPU 0x480_0040 Peri. ports pull-up control register ALIVECON 0x480_0044 Alive control register GPDAT_SLEEP 0x480_0048 GPIO output data for sleep mode GPOEN_SLEEP 0x480_004C GPIO output enable control for sleep mode GPPU_SLEEP 0x480_0050 GPIO pull-up control register for sleep mode PERIDAT_SLEEP0 0x480_0054 Peri. ports output data control register 0 for sleep
mode
PERIDAT_SLEEP1 0x480_0058 Peri. ports output data control register 1 for sleep
mode
PERIOEN_SLEEP0 0x480_005C Peri. ports output control register 0 for sleep mode
PERIOEN_SLEEP1 0x480_0060 Peri. ports output control register 1 for sleep mode
PERIPU_SLEEP 0x480_0064 Peri. ports pull-up control register for slee mode RSTCNT 0x480_0068 Reset count compare register GPRAM0~15 0x480_0080
General purpose RAM array
~0x480_00BC
Preliminary product information describe products that are in development, 1-53
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
1-54 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Image/Video Processing
Camera Interface
Register
Name
Offset Acc.
Unit
Read/
Write
Function
CISRCFMT 0x800_0000 W R/W Input source format CIWDOFST 0x800_0004 Window offset register CIGCTRL 0x800_0008 Global control register CICOYSA1 0x800_0018 CICOYSA2 0x800_001C CICOYSA3 0x800_0020 CICOYSA4 0x800_0024 CICOCBSA1 0x800_0028 CICOCBSA2 0x800_002C CICOCBSA3 0x800_0030 CICOCBSA4 0x800_0034 CICOCRSA1 0x800_0038 CICOCRSA2 0x800_003C CICOCRSA3 0x800_0040 CICOCRSA4 0x800_0044
st
frame start address for codec DMA
Y 1
nd
frame start address for codec DMA
Y 2
nd
frame start address for codec DMA
Y 3
th
frame start address for codec DMA
Y 4
st
frame start address for codec DMA
Cb 1
nd
frame start address for codec DMA
Cb 2
nd
frame start address for codec DMA
Cb 3
th
frame start address for codec DMA
Cb 4
st
frame start address for codec DMA
Cr 1
nd
frame start address for codec DMA
Cr 2
rd
frame start address for codec DMA
Cr 3
th
frame start address for codec DMA
Cr 4 CICOTRGFMT 0x800_0048 Target image format of codec DMA CICOCTRL 0x800_004C Codec DMA control related CICOSCPRERATIO 0x800_0050 Codec pre-scaler ratio control CICOSCPREDST 0x800_0054 Codec pre-scaler destination format CICOSCCTRL 0x800_0058 Codec main-scaler control CICOTAREA 0x800_005C Codec pre-scaler destination format CICOSTATUS 0x800_0064 R Codec path status CIPRCLRSA1 0x800_006C R/W CIPRCLRSA2 0x800_0070 CIPRCLRSA3 0x800_0074 CIPRCLRSA4 0x800_0078
RGB 1
RGB 2
RGB 3
RGB 4
st
frame start address for preview DMA
nd
frame start address for preview DMA
rd
frame start address for preview DMA
th
frame start address for preview DMA CIPRTRGFMT 0x800_007C Target image format of preview DMA CIPRCTRL 0x800_0080 Preview DMA control related CIPRSCPRERATIO 0x800_0084 Preview pre-scaler ratio control CIPRSCPREDST 0x800_0088 Preview pre-scaler destination format CIPRSCCTRL 0x800_008C Preview main-scaler control CIPRTAREA 0x800_0090 Preview pre-scaler destination format CIPRSTATUS 0x800_0098 R Preview path status CIIMGCPT 0x800_00A0 R/W Image capture enable command
Preliminary product information describe products that are in development, 1-55
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Video POST
Register
Name
Offset Acc.
Unit
Read/
Write
Function
MODE 0xA10_0000 W R/W Mode Register [9:0] PreScale_Ratio 0xA10_0004 Pre-Scale ratio for vertical and horizontal. PreScaleImgSize 0xA10_0008 Pre-Scaled image size SRCImgSize 0xA10_000C Source image size MainScale_H_Ratio 0xA10_0010 Main scale ratio along to horizontal direction MainScale_V_Ratio 0xA10_0014 Main scale ratio along to vertical direction DSTImgSize 0xA10_0018 Destination image size PreScale_SHFactor 0xA10_001C Pre-scale shift factor ADDRStart_Y 0xA10_0020 DMA Start address for Y or RGB component ADDRStart_Cb 0xA10_0024 DMA Start address for Cb component ADDRStart_Cr 0xA10_0028 DMA Start address for Cr component ADDRStart_RGB 0xA10_002C DMA Start address for RGB component ADDREnd_Y 0xA10_0030 DMA End address for Y or RGB component ADDREnd_Cb 0xA10_0034 DMA End address for Cb component ADDREnd_Cr 0xA10_0038 DMA End address for Cr component ADDREnd_RGB 0xA10_003C DMA End address for RGB component Offset_Y 0xA10_0040 Offset of Y component for fetching source image Offset_Cb 0xA10_0044 Offset of Cb component for fetching source
image Offset_Cr 0xA10_0048 Offset of Cr component for fetching source image Offset_RGB 0xA10_004C Offset of RGB component for restoring
destination image
1-56 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
ME
Register
Name
Offset Acc.
Unit
Read/
Write
Function
ME_CFSA 0x880_0000 W R/W Current Frame Start Address Register ME_PFSA 0x880_0004 Previous Frame Start Address Register ME_MVSA 0x880_0008 Motion Vector Start Address Register ME_CMND 0x880_000C Command Register ME_STAT_SWR 0x880_0010
Status & S/W Reset Register
ME_CNFG 0x880_0014 Configuration Register ME_IMGFMT 0x880_0018
Image Format Register
Preliminary product information describe products that are in development, 1-57
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
MC
Register
Name
Offset Acc.
Unit
Read/
Write
Function
MC_PFYSA_ENC 0x8C0_0000 W R/W Previous frame Y start address register for the
encoder MC_CFYSA_ENC 0x8C0_0004 MCed frame Y start address register for the
encoder MC_PFYSA_DEC 0x8C0_0008 Previous frame Y start address register for the
decoder MC_CFYSA_DEC 0x8C0_000C MCed frame Y start address register for the
decoder MC_PFCbSA_ENC 0x8C0_0010 Previous frame Cb start address register for the
encoder MC_PFCrSA_ENC 0x8C0_0014 Previous frame Cr start address register for the
encoder MC_CFCbSA_ENC 0x8C0_0018 MCed frame Cb start address register for the
encoder MC_CFCrSA_ENC 0x8C0_001C MCed frame Cr start address register for the
encoder MC_PFCbSA_DEC 0x8C0_0020 Previous frame Cb start address register for the
decoder MC_PFCrSA_DEC 0x8C0_0024 Previous frame Cr start address register for the
decoder MC_CFCbSA_DEC 0x8C0_0028 MCed frame Cb start address register for the
decoder MC_CFCrSA_DEC 0x8C0_002C MCed frame Cr start address register for the
decoder MC_MVSA_ENC 0x8C0_0030 Motion vector start address register for the
encoder MC_MVSA_DEC 0x8C0_0034 Motion vector start address register for the
decoder MC_CMND 0x8C0_0038 Command register MC_STAT_SWR 0x8C0_003C Status & S/W reset register MC_CNFG 0x8C0_0040 Configuration register MC_IMGFMT 0x8C0_0044 Image format register
1-58 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
DCTQ
Register
Name
Offset Acc.
Unit
Read/
Write
Function
SAYCF 0x900_0000 W R/W Current frame luminance start address SACBCF 0x900_0004 Current frame Cb start address SACRCF 0x900_0008 Current frame Cr start address SAYRF 0x900_000C Reconstruction frame luminance start address SACBRF 0x900_0010 Reconstruction frame Cb start address SACRRF 0x900_0014 Reconstruction frame Cr start address SAYDQF 0x900_0018 DCTQed frame luminance start address SACBDQF 0x900_001C DCTQed frame Cb start address SACRDQF 0x900_0020 DCTQed frame Cr start address SAQP 0x900_0024 Qp start address IMGSIZE 0x900_0028 Image horizontal and vertical pixel number SHQ 0x900_002C Short header quantization mode DCTQCTRL 0x900_0034 Control register
VLX
Register
Name
Offset Acc.
Unit
Read/
Write
Function
VLX_COMMON1 0x940_0000 W R/W VLX common control register1 VLX_FRAMESTARTY 0x940_0004 Y coeff. start address VLX_FRAMESTARTCB 0x940_0008 Cb coeff. frame start address VLX_FRAMESTARTCR 0x940_000C Cr coeff. frame start address VLC_CON1 0x940_0010 Control register in VLC mode VLC_CON2 0x940_0014 Reserved VLC_CON3 0x940_0018 VLC result external address VLC_CON4 0x940_001C Reserved VLD_CON1 0x940_0020 Control register in VLD mode VLD_CON2 0x940_0024 VLCed bit stream start address VLD_CON3 0x940_0028 Reserved VLX_OUT1 0x940_002C R VLX output information register 1 VLX_OUT2 0x940_0030 VLX output information register 2
Preliminary product information describe products that are in development, 1-59
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Display Control
TFT LCD Controller
Register Offset Acc.
R/W
Function
Unit
LCDCON1 0xA00_0000 W R/W LCD control 1 LCDCON2 0xA00_0004 R/W LCD control 2 LCDTCON1 0xA00_0008 R/W LCD time control 1 LCDTCON2 0xA00_000C R/W LCD time control 2 LCDTCON3 0xA00_0010 R/W LCD time control 3 LCDOSD1 0xA00_0014 R/W LCD OSD control register LCDOSD2 0xA00_0018 R/W Foreground image(OSD Image) left top position set LCDOSD3 0xA00_001C R/W Foreground image(OSD Image) right bottom
position set LCDSADDRB1 0xA00_0020 R/W frame buffer start address 1 (background buffer 1) LCDSADDRB2 0xA00_0024 R/W Frame buffer start address 2 (background buffer 2) LCDSADDRF1 0xA00_0028 R/W Frame buffer start address 1 (foreground buffer 1) LCDSADDRF2 0xA00_002C R/W Frame buffer start address 2 (foreground buffer 2) LCDEADDRB1 0xA00_0030 R/W Frame buffer end address 1 (background buffer 1) LCDEADDRB2 0xA00_0034 R/W Frame buffer end address 2 (background buffer 2) LCDEADDRF1 0xA00_0038 R/W Frame buffer end address 1 (foreground buffer 1) LCDEADDRF2 0xA00_003C R/W Frame buffer end address 2 (foreground buffer 2) LCDVSCRB1 0xA00_0040 R/W Virtual screen offsize and pagewidth
(Background buffer 1) LCDVSCRB2 0xA00_0044 R/W Virtual screen offsize and pagewidth
(Background buffer 2) LCDVSCRF1 0xA00_0048 R/W Virtual screen offsize and pagewidth
(Foreground buffer 1) LCDVSCRF2 0xA00_004C R/W Virtual screen offsize and pagewidth
(Foreground buffer 2) LCDINTCON 0xA00_0050 R/W LCD Interrupt Control LCDKEYCON 0xA00_0054 R/W Color key control 1 LCDKEYVAL 0xA00_0058 R/W Color key control 2 LCDBGCON 0xA00_005C R/W Back-ground color Control LCDFGCON 0xA00_0060 R/W Fore-ground color Control LCDDITHCON 0xA00_0064 R/W LCD dithering control for active matrix
1-60 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Input Devices
Keypad Interface
Register
Name
Offset Acc.
Unit
Read/
Write
Function
KEYDAT 0x490_0000 W R/W The data register for KEYPAD input KEYINTC 0x490_0004 KEYPAD input ports interrupt control KEYFLT0 0x490_0008 KEY PAD input filter control KEYFLT1 0x490_000C KEY PAD input filter control KEYMAN 0x490_0010 KEYPAD manual scan control
Analog-to-Digital Converter and Touch Screen Interface
Register
Name
Offset Acc.
Unit
Read/
Write
Function
ADCCON 0x580_0000 W R/W ADC control ADCTSC 0x580_0004 ADC touch screen control ADCDLY 0x580_0008 ADC start or interval delay ADCDAX 0x580_000C R ADC conversion data register X ADCDAY 0x580_0010 ADC conversion data register Y
Preliminary product information describe products that are in development, 1-61
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
PRODUCT OVERVIEW S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
Storage Devices
SD and SDIO / MMC
Register
Name
Offset Acc.
Unit
Read/
Write
Function
SDICON 0x600_0000 W R/W SDI control SDIPRE 0x600_0004 SDI buad rate prescaler SDICARG 0x600_0008 SDI command argument SDICCON 0x600_000C SDI command control SDICSTA 0x600_0010 R/(C) SDI command status SDIRSP0 0x600_0014 R SDI response SDIRSP1 0x600_0018 SDI response SDIRSP2 0x600_001C SDI response SDIRSP3 0x600_0020 SDI response SDIDTIMER 0x600_0024 R/W SDI data / busy timer SDIBSIZE 0x600_0028 SDI block size SDIDCON 0x600_002C W R/W SDI data control SDIDCNT 0x600_0030 R SDI data remain counter SDIDSTA 0x600_0034 R/(C) SDI data status SDIFSTA 0x600_0038 R/(C) SDI FIFO status SDIIMSK 0x600_003C R/W SDI interrupt mask SDIDAT0 0x600_0040 B, HW, W SDI data0 SDIDAT1 0x600_0044 W SDI data1 SDIDAT2 0x600_0048 SDI data2 SDIDAT3 0x600_004C SDI data3
1-62 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) PRODUCT OVERVIEW
Memory Stick
Register
Name
Offset Acc.
Unit
Read/
Write
Function
MSPRE 0x610_0000 W R/W Prescaler control MSFINTCON 0x610_0004 FIFO interrupt control TP_CMD 0x610_8000 Transfer protocol command CTRL_STA 0x610_8004 Command and status DAT_FIFO 0x610_8008 Data FIFO INTCTRL_STA 0x610_800C Interrupt control and status INS_CON 0x610_8010 INS port control ACMD_CON 0x610_8014 Auto command and polarity control ATP_CMD 0x610_8018 Auto transfer protocol command
System Management
PLL Clock Control and Power Management
Register
Name
Offset Acc.
Unit
Read/
Write
Function
LOCKTIME 0x000_0000 W R/W PLL lock time counter OSCWSET 0x000_0004 OSC settle-down wait time setting MPLLCON 0x000_0010 MPLL configuration UPLLCON 0x000_0014 UPLL configuration CLKCON 0x000_0020 Clock generator control CLKSRC 0x000_0024 Slow clock control CLKDIVN 0x000_0028 Clock divider control PWRMAN 0x000_0030 Power management SOFTRESET 0x000_0038 Software reset
IMPORTANT NOTES ABOUT S3C24A0A SPECIAL REGISTERS
1. The special registers have to be accessed by the recommended access unit.
2. All registers except ADC registers, RTC registers and UART registers must be read/written in word unit (32bit) at little/big endian.
3. It is very important that the ADC registers, RTC registers and UART registers be read/written by the specified access unit and the specified address. Moreover, one must carefully consider which endian mode is used.
4. W : 32-bit register, which must be accessed by LDR/STR or int type pointer (int *). HW : 16-bit register, which must be accessed by LDRH/STRH or short int type pointer (short int *). B : 8-bit register, which must be accessed by LDRB/STRB or char type pointer (char int *).
.
Preliminary product information describe products that are in development, 1-63
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) SROM CONTROLLER
2 SROM CONTROLLER
OVERVIEW
S3C24A0A support external 16-bit bus for NAND Flash/ NOR Flash/ PROM/ SRAM external memory. It’s not shared with SDRAM bus and support up to 3 Bank for one controller. From now on, we will refer this controller as SROM Controller.
Below figure show the Address Map configuration of S3C24A0A SROM Controller. S3C24A0A SROM Controller has 3 kinds of configuration. If user want to use NAND boot loader, it’ll be selected the third configuration which stepping stone (SRAM 4KB) is on the 0x00000000. And If user want to use ROM type boot, it’ll be selected the first or second configuration by selecting SFR (Special Function Register) of SROM Controller. In this case user can use NAND Flash Memory for other usage. At the first configuration, Stepping Stone is used just for buffer of any master.
0xFFFF_FFFF
0x5000_0000
0x4000_0000
0x2000_0000
0x1000_0000
0x0c00_0000
0x0800_0000
0x0400_0000
0x0000_0000
SROM_BW[9] = 0 TMODE[2:0] = 000
Reserved
AHB/APB SFRs
Reserved Reserved Reserved
SDRAM
(BANK0/1)
SRAM Buffer
(4KB, No CS)
SROM
(BANK2, XrCSn2)
SROM
(BANK1, XrCSn1)
SROM
(BANK0, XrCSn0)
[Not using NAND flash for boot ROM]
SROM_BW[9] = 1 TMODE[2:0] = 000
Reserved Reserved
AHB/APB SFRs AHB/APB SFRs
SDRAM SDRAM
(BANK0/1) (BANK0/1)
Reserved Reserved
Stepping stone
(4KBytes)
SROM
(BANK1, XrCSn1) (BANK1, XrCSn1)
SROM
(BANK0, XrCSn0)
TMODE[2:0] = 001
(BANK2, XrCSn2)
[Using NAND flash for boot ROM]
SROM
SROM
Stepping stone
(4KBytes)
256MB
256MB
64MB
64MB
64MB
64MB
Assigned for Special Function Registers
Assigned for SDRAM Bank0/1 Accessible Region
Assigned for SROM Bank0/1/2 Accessible Region
NOTES:
1. SROM means ROM or SRAM type memory.
2. SFR means Special Function Register.
Figure 2-1. SROM Controller Address Mapping
Preliminary product information describe products that are in development, 2-1
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
SROM CONTROLLER S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
FEATURE
Supports SRAM, various ROMs and NOR flash memory
Supports only 8 or 16-bit data bus
Address space : Up to 64MB per Bank
Supports 3 banks (XrCSn[2:0])
Boot by NAND Flash Memory : XrCSn0’s owner is not SROM Controller but NAND Controller. Boot by other Memory (Nor Flash or ROM): XrCSn2’s owner is either SROM Controller or NAND Controller (User can choose it by setting SFR).
Fixed memory bank start address
External wait to extend the bus cycle
Support byte, half-word and word access for external memory
BLOCK DIAGRAM
AHB I/F for SROM SFR
SROM
Decoder
AHB I/F for SROM MEM
SFR
Control &
State Machine
SROM I/F
Singal
Generation
SROM MEM I/F
Figure 2-2. SROM Controller Block Diagram
2-2 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) SROM CONTROLLER
FUNCTION DESCRIPTION
SROM Controller support SROM interface for Bank0 to Bank2. In case of NAND boot, SROM controller can’t control Bank0 because of its mastership is on NAND Flash Controller. In case of ROM boot, as it mentioned before, it is possible that Bank2’s master is NAND Flash Controller by setting of users.
Address-bus : 26-bit Data-bus : 8/16
SRAM/ROM/
NOR Flash/
NAND Flash
Bank 0
SROM
Controller
MEMORY BUS #1
SRAM/ROM/
NOR Flash
SRAM/ROM/
NOR Flash/
NAND Flash
Bank 1
Bank 2
Figure 2-3. Memory Interface Block Diagram
Preliminary product information describe products that are in development, 2-3
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
SROM CONTROLLER S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
XrWAITn Pin Operation
If the WAIT corresponding to each memory bank is enabled, the XrOEn duration should be prolonged by the external XrWAITn pin while the memory bank is active. XrWAITn is checked from Tacc-1.The XrOEn will be deasserted at the next clock after sampling XrWAITn is high. The XrWEn signal have the same relation with XrOEn.
HCLK
XrADDR
[25:0]
XrCSn
[2:0]
Tacs
XrOEn
XrWAITn
XrDATA
[15:0]
(R)
Tacc=4
Tcos
Figure 2-4. XrWAITn Pin Operation
Delayed
Sampling XrWAITn
2-4 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) SROM CONTROLLER
X
PROGRAMMABLE ACCESS CYCLE WRITE TO READ WAVEFORM
HCLK
XrADDR
[25:0]
XrCSn
XrOEn
XrWEn
rnWBE
XrDATA
[15:0]
XrDATA
[15:0]
[2:0]
[1:0]
(R)
(W)
Tacs
Tcos
Tacs = 1 cycle Tcos = 1 cycle Tacc = 2 cycles
Tcoh
c
c
a
T
Tcoh = 1 cycle Tcah = 2 cycles
Figure 2-5. Programmable Access Cycle
Tcah
Preliminary product information describe products that are in development, 2-5
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
SROM CONTROLLER S3C24A0A RISC MICROPROCESSOR (Preliminary Spec)
SPECIAL FUNCTION REGISTERS
SROM BUS WIDTH & WAIT CONTRL REGISTER(SROM_BW)
Register Address R/W Description Reset Value
SROM_BW 0x40C20000 R/W SROM Bus width & wait control 0x000x
SROM_BW Bit Description Initial State
Reserved [15:9] Reserved 0x00
BankNum [9] 0 = XrCSn2’s owner is SROM Controller (In this case Stepping Stone
is just used as 4KB SRAM buffer)
1 = XrCSn2’s owner is NAND Flash Controller
ST2 [8] This bit determines SRAM for using UB/LB for bank2
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
WS2 [7] This bit determines WAIT status for bank2
0 = WAIT disable 1 = WAIT enable
DW2 [6] Indicates data bus width for bank2
0 = 8-bit 1 = 16-bit
ST1 [5] This bit determines SRAM for using UB/LB for bank1
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
WS1 [4] This bit determines WAIT status for bank1
0 = WAIT disable 1 = WAIT enable
DW1 [3] Indicates data bus width for bank1
0 = 8-bit 1 = 16-bit
ST0 [2] This bit determines SRAM for using UB/LB for bank0
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0]) 1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
WS0 [1] This bit determines WAIT status for bank0
0 = WAIT disable 1 = WAIT enable
DW0 [0] Indicates data bus width for bank0 (read only)
0 = 8-bit 1 = 16-bit
0x00
0
0
0
0
0
0
0
0
H/W Set
* DW0 is read only. The value is written by external configuration pin (XfNFBW)
2-6 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
S3C24A0A RISC MICROPROCESSOR (Preliminary Spec) SROM CONTROLLER
SROM BANK CONTROL REGISTER (SROM_BC: XrCSn0 ~ XrCSn2)
Register Address R/W Description Reset Value
SROM_BC0 0x40C20004 R/W SROM Bank0 control register 0x0700 SROM_BC1 0x40C20008 R/W SROM Bank1 control register 0x0700 SROM_BC2 0x40C2000C R/W SROM Bank2 control register 0x0700
SROM_BCn Bit Description Initial State
Tacs [15:14] Adress set-up before XrCSn[2:0]
00
00 = 0 clock 01 = 2 clock 10 = 4 clocks 11 = 8 clocks
Tcos [13:12] Chip selection set-up XrOEn
00
00 = 0 clock 01 = 2 clock 10 = 4 clocks 11 = 8 clocks
Reserved [11] Reserved 0
Tacc [10:8] Access cycle
111
000 = 2 clock 001 = 3 clocks 010 = 4 clocks 011 = 10 clocks 100 = 12 clocks 101 = 14 clocks 110 = 16 clock 111 = 20 clocks
Tcoh [7:6] Chip selection hold on XrOEn
00
00 = 0 clock 01 = 2 clock 10 = 4 clocks 11 = 8 clocks
Tcah [5:4] Address holding time after XrCSn[2:0]
00
00 = 0 clock 01 = 2 clock 10 = 4 clocks 11 = 8 clocks
Reserved [3:0] Reserved 0000
Preliminary product information describe products that are in development, 2-7
for which full characterization data and associated errata are not yet available. Specifications and information herein are subject to change without notice.
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