SAMSUNG S3C24A0A User Guide

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S3C24A0A

32-BIT RISC

MICROPROCESSOR

USER'S MANUAL

Revision 0.4

(Preliminary)

Important Notice

The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.

Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes.

This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others.

Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.

S3C24A0A 32-Bit RISC Microprocessor User's Manual, Revision 0.4 Publication Number: 20-S3-CS3C24A0A-112004

"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts.

Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur.

Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product.

All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics.

Samsung Electronics' microcontroller business has been awarded full ISO-14001

certification (BVQ1 Certificate No. 9330). All semiconductor products are designed

and manufactured in accordance with the highest quality standards and objectives.

Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung- Eup Yongin-City, Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 449-900

TEL: (82)-(031)-209-1490 FAX: (82) (331) 209-1909 Home-Page URL: Http://www.samsungsemi.com/

Printed in the Republic of Korea

Table of Contents

Chapter 1 Product Overview

Architectural Overview ..................................................................................................................................1-1

Features................................................................................................................................................1-2

Microprocessor and Overall Architecture .............................................................................................1-2

Memory Subsystem ..............................................................................................................................1-2

General Peripherals..............................................................................................................................1-3

Serial Communication ..........................................................................................................................1-3

Parallel Communication........................................................................................................................1-4

Image and Video Processing................................................................................................................1-4

Display Control .....................................................................................................................................1-6

Input Devices ........................................................................................................................................1-6

Storage Devices ...................................................................................................................................1-7

System Management............................................................................................................................1-7

Electrical Characteristics ......................................................................................................................1-7

Package................................................................................................................................................1-7

Pin Assignment.....................................................................................................................................1-9

Pin Descriptions ............................................................................................................................................1-30

I/O Signal Descriptions .........................................................................................................................1-30

Address MAP ................................................................................................................................................1-38

Address Space Assignment Overview .................................................................................................1-38

Device Specific Address Space............................................................................................................1-39

Internal Registers..................................................................................................................................1-42

Important Notes About S3C24A0A Special Registers .........................................................................1-62

Chapter 2 SROM Controller

Overview........................................................................................................................................................2-1

Feature .................................................................................................................................................2-2

Block Diagram ......................................................................................................................................2-2

Function Description.............................................................................................................................2-3

Programmable Access Cycle Write to Read Waveform.......................................................................2-5

Special Function Registers ...........................................................................................................................2-6

Srom Bus Width & Wait Contrl Register(SROM_BW)..........................................................................2-6

Srom Bank Control Register (SROM_BC: XrCSn0 ~ XrCSn2)............................................................2-7

S3C24A0A MICROPROCESSOR iii

Table of Contents (Continued)

Chapter 3 SDRAM Controller

Overview....................................................................................................................................................... 3-1

Selection of SDRAM ..................................................................................................................................... 3-2

SELF Refresh....................................................................................................................................... 3-2

SDRAM Initialization Sequence........................................................................................................... 3-3

SDRAM Configuration Register.................................................................................................................... 3-6

SDRAM Control Register ..................................................................................................................... 3-7

Refresh Control Register ..................................................................................................................... 3-8

Chapter 4 NAND Flash Controller

Overview....................................................................................................................................................... 4-1

Features ............................................................................................................................................... 4-1

Pin Configuration ................................................................................................................................. 4-2

Block Diagram .............................................................................................................................................. 4-3

Boot Loader Function ................................................................................................................................... 4-4

Auto Load Mode ........................................................................................................................................... 4-6

Auto Load Programming Guide ........................................................................................................... 4-6

Auto Store Mode........................................................................................................................................... 4-7

Auto Store Programming Guide........................................................................................................... 4-7

Software Mode.............................................................................................................................................. 4-8

Stepping Stone (4K-Byte SRAM) ................................................................................................................. 4-9

Error Correction Code .................................................................................................................................. 4-9

ECC Module Features ......................................................................................................................... 4-10

ECC Programming Guide .................................................................................................................... 4-10

NAND Flash Memory Configurations ........................................................................................................... 4-11

NAND Flash Controller Special Registers.................................................................................................... 4-13

Configuration Register ......................................................................................................................... 4-13

Control Register ................................................................................................................................... 4-14

Command Register .............................................................................................................................. 4-15

Address Register ................................................................................................................................. 4-15

Main Data Area ECC0 Register ........................................................................................................... 4-16

Main Data Area ECC1 Register ........................................................................................................... 4-16

Main Data Area ECC2 Register ........................................................................................................... 4-16

Main Data Area ECC3 Register ........................................................................................................... 4-17

Spare Area ECC0 Register................................................................................................................. 4-17

Spare Area ECC1 Register.................................................................................................................. 4-17

Control Status Register........................................................................................................................ 4-18

ECC0 Status Register.......................................................................................................................... 4-19

ECC1 Status Register.......................................................................................................................... 4-19

Main Data Area ECC0 Status Register................................................................................................ 4-20

Main Data Area ECC1 Status Register................................................................................................ 4-20

Spare Area ECC Status Register ........................................................................................................ 4-20

Start Block Address Register ............................................................................................................... 4-21

END Block Address Register ............................................................................................................... 4-21

iv S3C24A0A MICROPROCESSOR

Table of Contents (Continued)

Chapter 5 Bus Matrix

Overview........................................................................................................................................................5-1

Special Function Registers ...........................................................................................................................5-2

SROMC/NFLASHC Arbiter Priority Register (Priority 0) ......................................................................5-2

SDRAMC Arbiter Priority Register (Priority 1) ......................................................................................5-2

Chapter 6 Interrupt Controller

Overview........................................................................................................................................................6-1

Functional Description...................................................................................................................................6-2

F-Bit and I-Bit Of PSR (Program Status Register) ...............................................................................6-2

Interrupt Mode ......................................................................................................................................6-2

Interrupt Pending Register....................................................................................................................6-2

Interrupt Mask Register ........................................................................................................................6-2

Interrupt Sources ..................................................................................................................................6-3

Interrupt Priority Generating Block .......................................................................................................6-4

Vectored Interrupt Mode (Only for IRQ) ...............................................................................................6-5

Source Pending Register (SRCPND)...................................................................................................6-7

Interrupt Mode Register (INTMOD) ......................................................................................................6-9

Interrupt Mask Register (INTMSK) .......................................................................................................6-11

Priority Register (PRIORITY)................................................................................................................6-13

Interrupt Pending Register (INTIPND)..................................................................................................6-14

Interrupt Offset Register (INTOFFSET)................................................................................................6-16

Sub Source Pending Register (SUBSRCPND)....................................................................................6-17

Interrupt Sub Mask Register (INTSUBMSK) ........................................................................................6-18

Vectored Interrupt Mode Register (VECT_INT_MODE) ......................................................................6-19

Vector Address Register (VAR)............................................................................................................6-19

S3C24A0A MICROPROCESSOR v

Table of Contents (Continued)

Chapter 7 PWM Timer

Overview....................................................................................................................................................... 7-1

Feature................................................................................................................................................. 7-1

PWM Timer Operation .................................................................................................................................. 7-3

Prescaler & Divider .............................................................................................................................. 7-3

Basic Timer Operation ......................................................................................................................... 7-3

Auto-Reload & Double Buffering.......................................................................................................... 7-4

TIMER Initialization Using Manual Update Bit and Inverter Bit ........................................................... 7-4

Example of a Timer Operation ............................................................................................................. 7-5

PWM (Pulse Width Modulation)........................................................................................................... 7-6

Output Level Control ............................................................................................................................ 7-7

DEAD Zone Generator......................................................................................................................... 7-8

DMA Request Mode............................................................................................................................. 7-9

PWM Timer Control Registers...................................................................................................................... 7-10

Timer Configuration Register 0 (TCFG0)............................................................................................. 7-10

Timer Configuration Register 1 (TCFG1)............................................................................................. 7-11

Timer Control Register (TCON) ........................................................................................................... 7-12

Timer 0 Count Observation Register (TCNTO0) ................................................................................. 7-13

Timer 1 Count Buffer Register & Compare Buffer Register (TCNTB1, TCMPB1) .............................. 7-14

Timer 1 Count Observation Register(TCNTO1) .................................................................................. 7-14

Timer 2 Count Buffer Register & Compare Buffer Register (TCNTB2, TCMPB2) .............................. 7-15

Timer 2 Count Observation Register (TCNTO2) ................................................................................. 7-15

Timer 3 Count Buffer Register & Compare Buffer Register (TCNTB3, TCMPB3) .............................. 7-16

Timer 3 Count Observation Register (TCNTO3) ................................................................................. 7-16

Timer 4 Count Buffer Register (TCNTB4)............................................................................................ 7-17

Timer 4 Count Observation Register (TCNTO4) ................................................................................. 7-17

Chapter 8 Watchdog Timer

Overview....................................................................................................................................................... 8-1

Features ............................................................................................................................................... 8-1

Watchdog Timer Operation.................................................................................................................. 8-2

WTDAT & WTCNT............................................................................................................................... 8-2

Consideration of Debugging Environment ........................................................................................... 8-2

Watchdog Timer Special Registers .............................................................................................................. 8-3

Watchdog Timer Control Register (WTCON) ...................................................................................... 8-3

Watchdog Timer Data Register (WTDAT) ........................................................................................... 8-4

Watchdog Timer Count Register (WTCNT)......................................................................................... 8-4

vi S3C24A0A MICROPROCESSOR

Table of Contents (Continued)

Chapter 9 DMA

Overview........................................................................................................................................................9-1

DMA Request Sources .........................................................................................................................9-1

DMA Operation..............................................................................................................................................9-2

External DMA DREQ/DACK Protocol...................................................................................................9-2

Examples of Possible Cases ................................................................................................................9-5

DMA Special Registers.........................................................................................................................9-6

DMA Initial Source Register (DISRC)...................................................................................................9-6

DMA Initial Source Control Register (DISRCC) ...................................................................................9-6

DMA Initial Destination Register (DIDST) ............................................................................................9-7

DMA Initial Destination Control Register (DIDSTC) .............................................................................9-7

DMA Control Register (DCON).............................................................................................................9-8

DMA Status Register (DSTAT).............................................................................................................9-10

DMA Current Source Register (DCSRC) .............................................................................................9-10

Current Destination Register (DCDST) ................................................................................................9-11

DMA Mask Trigger Register (DMASKTRIG) ........................................................................................9-12

S3C24A0A MICROPROCESSOR vii

Table of Contents (Continued)

Chapter 10 RTC (Real Time Clock)

Overview....................................................................................................................................................... 10-1

Feature................................................................................................................................................. 10-1

Real Time Clock Operation.................................................................................................................. 10-2

Leap Year Generator ........................................................................................................................... 10-2

Read/Write Registers........................................................................................................................... 10-2

Backup Battery Operation.................................................................................................................... 10-2

ALARM Function.................................................................................................................................. 10-3

TICK Time Interrupt ............................................................................................................................. 10-3

Round Reset Function ......................................................................................................................... 10-3

32.768kHz X-Tal Connection Example............................................................................................... 10-3

Real Time Clock Special Registers .............................................................................................................. 10-4

Real Time Clock Control Register (RTCCON) .................................................................................... 10-4

TICK Time Count Register (TICNT)..................................................................................................... 10-4

RTC ALARM Control Register (RTCALM)........................................................................................... 10-5

ALARM Second Data Register (ALMSEC) .......................................................................................... 10-6

ALARM Min Data Register (ALMMIN) ................................................................................................. 10-6

ALARM Hour Data Register (ALMHOUR) ........................................................................................... 10-6

ALARM Date Data Register (ALMDATE) ............................................................................................ 10-7

ALARM Mon Data Register (ALMMON) .............................................................................................. 10-7

ALARM Year Data Register (ALMYEAR) ............................................................................................ 10-7

BCD Second Register (BCDSEC) ....................................................................................................... 10-8

BCD Minute Register (BCDMIN) ......................................................................................................... 10-8

BCD Hour Register (BCDHOUR) ........................................................................................................ 10-9

BCD Date Register (BCDDATE).......................................................................................................... 10-9

BCD Day Register (BCDDAY) ............................................................................................................. 10-9

BCD Month Register (BCDMON) ........................................................................................................ 10-10

BCD Year Register (BCDYEAR) ......................................................................................................... 10-10

viii S3C24A0A MICROPROCESSOR

Table of Contents (Continued)

Chapter 11 UART

Overview........................................................................................................................................................11-1

Features................................................................................................................................................11-1

Block Diagram ......................................................................................................................................11-2

Uart Operation ......................................................................................................................................11-3

Uart Special Registers...................................................................................................................................11-10

Uart Line Control Register ....................................................................................................................11-10

Uart Control Register............................................................................................................................11-11

Uart FIFO Control Register...................................................................................................................11-13

Uart Modem Control Register...............................................................................................................11-14

Uart Tx/Rx Status Register...................................................................................................................11-15

Uart Error Status Register ....................................................................................................................11-16

Uart FIFO Status Register ....................................................................................................................11-17

Uart Modem Status Register ................................................................................................................11-18

Uart Transmit Buffer Register(Holding Register & FIFO Register) ......................................................11-19

Uart Receive Buffer Register (Holding Register & FIFO Register) ......................................................11-19

Uart Baud Rate Divisor Register ..........................................................................................................11-20

Chapter 12 IrDA Controller

Overview........................................................................................................................................................12-1

Feature .................................................................................................................................................12-1

Block Diagram ......................................................................................................................................12-2

External Interface Signals.....................................................................................................................12-2

Function Description.............................................................................................................................12-3

Core Initialization Procedure ................................................................................................................12-9

Special Function Registers ...........................................................................................................................12-10

IrDA Control Register (IrDA_CNT) .......................................................................................................12-10

IrDA Mode Definition Register(IrDA_MDR) ..........................................................................................12-11

IrDA Interrupt / DMA Configuration Register (IrDA_CNF)....................................................................12-11

IrDA Interupt Enalble Register (IrDA_IER) ...........................................................................................12-12

IrDA Interupt Identification Register (IrDA_IIR) ....................................................................................12-13

IrDA Line Status Register (IrDA_LSR) .................................................................................................12-14

IrDA FIFO Control Register (IrDA_FCR) ..............................................................................................12-15

IrDA Preamble Length Register (IrDA_PLR)........................................................................................12-16

IrDA Total Number of Data Bytes Remained in Rx FIFO (IrDA_RXNO)..............................................12-17

IrDA Transmit Frame-Length Register Low (IrDA_TXFLL) .................................................................. 12-17

IrDA Transmit Frame-Length Register High (IrDA_TXFLH).................................................................12-17

IrDA Receiver Frame-Length Register Low (IrDA_RXFLL) .................................................................12-18

IrDA Receiver Frame-Length Register High (IrDA_RXFLH) ................................................................12-18

S3C24A0A MICROPROCESSOR ix

Table of Contents (Continued)

Chapter 13 IIC-Bus Interface

Overview....................................................................................................................................................... 13-1

The IIC-Bus Interface........................................................................................................................... 13-2

Start and Stop Conditions .................................................................................................................... 13-2

Data Transfer Format........................................................................................................................... 13-4

ACK Signal Transmission .................................................................................................................... 13-5

Read-Write Operation .......................................................................................................................... 13-6

Bus Arbitration Procedures.................................................................................................................. 13-6

Abort Conditions .................................................................................................................................. 13-6

Configuring the IIC-Bus........................................................................................................................ 13-6

Flowcharts of the Operations in Each Mode........................................................................................ 13-7

IIC-Bus Interface Special Registers.............................................................................................................. 13-11

Multi-Master IIC-Bus Control Register (IICCON)................................................................................. 13-11

Multi-Master IIC-Bus Control/Status Register (IICSTAT) .................................................................... 13-12

Multi-Master IIC-Bus Address Register (IICADD)................................................................................ 13-13

Multi-Master IIC-Bus Transmit/Receive Data Shift Register (IICDS) .................................................. 13-13

Multi-Master IIC-Bus Sdaout Delay Register (SDADLY) ..................................................................... 13-13

Chapter 14 IIS-Bus Interface

Overview....................................................................................................................................................... 14-1

Features ............................................................................................................................................... 14-1

Block Diagram...................................................................................................................................... 14-1

Functional Descriptions........................................................................................................................ 14-2

Transmit or Receive Only Mode .......................................................................................................... 14-2

Dma Transfer ....................................................................................................................................... 14-2

Transmit and Receive Mode................................................................................................................ 14-2

Audio Serial Interface Format....................................................................................................................... 14-3

IIS-Bus Format ..................................................................................................................................... 14-3

MSB(Left) Justified............................................................................................................................... 14-3

Sampling Frequency and Master Clock............................................................................................... 14-4

IIS-Bus Interface Special Registers.............................................................................................................. 14-5

IIS Control Register (IISCON).............................................................................................................. 14-5

IIS Mode Register (IISMOD) ................................................................................................................ 14-6

IIS Prescaler Register (IISPSR)........................................................................................................... 14-7

IIS FIFO Control Register (IISFCON) .................................................................................................. 14-7

IIS FIFO Register (IISFIFO) ................................................................................................................. 14-8

x S3C24A0A MICROPROCESSOR

Table of Contents (Continued)

Chapter 15 SPI Interface

Overview........................................................................................................................................................15-1

Features................................................................................................................................................15-1

Block Diagram ......................................................................................................................................15-2

SPI Operation................................................................................................................................................15-3

SPI Special Registers....................................................................................................................................15-6

SPI Control Register.............................................................................................................................15-6

SPI Status Register ..............................................................................................................................15-7

SPI Pin Control Register.......................................................................................................................15-8

SPI Baud Rate Prescaler Register .......................................................................................................15-9

SPI Tx Data Register ............................................................................................................................15-9

SPI Rx Data Register............................................................................................................................15-9

Chapter 16 AC97 Controller

Overview........................................................................................................................................................16-1

Feature .................................................................................................................................................16-1

AC97 Controller Operation............................................................................................................................16-2

Block Diagram ......................................................................................................................................16-2

Internal Data Path.................................................................................................................................16-3

Operation Flow Chart ....................................................................................................................................16-4

AC-link Digital Interface protocol...................................................................................................................16-5

AC-link Output Frame (SDATA_OUT)..................................................................................................16-6

AC-link Input Frame (SDATA_IN).........................................................................................................16-6

AC97 Powerdown..........................................................................................................................................16-7

AC97 Controller Special Registers................................................................................................................16-9

AC97 Global Control Register (AC_GLBCTRL)...................................................................................16-9

AC97 Global Status Register (AC_GLBSTAT).....................................................................................16-10

AC97 Codec Command Register (AC_CODEC_CMD) .......................................................................16-11

AC97 Codec Status Register (AC_CODEC_STAT).............................................................................16-11

AC97 PCM Out/In Channel FIFO Address Register (AC_PCMADDR) ...............................................16-11

AC97 MIC in Channel FIFO Address Register (AC_MICADDR) .........................................................16-12

AC97 PCM Out/In Channel FIFO Data Register (AC_PCMDATA)......................................................16-12

AC97 MIC in Channel FIFO Data Register (AC_MICDATA)................................................................16-12

S3C24A0A MICROPROCESSOR xi

Table of Contents (Continued)

Chapter 17 USB Host Controller

Overview....................................................................................................................................................... 17-1

USB Host Controller Special Registers ........................................................................................................ 17-2

OHCI Registers for USB Host Controller ............................................................................................. 17-2

Chapter 18 USB Device

Overview....................................................................................................................................................... 18-1

Feature................................................................................................................................................. 18-1

USB Device Special Registers ..................................................................................................................... 18-3

FUNC_ADDR_REG ............................................................................................................................. 18-5

Power Management Register (PWR_REG) ........................................................................................ 18-6

Interrupt Register (EP_INT_REG, USB_INT_REG) ............................................................................ 18-7

Interrupt Enable Register (EP_INT_EN_REG, USB_INT_REG)......................................................... 18-9

Frame Number Register (FPAME_NUM1_REG, FRAME_NUM2_REG) ........................................... 18-10

Index Register (INDEX_REG).............................................................................................................. 18-11

End Point0 Control Status Register (EP0_CSR) ................................................................................. 18-12

End Point in Control Status Register (IN_CSR1_REG, IN_CSR2_REG) ........................................... 18-13

End Point Out Control Status Register (OUT_CSR1_REG, OUT_CSR2_REG) ................................ 18-15

End Point FIFO Register (EPN_FIFO_REG)....................................................................................... 18-17

Max Packet Register (MAXP_REG) .................................................................................................... 18-17

End Point Out Write Count Register (OUT_FIFO_CNT1_REG, OUT_FIFO_CNT2_REG) ................ 18-18

DMA Interface Control Register (EPN_DMA_CON)............................................................................ 18-19

DMA Unit Counter Register (EPN_DMA_UNIT).................................................................................. 18-20

DMA FIFO Counter Register (EPN_DMA_FIFO) ................................................................................ 18-21

DMA Total Transfer Counter Register

(EPN_DMA_TTC_L, EPN_DMA_TTC_M, EPN_DMA_TTC_H) ......................................................... 18-22

xii S3C24A0A MICROPROCESSOR

Table of Contents (Continued)

Chapter 19 MODEM Interface

Overview........................................................................................................................................................19-1

Features................................................................................................................................................19-2

Hardware Interface ...............................................................................................................................19-2

Signal Description.................................................................................................................................19-2

Interrupt Ports .......................................................................................................................................19-2

Address Mapping..................................................................................................................................19-3

Timing Diagram ....................................................................................................................................19-4

Software Interface.................................................................................................................................19-5

Modem Interface Special Registers ..............................................................................................................19-6

Interrupt Request to AP Register (INT2AP) .........................................................................................19-6

Interrupt Request to Modem Register (INT2MDM) ..............................................................................19-6

Chapter 20 General Purpose I/O Ports

Overview........................................................................................................................................................20-1

Port Control Descriptions ..............................................................................................................................20-3

Gpio Port Configuration Register For Normal Mode (GPCON_U, GPCON_M, GPCON_L) ...............20-3

Gpio Port Data Register For Normal Mode (GPDAT) ..........................................................................20-3

Gpio Port Pull-Pu Control Register for Normal Mode (GPPU) ............................................................. 20-3

External Interrupt Control Register (Extintcn/ Eintfltn/ Eintmask/ Eintpend) ........................................20-3

Peripheral Port Pull-Up Control Register for Normal Mode (PERIPU).................................................20-3

Alive Control Register (ALIVECON) .....................................................................................................20-4

Gpio Output Control Register for Sleep Mode (GPOEN_SLEEP) .......................................................20-4

Gpio Pull-Up Control Register for Sleep Mode (GPPU_SLEEP) .........................................................20-4

Peripheral Port Output Data Register for Sleep Mode (PERIDAT_SLEEPN)......................................20-4

Peripheral Port Output Control Register for Sleep Mode (PERIOEN_SLEEPN) .................................20-4

Peripheral Port Pull-Up Control Register for Sleep Mode (PERIPU_SLEEP) .....................................20-4

Reset Count Compare Register (RstCnt).............................................................................................20-4

General Purpose RAM Array (GPRAMn) .............................................................................................20-4

I/O Port Control Register ...............................................................................................................................20-5

GPIO Upper Port Control Register (GPCON_U).................................................................................. 20-5

Gpio Middle Port Control Register (GPCON_M) ..................................................................................20-6

Gpio Lower Port Control Register (GPCON_L)....................................................................................20-7

Gpio Port Data Register (GPDAT)........................................................................................................20-8

Gpio Port Pull Up Resister Control Register (GPPU)........................................................................... 20-8

External Interrupt Control Register (EXTINTC0) ..................................................................................20-9

S3C24A0A MICROPROCESSOR xiii

Table of Contents (Continued)

Chapter 20 General Purpose I/O Ports (Continued)

External Interrupt Control Register (EXTINTC1) ................................................................................. 20-10

External Interrupt Control Register (EXTINTC2) ................................................................................. 20-11

External Interrupt Filter Control Register (EINTFLTN) ........................................................................ 20-12

External Interrupt Mask Register (EINTMASK)) .................................................................................. 20-13

External Interrupt Pending Register (EINTPEND)............................................................................... 20-14

Peripheral Port Pull up Control Register (PERIPU)............................................................................. 20-15

Alive Control Register (ALIVECON) .................................................................................................... 20-16

GPIO Output Data Register (GPDAT_SLEEP).................................................................................... 20-17

GPIO Output Control Register for Sleep Mode (GPOEN_SLEEP) ..................................................... 20-17

GPIO Pull up Control Register for Sleep Mode (GPPU_SLEEP)........................................................ 20-17

Peripheral Port Output Data Register for Sleep Mode (PERIDAT_SLEEP0)...................................... 20-18

Peripheral Port Output Data Register for Sleep Mode (PERIDAT_SLEEP1)...................................... 20-19

Peripheral Port Output Control Register for Sleep Mode (PERIOEN_SLEEP0) ................................. 20-20

Peripheral Port Output Control Register for Sleep Mode (PERIOEN_SLEEP1) ................................. 20-21

Peripheral Port Pull up Control Register for Sleep Mode (PERIPU_SLEEP)...................................... 20-22

Reset Count Compare Register (RstCnt) ............................................................................................ 20-23

General Purpose RAM Array (GPRAMn) ............................................................................................ 20-24

Chapter 21 Camera Interface

Overview....................................................................................................................................................... 21-1

Features ............................................................................................................................................... 21-2

External Interface ................................................................................................................................. 21-2

Signal Description ................................................................................................................................ 21-2

Timing Diagram.................................................................................................................................... 21-3

External Connection Guide .................................................................................................................. 21-5

8-Bit Mode............................................................................................................................................ 21-5

16-Bit Mode.......................................................................................................................................... 21-5

Camera Interface Operation ......................................................................................................................... 21-6

Two DMA Ports .................................................................................................................................... 21-6

Clock DOMAIN..................................................................................................................................... 21-7

Frame Memory Hirerarchy ................................................................................................................... 21-8

Memory Storing Method....................................................................................................................... 21-9

Timing Diagram for Register Setting.................................................................................................... 21-10

Timing Diagram for Last IRQ ............................................................................................................... 21-11

Software Interface......................................................................................................................................... 21-11

xiv S3C24A0A MICROPROCESSOR

Table of Contents (Continued)

Chapter 21 Camera Interface

Camera Interface Special Registers .............................................................................................................21-12

Source Format Register .......................................................................................................................21-12

Window Option Register.......................................................................................................................21-13

Global Control Register ........................................................................................................................21-14

Y1 Start Address Register ....................................................................................................................21-14

Y2 Start Address Register ....................................................................................................................21-14

Y3 Start Address Register ....................................................................................................................21-15

Y4 Start Address Register ....................................................................................................................21-15

CB1 Start Address Register .................................................................................................................21-15

CB2 Start Address Register .................................................................................................................21-15

CB3 Start Address Register .................................................................................................................21-16

CB4 Start Address Register .................................................................................................................21-16

CR1 Start Address Register .................................................................................................................21-16

CR2 Start Address Register .................................................................................................................21-16

CR3 Start Address Register .................................................................................................................21-17

CR4 Start Address Register .................................................................................................................21-17

Codec Target Format Register .............................................................................................................21-18

Codec DMA Control Register ...............................................................................................................21-19

Register Setting Guide for Codec Scaler and Preview Scaler .............................................................21-19

Codec Pre-Scaler Control Register 1 ...................................................................................................21-22

Codec Pre-Scaler Control Register 2 ...................................................................................................21-22

Codec Main-Scaler Control Register....................................................................................................21-22

Codec DMA Target Area Register........................................................................................................21-23

Codec Status Register..........................................................................................................................21-23

RGB1 Start Address Register...............................................................................................................21-24

RGB2 Start Address Register...............................................................................................................21-24

RGB3 Start Address Register...............................................................................................................21-24

RGB4 Start Address Register...............................................................................................................21-24

Preview Target Format Register...........................................................................................................21-25

Preview DMA Control Register.............................................................................................................21-25

Preview Pre-Scaler Control Register 1.................................................................................................21-26

Preview Pre-Scaler Control Register 2.................................................................................................21-26

Preview Main-Scaler Control Register .................................................................................................21-26

Preview DMA Target Area Register .....................................................................................................21-27

Preview Status Register .......................................................................................................................21-27

Image Capture Enable Register ...........................................................................................................21-27

(Continued)

S3C24A0A MICROPROCESSOR xv

Table of Contents (Continued)

Chapter 22 MPEG-4 Video Codec

Overview....................................................................................................................................................... 22-1

Feature................................................................................................................................................. 22-1

Block Diagram...................................................................................................................................... 22-2

Chapter 23 MPEG-4 Motion Estimation

Overview....................................................................................................................................................... 23-1

Feature................................................................................................................................................. 23-1

MPEG-4 Motion Estimation Operation ......................................................................................................... 23-2

Block Diagram...................................................................................................................................... 23-2

Operation Flow..................................................................................................................................... 23-3

Result Data .......................................................................................................................................... 23-4

MPEG-4 Motion Estimation Special Registers ............................................................................................. 23-5

Current Frame Start Address Register (ME_CFSA)............................................................................ 23-5

Previous Frame Start Address Register (ME_PFSA).......................................................................... 23-5

Motion Vector Start Address Register (ME_MVSA) ............................................................................ 23-5

Command Register (ME_CMND) ........................................................................................................ 23-6

Status & S/W Reset Register (ME_STAT_SWR) ................................................................................ 23-7

Configuration Register (ME_CNFG) .................................................................................................... 23-8

Image Format Register (ME_IMGFMT) ............................................................................................... 23-8

xvi S3C24A0A MICROPROCESSOR

Table of Contents (Continued)

Chapter 24 MPEG-4 Motion Compensation

Overview........................................................................................................................................................24-1

Feature .................................................................................................................................................24-1

MPEG-4 Motion Compensation Operation ...................................................................................................24-2

Block Diagram ......................................................................................................................................24-2

Operation Flow .....................................................................................................................................24-3

Configuration of QCIF/CIF Frame ........................................................................................................24-4

MPEG-4 Motion Compensation Special Registers .......................................................................................24-6

Previous Frame Y Start Address Register for the Encoder (MC_PFYSA_ENC) .................................24-6

MCED Frame Y Start Address Register for the Encoder (MC_MFYSA_ENC)....................................24-6

Previous Frame Y Start Address Register for the Decoder (MC_PFYSA_DEC).................................24-6

MCED Frame Y Start Address Register for the Decoder (MC_MFYSA_DEC)....................................24-6

Previous Frame Cb Start Address Register for the Encoder (MC_PFCbSA_ENC) ............................24-7

Previous Frame Cr Start Address Register for the Encoder (MC_PFCrSA_ENC) ..............................24-7

MCED Frame Cb Start Address Register for the Encoder (MC_MFCbSA_ENC) ...............................24-7

MCED Frame Cr Start Address Register for the Encoder (MC_MFCrSA_ENC).................................24-7

Previous Frame Cb Start Address Register for the Decoder (MC_PFCbSA_DEC) ............................24-8

Previous Frame Cr Start Address Register for the Decoder (MC_PFCrSA_DEC)..............................24-8

MCED Frame Cb Start Address Register for the Decoder (MC_MFCbSA_DEC) ...............................24-8

MCED Frame Cr Start Address Register for the Decoder (MC_MFCrSA_DEC).................................24-8

Motion Vector Start Address Register for the Encoder (MC_MVSA_ENC) .........................................24-9

Motion Vector Start Address Register for the Decoder (MC_MVSA_DEC) .........................................24-9

Command Register (MC_CMND).........................................................................................................24-10

Status & S/W Reset Register (MC_STAT_SWR).................................................................................24-11

Configuration Register (MC_CNFG) ....................................................................................................24-12

Image Format Register (MC_IMGFMT) ...............................................................................................24-12

S3C24A0A MICROPROCESSOR xvii

Table of Contents (Continued)

Chapter 25 MPEG-4 DCTQ

Overview....................................................................................................................................................... 25-1

Features ............................................................................................................................................... 25-2

Timing Diagram.................................................................................................................................... 25-2

Separated Clock Domain ..................................................................................................................... 25-3

DCT...................................................................................................................................................... 25-3

IDCT..................................................................................................................................................... 25-3

Quantisation ......................................................................................................................................... 25-4

DEQuantisation.................................................................................................................................... 25-4

Frame Memory Map............................................................................................................................. 25-5

Q-Information ....................................................................................................................................... 25-6

Bit Format............................................................................................................................................. 25-7

Transposed Coefficeint Output ............................................................................................................ 25-8

Software Interface......................................................................................................................................... 25-8

MPEG-4 DCTQ Special Registers................................................................................................................ 25-9

Current Frame Y Start Address Register............................................................................................. 25-9

Current Frame Cb Start Address Register........................................................................................... 25-9

Current Frame Cr Start Address Register ........................................................................................... 25-9

Reference Frame Y Start Address Register ........................................................................................ 25-10

Reference Frame Cb Start Address Register ...................................................................................... 25-10

Reference Frame Cr Start Address Register....................................................................................... 25-10

Dctqed Frame Y Start Address Register ............................................................................................. 25-10

Dctqed Frame Cb Start Address Register ........................................................................................... 25-11

Dctqed Frame Cr Start Address Register ............................................................................................ 25-11

Quantisation Factor Start Address Register ........................................................................................ 25-11

Image Size Register............................................................................................................................. 25-11

SHQ Register ....................................................................................................................................... 25-12

Control Register ................................................................................................................................... 25-13

Chapter 26 VLX

Overview....................................................................................................................................................... 26-1

Feature................................................................................................................................................. 26-1

MPEG-4 VLX (Variable Length Coding, Decoding) Operation..................................................................... 26-2

VLC ...................................................................................................................................................... 26-2

Entropy Coder ...................................................................................................................................... 26-4

VLD ...................................................................................................................................................... 26-6

VLX (VLC and VLD) Special Registers ........................................................................................................ 26-10

VLX Common SFR .............................................................................................................................. 26-10

Frame Start Addr.................................................................................................................................. 26-11

VLX Control Register (VLX_CON)....................................................................................................... 26-12

VLD Control Register (VLD_CON) ...................................................................................................... 26-13

VLX Output Register 1 (VLX_CON 1) – Read Only ............................................................................ 26-14

VLX Output Register 2 (VLX_CON 2) – Read Only ............................................................................ 26-14

xviii S3C24A0A MICROPROCESSOR

Table of Contents (Continued)

Chapter 27 Post Processor

Overview........................................................................................................................................................27-1

Overall Features ...................................................................................................................................27-2

A Source and Destination Image Data Format .............................................................................................27-3

Image Size and Scale Ratio..........................................................................................................................27-6

DMA Operation of Source and Destination Image........................................................................................27-8

Starting and Terminating of Post Processor .................................................................................................27-11

Register File Lists..........................................................................................................................................27-12

Pre-Scale Image Size Register ............................................................................................................27-13

Source Image Size Register.................................................................................................................27-14

Destination Image Size Register ..........................................................................................................27-15

DMA Start Address Register ................................................................................................................27-15

DMA End Address Register..................................................................................................................27-16

Offset Register......................................................................................................................................27-16

Chapter 28 LCD Controller

Overview........................................................................................................................................................28-1

Features................................................................................................................................................28-1

External Interface Signal ......................................................................................................................28-2

Block Diagram ......................................................................................................................................28-3

Timing Controller Operation ..........................................................................................................................28-4

Video Operation ............................................................................................................................................28-5

OSD (On-Screen Display): Overlay......................................................................................................28-5

Color-Key Function...............................................................................................................................28-6

Dual Buffer............................................................................................................................................28-7

256 Palette Usage (TFT) ......................................................................................................................28-12

Virtual Display.......................................................................................................................................28-15

Register Description ......................................................................................................................................28-16

Memory Map.........................................................................................................................................28-16

S3C24A0A MICROPROCESSOR xix

Table of Contents (Continued)

Chapter 29 Key PAD I/F

Overview....................................................................................................................................................... 29-1

Keypad Control Register .............................................................................................................................. 29-2

Keypad Control Registers (KEYDAT, KEYPUP) ................................................................................. 29-2

Keypad Interrupt Control Register ....................................................................................................... 29-2

Debouncing Filter................................................................................................................................. 29-3

Keypad Filter Control Register ( KEYFLT ).......................................................................................... 29-3

Keypad Manual Scan Control Register (YMAN).................................................................................. 29-4

Chapter 30 ADC & Touch Screen Interface

Overview....................................................................................................................................................... 30-1

Features ............................................................................................................................................... 30-1

ADC & Touch Screen Interface Operation ................................................................................................... 30-2

Block Diagram...................................................................................................................................... 30-2

Example for Touch Screen .................................................................................................................. 30-3

Function Descriptions .......................................................................................................................... 30-4

ADC and Touch Screen Interface Special Registers ................................................................................... 30-7

ADC Control Register (ADCCON) ....................................................................................................... 30-7

ADC Touch Screen Control Register (ADCTSC) ................................................................................ 30-8

ADC Start Delay Register (ADCDLY) .................................................................................................. 30-9

ADC Conversion Data Register (ADCDAX) ........................................................................................ 30-10

ADC Conversion Data Register (ADCDAY) ........................................................................................ 30-11

xx S3C24A0A MICROPROCESSOR

Table of Contents (Continued)

Chapter 31 Secure Digital Interface

Overview........................................................................................................................................................31-1

Feature .................................................................................................................................................31-1

Block Diagram ......................................................................................................................................31-2

SDI Operation................................................................................................................................................31-3

SDIO Operation.............................................................................................................................................31-4

SDI Special Registers ...................................................................................................................................31-5

SDI Control Register (SDICON) ...........................................................................................................31-5

SDI Baud Rate Prescaler Register (SDIPRE) ......................................................................................31-6

SDI Command Argument Register (SDICARG) ...................................................................................31-6

SDI Command Control Register (SDICCON)....................................................................................... 31-6

SDI Command Status Register (SDICSTA) .........................................................................................31-7

SDI Response Register0 (SDIRSP0) ...................................................................................................31-7

SDI Response Register1 (SDIRSP1) ...................................................................................................31-7

SDI Response Register2 (SDIRSP2) ...................................................................................................31-8

SDI Response Register3 (SDIRSP3) ...................................................................................................31-8

SDI Data / Busy Timer Register (SDIDTIMER) .................................................................................... 31-8

SDI Block Size Register (SDIBSIZE)....................................................................................................31-8

SDI Data Control Register (SDIDCON)................................................................................................31-9

SDI Data Remain Counter Register (SDIDCNT)..................................................................................31-10

SDI Data Status Register (SDIDSTA) ..................................................................................................31-11

SDI FIFO Status Register (SDIFSTA) ..................................................................................................31-12

SDI Interrupt Mask Register (SDIIMSK)...............................................................................................31-13

SDI Data Register (SDIDATn) ..............................................................................................................31-14

Chapter 32 Memory Stick

Overview........................................................................................................................................................32-1

Features................................................................................................................................................32-1

Memory Stick Protocol..........................................................................................................................32-2

Mandatory Hardware Configuration .....................................................................................................32-2

Host Block Pin Description ...................................................................................................................32-3

Memory Stick Special Registers ...................................................................................................................32-4

Prescaler Control (MSPRE) Register ...................................................................................................32-4

FIFO Interrupt Control (MSFINTCON) Register ...................................................................................32-4

Transfer Protocol Command (TP_CMD) Register ...............................................................................32-5

Control and Status (CTRLSTA) Register .............................................................................................32-6

Data FIFO (DAT_FIFO) Register..........................................................................................................32-7

Interrupt Control and Status (INTCTRLSTA) Register .........................................................................32-7

INS Port Control (INSCON) Register ...................................................................................................32-8

Auto Command/POL Control (ACMD_CON) Register .........................................................................32-8

Auto Transfer Protocol Command (ATP_CMD) Register.....................................................................32-8

S3C24A0A MICROPROCESSOR xxi

Table of Contents (Continued)

Chapter 33 Clock & Power Management

Overview....................................................................................................................................................... 33-1

Function Description ............................................................................................................................ 33-2

Power Saving Modes ........................................................................................................................... 33-9

Clock Generator & Power Management Special Register ........................................................................... 33-13

Lock Time Count Register (LOCKTIME) ............................................................................................. 33-13

X-Tal Oscillation Wait Register (XTALWSET) ..................................................................................... 33-13

Pll Control Register (MPLLCON, UPLLCON)...................................................................................... 33-14

Clock Control Register (CLKCON) ...................................................................................................... 33-15

Clock Source Control Register (CLKSRC) .......................................................................................... 33-17

Clock Divider Control Register (CLKDIVN) ......................................................................................... 33-18

Power Management Control Register (PWRMAN).............................................................................. 33-18

Softreset Control Register (SOFTRESET) .......................................................................................... 33-19

Chapter 34 Mechanical Data

Package Dimensions.................................................................................................................................... 34-1

xxii S3C24A0A MICROPROCESSOR

List of Figures

Figure Title Page Number Number

1-1 An Overall Block Diagram of the S3C24A0A ..........................................................................1-8

1-2 337-Pin FBGA Pin Assignment ...............................................................................................1-9

1-3 Address map............................................................................................................................1-38

2-1 SROM Controller Address Mapping ........................................................................................2-1

2-2 SROM Controller Block Diagram.............................................................................................2-2

2-3 Memory Interface Block Diagram ............................................................................................2-3

2-4 XrWAITn Pin Operation ...........................................................................................................2-4

2-5 Programmable Access Cycle ..................................................................................................2-5

3-1 Memory Interface with 16-bit SDRAM (4Mx16, 4banks) ......................................................... 3-4

3-2 Memory Interface with 16-bit SDRAM (4Mx16 × 2ea, 4banks) ...............................................3-4

3-3 SDRAM Timing Diagram .........................................................................................................3-5

4-1 NAND Flash Controller Block Diagram ...................................................................................4-3

4-2 NAND Flash Controller Boot Loader Block Diagram...............................................................4-4

4-3 NAND Flash Controller Operation Mode Block Diagram ........................................................4-5

4-4 Auto Mode Timing Diagram (TACLS = 1, TWRPH0 = 0, TWRPH1 = 0) ................................4-5

4-5 NAND Flash Controller Auto Load Timing Diagram (TWRPH0 = 0, TWRPH1 = 0) ...............4-6

4-6 NAND Flash Controller Auto Store Timing Diagram (TWRPH0 = 0, TWRPH1 = 0)...............4-7

4-7 8-bit NAND Flash Memory Interface .......................................................................................4-11

4-8 Two 8-bit NAND Flash Memory Interface................................................................................4-11

4-9 16-bit NAND Flash Memory Interface .....................................................................................4-12

5-1 Configuration of MATRIX and Memory Sub-System...............................................................5-1

6-1 Priority Generating Block.........................................................................................................6-4

7-1 16-bit PWM Timer Block Diagram ...........................................................................................7-2

7-2 Timer operations......................................................................................................................7-3

7-3 Example of Double Buffering Feature .....................................................................................7-4

7-4 Example of a Timer Operation.................................................................................................7-5

7-5 Example of PWM .....................................................................................................................7-6

7-6 Inverter On/Off .........................................................................................................................7-7

7-7 The Wave Form When a Dead Zone Feature is Enabled .......................................................7-8

7-8 The Timer4 DMA Mode Operation ..........................................................................................7-9

S3C24A0A MICROPROCESSOR xxiii

List of Figures (Continued)

Figure Title Page Number Number

8-1 Watchdog Timer Block Diagram ............................................................................................. 8-2

9-1 Basic DMA Timing Diagram.................................................................................................... 9-3

9-2 Demand/Handshake Mode Comparison ................................................................................ 9-3

9-3 Burst 4 Transfer Size .............................................................................................................. 9-4

9-4 Single service, Demand Mode, Single Transfer Size ............................................................. 9-5

9-5 Single service, Handshake Mode, Single Transfer Size ........................................................ 9-5

9-6 Whole service, Handshake Mode, Single Transfer Size ........................................................ 9-5

10-1 Real Time Clock Block Diagram ............................................................................................. 10-2

11-1 UART Block Diagram (with FIFO)........................................................................................... 11-2

11-2 UART AFC Interface ............................................................................................................... 11-3

11-3 Example showing UART Receiving 5 Characters with 2 Errors............................................. 11-6

11-4 IrDA Function Block Diagram ................................................................................................. 11-8

11-5 Serial I/O Frame Timing Diagram (Normal UART) ................................................................. 11-9

11-6 Infrared Transmit Mode Frame Timing Diagram .................................................................... 11-9

11-7 Infrared Receive Mode Frame Timing Diagram ..................................................................... 11-9

11-8 nCTS and Delta CTS Timing Diagram.................................................................................... 11-18

12-1 Block Diagram......................................................................................................................... 12-2

12-2 Fir Modulation Process ........................................................................................................... 12-4

12-3 Fir Demodulation Process ...................................................................................................... 12-5

12-4 Pulse Modulation in MIR Mode............................................................................................... 12-6

12-5 Mir Modulation Process .......................................................................................................... 12-7

12-6 Mir Demodulation Process...................................................................................................... 12-8

12-7 General Program Flowchart.................................................................................................... 12-9

13-1 IIC-Bus Block Diagram............................................................................................................ 13-2

13-2 Start and Stop Condition......................................................................................................... 13-3

13-3 IIC-Bus Interface Data Format................................................................................................ 13-4

13-4 Data Transfer on the IIC-Bus.................................................................................................. 13-5

13-5 Acknowledge on the IIC-Bus .................................................................................................. 13-5

13-6 Operations for Master / Transmitter Mode.............................................................................. 13-7

13-7 Operations for Master / Receiver Mode.................................................................................. 13-8

13-8 Operations for Slave / Transmitter Mode................................................................................ 13-9

13-9 Operations for Slave / Receiver Mode.................................................................................... 13-10

xxiv S3C24A0A MICROPROCESSOR

List of Figures (Continued)

Figure Title Page Number Number

14-1 IIS-Bus Block Diagram ...........................................................................................................14-1

14-2 IIS-Bus and MSB(Left)-justified Data Interface Formats ........................................................14-4

15-1 SPI Block Diagram ..................................................................................................................15-2

15-2 SPI Transfer Format ................................................................................................................15-4

16-1 AC97 Block Diagram ...............................................................................................................16-2

16-2 Internal Data Path....................................................................................................................16-3

16-3 AC97 Operation Flow Chart ....................................................................................................16-4

16-4 Bi-directional AC-link Frame with Slot Assignments ...............................................................16-5

16-5 AC-link Output Frame..............................................................................................................16-6

16-6 AC-link Input Frame.................................................................................................................16-6

16-7 AC97 Powerdown Timing ........................................................................................................16-7

16-8 AC97 Power down/Power up Flow..........................................................................................16-8

17-1 USB Host Controller Block Diagram........................................................................................17-1

18-1 USB Device Block Diagram.....................................................................................................18-2

19-1 Modem Interface Overview......................................................................................................19-1

19-2 Modem Interface Address Mapping ........................................................................................19-3

19-3 Modem Interface Write Timing Diagram..................................................................................19-4

19-4 Modem Interface Read Timing Diagram .................................................................................19-5

21-1 Camera Interface Overview.....................................................................................................21-1

21-2 ITU-R BT 601 Input Timing Diagram.......................................................................................21-3

21-3 ITU-R BT 656 Input Timing Diagram.......................................................................................21-3

21-4 IO Connection Guide ...............................................................................................................21-5

21-5 Two DMA Ports........................................................................................................................21-6

21-6 Clock Generation.....................................................................................................................21-7

21-7 Ping-pong Memory Hierarchy..................................................................................................21-8

21-8 Memory Storing Style ..............................................................................................................21-9

21-9 Timing Diagram for Register Setting .......................................................................................21-10

21-10 Timing Diagram for Last IRQ...................................................................................................21-11

21-11 Window Offset Scheme ...........................................................................................................21-13

21-12 Image Mirror and Rotation.......................................................................................................21-18

21-13 Scaling scheme .......................................................................................................................21-20

S3C24A0A MICROPROCESSOR xxv

List of Figures (Continued)

Figure Title Page Number Number

22-1 MPEG-4 Video CODEC Block Diagram ................................................................................. 22-2

23-1 MPEG-4 Motion Estimation Block Diagram ............................................................................ 23-2

23-2 Memory Map of Y (Luminance) Image for Current and Previous Frames ............................. 23-3

23-3 Motion Estimation Result Data ............................................................................................... 23-4

24-1 MPEG-4 Motion Compensation Block Diagram ..................................................................... 24-2

24-2 Y/Cb/Cr Image Memory Map of Original and Padded Frames............................................... 24-3

24-3 Y/Cb/Cr Configuration for QCIF/CIF Original Frame .............................................................. 24-4

24-4 Y/Cb/Cr Configuration for QCIF/CIF Padded Frame .............................................................. 24-5

24-5 Motion Vector Configuration for QCIF/CIF Image .................................................................. 24-5

25-1 DCTQ Overview...................................................................................................................... 25-1

25-2 DCTQ Operation Timing Diagram .......................................................................................... 25-2

25-3 DCTQ clock domain................................................................................................................ 25-3

25-4 DCTQ Frame Memory Map in QCIF Case ............................................................................. 25-5

25-5 Q-Information Structure .......................................................................................................... 25-6

25-6 DCTQ Bit-Format .................................................................................................................... 25-7

25-7 Transposed Coefficient Output for MB ................................................................................... 25-8

26-1 VLX Top Interface Block Diagram .......................................................................................... 26-2

26-2 ZigZag Scanning Method........................................................................................................ 26-3

26-3 Previous Neighboring Blocks Used in DC Prediction ............................................................. 26-4

26-4 VLC output bit stream format .................................................................................................. 26-5

26-5 VLC Start, Busy, And Interrupt Signal Timing Diagram.......................................................... 26-6

26-6 VLD Bit Stream H/W and S/W Interface Format..................................................................... 26-6

26-7 External Memory Amount in VLD Mode. ................................................................................ 26-7

26-8 VLD Output Coefficient Format............................................................................................... 26-7

26-9 MSB is First Bit Value in Output Bit Stream............................................................................ 26-8

26-10 VLD Flow Chart and S/W and H/W Processing Partition ....................................................... 26-9

26-11 Start Signal, Busy Signal and Interrupt Signal in VLD Mode.................................................. 26-9

xxvi S3C24A0A MICROPROCESSOR

List of Figures (Continued)

Figure Title Page Number Number

27-1 Block Diagram of Post Processor............................................................................................27-1

27-2 Data Format Stored in External Memory.................................................................................27-4

27-3 Byte and Half-Word Organization............................................................................................27-4

27-4 Sampling Position of YCbCr420 and YCbCr422 Format

(X: Luma Sample and Ο: Chroma Sample).............................................................................27-5

27-5 Source Destination Image Size ...............................................................................................27-6

27-6 Start and End Address Set According to Memory Allocation Type.........................................27-8

27-7 Offset for (a) Source Image for Zoom In/Out Operation and

(b) Destination Image for PIP Applications..............................................................................27-10

27-8 Start and Termination of the Operation of Post Processor .....................................................27-11

28-1 LCD Controller Block Diagram ................................................................................................28-3

28-2 Clock Selection ........................................................................................................................28-4

28-3 OSD Procedure .......................................................................................................................28-6

28-4 Blending and Color Key Function of OSD ............................................................................... 28-7

28-5 16BPP Display Types..............................................................................................................28-13

28-6 TFT LCD Timing Example .......................................................................................................28-14

28-7 Example of Scrolling in Virtual Display....................................................................................28-15

29-1 Key Matrix Interface Guide ......................................................................................................29-1

30-1 ADC and Touch Screen Interface Functional Block Diagram .................................................30-2

30-2 Example of ADC and Touch Screen Interface ........................................................................30-3

31-1 SDI Block Diagram ..................................................................................................................31-2

32-1 Memory Stick Write Packet .....................................................................................................32-2

32-2 Memory Stick Read Packet .....................................................................................................32-2

33-1 Clock Generator Block Diagram..............................................................................................33-2

33-2 PLL (Phase-Locked Loop) Block Diagram ..............................................................................33-3

33-3 Power-On Reset Sequence.....................................................................................................33-5

33-4 The Case that Changes Slow Clock by Setting PMS Value ...................................................33-6

33-5 The Clock Distribution Block Diagram.....................................................................................33-8

33-6 Entering STOP Mode and Exiting STOP mode (Wake-up).....................................................33-10

33-7 Power mode state diagram......................................................................................................33-11

34-1 337-FBGA-1313 Package Dimension 1 (Top View)................................................................34-1

34-2 337-FBGA-1313 Package Dimension 2 (Bottom View) ..........................................................34-2

S3C24A0A MICROPROCESSOR xxvii

List of Tables

Table Title Page Number Number

1-1 337-Pin FBGA Pin Assignments – Pin Number Order ............................................................ 1-10

1-2 337-Pin FBGA Pin Assignments..............................................................................................1-14

3-1 Supported SDRAM Configuration ...........................................................................................3-2

4-1 Advance NAND Flash Controller Configuration (word means 16-bit in this table)..................4-2

4-2 2K Byte Main Area ECC Parity Code Assignment Table ........................................................4-9

4-3 16 Byte SPARE AREA ECC Parity Code Assignment Table..................................................4-9

9-1 DMA Request Sources for Each Channel...............................................................................9-1

11-1 Interrupts in Connection with FIFO..........................................................................................11-5

14-1 CODEC Clock (IISCDCLK = 256 or 384fs) .............................................................................14-4

14-2 Usable Serial Bit Clock Frequency (IISCLK = 16 or 32 or 48fs) .............................................14-4