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Image and Video Processing................................................................................................................1-4
Display Control .....................................................................................................................................1-6
Function Description.............................................................................................................................2-3
Programmable Access Cycle Write to Read Waveform.......................................................................2-5
Special Function Registers ...........................................................................................................................2-6
Srom Bus Width & Wait Contrl Register(SROM_BW)..........................................................................2-6
Srom Bank Control Register (SROM_BC: XrCSn0 ~ XrCSn2)............................................................2-7
Selection of SDRAM ..................................................................................................................................... 3-2
Selection of SDRAM ..................................................................................................................................... 3-2
Features ............................................................................................................................................... 4-1
Boot Loader Function ................................................................................................................................... 4-4
Auto Load Mode ........................................................................................................................................... 4-6
Auto Load Programming Guide ........................................................................................................... 4-6
Auto Store Mode........................................................................................................................................... 4-7
Auto Store Programming Guide........................................................................................................... 4-7
Control Register ................................................................................................................................... 4-14
Special Function Registers ...........................................................................................................................5-2
Features ............................................................................................................................................... 8-1
Uart Special Registers...................................................................................................................................11-10
Uart Line Control Register ....................................................................................................................11-10
Uart Control Register............................................................................................................................11-11
Uart FIFO Control Register...................................................................................................................11-13
Uart Modem Control Register...............................................................................................................11-14
Uart Tx/Rx Status Register...................................................................................................................11-15
Uart Error Status Register ....................................................................................................................11-16
Uart FIFO Status Register ....................................................................................................................11-17
Uart Modem Status Register ................................................................................................................11-18
Special Function Registers ...........................................................................................................................12-10
IrDA Control Register (IrDA_CNT) .......................................................................................................12-10
Configuring the IIC-Bus........................................................................................................................ 13-6
Flowcharts of the Operations in Each Mode........................................................................................ 13-7
IIC-Bus Interface Special Registers.............................................................................................................. 13-11
Multi-Master IIC-Bus Control Register (IICCON)................................................................................. 13-11
Features ............................................................................................................................................... 14-1
Transmit or Receive Only Mode .......................................................................................................... 14-2
Dma Transfer ....................................................................................................................................... 14-2
Transmit and Receive Mode................................................................................................................ 14-2
Audio Serial Interface Format....................................................................................................................... 14-3
IIS-Bus Format ..................................................................................................................................... 14-3
SPI Special Registers....................................................................................................................................15-6
SPI Control Register.............................................................................................................................15-6
SPI Status Register ..............................................................................................................................15-7
SPI Pin Control Register.......................................................................................................................15-8
Internal Data Path.................................................................................................................................16-3
AC-link Digital Interface protocol...................................................................................................................16-5
USB Device Special Registers ..................................................................................................................... 18-3
Signal Description.................................................................................................................................19-2
Port Control Descriptions ..............................................................................................................................20-3
Gpio Port Configuration Register For Normal Mode (GPCON_U, GPCON_M, GPCON_L) ...............20-3
Gpio Port Data Register For Normal Mode (GPDAT) ..........................................................................20-3
Gpio Port Pull-Pu Control Register for Normal Mode (GPPU) ............................................................. 20-3
External Interrupt Control Register (Extintcn/ Eintfltn/ Eintmask/ Eintpend) ........................................20-3
Peripheral Port Pull-Up Control Register for Normal Mode (PERIPU).................................................20-3
Alive Control Register (ALIVECON) .....................................................................................................20-4
Gpio Output Control Register for Sleep Mode (GPOEN_SLEEP) .......................................................20-4
Gpio Pull-Up Control Register for Sleep Mode (GPPU_SLEEP) .........................................................20-4
Peripheral Port Output Data Register for Sleep Mode (PERIDAT_SLEEPN)......................................20-4
Peripheral Port Output Control Register for Sleep Mode (PERIOEN_SLEEPN) .................................20-4
Peripheral Port Pull-Up Control Register for Sleep Mode (PERIPU_SLEEP) .....................................20-4
General Purpose RAM Array (GPRAMn) .............................................................................................20-4
I/O Port Control Register ...............................................................................................................................20-5
GPIO Upper Port Control Register (GPCON_U).................................................................................. 20-5
Gpio Middle Port Control Register (GPCON_M) ..................................................................................20-6
Gpio Lower Port Control Register (GPCON_L)....................................................................................20-7
Gpio Port Data Register (GPDAT)........................................................................................................20-8
Gpio Port Pull Up Resister Control Register (GPPU)........................................................................... 20-8
External Interrupt Control Register (EXTINTC0) ..................................................................................20-9
S3C24A0A MICROPROCESSOR xiii
Table of Contents (Continued)
Chapter 20 General Purpose I/O Ports (Continued)
External Interrupt Control Register (EXTINTC1) ................................................................................. 20-10
External Interrupt Control Register (EXTINTC2) ................................................................................. 20-11
External Interrupt Filter Control Register (EINTFLTN) ........................................................................ 20-12
Features ............................................................................................................................................... 21-2
Signal Description ................................................................................................................................ 21-2
Camera Interface Operation ......................................................................................................................... 21-6
Two DMA Ports .................................................................................................................................... 21-6
Result Data .......................................................................................................................................... 23-4
MPEG-4 Motion Estimation Special Registers ............................................................................................. 23-5
Current Frame Start Address Register (ME_CFSA)............................................................................ 23-5
Features ............................................................................................................................................... 25-2
Bit Format............................................................................................................................................. 25-7
Control Register ................................................................................................................................... 25-13
Overall Features ...................................................................................................................................27-2
A Source and Destination Image Data Format .............................................................................................27-3
Image Size and Scale Ratio..........................................................................................................................27-6
DMA Operation of Source and Destination Image........................................................................................27-8
Starting and Terminating of Post Processor .................................................................................................27-11
Video Operation ............................................................................................................................................28-5
Keypad Control Register .............................................................................................................................. 29-2
Keypad Control Registers (KEYDAT, KEYPUP) ................................................................................. 29-2
Keypad Interrupt Control Register ....................................................................................................... 29-2
Features ............................................................................................................................................... 30-1
SDI Special Registers ...................................................................................................................................31-5
SDI Control Register (SDICON) ...........................................................................................................31-5
The S3C24A0A is a 16/32-bit RISC microprocessor, designed to provide a cost-effective, low power, and high
performance micro-controller solution for mobile phones and general applications. To provide a sufficient H/W
performance for the 2.5G & 3G communication services, the S3C24A0A adopts dual-32-bit bus architecture and
includes many powerful hardware accelerators for the motion video processing, serial communications, and etc.
For the real time video conferencing, an optimized MPEG4 H/W Encoder/Decoder is integrated.
To reduce total system cost and enhance overall functionality, the S3C24A0A also includes following
components: separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management,
LCD controller (TFT), Camera Interface, MPEG-4 ME, MC, DCTQ, NAND Flash Boot loader, System Manager
(power management & etc.), SDRAM controller, 2-ch UART, 4-ch DMA, 4-ch Timers, General I/O Ports, IICBUS interface, USB Host, SD Host & Multi-Media Card Interface, Memory Stick Interface, PLL for clock
generation & etc. The S3C24A0A can be used as a most powerful Application Processor for mobiles phones. For
this application, the S3C24A0A has a Modem Interface to communicate with various Modem Chips.
The S3C24A0A is developed using an ARM926EJ-S core, advanced 0.13um CMOS standard cells and memory
compliers. Its low-power, simple, elegant and fully static-design scheme is particularly suitable for cost-sensitive
and power-sensitive applications. Also, the S3C24A0A adopts a de-facto standard bus architecture – the AMBA
(Advanced Microcontroller Bus Architecture).
One of the outstanding features of the S3C24A0A is it’s CPU core, a 16/32-bit ARM926EJ-S RISC processor
designed by ARM, Ltd. The ARM926EJ-S is a single chip MCU and Java enabled microprocessor. The
ARM926EJ-S also implements the MMU, the AMBA BUS, and the Harvard cache architecture with separate 16KB
instruction and 16KB data caches, each cache with an 8-word line length.
By providing a complete set of common system peripherals, the S3C24A0A minimizes overall system costs and
eliminates the need to configure additional components.
Preliminary product information describe products that are in development, 1-1
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
This section will explain the features of the S3C24A0A. Figure 1-1 is an overall block diagram of the S3C24A0A.
MICROPROCESSOR AND OVERALL ARCHITECTURE
• SoC (System-on-Chip) for mobile phones and general embedded applications.
• 16/32-Bit RISC architecture and powerful instruction set with ARM926EJ-S CPU core.
• ARM’s Jazelle Java technology enhanced ARM architecture MMU to support WinCE, Symbian and Linux
• Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main
memory bandwidth and latency on performance
• 4 way set-associative cache with I-Cache (16KB) and D-Cache (16KB).
• 8-words per line with one valid bit and two dirty bits per line
• Pseudo random or round robin replacement algorithm.
• Write through or write back cache operation to update the main memory.
• The write buffer can hold 16 words of data and four addresses.
• ARM926EJ-S core supports the ARM debug architecture
• Internal AMBA (Advanced Microcontroller Bus Architecture) (AMBA2.0, AHB/APB)
• Dual AHB bus for high-performance processing (AHB-I & AHB-S)
MEMORY SUBSYSTEM
•High bandwidth Memory subsystem with two access channels (accesses from two AHB buses) and three-
channel memory ports
• Double the bandwidth with the simultaneous access capability
• ROM/SRAM/NOR-Flash/NAND-Flash channel
• One SDRAM channels
• Up to 1GB Address space
• Low-power SDRAM interface support : Mobile SDRAM function
– DS: Driver Strength Control
– TCSR: Temperature Compensated Self-Refresh Control
– PASR: Partial Array Self-Refresh Control
•NAND Flash Boot Loader with the ECC circuitry to support booting from NAND Flash
– 4KB Stepping Stone
– Support 1G, 2G bit NAND Flash
1-2 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
• UART
– 2-channel UART with DMA-based or interrupt-based operation
– Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data transmit/receive
– Supports external clock for the UART operation (XuCLK)
– Programmable baud rate
– Supports IrDA 1.0
– Loop back mode for testing
– Each channel has internal 64-byte Tx FIFO and 64-byte Rx FIFO
• IrDA
– Support IrDA 1.1 (1.152Mbps and 4Mbps)
– Support FIFO operation in the MIR and FIR mode
– Configurable FIFO Size (16-byte or 64-byte)
– Support Back-to-Back Transactions
– Support Software Selection Temic-IBM or HP Transceiver
– Support Little-endian access
• IIC-Bus Interface
– 1-ch Multi-Master IIC-Bus
– Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in the standard
mode
Preliminary product information describe products that are in development, 1-3
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
• IIS-Bus Interface
– 1-ch IIS-bus for the audio-codec interface with DMA-based operation
– Serial, 8/16-bit per channel data transfers
– 128 Bytes (64-Byte + 64-Byte) FIFO for receive/transmit
– Supports IIS format and MSB-justified data format
• SPI Interface
– 2-ch Serial Peripheral Interface Protocol version 2.11 compatible
– 2x8 bits Shift register for receive/transmit.
– DMA-based or interrupt-based operation.
• USB Host
– 2-port USB Host
– Complies with OHCI Rev. 1.0
– Compatible with the USB Specification version 1.1
• USB Device
– 1-port USB Device
– 5 End-points for USB Device
– Compatible with the USB Specification version 1.1
PARALLEL COMMUNICATION
•Modem Chip Interface
– 8-bit Asynchronous SRAM interface-style interface
– On-chip 2KB dual-ported SRAM buffer
– Interrupt Request for Data Exchange
– Programmable Interrupt Port Address
• 32-bit GPIO
– Fully configurable 32-bit GPIO
IMAGE AND VIDEO PROCESSING
• Camera Inteface
– ITU601/ITU656 YCbCr 4:2:2 8/16-bit mode
– Image down scaling capability for variable applications
– Digital Zoom-In
– Image X, Y-flip, 180 rotation
– Input Image Window Cut
– Two master for dedicated DMA operation
– Programmable burst length for DMA operation
– Programmable polarity of video sync signals
– Wide horizontal line buffer (maximum 2048 pixel)
– Up to 4M pixel resolution support for scaled image (image preview or motion video capturing) and 16M
pixel for unscaled image (JPEG)
– Format conversion from YCrCb 4:2:2 to 4:2:0 for codec, and to RGB 4:4:4 for preview
1-4 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
•Hardware Accelerated MPEG4 Video Encoding/Decoding
– A AHB Interface
– Realtime MPEG-4 Video Encoding & Decoding
– Up to Simple Profile at Level 3 (352x288 at 30fps)
– Supports H.263 Base Line
•MPEG-4 ME (Motion Estimation)
– Highly optimized hard-wired engine
– Unrestricted Mode and Advanced Prediction Mode (4MV)
– Use the advanced MRMCS algorithm
– Half-pel search
– Programmable Image size up to 2048x2048
– Padding for Macro-block basis
– Search Range: [-16, 15.5]
– Intra/Inter Mode Decision MC (Motion Compensation)
• DCTQ
– DCT/IDCT/Q/IQ operations
– AMBA AHB Interface
– Support MPEG-4 Simple Profile Level 3 / H.263 Base-Line
– Support programmable image size up to 4096x4096
– Macroblock-based processing
– Rate Control by Qp Information
– Local DMA
– Support MPEG-4 Encoding / Decoding
– Support JPEG DCT / IDCT Operation
– Operation unit : 1MB(MacroBlock) ~ 1 Frame
• VLX
– VLC/VLD operations
– AMBA AHB Interface
– Support MPEG4 Simple Profile Level 3/ H.263. Baseline
– Macro block-based processing
– Dedicated DMA
– Only DCTQ coefficient VLC/VLD operation
– Only DC prediction operation in VLC
Preliminary product information describe products that are in development, 1-5
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
• Post Processor
– Dedicate DMA with Offset Address
– 3 Channel Scaling Pipelines for Video/Graphis Signal
– Input Format: YCbCr4:2:0, YCbCr4:2:2, or RGB 16b/24b
– Output Format: RGB 16b/24b
– Programmable Image Size (Source up to 4096x4096, Destination up to 2048x2048)
– Programmable Scale Ratio (Up-scale: up to Max. Destination Size, Down-scale: ~>1/64 in X & Y)
– Format Conversion for Video Signal (YCbCr4:2:0 or YCbCr4:2:2)
– Color Space Conversion (YCbCr2RGB)
– Separate Processing Clock from AHB Interface Clock
DISPLAY CONTROL
•TFT LCD Interface
– 18-bit Parallel or 6bit*3 Interface
– 1/2/4/8-bpp Palletized or 8/16/18-bpp Non-Palletized Color-TFF support
– Supports 640x480, 320x240, 176x192 and others
– Up to 16 Mbyte virtual screen size
– Supports Multiple Virtual Display Screen (Supports Hardware Horizontal/Vertical Scrolling)
– Programmable timing control for different display panels
– Dual Buffer
•OSD (On Screen Display)
– Realtime overlay plane multiplexing
– Programmable OSD window positioning
– Per-pixel alpha blending for 18-bpp OSD images
– Fixed alpha-value for 8-/16-/18-bpp OSD image
– 56-level alpha blending
– 24-bit color key support
– Dual buffer
•A/D Converter and Touch Screen Interface
– 8-ch multiplexed ADC
– Max. 500K samples/sec and 10-bit resolution
1-6 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
• SD Host
– Compatible with SD Memory Card Protocol version 1.0
– Compatible with SDIO Card Protocol version 1.0
– 64 Bytes FIFO for Tx/Rx
– DMA based or Interrupt based operation
– Compatible with Multimedia Card Protocol version 2.11
•Memory Stick Host
– Memory Stick version 1.3 compliant
SYSTEM MANAGEMENT
• Little Endian format support
• System operating clock generation
– Two on-chip PLLs, MPLL & UPLL
– MPLL generates the system reference clock, 200MHz@1.3V
– UPLL generates clocks for the USB Host/Device, IrDA and Camera
• Power Management
– Clock-off control for individual components
– Various power-down modes are available such as IDLE, STOP and SLEEP
– Wake-up by one of external interrupts or by the RTC alarm interrupt, etc.
Preliminary product information describe products that are in development, 1-7
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Figure 1-1. An Overall Block Diagram of the S3C24A0A
1-8 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Preliminary product information describe products that are in development, 1-9
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1-10 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Preliminary product information describe products that are in development, 1-11
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1-12 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Preliminary product information describe products that are in development, 1-13
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
AA7 VSSadc VSSadc PP P P P
AB7 VSSMpll VSSMpll PP P P P
AC7 VSSUpll VSSUpll PP P P P
AB13 VSSpadUSB VSSpadUSB PP P P P
AC1 VSSrtc VSSrtc PP P P P
AA18 VDDlogic VDDlogic PP P P P
J21 VDDlogic VDDlogic PP P P P
M14 VDDlogic VDDlogic PP P P P
N9 VDDlogic VDDlogic PP P P P
R11 VDDlogic VDDlogic PP P P P
W21 VDDlogic VDDlogic PP P P P
K11 VDDpadIO VDDpadIO PP P P P
M3 VDDpadIO VDDpadIO PP P P P
N10 VDDpadIO VDDpadIO PP P P P
R12 VDDpadModem VDDpadModem PP P P P
C12 VDDarm VDDarm PP P P P
L10 VDDarm VDDarm PP P P P
L9 VDDarm VDDarm PP P P P
AA21 VDDpadSDRAM VDDpadSDRAM PP P P P
H21 VDDpadSDRAM VDDpadSDRAM PP P P P
N14 VSSpadSDRAM VSSpadSDRAM PP P P P
N15 VDDpadSDRAM VDDpadSDRAM PP P P P
W20 VDDpadSDRAM VDDpadSDRAM PP P P P
Y20 VDDpadSDRAM VDDpadSDRAM PP P P P
J13 VDDpadFlash VDDpadFlash PP P P P
L14 VDDpadFlash VDDpadFlash PP P P P
M10 VDDalive VDDalive PP P P P
P12 VDDalive VDDalive PP P P P
AB1 VDDrtc VDDrtc PP P P P
AB6 VDDadc VDDadc PP P P P
AA8 VDDMpll VDDMpll PP P P P
Y8 VDDupll VDDupll PP P P P
Name Default
Function
I/OI/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
1-14 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Y12 VDDpadUSB VDDpadUSB PP P P P
K12 VSS VSS PP P P P
L11 VSS VSS PP P P P
L12 VSS VSS PP P P P
L13 VSS VSS PP P P P
M11 VSS VSS PP P P P
M12 VSS VSS PP P P P
M13 VSS VSS PP P P P
N11 VSS VSS PP P P P
N12 VSS VSS PP P P P
N13 VSS VSS PP P P P
A2 VSSpadIO VSSpadIO PP P P P
J11 VSSpadIO VSSpadIO PP P P P
M9 VSSpadIO VSSpadIO PP P P P
P11 VSSpadIO VSSpadIO PP P P P
L15 VSSpadSDRAM VSSpadSDRAM PP P P P
M15 VSSpadSDRAM VSSpadSDRAM PP P P P
P13 VSSpadSDRAM VSSpadSDRAM PP P P P
R13 VSSpadSDRAM VSSpadSDRAM PP P P P
J12 VSSpadFlash VSSpadFlash PP P P P
K13 VSSpadFlash VSSpadFlash PP P P P
E3 X2cSCL X2cSCL I/OI/H L or I H phbsud8sm
E2 X2cSDA X2cSDA I/OI/H L or I H phbsud8sm
T1 X2sCDCLK X2sCDCLK OH or L/L Hi-z or H or L H phot8
W4 X2sCLK X2sCLK I/OL/L/L H or L or I L phbsu100ct8sm
Y4 X2sDI X2sDI I I – – phis
U1 X2sDO X2sDO OL/L Hi-z or H or L L phot8
U2 X2sLRCK X2sLRCK I/OH/L/L H or L or I Pre phbsu100ct8sm
P3 X97BITCLK X97BITCLK I I – – phis
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
Preliminary product information describe products that are in development, 1-15
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
N2 X97RESET n X97RESETn OL/L Hi-z or H or L H phot8
T3 X97SDI X97SDI I I – – phis
P2 X97SDO X97SDO OL/L Hi-z or H or L L phot8
N1 X97SYNC X97SYNC OL/L Hi-z or H or L L phot8
AB5 XadcAIN[0] XadcAIN[0] AinI – – phiar10
AC5 XadcAIN[1] XadcAIN[1] AinI – – phiar10
AA6 XadcAIN[2] XadcAIN[2] AinI – – phiar10
Name Default
Function
I/OI/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
_abb
_abb
_abb
1-16 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
AC4 XadcAIN[3] XadcAIN[3] Ain I – – phiar10_abb
AC3 XadcAIN[4] XadcAIN[4] Ain I – – phiar10_abb
AA4 XadcAIN[5] XadcAIN[5] Ain I – – phiar10_abb
AC2 XadcAIN[6] XadcAIN[6] Ain I – – phiar10_abb
AB2 XadcAIN[7] XadcAIN[7] Ain I – – phiar10_abb
AA5 XadcAVREF XadcAVREF Ain I – – phia_abb
A3 XciCDATA[0] XciCDATA[0] I I/H/L – – phbsu100ct8sm
C4 XciCDATA[1] XciCDATA[1] I I/H/L – – phbsu100ct8sm
B5 XciCDATA[2] XciCDATA[2] I I/H/L – – phbsu100ct8sm
B6 XciCDATA[3] XciCDATA[3] I I/H/L – – phbsu100ct8sm
C7 XciCDATA[4] XciCDATA[4] I I/H/L – – phbsu100ct8sm
D9 XciCDATA[5] XciCDATA[5] I I/H/L – – phbsu100ct8sm
C8 XciCDATA[6] XciCDATA[6] I I/H/L – – phbsu100ct8sm
A10 XciCDATA[7] XciCDATA[7] I I/H/L – – phbsu100ct8sm
C3 XciCLK XciCLK O L/L Hi-z or H or LL phot12sm
C6 XciHREF XciHREF I I – – phis
A5 XciPCLK XciPCLK I I – – phis
D4 XciRSTn XciRSTn O L/L Hi-z or H or LPre phot8
D6 XciVSYNC XciVSYNC I I – – phis
B2 XciYDATA[0] XciYDATA[0] I I – – phis
E4 XciYDATA[1] XciYDATA[1] I I – – phis
B3 XciYDATA[2] XciYDATA[2] I I – – phis
F4 XciYDATA[3] XciYDATA[3] I I – – phis
A1 XciYDATA[4] XciYDATA[4] I I – – phis
D5 XciYDATA[5] XciYDATA[5] I I – – phis
B4 XciYDATA[6] XciYDATA[6] I I – – phis
A4 XciYDATA[7] XciYDATA[7] I I – – phis
B22 XfALE XfALE O L/L Hi-z or H or LL phot8
D19 XfCLE XfCLE O L/L Hi-z or H or LL phot8
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
Preliminary product information describe products that are in development, 1-17
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
B23 XfNFACYC XfNFACYC I I – – phis
C23 XfNFADV XfNFADV I I – – phis
D22 XfNFBW XfNFBW I I – – phis
C22 XfNFPS XfNFPS I I – – phis
A23 XfRnB[0] XfRnB[0] I I – – phisu
E20 XfRnB[1] XfRnB[1] I I – – phisu
Y5 XgBATFLT XgBATFLT I H – – phis
AC8 XgMONHCLK XgMONHCLK OL/L Hi-z or H or LL phot8
M1 XgpIO[0]/EINT0 XgpIO[0] I/OI/H/L H or L or I – phbsu100ct8sm
Y6 XgpIO[1]/EINT1/
L2 XgpIO[10]/YMON XgpIO[10] I/OI/H/L H or L or I – phbsu100ct8sm
K1 XgpIO[11]/EINT11
L3 XgpIO[12]/EINT12/
T4 XgpIO[13]/EINT13/
K2 XgpIO[14]/EINT14/
R4 XgpIO[15]/EINT15/
K3 XgpIO[16]/EINT16/
J1 XgpIO[17]/EINT17/
J2 XgpIO[18]/EINT18/
M4 XgpIO[19]/PWM_
R3 XgpIO[2]/EINT2/
H1 XgpIO[20]/PWM_
Name Default
Function
XgpIO[1] I/OI/H/L H or L or I – phbsu100ct8sm
PWM_ECLK
XgpIO[11] I/OI/H/L H or L or I – phbsu100ct8sm
/YPON
XgpIO[12] I/OI/H/L H or L or I – phbsu100ct8sm
XMON
XgpIO[13] I/OI/H/L H or L or I – phbsu100ct8sm
XPON
XgpIO[14] I/OI/H/L H or L or I – phbsu100ct8sm
RTC_ALMINT
XgpIO[15] I/OI/H/L H or L or I – phbsu100ct8sm
XspiMOSI
XgpIO[16] I/OI/H/L H or L or I – phbsu100ct8sm
XspiMISO
XgpIO[17] I/OI/H/L H or L or I – phbsu100ct8sm
XspiCLK
XgpIO[18] I/OI/H/L H or L or I – phbsu100ct8sm
XkpROW0
XgpIO[19] I/OI/H/L H or L or I – phbsu100ct8sm
ECLK/XkpROW1
XgpIO[2] I/OI/H/L H or L or I – phbsu100ct8sm
PWM_TOUT0
XgpIO[20] I/OI/H/L H or L or I – phbsu100ct8sm
TOUT0/ XkpROW2
I/OI/O state@
Reset mode
(Data/En/
PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
1-18 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
M2 XgpIO[6]/EINT6 XgpIO[6] I/OI/H/L H or L or I – phbsu100ct8sm
L1 XgpIO[7]/EINT7 XgpIO[7] I/OI/H/L H or L or I – phbsu100ct8sm
N4 XgpIO[8]/EINT8 XgpIO[8] I/OI/H/L H or L or I – phbsu100ct8sm
U4 XgpIO[9]/EINT9 XgpIO[9] I/OI/H/L H or L or I – phbsu100ct8sm
AA3 XgPWROFFn XgPWROFFnOH L H phob8
Name Default
UT1/XkpROW3
UT2/XkpROW4
UT3/XkpCOL0
EXTDMA_REQ0/
XkpCOL1
REQ1/XkpCOL2
ACK0/ XkpCOL3
ACK1/XkpCOL4
RTC_ALMINT
IrDA_SDBW
PWM_TOUT1
XuTXD1/IrDA_TXD
XuRXD1/ IrDA_RXD
PWM_TOUT2
PWM_TOUT3
I/OI/O state@
Function
XgpIO[21] I/OI/H/L H or L or I – phbsu100ct8sm
XgpIO[22] I/OI/H/L H or L or I – phbsu100ct8sm
XgpIO[23] I/OI/H/L H or L or I – phbsu100ct8sm
XgpIO[24] I/OI/H/L H or L or I – phbsu100ct8sm
XgpIO[25] I/OI/H/L H or L or I – phbsu100ct8sm
XgpIO[26] I/OI/H/L H or L or I – phbsu100ct8sm
XgpIO[27] I/OI/H/L H or L or I – phbsu100ct8sm
XgpIO[28] I/OI/H/L H or L or I – phbsu100ct8sm
XgpIO[29] I/OI/H/L H or L or I – phbsu100ct8sm
XgpIO[3] I/OI/H/L H or L or I – phbsu100ct8sm
XgpIO[30] I/OI/H/L H or L or I – phbsu100ct8sm
XgpIO[31] I/OI/H/L H or L or I – phbsu100ct8sm
XgpIO[4] I/OI/H/L H or L or I – phbsu100ct8sm
XgpIO[5] I/OI/H/L H or L or I – phbsu100ct8sm
Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>
PullUp
I/O State@
SLEEP
Mode
I/O State@
STOP
Mode
Cell Type
(S3C24A0A)
Preliminary product information describe products that are in development, 1-19
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Y15 XmiCSn XmiCSn II – – phisu
AB19 XmiDATA[0] XmiDATA[0] I/OI/H/L H or L or I– phbsu100ct8sm
AC18 XmiDATA[1] XmiDATA[1] I/OI/H/L H or L or I– phbsu100ct8sm
AA19 XmiDATA[2] XmiDATA[2] I/OI/H/L H or L or I– phbsu100ct8sm
AC17 XmiDATA[3] XmiDATA[3] I/OI/H/L H or L or I– phbsu100ct8sm
AB17 XmiDATA[4] XmiDATA[4] I/OI/H/L H or L or I– phbsu100ct8sm
AC16 XmiDATA[5] XmiDATA[5] I/OI/H/L H or L or I– phbsu100ct8sm
AA17 XmiDATA[6] XmiDATA[6] I/OI/H/L H or L or I– phbsu100ct8sm
AB16 XmiDATA[7] XmiDATA[7] I/OI/H/L H or L or I– phbsu100ct8sm
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP
Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
1-20 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
AB18 XmiIRQn XmiIRQn O H/L Hi-z or H or LH phot8
AB14 XmiOEn XmiOEn I I – – phisu
AA14 XmiWEn XmiWEn I I – – phisu
AA13 XmsBS XmsBS O L/L Hi-z or H or LL phot8
Y14 XmsPI XmsPI I I – – phis
AC11 XmsSCLKO XmsSCLKO O H/L Hi-z or H or LH phot8
Y13 XmsSDIO XmsSDIO I/O I/H/L H or L or I – phbsu100ct12sm
L23 XpADDR[0] XpADDR[0] O L/L Hi-z or H or LPre phot12sm
M22 XpADDR[1] XpADDR[1] O L/L Hi-z or H or LPre phot12sm
AC22 XpADDR[10] XpADDR[10] O L/L Hi-z or H or LPre phot12sm
AB21 XpADDR[11] XpADDR[11] O L/L Hi-z or H or LPre phot12sm
AC21 XpADDR[12] XpADDR[12] O L/L Hi-z or H or LPre phot12sm
Y17 XpADDR[13] XpADDR[13] O L/L Hi-z or H or LPre phot12sm
AC20 XpADDR[14] XpADDR[14] O L/L Hi-z or H or LPre phot12sm
M20 XpADDR[2] XpADDR[2] O L/L Hi-z or H or LPre phot12sm
M23 XpADDR[3] XpADDR[3] O L/L Hi-z or H or LPre phot12sm
N21 XpADDR[4] XpADDR[4] O L/L Hi-z or H or LPre phot12sm
N22 XpADDR[5] XpADDR[5] O L/L Hi-z or H or LPre phot12sm
N23 XpADDR[6] XpADDR[6] O L/L Hi-z or H or LPre phot12sm
P22 XpADDR[7] XpADDR[7] O L/L Hi-z or H or LPre phot12sm
AB23 XpADDR[8] XpADDR[8] O L/L Hi-z or H or LPre phot12sm
AC23 XpADDR[9] XpADDR[9] O L/L Hi-z or H or LPre phot12sm
V23 XpCASn XpCASn O H/L Hi-z or H or LPre phot12sm
U22 XpCKE XpCKE O L/L Hi-z or H or LL phot12sm
Name Default
Function
I/O I/O state@
Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
Preliminary product information describe products that are in development, 1-21
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
W22 XpCSN[0] XpCSN[0] O H/L Hi-z or H or LH phot12sm
W23 XpCSN[1] XpCSN[1] O H/L Hi-z or H or LH phot12sm
F21 XpDATA[0] XpDATA[0] I/O I/H/L H or L or I – phbsu100ct12sm
E23 XpDATA[1] XpDATA[1] I/O I/H/L H or L or I – phbsu100ct12sm
K22 XpDATA[10] XpDATA[10] I/O I/H/L H or L or I – phbsu100ct12sm
K23 XpDATA[11] XpDATA[11] I/O I/H/L H or L or I – phbsu100ct12sm
L21 XpDATA[12] XpDATA[12] I/O I/H/L H or L or I – phbsu100ct12sm
L22 XpDATA[13] XpDATA[13] I/O I/H/L H or L or I – phbsu100ct12sm
L20 XpDATA[14] XpDATA[14] I/O I/H/L H or L or I – phbsu100ct12sm
M21 XpDATA[15] XpDATA[15] I/O I/H/L H or L or I – phbsu100ct12sm
P21 XpDATA[16] XpDATA[16] I/O I/H/L H or L or I – phbsu100ct12sm
R21 XpDATA[17] XpDATA[17] I/O I/H/L H or L or I – phbsu100ct12sm
P23 XpDATA[18] XpDATA[18] I/O I/H/L H or L or I – phbsu100ct12sm
R22 XpDATA[19] XpDATA[19] I/O I/H/L H or L or I – phbsu100ct12sm
E22 XpDATA[2] XpDATA[2] I/O I/H/L H or L or I – phbsu100ct12sm
T21 XpDATA[20] XpDATA[20] I/O I/H/L H or L or I – phbsu100ct12sm
T22 XpDATA[21] XpDATA[21] I/O I/H/L H or L or I – phbsu100ct12sm
U21 XpDATA[22] XpDATA[22] I/O I/H/L H or L or I – phbsu100ct12sm
T23 XpDATA[23] XpDATA[23] I/O I/H/L H or L or I – phbsu100ct12sm
T20 XpDATA[24] XpDATA[24] I/O I/H/L H or L or I – phbsu100ct12sm
Y21 XpDATA[25] XpDATA[25] I/O I/H/L H or L or I – phbsu100ct12sm
Y23 XpDATA[26] XpDATA[26] I/O I/H/L H or L or I – phbsu100ct12sm
Y22 XpDATA[27] XpDATA[27] I/O I/H/L H or L or I – phbsu100ct12sm
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
1-22 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
AA23 XpDATA[28] XpDATA[28] I/OI/H/L H or L or I – phbsu100ct12sm
V21 XpDATA[29] XpDATA[29] I/OI/H/L H or L or I – phbsu100ct12sm
F23 XpDATA[3] XpDATA[3] I/OI/H/L H or L or I – phbsu100ct12sm
AB22 XpDATA[30] XpDATA[30] I/OI/H/L H or L or I – phbsu100ct12sm
AA22 XpDATA[31] XpDATA[31] I/OI/H/L H or L or I – phbsu100ct12sm
H20 XpDATA[4] XpDATA[4] I/OI/H/L H or L or I – phbsu100ct12sm
G21 XpDATA[5] XpDATA[5] I/OI/H/L H or L or I – phbsu100ct12sm
F22 XpDATA[6] XpDATA[6] I/OI/H/L H or L or I – phbsu100ct12sm
G23 XpDATA[7] XpDATA[7] I/OI/H/L H or L or I – phbsu100ct12sm
J23 XpDATA[8] XpDATA[8] I/OI/H/L H or L or I – phbsu100ct12sm
K21 XpDATA[9] XpDATA[9] I/OI/H/L H or L or I – phbsu100ct12sm
G22 XpDQM[0] XpDQM[0] OH/L Hi-z or H or L– phot12sm
H22 XpDQM[1] XpDQM[1] OH/L Hi-z or H or L– phot12sm
H23 XpDQM[2] XpDQM[2] OH/L Hi-z or H or L– phot12sm
J22 XpDQM[3] XpDQM[3] OH/L Hi-z or H or L– phot12sm
U23 XpRASn XpRASn OH/L Hi-z or H or L– phot12sm
R23 XpSCLK XpSCLK I/OH or L /L H or L or I L phbst12sm
V22 XpWEn XpWEn OH/L Hi-z or H or LH phot12sm
D16 XrADDR[0] XrADDR[0] OL/L Hi-z or H or LPre phot8
C14 XrADDR[1] XrADDR[1] OL/L Hi-z or H or LPre phot8
A18 XrADDR[10] XrADDR[10] OL/L Hi-z or H or LPre phot8
B19 XrADDR[11] XrADDR[11] OL/L Hi-z or H or LPre phot8
D21 XrADDR[12] XrADDR[12] OL/L Hi-z or H or LPre phot8
Name Default
Function
I/OI/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
Preliminary product information describe products that are in development, 1-23
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
G20 XrADDR[13] XrADDR[13] O L/L Hi-z or H or LPre phot8
D17 XrADDR[14] XrADDR[14] O L/L Hi-z or H or LPre phot8
B20 XrADDR[15] XrADDR[15] O L/L Hi-z or H or LPre phot8
A19 XrADDR[16] XrADDR[16] O L/L Hi-z or H or LPre phot8
A20 XrADDR[17] XrADDR[17] O L/L Hi-z or H or LPre phot8
D15 XrADDR[2] XrADDR[2] O L/L Hi-z or H or LPre phot8
A13 XrADDR[3] XrADDR[3] O L/L Hi-z or H or LPre phot8
D14 XrADDR[4] XrADDR[4] O L/L Hi-z or H or LPre phot8
B14 XrADDR[5] XrADDR[5] O L/L Hi-z or H or LPre phot8
C15 XrADDR[6] XrADDR[6] O L/L Hi-z or H or LPre phot8
A14 XrADDR[7] XrADDR[7] O L/L Hi-z or H or LPre phot8
D20 XrADDR[8] XrADDR[8] O L/L Hi-z or H or LPre phot8
C20 XrADDR [9] XrADDR [9] O L/L Hi-z or H or LPre phot8
F20 XrADDR[18] XrADDR[18] O L/L/H Hi-z or H or LPre phbsu100ct8sm
D18 XrADDR[19] XrADDR[19] O L/L/H Hi-z or H or LPre phbsu100ct8sm
A21 XrADDR[20] XrADDR[20] O L/L/H Hi-z or H or LPre phbsu100ct8sm
C21 XrADDR[21] XrADDR[21] O L/L/H Hi-z or H or LPre phbsu100ct8sm
B21 XrADDR[22] XrADDR[22] O L/L/H Hi-z or H or LPre phbsu100ct8sm
A22 XrADDR[23] XrADDR[23] O L/L/H Hi-z or H or LPre phbsu100ct8sm
E21 XrADDR[24] XrADDR[24] O L/L/H Hi-z or H or LPre phbsu100ct8sm
D23 XrADDR[25] XrADDR[25] O L/L/H Hi-z or H or LPre phbsu100ct8sm
P20 XrCSn[0] XrCSn[0] O H/L Hi-z or H or LPre phot8
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
1-24 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
C17 XrCSn[1] XrCSn[1] O H/L Hi-z or H or LPre phot8
B17 XrCSn[2] XrCSn[2] O H/L Hi-z or H or LPre phot8
A11 XrDATA[0] XrDATA[0] I/O I/H/L H or L or I – phbsu100ct8sm
B11 XrDATA[1] XrDATA[1] I/O I/H/L H or L or I – phbsu100ct8sm
C18 XrDATA[10] XrDAT A[10] I/O I/H/L H or L or I – phbsu100ct8sm
K20 XrDATA[11] XrDATA[11] I/O I/H/L H or L or I – phbsu100ct8sm
C19 XrDATA[12] XrDAT A[12] I/O I/H/L H or L or I – phbsu100ct8sm
A17 XrDATA[13] XrDATA[13] I/O I/H/L H or L or I – phbsu100ct8sm
B18 XrDATA[14] XrDATA[14] I/O I/H/L H or L or I – phbsu100ct8sm
J20 XrDAT A[15] XrDATA[15] I/O I/H/L H or L or I – phbsu100ct8sm
V20 XrDATA[2] XrDATA[2] I/O I/H/L H or L or I – phbsu100ct8sm
B12 XrDATA[3] XrDATA[3] I/O I/H/L H or L or I – phbsu100ct8sm
U20 XrDATA[4] XrDATA[4] I/O I/H/L H or L or I – phbsu100ct8sm
A12 XrDATA[5] XrDATA[5] I/O I/H/L H or L or I – phbsu100ct8sm
C13 XrDATA[6] XrDATA[6] I/O I/H/L H or L or I – phbsu100ct8sm
B13 XrDATA[7] XrDATA[7] I/O I/H/L H or L or I – phbsu100ct8sm
A16 XrDATA[8] XrDATA[8] I/O I/H/L H or L or I – phbsu100ct8sm
N20 XrDATA[9] XrDATA[9] I/O I/H/L H or L or I – phbsu100ct8sm
B15 XrnWBE[0] XrnWBE[0] O H/L Hi-z or H or LPre phot8
A15 XrnWBE[1] XrnWBE[1] O H/L Hi-z or H or LPre phot8
R20 XrOEn XrOEn O H/L Hi-z or H or LH phot8
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
Preliminary product information describe products that are in development, 1-25
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
AA1 XrtcXTI XrtcXTI Ain L – – rtc_osc
AB3 XrtcXTO XrtcXTO Aout X – – rtc_osc
C16 XrWAITn XrWAITn I I – – phis
B16 XrWEn XrWEn O H/L Hi-z or H or LH phot8
AC13 XsdDAT[0] XsdDAT[0] I/O I/H/L H or L or I – phbsu100ct12sm
AB12 XsdDAT[1] XsdDAT[1] I/O I/H/L H or L or I – phbsu100ct12sm
AC12 XsdDAT[2] XsdDAT[2] I/O I/H/L H or L or I – phbsu100ct12sm
Y11 XsdDAT[3] XsdDAT[3] I/O I/H/L H or L or I – phbsu100ct12sm
AB9 XsEXTCLK XsEXTCLK I I – – phis
AC6 XsMPLLCAP XsMPLLCAP Aout X – – Phoar50_abb
Y3 XspiCLK XspiCLK I/O I/H/L H or L or I – phtbsu100ct8sm
W2 XspiMISO XspiMISO I/O H/L/L H or L or I H phtbsu100ct8sm
V1 XspiMOSI XspiMOSI I/O I/H/L H or L or I – phtbsu100ct8sm
W3 XspiSSIn[0] XspiSSIn[0] I I – – phisu
V2 XspiSSIn[1] XspiSSIn[1] I I – – phisu
AA9 XsRESETn XsRESETn I L – – phisu
Y9 XsRSTOUTn XsRSTOUTn O L Hi-z or H or LH phot8
AB8 XsUPLLCAP XsUPLLCAP Aout X – – Phoar50_abb
Y1 XsWRESETn XsWRESETn I L – – phisu
AC9 XsXTIN XsXTIN I H or L – – phsoscm26_schmitt
AA10 XsXTOUT XsXTOUT O H or L – – phsoscm26_schmitt
V4 XuCLK XuCLK I I – – phis
T2 XuCTSn XuCTSn I I – – phis
AB11 XudDN XudDN I/O I H or L or I – pbusb1
Y10 XudDP XudDP I/O I H or L or I – pbusb1
P1 XuRTSn XuRTSn O H/L Hi-z or H or LH phot8
R2 XuRXD XuRXD I I – – phisu
AA12 XusDN[0] XusDN[0] I/O X H or L or I – pbusb1
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
1-26 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
AC10 XusDN[1] XusDN[1] I/OX H or L or I – pbusb1
AA11 XusDP[0] XusDP[0] I/OX H or L or I – pbusb1
AB10 XusDP[1] XusDP[1] I/OX H or L or I – pbusb1
U3 XuTXD XuTXD O H/L Hi-z or H or LH phot8
A9 XvDEN XvDEN O L/L Hi-z or H or LL phot8
C9 XvHSYNC XvHSYNC O L/L Hi-z or H or LPre phot8
A8 XvVCLK XvVCLK O H or L /L Hi-z or H or LL phot12sm
J4 XvVD[6] XvVD[6] O L/L H or L or I Pre phot12sm
B7 XvVD[7] XvVD[7] O L/L H or L or I Pre phot12sm
K4 XvVD[8] XvVD[8] O L/L H or L or I Pre phot12sm
D7 XvVD[9] XvVD[9] O L/L H or L or I Pre phot12sm
D8 XvVD[10] XvVD[10] O L/L H or L or I Pre phot12sm
B8 XvVD[11] XvVD[11] O L/L H or L or I Pre phot12sm
B9 XvVD[12] XvVD[12] O L/L H or L or I Pre phot12sm
D12 XvVD[13] XvVD[13] O L/L H or L or I Pre phot12sm
D3 XvVD[0] XvVD[0] O L/L H or L or I Pre phot12sm
C10 XvVD[14] XvVD[14] O L/L H or L or I Pre phot12sm
B10 XvVD[15] XvVD[15] O L/L H or L or I Pre phot12sm
D13 XvVD[16] XvVD[16] O L/L H or L or I Pre phot12sm
C11 XvVD[17] XvVD[17] O L/L H or L or I Pre phot12sm
G4 XvVD[1] XvVD[1] O L/L H or L or I Pre phot12sm
Name Default
Function
I/OI/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
Preliminary product information describe products that are in development, 1-27
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
C5 XvVD[2] XvVD[2] O L/L H or L or I Pre phot12sm
A6 XvVD[3] XvVD[3] O L/L H or L or I Pre phot12sm
H4 XvVD[4] XvVD[4] O L/L H or L or I Pre phot12sm
A7 XvVD[5] XvVD[5] O L/L H or L or I Pre phot12sm
D11 XvVSYNC XvVSYNC O L/L Hi-z or H or LL phot8
NOTES:
1. ‘–‘ mark indicates the unchanged pin state
2. Hi-z or Pre means Hi-z or Previous value
3. P, I and O mean power, input and output respectively
4. AI/AO means analog input/output
Name Default
Function
I/O I/O state@ Reset mode
(Data/En/PullupEn)
En(L)=>output
PullupEn(L)=>PullUp
I/O State@
SLEEP Mode
I/O State@
STOP Mode
Cell Type
(S3C24A0A)
1-28 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
The table below shows I/O types and the descriptions.
I/O Type Descriptions
vdd12ih 1.2V Vdd for alive
vdd12ih_core 1.2V Vdd for internal logic
vdd33oph 3.3V Vdd for external logic
vdd33th_abb 3.3V Vdd for analog circuit
vdd30th_rtc 3.3V Vdd for rtc circuit
vdd33th_abb 3.3V Vdd for pll circuit
Vss Vss
Phis Input pad, LVCMOS schmitt-trigger level
Phisu Input pad, schmitt-trigger level, pull-up
Phisd Input pad, schmitt-trigger level, pull-down
Pbusb USB pad
phot8 Output pad, tri-state, Io=8mA
phob8 Output pad, Io=8mA
phot12sm Output pad, tri-state, medium slew rate, Io=12mA
phbst12sm Bi-directional pad, LVCMOS schmitt-trigger, pull-up resistor with
control, tri-state, Io=12mA
pbusb1 USB pad
Rtc-osc rtc X-tal
phob1-abb Analog pad
phiar10_abb Analog input pad with 10-ohm resistor
phia_abb Analog input pad
phsoscm26_shmitt Oscillator cell with enable and feedback resistor
phbsu100ct8sm Bi-directional pad, LVCMOS schmitt-trigger, 100Kohm pull-up resistor with
NOTE: phbsu100ct8sm means a bi-directional pad, but this means input pad so long as phbsu100ct8sm is used for
XciCDATA[7:0]
Preliminary product information describe products that are in development, 1-29
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
• Shared Memory Bus (ROM/SRAM/NOR Flash/NAND Flash/External Bus)
Signal I/O Description
XrADDR[25:0] O XrADDR[25:0] (Address Bus for shared memory) outputs the memory address of the
corresponding bank .
XrDATA[15:0] IO XrDATA[15:0] (Data Bus) inputs data during memory read and outputs data during
memory write. The bus width is programmable among 8/16-bit.
XrCSn[2:0] O XrCSn[2:0] (Chip Select) are activated when the address of a memory is within the
address region of each bank. The number of access cycles and the bank size can
be programmed.
XrWEn O XrWEn (Write Enable) indicates that the current bus cycle is a write cycle.
XrOEn O XrOEn (Output Enable) indicates that the current bus cycle is a read cycle.
XrWAITn I XrWAITn requests to prolong a current bus cycle. As long as XrWAITn n is L, the
current bus cycle cannot be completed.
XrnWBE[1:0] O Write Byte Enable
XfCLE O Nand Flash Command Latch Enable
XfALE O Nand Flash Address Latch Enable
XfNFPS I Nand Flash Page Size (0:256HWord, 1:512Byte)
or Advanced Page size(0:1K Hword , 1:2K Byte)
XfNFBW I Nand Flash Bus Width (0:8-bit, 1:16-bit)
XfNFACYC I Nand Flash Address Step (0:3-step, 1:4-step)
or Advanced Address step(0:4-step, 1:5-step)
XfNFADV I To Support advanced 2G Nand Flash
XfRnB[1:0] I Nand Flash Ready and Busy
• SDRAM BUS
Signal I/O Description
XpCSN[1:0] O SDRAM Chip Select
XpCASn O SDRAM Column Address Strobe
XpRASn O SDRAM Row Address Strobe
XpWEn O SDRAM Write Enable
XpCKE O SDRAM Clock Enable
XpDQM[3:0] O SDRAM Data Mask
XpSCLK IO SDRAM Clock
XpADDR[14:0] O SDRAM Address bus
XpDATA[31:0] O SDRAM Data bus
1-30 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
XuCLK I UART 0 clock signal
XuRXD0 I UART 0 receives data input
XuCTSn0 I UART 0 clear to send input signal
XuTXD0 O UART 0 transmits data output
XuRTSn0 O UART 0 request to send output signal
• IIC Bus
Signal I/O Description
X2cSDA IO IIC-bus data
X2cSCL IO IIC-bus clock
• IIS Bus
Signal I/O Description
X2sLRCK IO IIS-bus channel select clock
X2sDO O IIS-bus serial data output
X2sDI I IIS-bus serial data input
X2sCLK IO IIS-bus serial clock
X2sCDCLK O CODEC system clock
• SPI Bus
Signal I/O Description
XspiSSIn[1:0] I SPI chip select(only for slave mode)
XspiCLK IO SPI clock for channel 0
XspiMISO IO XspiMISO is the master data input line, when SPI is configured as a master.
When SPI is configured as a slave, these pins reverse its role. For channel 0
XspiMOSI IO XspiMOSI is the master data output line, when SPI is configured as a master.
When SPI is configured as a slave, these pins reverse its role. For channel 0
Preliminary product information describe products that are in development, 1-31
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
X97BITCLK I AC-Link bit clock(12.288MHz) from AC97 Codec
X97SDI I AC-link Serial Data input from AC97 Codec
X97RESETn O AC-link Reset to Codec
X97SYNC O AC-link Frame Synchronization (Sampling Frequency 48kHz) from AC97 Controllor
X97SDO O AC-link Serial Data output to AC97 Codec
• USB Host
Signal I/O Description
XusDN[1:0] IO DATA(–) from USB host
XusDP[1:0] IO DATA(+) from USB host
• USB Device
Signal I/O Description
XudDN IO DATA(–) for USB peripheral device
XudDP IO DATA(+) for USB peripheral device
Parallel Communzication
• GPIO
Signal I/O Description
XgpIO[31:0] IO General input/output ports
•Modem Interface (8-bit Parallel)
Signal I/O Description
XmiCSn I Chip select, driven by the Modem chip
XmiWEn I Write enable, driven by the Modem chip
XmiOEn I Read enable, driven by the Modem chip
XmiADR[10:0] I Address bus, driven by the Modem chip
XmiDATA[7:0] IO Data bus, driven by the Modem chip
XmiIRQn O Interrupt request to the Modem chip
1-32 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
XciPCLK I Pixel Clock, driven by the Camera processor
XciVSYNC I Vertical Sync, driven by the Camera processor
XciHREF I Horizontal Sync, driven by the Camera processor
XciCDATA[7:0] I Pixel Data for CbCr in 16-bit mode, driven by the Camera processor
XciYDATA[7:0] I Pixel Data for YCbCr in 8-bit mode or for Y in 16-bit mode, driven by the Camera
processor
XciCLK O Master Clock to the Camera processor
XciRSTn O Software Reset to the Camera processor
Display Control
• TFT LCD Display Interface
Signal I/O Description
XvVD[17:0] O LCD pixel data output ports
XvVCLK O Pixel clock signal
XvVSYNC O Vertical synchronous signal
XvHSYNC O Horizontal synchronous signal
XvDEN O Data enable signal
Input Devices
• Analog-to-Digital Converter and Touch Screen Interface
Signal I/O Description
XadcAVREF AI ADC reference top
XadcAIN[7:0] AI ADC analog input
Preliminary product information describe products that are in development, 1-33
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
XsdDAT[3:0] IO SD/MMC card receive/transmit Data
XmsPI I Input port used for insertion/extraction detect of Memory stick
XmsSDIO IO SD/MMC card command signal port (default). If MemoryStick card enable, Memory
stick Serial data in/out port
XmsSCLKO O SD/MMC card Clock (default). If MemoryStick card enable, MemoryStick Clock
XmsBS O MemoryStick Serial bus control signal
System Management
• Reset
Signal I/O Description
XsRESETn I XsRESETn suspends any operation in progress and places S3C24A0A into a known
reset state. For a reset, XsRESETn must be held to L level for at least 4 External
clock after the processor power has been stabilized.
XsWRESETn I System Warm Reset. Reset the whole system while preserves the SDRAM contents
XsRSTOUTn O For external device reset control (XsRSTOUTn = XsRESETn & nWDTRST
& SW_RESET & XsWRESETn)
• Clock
Signal I/O Description
XsMPLLCAP AO Loop filter capacitor for main clock.
XsUPLLCAP AO Loop filter capacitor for USB clock.
XrtcXTI AI 32.768KHz crystal input for RTC.
XrtcXTO AO 32.768KHz crystal output for RTC.
XsXTIN I Crystal Input for internal osc circuit.
XsXTOUT O Crystal Input for internal osc circuit.
XsEXTCLK I External clock source.
1-34 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
XjTRSTn I XjTRSTn (TAP Controller Reset) resets the TAP controller at start.
If debugger(black ICE) is not used, XjTRSTn pin must be issued by a low
active pulse (Typically connected to XsRESETn)
XjTMS I XjTMS (TAP Controller Mode Select) controls the sequence of the TAP
controller’s states.
XjTCK I XjTCK (TAP Controller Clock) provides the clock input for the JTAG logic.
XjRTCK O XjRTCK (TAP Controller Returned Clock) provides the clock output for the
JTAG logic.
XjTDI I XjTDI (TAP Controller Data Input) is the serial input for test instructions and
data.
XjTDO O XjTDO (TAP Controller Data Output) is the serial output for test instructions
and data.
• Misc
Signal I/O Description
XgREFCLKSEL[1:0] I Clock Source Selection
XgREFCLKSEL determines how the clock is made.
XgREFCLKSEL[0] - ‘0’: Main clock source is from XsXTIN,
‘1’: Main clock source is from XsEXTCLK
XgREFCLKSEL[1] - ‘0’: USB clock source is from XsXTIN
‘1’: USB clock source is from XsEXTCLK
XgTMODE[3] I ‘0’ : PAD JTAG(Selection of S3C24A0A boundary scan)
‘1’ : ARM JTAG(Selection of ARM core boundary scan)
XgTMODE[2:1] I These signals must be reserved ‘00’
XgTMODE[0] I ‘0’ : Normal Operation without NAND BOOT
‘1’ : Normal Operation with NAND BOOT
XgBATFLTn I Probe for battery state
(Does not wake up at Stop and Sleep mode in case of low battery state)
XgPWROFFn O 1.2V core power on-off control signal
XgMONHCLK O HCLK clock monitoring. HCLK clock can be monitored through this pin when
the ClkMonOn bit in the CLKCON register is set.
Preliminary product information describe products that are in development, 1-35
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
XxVDDlogic P Core logic VDD (1.2V) for internal logic
XxVDDalive P S3C24A0A reset block and port status register VDD (1.2V).
It should be always supplied whether in normal mode or in Stop and Sleep
mode.
XxVDDarm P Core logic VDD (1.2V) for CPU
XxVDDMpll P S3C24A0A MPLL analog and digital VDD (1.2 V).
XxVDDUpll P S3C24A0A UPLL analog and digital VDD (1.2V)
XxVDDpadIO P S3C24A0A I/O port VDD (3.3V)
XxVDDpadSDRAM P S3C24A0A SDRAM memory IO VDD (3.3V)
XxVDDpadFlash P S3C24A0A NFLASH memory IO VDD (3.3V)
XxVDDpadUSB P S3C24A0A USB IO VDD (3.3V)
XrtcVDD P RTC VDD (3.3V)
(Although RTC function is not used, this pin should be connected to power)
XadcVDD P S3C24A0A ADC VDD(3.3V)
XxVDDpadModem P S3C24A0A MODEM IO VDD (3.3V)
1-36 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
VSS P Core logic VSS for internal logic
VSS for S3C24A0A reset block and port status register
Core logic VSS for CPU
S3C24A0A I/O port VSS
XxVSSpadSDRAM P S3C24A0A SDRAM memory IO VSS
XxVSSpadFlash P S3C24A0A Flash memory IO VSS
XxVSSpadUSB P S3C24A0A USB IO VSS
XxVSSMpll P S3C24A0A MPLL analog and digital VSS.
XxVSSUpll P S3C24A0A UPLL analog and digital VSS
XrtcVSS P RTC VSS
XadcVSS P S3C24A0A ADC VSS
NOTES:
1. I/O means input/output.
2. AI/AO means analog input/output.
3. P means power.
Preliminary product information describe products that are in development, 1-37
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1-38 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Preliminary product information describe products that are in development, 1-39
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1-40 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Preliminary product information describe products that are in development, 1-41
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
The base of all devices internal registers = 0x4000_0000
External Memory Interface
• NAND Flash Controller
Register
Name
Offset Acc.
Unit
Read/
Write
Function
NFCONF 0x0C0_0000W R/W NAND flash configuration
NFCONT 0x0C0_0004NAND flash control
NFCMMD 0x0C0_0008NAND flash command
NFADDR 0x0C0_000CNAND flash address
NFDATA 0x0C0_0010NAND flash data
NFMECCDATA0 0x0C0_0014 NAND flash main area ECC data reg.0
NFMECCDATA1 0x0C0_0018 NAND flash main area ECC data reg.1
NFMECCDATA2 0x0C0_001C NAND flash main area ECC data reg.2
NFMECCDATA3 0x0C0_0020 NAND flash main area ECC data reg.3
NFSECCDATA0 0x0C0_0024 NAND flash spare area ECC data
reg.1
NFSECCDATA1 0x0C0_0028 NAND flash spare area ECC data
reg.2
NFSTAT 0x0C0_002CR NAND flash status
NFESTAT0 0x0C0_0030NAND flash ECC status 0 for I/O[7:0]
NFESTAT1 0x0C0_0034NAND flash ECC status 1 for
I/O[15:8]
NFMECC0 0x0C0_0038NAND flash main area ECC reg.0
NFMECC1 0x0C0_003CNAND flash main area ECC reg.1
NFSECC 0x0C0_0040NAND flash spare area ECC reg.
NFSBLK 0x0C0_0044R/W NAND flash start block address
NFEBLK 0x0C0_0048NAND flash end block address
1-42 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SROM_BW 0x0C2_0000 W R/W SROM bus width & wait control
SROM_BC0 0x0C2_0004 SROM bank0 Control register
SROM_BC1 0x0C2_0008 SROM bank1 Control register
SROM_BC2 0x0C2_000C SROM bank2 Control register
• SDRAM Controller
Register
Name
Offset Acc.
Unit
Read/
Write
Function
SDRAM_BANKCFG 0x0C4_0000 W R/W SDRAM configuration
SDRAM_BANKCON 0x0C4_0004 SDRAM control
SDRAM_REFRESH 0x0C4_0008 SDRAM refresh control
• BUS Matrix
Register
Name
Offset Acc.
Unit
Read/
Write
Function
PRIORITY0 0x0CE_0000 W R/W Priority control for SROMC/NFLASHC
PRIORITY1 0x0CE_0004 Priority control for SDRAMC
General Peripherals
• Interrupt Controller
Register
Name
Offset Acc.
Unit
Read/
Write
Function
SRCPND 0x020_0000 W R/W Interrupt request status
INTMOD 0x020_0004 Interrupt mode control
INTMSK 0x020_0008 Interrupt mask control
PRIORITY 0x020_000C IRQ priority control
INTPND 0x020_0010 Interrupt request status
INTOFFSET 0x020_0014 R Interrupt request source offset
SUBSRCPND 0x020_0018 R/W Sub source pending
INTSUBMSK 0x020_001C Interrupt sub mask
VECINTMOD 0x020_0020 Vectored interrupt mode
VECADDR 0x020_0024 R Vectored mode address
NVECADDR 0x020_0028 R/W Non-vectored mode address
VAR 0x020_002C R Vector address register
Preliminary product information describe products that are in development, 1-43
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
WTCON 0x410_0000 W R/W Watch-dog timer mode
WTDAT 0x410_0004 Watch-dog timer data
WTCNT 0x410_0008 Watch-dog timer count
Function
1-44 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
DISRC0 0x040_0000 W R/W DMA 0 initial source
DISRCC0 0x040_0004 DMA 0 initial source control
DIDST0 0x040_0008 DMA 0 initial destination
DIDSTC0 0x040_000C DMA 0 initial destination control
DCON0 0x040_0010 DMA 0 control
DSTAT0 0x040_0014 R DMA 0 count
DCSRC0 0x040_0018 DMA 0 current source
DCDST0 0x040_001C DMA 0 current destination
DMASKTRIG0 0x040_0020 W R/W DMA 0 mask trigger
DISRC1 0x050_0000 DMA 1 initial source
DISRCC1 0x050_0004 DMA 1 initial source control
DIDST1 0x050_0008 DMA 1 initial destination
DIDSTC1 0x050_000C DMA 1 initial destination control
DCON1 0x050_0010 DMA 1 control
DSTAT1 0x050_0014 R DMA 1 count
DCSRC1 0x050_0018 DMA 1 current source
DCDST1 0x050_001C W DMA 1 current destination
DMASKTRIG1 0x050_0020 R/W DMA 1 mask trigger
DISRC2 0x060_0000 DMA 2 initial source
DISRCC2 0x060_0004 DMA 2 initial source control
DIDST2 0x060_0008 DMA 2 initial destination
DIDSTC2 0x060_000C DMA 2 initial destination control
DCON2 0x060_0010 DMA 2 control
DSTAT2 0x060_0014 R DMA 2 count
DCSRC2 0x060_0018 W DMA 2 current source
DCDST2 0x060_001C DMA 2 current destination
DMASKTRIG2 0x060_0020 R/W DMA 2 mask trigger
DISRC3 0x070_0000 W R/W DMA 3 initial source
DISRCC3 0x070_0004 DMA 3 initial source control
DIDST3 0x070_0008 DMA 3 initial destination
DIDSTC3 0x070_000C DMA 3 initial destination control
DCON3 0x070_0010 DMA 3 control
DSTAT3 0x070_0014 R DMA 3 count
DCSRC3 0x070_0018 DMA 3 current source
DCDST3 0x070_001C DMA 3 current destination
DMASKTRIG3 0x070_0020 R/W DMA 3 mask trigger
Preliminary product information describe products that are in development, 1-45
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
RTCCON 0x420_0040 B R/W RTC control
TICINT 0x420_0044 Tick time count
RTCALM 0x420_0050 RTC alarm control
ALMSEC 0x420_0054 Alarm second
ALMMIN 0x420_0058 Alarm minute
ALMHOUR 0x420_005C Alarm hour
ALMDATE 0x420_0060 Alarm day
ALMMON 0x420_0064 Alarm month
ALMYEAR 0x420_0068 Alarm year
RTCRST 0x420_006C RTC round reset
BCDSEC 0x420_0070 BCD second
BCDMIN 0x420_0074 BCD minute
BCDHOUR 0x420_0078 BCD hour
BCDDATE 0x420_007C BCD day
BCDDAY 0x420_0080 BCD date
BCDMON 0x420_0084 BCD month
BCDYEAR 0x420_0088 BCD year
Function
1-46 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
ULCON0 0x440_0000 W R/W UART 0 line control
UCON0 0x440_0004 UART 0 control
UFCON0 0x440_0008 UART 0 FIFO control
UMCON0 0x440_000C UART 0 modem control
UTRSTAT0 0x440_0010 R UART 0 Tx/Rx status
UERSTAT0 0x440_0014 UART 0 Rx error status
UFSTAT0 0x440_0018 UART 0 FIFO status
UMSTAT0 0x440_001C UART 0 modem status
UTXH0 0x440_0020B W UART 0 transmission hold
URXH0 0x440_0024R UART 0 receive buffer
UBRDIV0 0x440_0028 W R/W UART 0 baud rate divisor
ULCON1 0x440_4000 W R/W UART 1 line control
UCON1 0x440_4004 UART 1 control
UFCON1 0x440_4008 UART 1 FIFO control
UMCON1 0x440_400C UART 1 modem control
UTRSTAT1 0x440_4010 R UART 1 Tx/Rx status
UERSTAT1 0x440_4014 UART 1 Rx error status
UFSTAT1 0x440_4018 UART 1 FIFO status
UMSTAT1 0x440_401C UART 1 modem status
UTXH1 0x440_4020B W UART 1 transmission hold
URXH1 0x440_4024R UART 1 receive buffer
UBRDIV1 0x440_4028W R/W UART 1 baud rate divisor
Preliminary product information describe products that are in development, 1-47
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SPCON0 0x450_0000 W R/W SPI channel 0 control
SPSTA0 0x450_0004 R SPI channel 0 status
SPPIN0 0x450_0008 R/W SPI channel 0 pin control
SPPRE0 0x450_000C SPI channel 0 baud rate prescaler
SPTDAT0 0x450_0010 SPI channel 0 Tx data
SPRDAT0 0x450_0014 R SPI channel 0 Rx data
SPCON1 0x450_0020 R/W SPI channel 1 control
SPSTA1 0x450_0024 R SPI channel 1 status
SPPIN1 0x450_0028 R/W SPI channel 1 pin control
SPPRE1 0x450_002C SPI channel 1 baud rate prescaler
SPTDAT1 0x450_0030 SPI channel 1 Tx data
SPRDAT1 0x450_0034 R SPI channel 1 Rx data
1-48 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
AC_GLBCTRL 0x500_0000 W R/W AC97 global control
AC_GLBSTAT 0x500_0004 R AC97 global status
AC_CODEC_CMD 0x500_0008 R/W AC97 codec command
AC_CODEC_STAT 0x500_000C R AC97 codec status
AC_PCM_ADDR 0x500_0010 R AC97 PCM out/in channel FIFO address
AC_MICADDR 0x500_0014 R AC97 MIC in channel FIFO address
AC_PCMDATA 0x500_0018 R/W AC97 PCM out/in channel FIFO data
AC_MICDATA 0x500_001C R/W AC97 MIC in channel FIFO data
• USB Host
Register
Name
Offset Acc.
Unit
Read/
Write
Function
HcRevision 0x100_0000 W Control and status group
HcControl 0x100_0004
HcCommonStatus 0x100_0008
HcInterruptStatus 0x100_000C
HcInterruptEnable 0x100_0010
HcInterruptDisable 0x100_0014
HcHCCA 0x100_0018 Memory pointer group
HcPeriodCuttentED 0x100_001C
HcControlHeadED 0x100_0020
HcControlCurrentED 0x100_0024
HcBulkHeadED 0x100_0028
HcBulkCurrentED 0x100_002C
HcDoneHead 0x100_0030
HcRmInterval 0x100_0034 Frame counter group
HcFmRemaining 0x100_0038
HcFmNumber 0x100_003C
Preliminary product information describe products that are in development, 1-49
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
FUNC_ADDR_REG 0x4A0_0140B R/W Function address
PWR_REG 0x4A0_0144 Power management
EP_INT_REG 0x4A0_0148EP interrupt pending and clear
USB_INT_REG 0x4A0_0158USB interrupt pending and clear
EP_INT_EN_REG 0x4A0_015C Interrupt enable
USB_INT_EN_REG 0x4A0_016C Interrupt enbale
FRAME_NUM1_REG 0x4A0_0170 R Frame number lower byte
INDEX_REG 0x4A0_0178 R/W Register index
EP0_CSR 0x4A0_0184 Endpoint 0 status
IN_CSR1_REG 0x4A0_0184 In endpoint control status
IN_CSR2_REG 0x4A0_0188 In endpoint control status
MAXP_REG 0x4A0_0180 Endpoint max packet
OUT_CSR1_REG 0x4A0_0190 Out endpoint control status
OUT_CSR2_REG 0x4A0_0194 Out endpoint control status
OUT_FIFO_CNT1_REG 0x4A0_0198 R Endpoint out write count
OUT_FIFO_CNT2_REG 0x4A0_019C Endpoint out write count
EP0_FIFO 0x4A0_01C0 R/W Endpoint 0 FIFO
EP1_FIFO 0x4A0_01C4 Endpoint 1 FIFO
EP2_FIFO 0x4A0_01C8 Endpoint 2 FIFO
EP3_FIFO 0x4A0_01CC Endpoint 3 FIFO
EP4_FIFO 0x4A0_01D0 Endpoint 4 FIFO
EP1_DMA_CON 0x4A0_0200 EP1 DMA interface control
EP1_DMA_UNIT 0x4A0_0204 EP1 DMA Tx unit counter
EP1_DMA_FIFO 0x4A0_0208 EP1 DMA Tx FIFO counter
EP1_DMA_TTC_L 0x4A0_020C EP1 DMA total Tx counter
EP1_DMA_TTC_M 0x4A0_0210 EP1 DMA total Tx counter
EP1_DMA_TTC_H 0x4A0_0214 EP1 DMA total Tx counter
EP2_DMA_CON 0x4A0_0218 B R/W EP2 DMA interface control
EP2_DMA_UNIT 0x4A0_021C EP2 DMA Tx Unit counter
EP2_DMA_FIFO 0x4A0_0220 EP2 DMA Tx FIFO counter
EP2_DMA_TTC_L 0x4A0_0224 EP2 DMA total Tx counter
EP2_DMA_TTC_M 0x4A0_0228 EP2 DMA total Tx counter
EP2_DMA_TTC_H 0x4A0_022C EP2 DMA total Tx counter
EP3_DMA_CON 0x4A0_0240 EP3 DMA interface control
1-50 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
EP3_DMA_UNIT 0x4A0_0244 EP3 DMA Tx unit counter
EP3_DMA_FIFO 0x4A0_0248 EP3 DMA Tx FIFO counter
EP3_DMA_TTC_L 0x4A0_024C EP3 DMA total Tx counter
EP3_DMA_TTC_M 0x4A0_0250 EP3 DMA total Tx counter
EP3_DMA_TTC_H 0x4A0_0254 EP3 DMA total Tx counter
EP4_DMA_CON 0x4A0_0258EP4 DMA interface control
EP4_DMA_UNIT 0x4A0_025C EP4 DMA Tx Unit counter
EP4_DMA_FIFO 0x4A0_0260 EP4 DMA Tx FIFO counter
EP4_DMA_TTC_L 0x4A0_0264 EP4 DMA total Tx counter
EP4_DMA_TTC_M 0x4A0_0268 EP4 DMA total Tx counter
EP4_DMA_TTC_H 0x4A0_026C EP4 DMA total Tx counter
Preliminary product information describe products that are in development, 1-51
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
IrDA _CNT 0x180_0000 W R/W IrDA control
IrDA_MDR 0x180_0004 IrDA mode definition
IrDA_CNF 0x180_0008 IrDA interrupt / DMA configuration
IrDA _IER 0x180_000C IrDA interrupt enable
IrDA _IIR 0x180_0010 R IrDA interrupt identification
IrDA _LSR 0x180_0014 IrDA line status
IrDA _FCR 0x180_0018 R/W IrDA FIFO control
IrDA _PLR 0x180_001C IrDA preamble length
IrDA_RBR 0x180_0020 IrDA receiver & transmitter buffer
IrDA_TXNO 0x180_0024 R The total number of data bytes remained in Tx FIFO
IrDA_RXNO 0x180_0028 The total number of data bytes remained in Rx FIFO
IrDA _TXFLL 0x180_002C R/W IrDA transmit frame-length register low
IrDA _TXFLH 0x180_0030 IrDA transmit frame-length register high
IrDA _RXFLL 0x180_0034 IrDA receive frame-length register low
IrDA _RXFLH 0x180_0038 IrDA receive frame-length register high
1-52 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
INT2AP 0x118_0000 W R/W Interrupt request to AP register
INT2MDM 0x118_0004 Interrupt request to modem register
• GPIO
Register
Name
Offset Acc.
Unit
Read/
Write
Function
GPCON_U 0x480_0000 W R/W GPIO ports configuration register
GPCON_M 0x480_0004 GPIO ports configuration register
GPCON_L 0x480_0008 GPIO ports configuration register
GPDAT 0x480_000C GPIO ports data register
GPPU 0x480_0010 GPIO ports pull-up control register
EXTINTC0 0x480_0018 External interrupt control register 0
EXTINTC1 0x480_001C External interrupt control register 1
EXTINTC2 0x480_0020 External interrupt control register 2
EINTFLT0 0x480_0024 External interrupt filter control register 0
EINTFLT1 0x480_0028 External interrupt filter control register 1
EINTMASK 0x480_0034 External interupt mask register
EINTPEND 0x480_0038 External interupt pending register
PERIPU 0x480_0040 Peri. ports pull-up control register
ALIVECON 0x480_0044 Alive control register
GPDAT_SLEEP 0x480_0048 GPIO output data for sleep mode
GPOEN_SLEEP 0x480_004C GPIO output enable control for sleep mode
GPPU_SLEEP 0x480_0050 GPIO pull-up control register for sleep mode
PERIDAT_SLEEP0 0x480_0054 Peri. ports output data control register 0 for sleep
mode
PERIDAT_SLEEP1 0x480_0058 Peri. ports output data control register 1 for sleep
mode
PERIOEN_SLEEP0 0x480_005C Peri. ports output control register 0 for sleep mode
PERIOEN_SLEEP1 0x480_0060 Peri. ports output control register 1 for sleep mode
PERIPU_SLEEP 0x480_0064 Peri. ports pull-up control register for slee mode
RSTCNT 0x480_0068 Reset count compare register
GPRAM0~15 0x480_0080
General purpose RAM array
~0x480_00BC
Preliminary product information describe products that are in development, 1-53
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1-54 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Cr 4
CICOTRGFMT 0x800_0048 Target image format of codec DMA
CICOCTRL 0x800_004C Codec DMA control related
CICOSCPRERATIO 0x800_0050 Codec pre-scaler ratio control
CICOSCPREDST 0x800_0054 Codec pre-scaler destination format
CICOSCCTRL 0x800_0058 Codec main-scaler control
CICOTAREA 0x800_005C Codec pre-scaler destination format
CICOSTATUS 0x800_0064 R Codec path status
CIPRCLRSA1 0x800_006C R/W
CIPRCLRSA2 0x800_0070
CIPRCLRSA3 0x800_0074
CIPRCLRSA4 0x800_0078
RGB 1
RGB 2
RGB 3
RGB 4
st
frame start address for preview DMA
nd
frame start address for preview DMA
rd
frame start address for preview DMA
th
frame start address for preview DMA
CIPRTRGFMT 0x800_007C Target image format of preview DMA
CIPRCTRL 0x800_0080 Preview DMA control related
CIPRSCPRERATIO 0x800_0084 Preview pre-scaler ratio control
CIPRSCPREDST 0x800_0088 Preview pre-scaler destination format
CIPRSCCTRL 0x800_008C Preview main-scaler control
CIPRTAREA 0x800_0090 Preview pre-scaler destination format
CIPRSTATUS 0x800_0098 R Preview path status
CIIMGCPT 0x800_00A0 R/W Image capture enable command
Preliminary product information describe products that are in development, 1-55
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
MODE 0xA10_0000 W R/W Mode Register [9:0]
PreScale_Ratio 0xA10_0004 Pre-Scale ratio for vertical and horizontal.
PreScaleImgSize 0xA10_0008 Pre-Scaled image size
SRCImgSize 0xA10_000C Source image size
MainScale_H_Ratio 0xA10_0010 Main scale ratio along to horizontal direction
MainScale_V_Ratio 0xA10_0014 Main scale ratio along to vertical direction
DSTImgSize 0xA10_0018 Destination image size
PreScale_SHFactor 0xA10_001C Pre-scale shift factor
ADDRStart_Y 0xA10_0020 DMA Start address for Y or RGB component
ADDRStart_Cb 0xA10_0024 DMA Start address for Cb component
ADDRStart_Cr 0xA10_0028 DMA Start address for Cr component
ADDRStart_RGB 0xA10_002C DMA Start address for RGB component
ADDREnd_Y 0xA10_0030 DMA End address for Y or RGB component
ADDREnd_Cb 0xA10_0034 DMA End address for Cb component
ADDREnd_Cr 0xA10_0038 DMA End address for Cr component
ADDREnd_RGB 0xA10_003C DMA End address for RGB component
Offset_Y 0xA10_0040 Offset of Y component for fetching source image
Offset_Cb 0xA10_0044 Offset of Cb component for fetching source
image
Offset_Cr 0xA10_0048 Offset of Cr component for fetching source image
Offset_RGB 0xA10_004C Offset of RGB component for restoring
destination image
1-56 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Preliminary product information describe products that are in development, 1-57
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1-58 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
VLX_COMMON1 0x940_0000 W R/W VLX common control register1
VLX_FRAMESTARTY 0x940_0004 Y coeff. start address
VLX_FRAMESTARTCB 0x940_0008 Cb coeff. frame start address
VLX_FRAMESTARTCR 0x940_000C Cr coeff. frame start address
VLC_CON1 0x940_0010 Control register in VLC mode
VLC_CON2 0x940_0014 Reserved
VLC_CON3 0x940_0018 VLC result external address
VLC_CON4 0x940_001C Reserved
VLD_CON1 0x940_0020 Control register in VLD mode
VLD_CON2 0x940_0024 VLCed bit stream start address
VLD_CON3 0x940_0028 Reserved
VLX_OUT1 0x940_002C R VLX output information register 1
VLX_OUT2 0x940_0030 VLX output information register 2
Preliminary product information describe products that are in development, 1-59
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
LCDCON1 0xA00_0000 W R/W LCD control 1
LCDCON2 0xA00_0004 R/W LCD control 2
LCDTCON1 0xA00_0008 R/W LCD time control 1
LCDTCON2 0xA00_000C R/W LCD time control 2
LCDTCON3 0xA00_0010 R/W LCD time control 3
LCDOSD1 0xA00_0014 R/W LCD OSD control register
LCDOSD2 0xA00_0018 R/W Foreground image(OSD Image) left top position set
LCDOSD3 0xA00_001C R/W Foreground image(OSD Image) right bottom
(Foreground buffer 2)
LCDINTCON 0xA00_0050 R/W LCD Interrupt Control
LCDKEYCON 0xA00_0054 R/W Color key control 1
LCDKEYVAL 0xA00_0058 R/W Color key control 2
LCDBGCON 0xA00_005C R/W Back-ground color Control
LCDFGCON 0xA00_0060 R/W Fore-ground color Control
LCDDITHCON 0xA00_0064 R/W LCD dithering control for active matrix
1-60 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
KEYDAT 0x490_0000 W R/W The data register for KEYPAD input
KEYINTC 0x490_0004 KEYPAD input ports interrupt control
KEYFLT0 0x490_0008 KEY PAD input filter control
KEYFLT1 0x490_000C KEY PAD input filter control
KEYMAN 0x490_0010 KEYPAD manual scan control
•Analog-to-Digital Converter and Touch Screen Interface
Register
Name
Offset Acc.
Unit
Read/
Write
Function
ADCCON 0x580_0000 W R/W ADC control
ADCTSC 0x580_0004 ADC touch screen control
ADCDLY 0x580_0008 ADC start or interval delay
ADCDAX 0x580_000C R ADC conversion data register X
ADCDAY 0x580_0010 ADC conversion data register Y
Preliminary product information describe products that are in development, 1-61
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SDICON 0x600_0000 W R/W SDI control
SDIPRE 0x600_0004 SDI buad rate prescaler
SDICARG 0x600_0008 SDI command argument
SDICCON 0x600_000C SDI command control
SDICSTA 0x600_0010 R/(C) SDI command status
SDIRSP0 0x600_0014 R SDI response
SDIRSP1 0x600_0018 SDI response
SDIRSP2 0x600_001C SDI response
SDIRSP3 0x600_0020 SDI response
SDIDTIMER 0x600_0024 R/W SDI data / busy timer
SDIBSIZE 0x600_0028 SDI block size
SDIDCON 0x600_002C W R/W SDI data control
SDIDCNT 0x600_0030 R SDI data remain counter
SDIDSTA 0x600_0034 R/(C) SDI data status
SDIFSTA 0x600_0038 R/(C) SDI FIFO status
SDIIMSK 0x600_003C R/W SDI interrupt mask
SDIDAT0 0x600_0040 B, HW, WSDI data0
SDIDAT1 0x600_0044 W SDI data1
SDIDAT2 0x600_0048 SDI data2
SDIDAT3 0x600_004C SDI data3
1-62 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
MSPRE 0x610_0000 W R/W Prescaler control
MSFINTCON 0x610_0004 FIFO interrupt control
TP_CMD 0x610_8000 Transfer protocol command
CTRL_STA 0x610_8004 Command and status
DAT_FIFO 0x610_8008 Data FIFO
INTCTRL_STA 0x610_800C Interrupt control and status
INS_CON 0x610_8010 INS port control
ACMD_CON 0x610_8014 Auto command and polarity control
ATP_CMD 0x610_8018 Auto transfer protocol command
System Management
• PLL Clock Control and Power Management
Register
Name
Offset Acc.
Unit
Read/
Write
Function
LOCKTIME 0x000_0000 W R/W PLL lock time counter
OSCWSET 0x000_0004 OSC settle-down wait time setting
MPLLCON 0x000_0010 MPLL configuration
UPLLCON 0x000_0014 UPLL configuration
CLKCON 0x000_0020 Clock generator control
CLKSRC 0x000_0024 Slow clock control
CLKDIVN 0x000_0028 Clock divider control
PWRMAN 0x000_0030 Power management
SOFTRESET 0x000_0038 Software reset
IMPORTANT NOTES ABOUT S3C24A0A SPECIAL REGISTERS
1. The special registers have to be accessed by the recommended access unit.
2. All registers except ADC registers, RTC registers and UART registers must be read/written in word unit (32bit)
at little/big endian.
3. It is very important that the ADC registers, RTC registers and UART registers be read/written by the specified
access unit and the specified address. Moreover, one must carefully consider which endian mode is used.
4. W : 32-bit register, which must be accessed by LDR/STR or int type pointer (int *).
HW : 16-bit register, which must be accessed by LDRH/STRH or short int type pointer (short int *).
B : 8-bit register, which must be accessed by LDRB/STRB or char type pointer (char int *).
.
Preliminary product information describe products that are in development, 1-63
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
S3C24A0A support external 16-bit bus for NAND Flash/ NOR Flash/ PROM/ SRAM external memory. It’s not
shared with SDRAM bus and support up to 3 Bank for one controller. From now on, we will refer this controller as
SROM Controller.
Below figure show the Address Map configuration of S3C24A0A SROM Controller. S3C24A0A SROM Controller
has 3 kinds of configuration. If user want to use NAND boot loader, it’ll be selected the third configuration which
stepping stone (SRAM 4KB) is on the 0x00000000. And If user want to use ROM type boot, it’ll be selected the
first or second configuration by selecting SFR (Special Function Register) of SROM Controller. In this case user
can use NAND Flash Memory for other usage. At the first configuration, Stepping Stone is used just for buffer of
any master.
0xFFFF_FFFF
0x5000_0000
0x4000_0000
0x2000_0000
0x1000_0000
0x0c00_0000
0x0800_0000
0x0400_0000
0x0000_0000
SROM_BW[9] = 0
TMODE[2:0] = 000
Reserved
AHB/APB SFRs
ReservedReservedReserved
SDRAM
(BANK0/1)
SRAM Buffer
(4KB, No CS)
SROM
(BANK2, XrCSn2)
SROM
(BANK1, XrCSn1)
SROM
(BANK0, XrCSn0)
[Not using NAND flash for boot ROM]
SROM_BW[9] = 1
TMODE[2:0] = 000
ReservedReserved
AHB/APB SFRsAHB/APB SFRs
SDRAMSDRAM
(BANK0/1)(BANK0/1)
ReservedReserved
Stepping stone
(4KBytes)
SROM
(BANK1, XrCSn1)(BANK1, XrCSn1)
SROM
(BANK0, XrCSn0)
TMODE[2:0] = 001
(BANK2, XrCSn2)
[Using NAND flash for boot ROM]
SROM
SROM
Stepping stone
(4KBytes)
256MB
256MB
64MB
64MB
64MB
64MB
Assigned
for
Special Function
Registers
Assigned
for
SDRAM Bank0/1
Accessible Region
Assigned
for
SROM Bank0/1/2
Accessible Region
NOTES:
1. SROM means ROM or SRAM type memory.
2. SFR means Special Function Register.
Figure 2-1. SROM Controller Address Mapping
Preliminary product information describe products that are in development, 2-1
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
• Supports SRAM, various ROMs and NOR flash memory
• Supports only 8 or 16-bit data bus
• Address space : Up to 64MB per Bank
• Supports 3 banks (XrCSn[2:0])
Boot by NAND Flash Memory : XrCSn0’s owner is not SROM Controller but NAND Controller.
Boot by other Memory (Nor Flash or ROM): XrCSn2’s owner is either SROM Controller or NAND Controller
(User can choose it by setting SFR).
• Fixed memory bank start address
• External wait to extend the bus cycle
• Support byte, half-word and word access for external memory
BLOCK DIAGRAM
AHB I/F for SROM SFR
SROM
Decoder
AHB I/F for SROM MEM
SFR
Control &
State Machine
SROM I/F
Singal
Generation
SROM MEM I/F
Figure 2-2. SROM Controller Block Diagram
2-2 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SROM Controller support SROM interface for Bank0 to Bank2. In case of NAND boot, SROM controller can’t
control Bank0 because of its mastership is on NAND Flash Controller. In case of ROM boot, as it mentioned
before, it is possible that Bank2’s master is NAND Flash Controller by setting of users.
Address-bus : 26-bit
Data-bus : 8/16
SRAM/ROM/
NOR Flash/
NAND Flash
Bank 0
SROM
Controller
MEMORY BUS #1
SRAM/ROM/
NOR Flash
SRAM/ROM/
NOR Flash/
NAND Flash
Bank 1
Bank 2
Figure 2-3. Memory Interface Block Diagram
Preliminary product information describe products that are in development, 2-3
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
If the WAIT corresponding to each memory bank is enabled, the XrOEn duration should be prolonged by the
external XrWAITn pin while the memory bank is active. XrWAITn is checked from Tacc-1.The XrOEn will be
deasserted at the next clock after sampling XrWAITn is high. The XrWEn signal have the same relation with
XrOEn.
HCLK
XrADDR
[25:0]
XrCSn
[2:0]
Tacs
XrOEn
XrWAITn
XrDATA
[15:0]
(R)
Tacc=4
Tcos
Figure 2-4. XrWAITn Pin Operation
Delayed
Sampling XrWAITn
2-4 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Preliminary product information describe products that are in development, 2-5
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
SROM_BW 0x40C20000R/W SROM Bus width & wait control 0x000x
SROM_BW Bit Description Initial State
Reserved [15:9] Reserved 0x00
BankNum [9] 0 = XrCSn2’s owner is SROM Controller (In this case Stepping Stone
is just used as 4KB SRAM buffer)
1 = XrCSn2’s owner is NAND Flash Controller
ST2 [8] This bit determines SRAM for using UB/LB for bank2
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
WS2 [7] This bit determines WAIT status for bank2
0 = WAIT disable 1 = WAIT enable
DW2 [6] Indicates data bus width for bank2
0 = 8-bit 1 = 16-bit
ST1 [5] This bit determines SRAM for using UB/LB for bank1
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
WS1 [4] This bit determines WAIT status for bank1
0 = WAIT disable 1 = WAIT enable
DW1 [3] Indicates data bus width for bank1
0 = 8-bit 1 = 16-bit
ST0 [2] This bit determines SRAM for using UB/LB for bank0
0 = Not using UB/LB (XrnWBE[1:0] is dedicated nWBE[1:0])
1 = Using UB/LB (XrnWBE[1:0] is dedicated nBE[1:0]
WS0 [1] This bit determines WAIT status for bank0
0 = WAIT disable 1 = WAIT enable
DW0 [0] Indicates data bus width for bank0 (read only)
0 = 8-bit 1 = 16-bit
0x00
0
0
0
0
0
0
0
0
H/W Set
* DW0 is read only. The value is written by external configuration pin (XfNFBW)
2-6 Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Preliminary product information describe products that are in development, 2-7
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
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