This manual describes SAMSUNG's S3C2440X 16/32-bit RISC microprocessor. SAMSUNG’s S3C24440X is
designed to provide hand-held devices and general applications with low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2440X includes the following components
separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller
(STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART,
4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, Camera
interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2ch SPI and PLL for clock generation.
The S3C2440X has been developed using an ARM920T core, 0.13um CMOS standard cells and a memory
complier. Its low-power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive
applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).
The S3C2440X offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by
Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture
with separate 16KB instruction and 16KB data caches, each with an 8-word line length.
By providing a complete set of common system peripherals, the S3C2440X minimizes overall system costs and
eliminates the need to configure additional components. The integrated on-chip functions that are described in this
document include:
• Power control: Normal, Slow, Idle and Sleep mode
• 8-ch 10-bit ADC and Touch screen interface
• RTC with calendar function
• On-chip clock generator with PLL
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
1-1
2003.10.15
PRODUCT OVERVIEWS3C2440X
FEATURES
Architecture
• Integrated system for hand-held devices and
general embedded applications.
• 16/32-Bit RISC architecture and powerful
instruction set with ARM920T CPU core.
• Enhanced ARM architecture MMU to support
WinCE, EPOC 32 and Linux.
• Instruction cache, data cache, write buffer and
Physical address TAG RAM to reduce the effect
of main memory bandwidth and latency on
performance.
• ARM920T CPU core supports the ARM debug
architecture.
• Internal Advanced Microcontroller Bus
Architecture (AMBA) (AMBA2.0, AHB/APB).
System Manager
• Little/Big Endian support.
• Address space: 128M bytes for each bank (total
1G bytes).
• Supports programmable 8/16/32-bit data bus
width for each bank.
• Fixed bank start address from bank 0 to bank 6.
• Programmable bank start address and bank size
for bank 7.
• Eight memory banks:
– Six memory banks for ROM, SRAM, and others.
– Two memory banks for ROM/SRAM/
Synchronous DRAM.
• Complete Programmable access cycles for all
memory banks.
• Supports external wait signals to expend the bus
cycle.
• Supports self-refresh mode in SDRAM for power-
down.
NAND Flash Boot Loader
• Supports booting from NAND flash memory.
• 4KB internal buffer for booting.
• Supports storage memory for NAND flash
memory after booting.
• Supports Advanced NAND flash
Cache Memory
• 64-way set-associative cache with I-Cache
(16KB) and D-Cache (16KB).
• 8words length per line with one valid bit and two
dirty bits per line.
• Pseudo random or round robin replacement
algorithm.
• Write-through or write-back cache operation to
update the main memory.
• The write buffer can hold 16 words of data and
four addresses.
Clock & Power Manager
• On-chip MPLL and UPLL:
UPLL generates the clock to operate USB
Host/Device.
MPLL generates the clock to operate MCU at
maximum 400Mhz@ 1.2V.
• Clock can be fed selectively to each function
block by software.
•Power mode: Normal, Slow, Idle, and Sleep
mode
Normal mode: Normal operating mode
Slow mode: Low frequency clock without PLL
Idle mode: The clock for only CPU is stopped.
Sleep mode: The Core power including all
peripherals is shut down.
• Woken up by EINT[15:0] or RTC alarm interrupt
from Sleep mode
• Supports various types of ROM for booting
(NOR/NAND Flash, EEPROM, and others).
1-2
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
• 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal
timer with DMA-based or interrupt-based
operation
• Programmable duty cycle, frequency, and polarity
• Dead-zone generation
• Supports external clock sources
RTC (Real Time Clock)
• Full clock feature: msec, second, minute, hour,
date, day, month, and year
• 32.768 KHz operation
• Alarm interrupt
• Time tick interrupt
General Purpose Input/Output Ports
64-byte Rx FIFO.
DMA Controller
• 4-ch DMA controller
• Supports memory to memory, IO to memory,
memory to IO, and IO to IO transfers
• Burst transfer mode to enhance the transfer rate
A/D Converter & Touch Screen Interface
• 8-ch multiplexed ADC
• Max. 500KSPS and 10-bit Resolution
• Internal FET for direct Touch screen interface
LCD Controller STN LCD Displays Feature
• Supports 3 types of STN LCD panels: 4-bit dual
scan, 4-bit single scan, 8-bit single scan display
type
• Supports monochrome mode, 4 gray levels, 16
gray levels, 256 colors and 4096 colors for STN
LCD
• Supports multiple screen size
– Maximum screen size: 2048x1024
– Recommended screen size: max 800x600
– Maximum virtual screen size is 4 Mbytes.
– Maximum virtual screen size in 256 color mode:
4096x1024, 2048x2048, 1024x4096 and others
• 24 external interrupt ports
• Multiplexed input/output ports
UART
• 3-channel UART with DMA-based or interrupt-
based operation
• Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data
transmit/receive (Tx/Rx)
• Supports external clocks for the UART operation
(UARTCLK)
• Programmable baud rate
• Supports IrDA 1.0
• Loopback mode for testing
• Each channel has internal 64-byte Tx FIFO and
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
TFT(Thin Film Transistor) Color Displays Feature
• Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette
color displays for color TFT
• Supports 16 bpp non-palette true-color displays
for color TFT
• Supports maximum 16M color TFT at 24 bpp
mode
• Supports multiple screen size
– Maximum screen size: 2048x1024
– Recommended screen size: max 800x600
– Maximum virtual screen size is 4Mbytes.
–Maximum virtual screen size in 64K color mode:
2048x1024, and others
1-3
2003.10.15
PRODUCT OVERVIEWS3C2440X
FEATURES (Continued)
Watchdog Timer
• 16-bit Watchdog Timer
• Interrupt request or system reset at time-out
IIC-Bus Interface
• 1-ch Multi-Master IIC-Bus
• Serial, 8-bit oriented and bi-directional data
transferscanbemadeatupto100Kbit/sin
Standard mode or up to 400 Kbit/s in Fast mode.
IIS-Bus Interface
• 1-ch IIS-bus for audio interface with DMA-based
operation
• Serial, 8-/16-bit per channel data transfers
• 128 Bytes (64-Byte + 64-Byte) FIFO for Tx/Rx
• Supports IIS format and MSB-justified data format
USB Host
• 2-port USB Host
• Complies with OHCI Rev. 1.0
• Compatible with USB Specification version 1.1
• Compatible with SDIO Card Protocol version 1.0
• Bytes FIFO for Tx/Rx
• DMA based or Interrupt based operation
• Compatible with Multimedia Card Protocol version
2.11
SPI Interface
• Compatible with 2-ch Serial Peripheral Interface
Protocol version 2.11
• 2x8 bits Shift register for Tx/Rx
• DMA-based or interrupt-based operation
Camera Interface
• ITU601/ITU656-format input support (8-bit)
• YCrCb 4:2:2 to 4:2:0 down-sampling
• Up to 1016 Horizontal resolution support
Operating Voltage Range
• Core: 1.2V
• Memory :1.8V/ 2.5V/3.3V
• I/O : 3.3V
USB Device
• 1-port USB Device
• 5 Endpoints for USB Device
• Compatible with USB Specification version 1.1
SD Host Interface
• Compatible with SD Memory Card Protocol
version 1.0
Operating Frequency
• Up to 400MHz
Package
• 289-FBGA
1-4
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440XPRODUCT OVERVIEW
BLOCK DIAGRAM
JTAG
ARM920T
Instruction
MMU
2
A[31:0]
IV
ARM9TDMI
Processor core
(Internal Embedded ICE)
Data
MMU
LCD
CONT.
USB Host CONT.
ExtMaster
NAND Ctrl.
NAND Flash Boot
Loader
C13
C13
IPA[31:0]
DPA[31:0]
LCD
DMA
Instruction
ID[31:0]
DD[31:0]
DVA[31:0]DV2A[31:0]
CACHE
(16KB)
CP15
Data
CACHE
(16KB)
A
H
B
B
U
S
External
Coproc
Interface
Write
Buffer
WriteBack
PA Tag
RAM
BUS CONT.
Arbitor/Decode
Interrupt CONT.
Power
Management
Camera
Interface
Memory CONT.
SRAM/NOR/SDRAM
AMBA
Bus
I/F
WBPA[31:0]
Clock Generator
(MPLL)
Bridge & DMA (4Ch)
UART 0, 1, 2
USB Device
A
P
SDI/MMC
Watchdog
Timer
BUS CONT.
Arbitor/Decode
SPI0,1
SPI
Figure 1-1. S3C2440X Block Diagram
B
B
U
S
I2C
I2S
GPIO
RTC
ADC
Timer/PWM
0 ~ 3, 4(Internal)
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
1-5
2003.10.15
PRODUCT OVERVIEWS3C2440X
PIN ASSIGNMENTS
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1234567891011121314151617
1-6
BOTTOM VIEW
Figure 1-2. S3C2440X Pin Assignments (289-FBGA)
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440XPRODUCT OVERVIEW
Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 1 of 3)
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440XPRODUCT OVERVIEW
NOTE:
1. The @BUS REQ. shows the pin state at the external bus, which i s used by the other bus master.
2. ' – ‘ mark indicates the unchange d pin state at Bus Request mode.
3. Hi-z or Pre means Hi-z or early state and it is det ermined by th e setting of MISCCR register.
4. AI/AO means analog input/analog output.
5. P, I, and O mean power, input and output respectively.
6. The I/O state @nRESET shows the pin status in the @nRESET duration below.
@nRESET4FCLK
nRESET
FCLK
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
1-19
2003.10.15
PRODUCT OVERVIEWS3C2440X
7.The t able below shows I/O types and the descriptions.
I/O TypeDescriptions
d12i(vdd12ih)1.2V Vdd for alive power
d12c(vdd12ih_core), si(vssih)1.2V Vdd/Vss for internal logic
d33o(vdd33oph), so(vssoph)3.3V Vdd/Vss for external logic
d33t(vdd33th_abb), st(vssbbh_abb) 3.3V Vdd/Vss for analog circuitry
drtc(vdd30th_rtc)3.0V Vdd for RTC power
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440XPRODUCT OVERVIEW
SIGNAL DESCRIPTIONS
Table 1-3. S3C2440X Signal Descriptions (Sheet 1 of 6)
SignalI/ODescriptions
Bus Controller
OM[1:0]IOM[1:0] sets S3C2440X in the TEST mode, which is used only at fabrication. Also, it
determines the bus width of nGCS0. The pull-up/down resistor determines the logic
level during RESET cycle.
00:Nand-boot01:16-bit10:32-bit11:Test mode
ADDR[26:0]OADDR[26:0] (Address Bus) outputs the memory address of the corresponding bank .
DATA[31:0]IODATA[31:0] (Data Bus) inputs data during memory read and outputs data during
memory write. The bus width is programmable among 8/16/32-bit.
nGCS[7:0]OnGCS[7:0] (General Chip Select) are activated when the address of a memory is
within the address region of each bank. The number of access cycles and the bank
size can be programmed.
nWEOnWE (Write Enable) indicates that the current bus cycle is a write cycle.
nOEOnOE (Output Enable) indicates that the current bus cycle is a read cycle.
nXBREQInXBREQ (Bus Hold Request) allows another bus master to request control of the
local bus. BACK active indicates that bus control has been granted.
nXBACKOnXBACK (Bus Hold Acknowledge) indicates that the S3C2440X has surrendered
control of the local bus to another bus master.
nWAITInWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the current
bus cycle cannot be completed.
SDRAM/SRAM
nSRASOSDRAM Row Address Strobe
nSCASOSDRAM Column Address Strobe
nSCS[1:0]OSDRAM Chip Select
DQM[3:0]OSDRAM Data Mask
SCLK[1:0]OSDRAM Clock
SCKEOSDRAM Clock Enable
nBE[3:0]OUpper Byte/Lower Byte Enable(In case of 16-bit SRAM)
nWBE[3:0]OWrite Byte Enable
STN/TFT/SEC TFT: LCD Data Bus
STN/TFT/SEC TFT: LCD panel power enable control signal
STN/TFT: LCD clock signal
STN: LCD Frame signal
STN: LCD line signal
STN: VM alternates the polarity of the row and column voltage
TFT: Vertical synchronous signal
TFT: Horizontal synchronous signal
TFT: Data enable signal
TFT: Line End signal
SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal
SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal
SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal
SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal
SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal
SEC TFT: Timing control signal for specific TFT LCD
SEC TFT: Timing control signal for specific TFT LCD
LCD_LPCREVBO
SEC TFT: Timing control signal for specific TFT LCD
CAMERA Interface
CAMRESETOSoftware Reset to the Camera
CAMCLKOUTOMaster Clock to the Camera
CAMPCLKIPixel clock from Camera
CAMHREFIHorizontal sync signal from Camera
CAMVSYNCIVertical sync signal from Camera
CAMDATA[7:0]IPixel data for YCbCr
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440XPRODUCT OVERVIEW
Table 1-3. S3C2440X Signal Descriptions (Sheet 3 of 6)
SignalI/ODescriptions
UART
RxD[2:0]IUART receives data input
TxD[2:0]OUART transmits data output
nCTS[1:0]IUART clear to send input signal
nRTS[1:0]OUART request to send output signal
UARTCLKIUART clock signal
ADC
AIN[7:0]AIADC input[7:0]. If it isn’t used pin, it has to be Low (Ground).
VrefAIADC Vref
IIC-Bus
IICSDAIOIIC-bus data
IICSCLIOIIC-bus clock
IIS-Bus
I2SLRCKIOIIS-bus channel select clock
I2SSDOOIIS-bus serial data output
I2SSDIIIIS-bus serial data input
I2SSCLKIOIIS-bus serial clock
CDCLKOCODEC system clock
Touch Screen
nXPONOPlus X-axis on-off control signal
XMONOMinus X-axis on-off control signal
nYPONOPlus Y-axis on-off control signal
YMONOMinus Y-axis on-off control signal
USB Host
DN[1:0]IODATA(–) from USB host
DP[1:0]IODATA(+) from USB host
USB Device
PDN0IODATA(–) for USB peripheral
PDP0IODATA(+) for USB peripheral
SPI
SPIMISO[1:0]IOSPIMISO is the master data input line, when SPI is configured as a master.
When SPI is configured as a slave, these pins reverse its role.
SPIMOSI[1:0]IOSPIMOSI is the master data output line, when SPI is configured as a master.
When SPI is configured as a slave, these pins reverse its role.
SPICLK[1:0]IOSPI clock
nSS[1:0]ISPI chip select(only for slave mode)
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
1-23
2003.10.15
PRODUCT OVERVIEWS3C2440X
Table 1-3. S3C2440X Signal Descriptions (Sheet 4 of 6)
SignalI/ODescription
SD
SDDAT[3:0]IOSD receive/transmit data
SDCMDIOSD receive response/ transmit command
SDCLKOSD clock
General Port
GPn[116:0]IOGeneral input/output ports (some ports are output only)
nTRSTInTRST(TAP Controller Reset) resets the TAP controller at start.
If debugger is used, A 10K pull-up resistor has to be connected.
If debugger(black ICE) is not used, nTRST pin must be issued by a low active
pulse(Typically connected to nRESET).
TMSITMS (TAP Controller Mode Select) controls the sequence of the TAP controller's
states. A 10K pull-up resistor has to be connected to TMS pin.
TCKITCK (TAP Controller Clock) provides the clock input for the JTAG logic.
A 10K pull-up resistor must be connected to TCK pin.
TDIITDI (TAP Controller Data Input) is the serial input for test instructions and data.
A 10K pull-up resistor must be connected to TDI pin.
TDOOTDO (TAP Controller Data Output) is the serial output for test instructions and data.
1-24
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440XPRODUCT OVERVIEW
Table 1-3. S3C2440X Signal Descriptions (Sheet 5 of 6)
SignalI/ODescription
Reset, Clock & Power
XTOpllAOCrystal Output for internal osc circuit.
When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source.
When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only.
When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only.
If it isn't used, it has to be a floating pin.
MPLLCAPAILoop filter capacitor for main clock.
UPLLCAPAILoop filter capacitor for USB clock.
XTIrtcAI32 kHz crystal input for RTC. If it isn’t used, it has to be High (3.3V).
XTOrtcAO32 kHz crystal output for RTC. If it isn’t used, it has to be Float.
CLKOUT[1:0]OClock output signal. The CLKSEL of MISCCR register configures the clock output
mode among the MPLL CLK, UPLL CLK, FCLK, HCLK, PCLK.
nRESETSTnRESET suspends any operation in progress and places S3C2440X into a known
reset state. For a reset, nRESET must be held to L level for at least 4 FCLK after the
processor power has been stabilized.
nRSTOUTOFor external device reset control(nRSTOUT = nRESET & nWDTRST & SW_RESET)
PWRENO1.2V core power on-off control signal
nBATT_FLTIProbe for battery state(Does not wake up at Sleep mode in case of low battery state).
If it isn’t used, it has to be High (3.3V).
OM[3:2]IOM[3:2] determines how the clock is made.
OM[3:2] = 00b, Crystal is used for MPLL CLK source and UPLL CLK source.
OM[3:2] = 01b, Crystal is used for MPLL CLK source
and EXTCLK is used for UPLL CLK source.
OM[3:2] = 10b, EXTCLK is used for MPLL CLK source
and Crystal is used for UPLL CLK source.
OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source.
EXTCLKIExternal clock source.
When OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source.
When OM[3:2] = 10b, EXTCLK is used for MPLL CLK source only.
When OM[3:2] = 01b, EXTCLK is used for UPLL CLK source only.
If it isn't used, it has to be High (3.3V).
XTIpllAICrystal Input for internal osc circuit.
When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source.
When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only.
When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only.
If it isn't used, XTIpll has to be High (3.3V).
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
1-25
2003.10.15
PRODUCT OVERVIEWS3C2440X
Table 1-3. S3C2440X Signal Descriptions (Sheet 6 of 6)
SignalI/ODescription
Power
VDDalivePS3C2440X reset block and port status register VDD(1.2V).
It should be always supplied whether in normal mode or in Sleep mode.
VDDi/VDDiarmPS3C2440X core logic VDD(1.2V) for CPU.
VSSi/VSSiarmPS3C2440X core logic VSS
VDDi_MPLLPS3C2440X MPLL analog and digital VDD (1.2 V).
VSSi_MPLLPS3C2440X MPLL analog and digital VSS.
VDDOPPS3C2440X I/O port VDD(3.3V)
VDDMOPPS3C2440X Memory I/O VDD
3.3V : SCLK up to 100MHz
2.5V : SCLK up to 80MHz
VSSOPPS3C2440X I/O port VSS
RTCVDDPRTC VDD (3.0V)
(This pin must be connected to power properly if RTC isn't used)
VDDi_UPLLPS3C2440X UPLL analog and digital VDD (1.2V)
VSSi_UPLLPS3C2440X UPLL analog and digital VSS
VDDA_ADCPS3C2440X ADC VDD(3.3V)
VSSA_ADCPS3C2440X ADC VSS
NOTE:
1.I/O means input/output.
2.AI/AO means analog input/analog output.
3.ST means schmitt-trigger.
4.P means power.
1-26
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440XPRODUCT OVERVIEW
S3C2440X SPECIAL REGISTERS
Table 1-4. S3C2440X Special Registers (Sheet 1 of 14)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
Memory Controller
BWSCON0x48000000
←
WR/WBus Width & Wait Status Control
BANKCON00x48000004Boot ROM Control
BANKCON10x48000008BANK1 Control
BANKCON20x4800000CBANK2 Control
BANKCON30x48000010BANK3 Control
BANKCON40x48000014BANK4 Control
BANKCON50x48000018BANK5 Control
BANKCON60x4800001CBANK6 Control
BANKCON70x48000020BANK7 Control
REFRESH0x48000024DRAM/SDRAM Refresh Control
BANKSIZE0x48000028Flexible Bank Size
MRSRB60x4800002CMode register set for SDRAM BANK6
MRSRB70x48000030Mode register set for SDRAM BANK7
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
1-27
2003.10.15
PRODUCT OVERVIEWS3C2440X
Table 1-4. S3C2440X Special Registers (Sheet 2 of 14)
Register NameAddress
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
USB Host Controller
HcRevision0x49000000
←
WControl and Status Group
HcControl0x49000004
HcCommonStatus0x49000008
HcInterruptStatus0x4900000C
HcInterruptEnable0x49000010
HcInterruptDisable0x49000014
HcHCCA0x49000018Memory Pointer Group
HcPeriodCuttentED0x4900001C
HcControlHeadED0x49000020
HcControlCurrentED0x49000024
HcBulkHeadED0x49000028
HcBulkCurrentED0x4900002C
HcDoneHead0x49000030
HcRmInterval0x49000034Frame Counter Group
HcFmRemaining0x49000038
HcFmNumber0x4900003C
HcPeriodicStart0x49000040
HcLSThreshold0x49000044
HcRhDescriptorA0x49000048Root Hub Group
HcRhDescriptorB0x4900004C
HcRhStatus0x49000050
HcRhPortStatus10x49000054
HcRhPortStatus20x49000058
Interrupt Controller
SRCPND0X4A000000
←
WR/WInterrupt Request Status
INTMOD0X4A000004WInterrupt Mode Control
INTMSK0X4A000008R/WInterrupt Mask Control
PRIORITY0X4A00000CWIRQ Priority Control
INTPND0X4A000010R/WInterrupt Request Status
INTOFFSET0X4A000014RInterrupt request source offset
SUBSRCPND0X4A000018R/WSub source pending
INTSUBMSK0X4A00001CR/WInterrupt sub mask
1-28
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
2003.10.15
S3C2440XPRODUCT OVERVIEW
Table 1-4. S3C2440X Special Registers (Sheet 3 of 14)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
DMA
DISRC00x4B000000
←
WR/WDMA 0 Initial Source
DISRCC00x4B000004DMA 0 Initial Source Control
DIDST00x4B000008DMA 0 Initial Destination
DIDSTC00x4B00000CDMA 0 Initial Destination Control
DCON00x4B000010DMA 0 Control
DSTAT00x4B000014RDMA 0 Count
DCSRC00x4B000018DMA 0 Current Source
DCDST00x4B00001CDMA 0 Current Destination
DMASKTRIG00x4B000020R/WDMA 0 Mask Trigger
DISRC10x4B000040DMA 1 Initial Source
DISRCC10x4B000044DMA 1 Initial Source Control
DIDST10x4B000048DMA 1 Initial Destination
DIDSTC10x4B00004CDMA 1 Initial Destination Control
DCON10x4B000050DMA 1 Control
DSTAT10x4B000054RDMA 1 Count
DCSRC10x4B000058DMA 1 Current Source
DCDST10x4B00005CDMA 1 Current Destination
DMASKTRIG10x4B000060R/WDMA 1 Mask Trigger
DISRC20x4B000080DMA 2 Initial Source
DISRCC20x4B000084DMA 2 Initial Source Control
DIDST20x4B000088DMA 2 Initial Destination
DIDSTC20x4B00008CDMA 2 Initial Destination Control
DCON20x4B000090DMA 2 Control
DSTAT20x4B000094RDMA 2 Count
DCSRC20x4B000098DMA 2 Current Source
DCDST20x4B00009CDMA 2 Current Destination
DMASKTRIG20x4B0000A0R/WDMA 2 Mask Trigger
DISRC30x4B0000C0
←
WR/WDMA 3 Initial Source
DISRCC30x4B0000C4DMA 3 Initial Source Control
DIDST30x4B0000C8DMA 3 Initial Destination
DIDSTC30x4B0000CCDMA 3 Initial Destination Control
DCON30x4B0000D0DMA 3 Control
DSTAT30x4B0000D4RDMA 3 Count
DCSRC30x4B0000D8DMA 3 Current Source
DCDST30x4B0000DCDMA 3 Current Destination
DMASKTRIG30x4B0000E0R/WDMA 3 Mask Trigger
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
1-29
2003.10.15
PRODUCT OVERVIEWS3C2440X
Table 1-4. S3C2440X Special Registers (Sheet 4 of 14)
Register
Name
Address
(B. Endian)
Address
(L. Endian)
Acc.
Unit
Read/
Write
Function
Clock & Power Management
LOCKTIME0x4C000000
←
WR/WPLL Lock Time Counter
MPLLCON0x4C000004MPLL Control
UPLLCON0x4C000008UPLL Control
CLKCON0x4C00000CClock Generator Control
CLKSLOW0x4C000010Slow Clock Control
CLKDIVN0x4C000014Clock divider Control
CAMDIVN0x4C000018Camera Clock divider Control
LCD Controller
LCDCON10X4D000000
←
WR/WLCD Control 1
LCDCON20X4D000004LCD Control 2
LCDCON30X4D000008LCD Control 3
LCDCON40X4D00000CLCD Control 4
LCDCON50X4D000010LCD Control 5
LCDSADDR10X4D000014STN/TFT: Frame Buffer Start
Address1
LCDSADDR20X4D000018STN/TFT: Frame Buffer Start
Address2
LCDSADDR30X4D00001CSTN/TFT: Virtual Screen Address Set
REDLUT0X4D000020STN: Red Lookup Table
GREENLUT0X4D000024STN: Green Lookup Table
BLUELUT0X4D000028STN: Blue Lookup Table
DITHMODE0X4D00004CSTN: Dithering Mode
TPAL0X4D000050TFT: Temporary Palette
LCDINTPND0X4D000054LCD Interrupt Pending
LCDSRCPND0X4D000058LCD Interrupt Source
LCDINTMSK0X4D00005CLCD Interrupt Mask
TCONSEL0X4D000060TCON(LPC3600/LCC3600) Control
1-30
Preliminary product information describes products that are in development,
for which full characterization data and associated errata are not yet available
Specifications and information herein are subject to change without notice.
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