SAMSUNG S3C2440A User Guide

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S3C2440A

32-BIT CMOS

MICROCONTROLLER

USER'S MANUAL

Revision 1

Important Notice

The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.

Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes.

This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others.

Samsung makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability, including without limitation any consequential or incidental damages.

"Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts.

Samsung products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, for other applications intended to support or sustain life, or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur.

Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application, the Buyer shall indemnify and hold Samsung and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, expenses, and reasonable attorney fees arising out of, either directly or indirectly, any claim of personal injury or death that may be associated with such unintended or unauthorized use, even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product.

S3C2440A 32-Bit CMOS Microcontroller User's Manual, Revision 1 Publication Number: 21-S3-C2440A-072004

form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written consent of Samsung Electronics.

Samsung Electronics' microcontroller business has been awarded full ISO-14001 certification (BVQ1 Certificate No. 9330). All semiconductor products are designed and manufactured in accordance with the highest quality standards and objectives.

Samsung Electronics Co., Ltd. San #24 Nongseo-Ri, Giheung- Eup Yongin-City, Gyeonggi-Do, Korea C.P.O. Box #37, Suwon 449-900

TEL: (82)-(031)-209-1490 FAX: (82) (331) 209-1909 Home-Page URL: Http://www.samsungsemi.com/

Printed in the Republic of Korea

Table of Contents

Chapter 1 Product Overview

Introduction.........................................................................................................................................1-1

Features.............................................................................................................................................1-2

Block Diagram ....................................................................................................................................1-5

Pin Assignments .................................................................................................................................1-6

Signal Descriptions ..............................................................................................................................1-20

S3C2440A Special Registers ................................................................................................................1-26

Chapter 2 Programmer's Model

Overview.............................................................................................................................................2-1

Processor Operating States .........................................................................................................2-1

Switching State...........................................................................................................................2-1

Memory Formats .........................................................................................................................2-1

Big-Endian Format .......................................................................................................................2-2

Little-Endian Format ....................................................................................................................2-2

Instruction Length........................................................................................................................2-2

Operating Modes.........................................................................................................................2-3

Registers....................................................................................................................................2-3

The Program Status Registers......................................................................................................2-7

Exceptions .................................................................................................................................2-10

Interrupt Latencies.......................................................................................................................2-15

Reset .........................................................................................................................................2-15

S3C2440A MICROCONTROLLER iii

Table of Contents (Continued)

Chapter 3 ARM Instruction Set

Instruction Set Summay .......................................................................................................................3-1

Format Summary ........................................................................................................................3-1

Instruction Summary ....................................................................................................................3-2

The Condition Field ..............................................................................................................................3-4

Branch and Exchange (Bx)...................................................................................................................3-5

Instruction Cycle Times ................................................................................................................3-5

Assembler Syntax.......................................................................................................................3-5

Using R15 as an Operand ............................................................................................................3-5

Branch and Branch with Link (B, Bl) ......................................................................................................3-7

The Link Bit ................................................................................................................................3-7

Instruction Cycle Times ................................................................................................................3-7

Assembler Syntax.......................................................................................................................3-8

Data Processing..................................................................................................................................3-9

Cpsr Flags..................................................................................................................................3-11

Shifts .........................................................................................................................................3-12

Immediate Operand Rotates .........................................................................................................3-16

Writing to R15 .............................................................................................................................3-16

Using R15 as an Operandy ...........................................................................................................3-16

TEQ, TST, Cmp and Cmn Opcodes ...............................................................................................3-16

Instruction Cycle Times ................................................................................................................3-16

Assembler Syntax.......................................................................................................................3-17

Examples ...................................................................................................................................3-17

Psr Transfer (MRS, MSR).....................................................................................................................3-18

Operand Restrictions ...................................................................................................................3-18

Reserved Bits..............................................................................................................................3-20

Examples ...................................................................................................................................3-20

Instruction Cycle Times ................................................................................................................3-20

Assembly Syntax........................................................................................................................3-21

Examples ...................................................................................................................................3-21

Multiply And Multiply-Accumulate (MUL, MLA).......................................................................................3-22

Cpsr Flags..................................................................................................................................3-24

Instruction Cycle Times ................................................................................................................3-24

Assembler Syntax.......................................................................................................................3-24

Examples ...................................................................................................................................3-24

Multiply Long And Multiply-Accumulate Long (MULL, MLAL)...................................................................3-25

Operand Restrictions ...................................................................................................................3-26

Cpsr Flags..................................................................................................................................3-26

Instruction Cycle Times ................................................................................................................3-26

Assembler Syntax.......................................................................................................................3-27

Examples ...................................................................................................................................3-27

iv S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 3 ARM Instruction Set (Continued)

Single Data Transfer (LDR, STR) ...........................................................................................................3-28

Offsets and Auto-Indexing ............................................................................................................3-29

Shifted Register Offset .................................................................................................................3-29

Bytes and Words ........................................................................................................................3-29

Use of R15..................................................................................................................................3-31

Example.....................................................................................................................................3-31

Data Aborts ................................................................................................................................3-31

Instruction Cycle Times ................................................................................................................3-31

Assembler Syntax.......................................................................................................................3-32

Examples ...................................................................................................................................3-33

Halfword and Signed Data Transfer (LDRH/STRH/LDRSB/LDRSH) ...........................................................3-34

Offsets and Auto-Indexing ............................................................................................................3-35

Halfword Load and Stores .............................................................................................................3-36

Use of R15..................................................................................................................................3-37

Data Aborts ................................................................................................................................3-37

Instruction Cycle Times ................................................................................................................3-37

Assembler Syntax.......................................................................................................................3-38

Examples ...................................................................................................................................3-39

Block Data Transfer (LDM, STM)...........................................................................................................3-40

The Register List.........................................................................................................................3-40

Addressing Modes .......................................................................................................................3-41

Address Alignment ......................................................................................................................3-41

Use of the S Bit...........................................................................................................................3-43

Use of R15 as The Base..............................................................................................................3-43

Inclusion of the Base in the Register List.......................................................................................3-44

Data Aborts ................................................................................................................................3-44

Instruction Cycle Times ................................................................................................................3-44

Assembler Syntax.......................................................................................................................3-45

Examples ...................................................................................................................................3-46

Single Data Swap (SWP) .....................................................................................................................3-47

Bytes and Words ........................................................................................................................3-47

Use of R15..................................................................................................................................3-48

Data Aborts ................................................................................................................................3-48

Instruction Cycle Times ................................................................................................................3-48

Assembler Syntax.......................................................................................................................3-48

Software Interrupt (SWI).......................................................................................................................3-49

Return from the Supervisor ...........................................................................................................3-49

Comment Field............................................................................................................................3-49

Instruction Cycle Times ................................................................................................................3-49

Assembler Syntax.......................................................................................................................3-50

Coprocessor Data Operations (CDP) .....................................................................................................3-51

Coprocessor Instructions ..............................................................................................................3-51

Instruction Cycle Times ................................................................................................................3-52

Examples ...................................................................................................................................3-52

S3C2440A MICROCONTROLLER v

Table of Contents (Continued)

Chapter 3 ARM Instruction Set (Continued)

Coprocessor Data Transfers (LDC, STC) ................................................................................................3-53

The Coprocessor Fields ...............................................................................................................3-54

Addressing Modes .......................................................................................................................3-54

Address Alignment ......................................................................................................................3-54

Data Aborts ................................................................................................................................3-54

Assembler Syntax.......................................................................................................................3-55

Examples ...................................................................................................................................3-55

Coprocessor Register Transfers (MRC, MCR).................................................................................3-56

The Coprocessor Fields ...............................................................................................................3-56

Transfers to R15 ..........................................................................................................................3-57

Transfers from R15 ......................................................................................................................3-57

Instruction Cycle Times ................................................................................................................3-57

Assembler Syntax.......................................................................................................................3-57

Examples ...................................................................................................................................3-57

Undefined Instruction ...................................................................................................................3-58

Instruction Cycle Times ................................................................................................................3-58

Assembler Syntax.......................................................................................................................3-58

Instruction Set Examples .............................................................................................................3-59

Using the Conditional Instructions .................................................................................................3-59

Pseudo-Random Binary Sequence Generator.................................................................................3-61

Multiplication by Constant Using the Barrel Shifter..........................................................................3-61

Loading a Word from an Unknown Alignment .................................................................................3-63

Chapter 4 Thumb Instruction Set

Thumb Instruction Set Format ...............................................................................................................4-1

Format Summary ........................................................................................................................4-2

Opcode Summary .......................................................................................................................4-3

Format 1: Move Shifted Register...........................................................................................................4-5

Operation....................................................................................................................................4-5

Instruction Cycle Times ................................................................................................................4-6

Examples ...................................................................................................................................4-6

Format 2: Add/Subtract........................................................................................................................4-7

Operation....................................................................................................................................4-7

Instruction Cycle Times ................................................................................................................4-8

Examples ...................................................................................................................................4-8

Format 3: Move/Compare/Add/Subtract Immediate .................................................................................4-9

Operations..................................................................................................................................4-9

Instruction Cycle Times ................................................................................................................4-10

Examples ...................................................................................................................................4-10

vi S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 4 Thumb Instruction Set (Continued)

Format 4: ALU Operations ....................................................................................................................4-11

Operation....................................................................................................................................4-11

Instruction Cycle Times ................................................................................................................4-12

Examples ...................................................................................................................................4-12

Format 5: Hi-Register Operations/Branch Exchange...............................................................................4-13

Operation....................................................................................................................................4-13

Instruction Cycle Times ................................................................................................................4-14

The BX Instruction .......................................................................................................................4-14

Examples ...................................................................................................................................4-15

Using R15 As an Operand ............................................................................................................4-15

Format 6: PC-Relative Load ..................................................................................................................4-16

Operation....................................................................................................................................4-16

Instruction Cycle Times ................................................................................................................4-17

Examples ...................................................................................................................................4-17

Format 7: Load/Store With Register Offset .............................................................................................4-18

Operation....................................................................................................................................4-19

Instruction Cycle Times ................................................................................................................4-19

Examples ...................................................................................................................................4-19

Format 8: Load/Store Sign-Extended Byte/Halfword................................................................................4-20

Operation....................................................................................................................................4-20

Instruction Cycle Times ................................................................................................................4-21

Examples ...................................................................................................................................4-21

Format 9: Load/Store With Immediate Offset ..........................................................................................4-22

Operation....................................................................................................................................4-23

Instruction Cycle Times ................................................................................................................4-23

Examples ...................................................................................................................................4-23

Format 10: Load/Store Halfword ............................................................................................................4-24

Operation....................................................................................................................................4-24

Examples ...................................................................................................................................4-25

Format 11: SP-Relative Load/Store .......................................................................................................4-26

Operation....................................................................................................................................4-26

Instruction Cycle Times ................................................................................................................4-27

Examples ...................................................................................................................................4-27

Format 12: Load Address .....................................................................................................................4-28

Operation....................................................................................................................................4-28

Instruction Cycle Times ................................................................................................................4-29

Examples ...................................................................................................................................4-29

Format 13: Add Offset to Stack Pointer.................................................................................................4-30

Operation....................................................................................................................................4-30

Instruction Cycle Times ................................................................................................................4-30

Examples ...................................................................................................................................4-30

S3C2440A MICROCONTROLLER vii

Table of Contents (Continued)

Chapter 4 Thumb Instruction Set (Continued)

Format 14: Push/Pop Registers............................................................................................................4-31

Operation....................................................................................................................................4-31

Instruction Cycle Times ................................................................................................................4-32

Examples ...................................................................................................................................4-32

Format 15: Multiple Load/Store .............................................................................................................4-33

Operation....................................................................................................................................4-33

Instruction Cycle Times ................................................................................................................4-33

Examples ...................................................................................................................................4-33

Format 16: Conditional Branch..............................................................................................................4-34

Operation....................................................................................................................................4-34

Instruction Cycle Times ................................................................................................................4-35

Examples ...................................................................................................................................4-35

Format 17: Software Interrupt ................................................................................................................4-36

Operation....................................................................................................................................4-36

Instruction Cycle Times ................................................................................................................4-36

Examples ...................................................................................................................................4-36

Format 18: Unconditional Branch ..........................................................................................................4-37

Operation....................................................................................................................................4-37

Examples ...................................................................................................................................4-37

Format 19: long branch with link ...........................................................................................................4-38

Operation....................................................................................................................................4-38

Instruction Cycle Times ................................................................................................................4-39

Examples ...................................................................................................................................4-39

Instruction Set Examples .....................................................................................................................4-40

Multiplication by A Constant Using Shifts and Adds ........................................................................4-40

General Purpose Signed Divide .....................................................................................................4-41

Division by a Constant .................................................................................................................4-43

viii S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 5 Memory Controller

Overview.............................................................................................................................................5-1

Function Description ............................................................................................................................5-4

Bank0 Bus Width ........................................................................................................................5-4

Memory (SROM/SDRAM) Address Pin Connections .......................................................................5-4

Sdram Bank Address Pin Connection Example ..............................................................................5-5

nWAIT Pin Operation...................................................................................................................5-6

nXBREQ/nXBACK Pin Operation...................................................................................................5-7

Programmable Access Cycle .......................................................................................................5-12

Bus Width & Wait Control Register (Bwscon).................................................................................5-14

Bank Control Register (Bankconn: NGCS0-NGCS5) .......................................................................5-16

Bank Control Register (Bankconn: NGCS6-NGCS7) .......................................................................5-17

Refresh Control Register ..............................................................................................................5-18

Banksize Register.......................................................................................................................5-19

Sdram Mode Register Set Register (MRSR)...................................................................................5-20

Chapter 6 Nand Flash Contorller

Overview.............................................................................................................................................6-1

Features.....................................................................................................................................6-1

Block Diagram ............................................................................................................................6-2

Boot Loader Function...................................................................................................................6-2

Pin Configuration.........................................................................................................................6-3

Nand Flash Memory Configuration Table ........................................................................................6-3

Nand Flash Memory Timing ..........................................................................................................6-4

Software Mode....................................................................................................................................6-5

Steppingstone (4K-Byte SRAM)....................................................................................................6-6

Ecc (Error Correction Code)..................................................................................................................6-7

2048 Byte ECC Parity Code Assignment Table..............................................................................6-7

16 Byte ECC Parity Code Assignment Table..................................................................................6-7

ECC Module Features ..................................................................................................................6-8

ECC Programming Guide.............................................................................................................6-8

Nand Flash Memory Mapping.......................................................................................................6-9

Nand Flash Memory Configuration.................................................................................................6-10

Nand Flash Configuration Register ................................................................................................6-12

Control Register ..........................................................................................................................6-13

Command Register ......................................................................................................................6-15

Address Register.........................................................................................................................6-15

Data Register ..............................................................................................................................6-15

Main Data Area Register..............................................................................................................6-16

Spare Area Ecc Register.............................................................................................................6-17

NFCON Status Register ...............................................................................................................6-18

ECC0/1 Status Register ...............................................................................................................6-19

Main Data Area ECC0 Status Register..........................................................................................6-20

Spare Area ECC Status Register..................................................................................................6-20

Block Address Register ...............................................................................................................6-21

S3C2440A MICROCONTROLLER ix

Table of Contents (Continued)

Chapter 7 Clock & Power Management

Overview.............................................................................................................................................7-1

Functional Description .........................................................................................................................7-2

Clock Architecture .......................................................................................................................7-2

Clock Source Selection................................................................................................................7-2

Phase Locked Loop (PLL)............................................................................................................7-4

Clock Control Logic .....................................................................................................................7-6

Power Management.....................................................................................................................7-10

Clock Generator & Power Management Special Register ........................................................................7-20

Lock Time Count Register (LOCKTIME).........................................................................................7-20

PLL Control Register (MPLLCON & UPLLCON) ..............................................................................7-21

PLL Value Selection Table ...........................................................................................................7-21

Clock Control Register (CLKCON) .................................................................................................7-22

Clock Slow Control (CLKSLOW) Register......................................................................................7-23

Clock Divider Control (CLKDIVN) Register ......................................................................................7-24

Camera Clock Divider (CAMDIVN) Register ....................................................................................7-25

Chapter 8 DMA

Overview.............................................................................................................................................8-1

DMA Request Sources ........................................................................................................................8-2

DMA Operation ...................................................................................................................................8-2

External DMA DREQ/DACK Protocol............................................................................................8-3

Examples ...........................................................................................................................................8-6

DMA Special Registers........................................................................................................................8-7

DMA Initial Source (DISRC) Register .............................................................................................8-7

DMA Initial Source Control (DISRCC) Register ...............................................................................8-7

DMA Initial Destination (DIDST) Register .......................................................................................8-8

DMA Initial Destination Control (DIDSTC) Register ..........................................................................8-8

DMA Control (DCON) Register ......................................................................................................8-9

DMA Status (DSTAT) Register......................................................................................................8-12

DMA Current Source (DCSRC) Register ........................................................................................8-13

Current Destination (DCDST) Register...........................................................................................8-13

DMA Mask Trigger (DMASKTRIG) Register....................................................................................8-14

x S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 9 I/O PORTS

Overview.............................................................................................................................................9-1

Port Control Descriptions .....................................................................................................................9-7

Port Configuration Register (GPACON-GPJCON)............................................................................9-7

Port Data Register (GPADAT-GPJDAT) .........................................................................................9-7

Port Pull-Up Register (GPBUP-GPJUP).........................................................................................9-7

Miscellaneous Control Register.....................................................................................................9-7

External Interrupt Control Register.................................................................................................9-7

I/O Port Control Register......................................................................................................................9-8

Port A Control Registers (GPACON, GPADAT) ..............................................................................9-8

Port B Control Registers (GPBCON, GPBDAT, GPBUP).................................................................9-10

Port C Control Registers (GPCCON, GPCDAT, GPCUP).................................................................9-11

Port D Control Registers (GPDCON, GPDDAT, GPDUP).................................................................9-13

Port E Control Registers (GPECON, GPEDAT, GPEUP).................................................................9-15

Port F Control Registers (GPFCON, GPFDAT)...............................................................................9-17

Port G Control Registers (GPGCON, GPGDAT) .............................................................................9-18

Port H Control Registers (GPHCON, GPHDAT) ..............................................................................9-20

Port J Control Registers (GPJCON, GPJDAT) ................................................................................9-21

Miscellaneous Control Register (MISCCR).....................................................................................9-23

DCLK Control Registers (DCLKCON).............................................................................................9-25

EXTINTn (External Interrupt Control Register n)...............................................................................9-26

EINTFLTn (External Interrupt Filter Register n)................................................................................9-30

EINTMASK (External Interrupt Mask Register) ...............................................................................9-31

EINTPEND (External Interrupt Pending Register)............................................................................9-32

GSTATUSn (General Status Registers).........................................................................................9-33

DSCn (Drive Strength Control).......................................................................................................9-34

DSCn (Drive Strength Control).......................................................................................................9-35

MSLCON (Memory Sleep Control Register)....................................................................................9-36

S3C2440A MICROCONTROLLER xi

Table of Contents (Continued)

Chapter 10 Basic Timer

Overview.............................................................................................................................................10-1

Feature.......................................................................................................................................10-1

PWM Timer Operation .........................................................................................................................10-3

Prescaler & Divider......................................................................................................................10-3

Basic Timer Operation .................................................................................................................10-3

Auto Reload & Double Buffering....................................................................................................10-4

Timer Initialization Using Manual Update Bit and Inverter Bit............................................................10-5

Timer Operation...........................................................................................................................10-6

Pulse Width Modulation (PWM) ....................................................................................................10-7

Output Level Control ....................................................................................................................10-8

Dead Zone Generator ...................................................................................................................10-9

DMA Request Mode ....................................................................................................................10-10

PWM Timer Control Registers ..............................................................................................................10-11

Timer Configuration Register0 (TCFG0) ..........................................................................................10-11

Timer Configuration Register1 (TCFG1) ..........................................................................................10-12

Timer Control (TCON) Register......................................................................................................10-13

Timer 0 Count Buffer Register & Compare Buffer Register (TCNTB0/TCMPB0)...................................10-15

Timer 0 Count Observation Register (TCNTO0)...............................................................................10-15

Timer 1 Count Buffer Register & Compare Buffer Register (TCNTB1/TCMPB1)...................................10-16

Timer 1 Count Observation Register (TCNTO1)...............................................................................10-16

Timer 2 Count Buffer Register & Compare Buffer Register (TCNTB2/TCMPB2)...................................10-17

Timer 2 Count Observation Register (TCNTO2)...............................................................................10-17

Timer 3 Count Buffer Register & Compare Buffer Register (TCNTB3/TCMPB3)...................................10-18

Timer 3 Count Observation Register (TCNTO3)...............................................................................10-18

Timer 4 Count Buffer Register (TCNTB4)........................................................................................10-19

Timer 4 Count Observation Register (TCNTO4)...............................................................................10-19

xii S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 11 UART

Overview.............................................................................................................................................11-1

Features.....................................................................................................................................11-1

Block Diagram ....................................................................................................................................11-2

Uart Operation.............................................................................................................................11-3

Uart Special Registers .........................................................................................................................11-10

Uart Line Control Register ............................................................................................................11-10

Uart Control Register ...................................................................................................................11-11

Uart FIFO Control Register...........................................................................................................11-14

Uart Modem Control Register........................................................................................................11-15

Uart Tx/Rx Status Register...........................................................................................................11-16

Uart Error Status Register............................................................................................................11-17

Uart FIFO Status Register ............................................................................................................11-18

Uart Modem Status Register ........................................................................................................11-19

Uart Transmit Buffer Register (HOLDING Register & FIFO Register).................................................11-20

Uart Receive Buffer Register (HOLDING Register & FIFO Register) ..................................................11-20

Uart Baud Rate Divisor Register ....................................................................................................11-21

Chapter 12 USB HOST Controller

Overview.............................................................................................................................................12-1

Usb Host Controller Special Registers...................................................................................................12-2

OHCI Registers for Usb Host Controller .........................................................................................12-2

S3C2440A MICROCONTROLLER xiii

Table of Contents (Continued)

Chapter 13 USB Device Controller

Overview.............................................................................................................................................13-1

Feature.......................................................................................................................................13-1

Usb Device Controller Special Registers ................................................................................................13-3

Function Address Register (FUNC_ADDR_REG) ............................................................................13-5

Power Management Register (PWR_REG) ....................................................................................13-6

Interrupt Register (EP_INT_REG/USB_INT_REG)...........................................................................13-7

Interrupt Enable Register (EP_INT_EN_REG/USB_INT_EN_REG)....................................................13-9

Frame Number Register (FPAME_NUM1_REG/FRAME_NUM2_REG).............................................13-10

Index Register (INDEX_REG) ........................................................................................................13-11

MAX Packet Register (MAXP_REG) ..............................................................................................13-11

END Point0 Control Status Register (EP0_CSR)............................................................................13-12

END Point In Control Status Register (IN_CSR1_REG/IN_CSR2_REG)............................................13-13

END Point Out Control Status Register (OUT_CSR1_REG/OUT_CSR2_REG) ..................................13-15

END Point Out Write Count Register (OUT_FIFO_CNT1_REG/OUT_FIFO_CNT2_REG) .....................13-17

END Point FIFO Register (EPN_FIFO_REG)..................................................................................13-17

DMA Interface Control Register (EPN_DMA_CON) .........................................................................13-18

DMA Unit Counter Register (EPN_DMA_UNIT)...............................................................................13-19

DMA FIFO Counter Register (EPN_DMA_FIFO).............................................................................13-20

DMA Total Transfer Counter Register (EPn_DMA_TTC_L, M, H) ......................................................13-21

Chapter 14 Interrupt Controller

Overview.............................................................................................................................................14-1

Interrupt Controller Operation........................................................................................................14-2

Interrupt Sources.........................................................................................................................14-3

Interrupt Sub Sources ..................................................................................................................14-4

Interrupt Priority Generating Block.................................................................................................14-5

Interrupt Priority...........................................................................................................................14-6

Interrupt Controller Special Registers .....................................................................................................14-7

Source Pending (SRCPND) Register.............................................................................................14-7

Interrupt Mode (INTMOD) Register.................................................................................................14-9

Interrupt Mask (INTMSK) Register .................................................................................................14-11

Priority Register (PRIORITY).........................................................................................................14-13

Interrupt Pending (INTPND) Register..............................................................................................14-14

Interrupt Offset (INTOFFSET) Register ...........................................................................................14-16

Sub Source Pending (SUBSRCPND) Register................................................................................14-17

Interrupt Sub Mask (INTSUBMSK) Register ...................................................................................14-18

xiv S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 15 LCD Controller

Overview.............................................................................................................................................15-1

Features.....................................................................................................................................15-1

Common Features.......................................................................................................................15-2

External Interface Signal ..............................................................................................................15-2

Block Diagram ............................................................................................................................15-3

STN LCD Controller Operation ..............................................................................................................15-4

Timing Generator (TIMEGEN) .......................................................................................................15-4

Video Operation ..........................................................................................................................15-5

Dithering and Frame Rate Control .................................................................................................15-7

Memory Data Format (STN, BSWP = 0) ........................................................................................15-9

TFT LCD Controller Operation...............................................................................................................15-16

Video Operation ..........................................................................................................................15-16

Memory Data Format (TFT) ..........................................................................................................15-17

256 Palette Usage (TFT) ..............................................................................................................15-21

Samsung TFT LCD Panel

(3.5” PORTRAIT/256K COLOR/REFLECTIVE A-SI/TRANSFLECTIVE A-SI TFT LCD).........................15-24

Virtual Display (TFT/STN) .............................................................................................................15-25

LCD Power Enable (STN/TFT) .......................................................................................................15-26

LCD Controller Special Registers ..................................................................................................15-27

Frame Buffer Start Address 1 Register ..........................................................................................15-33

Chapter 16 ADC & Touch Screen Interface

Overview.............................................................................................................................................16-1

Features.....................................................................................................................................16-1

ADC & Touch Screen Interface Operation ..............................................................................................16-2

Block Diagram ............................................................................................................................16-2

Function Descriptions ..................................................................................................................16-3

ADC AND Touch Screen Interface Special Registers ..............................................................................16-5

ADC Control Register (ADCCON) ..................................................................................................16-5

ADC Touch Screen Control Register (ADCTSC)..............................................................................16-6

ADC Start Delay Register (ADCDLY).............................................................................................16-7

ADC Conversion Data Register (ADCDAT0)....................................................................................16-8

ADC Conversion Data Register (ADCDAT1)....................................................................................16-9

ADC Touch Screen Up-Down INT Check Register (ADCUPDN)........................................................16-9

S3C2440A MICROCONTROLLER xv

Table of Contents (Continued)

Chapter 17 Real Time Clock

Overview.............................................................................................................................................17-1

Features.....................................................................................................................................17-1

Real Time Clock Operation ...........................................................................................................17-2

Leap Year Generator....................................................................................................................17-2

Read/Write Registers ...................................................................................................................17-2

Backup Battery Operation............................................................................................................17-2

Alarm Function............................................................................................................................17-3

TICK Time Interrupt......................................................................................................................17-3

32.768kHz X-Tal Connection Example..........................................................................................17-3

Real Time Clock Special Registers .......................................................................................................17-4

Real Time Clock Control (RTCCON) Register .................................................................................17-4

TICK Time Count (TICNT) Register ................................................................................................17-4

RTC Alarm Control (RTCALM) Register..........................................................................................17-5

ALARM Second Data (ALMSEC) Register.....................................................................................17-6

ALARM Min Data (ALMMIN) Register ............................................................................................17-6

ALARM Hour Data (ALMHOUR) Register .......................................................................................17-6

ALARM Date Data (ALMDATE) Register........................................................................................17-7

ALARM Mon Data (ALMMON) Register.........................................................................................17-7

ALARM Year Data (ALMYEAR) Register.......................................................................................17-7

BCD Second (BCDSEC) Register .................................................................................................17-8

BCD Minute (BCDMIN) Register....................................................................................................17-8

BCD Hour (BCDHOUR) Register...................................................................................................17-8

BCD Date (BCDDATE) Register ....................................................................................................17-9

BCD Day (BCDDAY) Register.......................................................................................................17-9

BCD Month (BCDMON) Register...................................................................................................17-9

BCD Year (BCDYEAR) Register ...................................................................................................17-10

Chapter 18 Watchdog Timer

Overview.............................................................................................................................................18-1

Features.....................................................................................................................................18-1

Watchdog Timer Operation ...........................................................................................................18-2

Wtdat & Wtcnt............................................................................................................................18-2

Consideration of Debugging Environment .......................................................................................18-2

Watchdog Timer Special Registers .......................................................................................................18-3

Watchdog Timer Control (WTCON) Register...................................................................................18-3

Watchdog Timer Data (WTDAT) Register .......................................................................................18-4

Watchdog Timer Count (WTCNT) Register.....................................................................................18-4

xvi S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 19 MMC/SD/SDIO Controller

Features.............................................................................................................................................19-1

Block Diagram ....................................................................................................................................19-1

SD Operation......................................................................................................................................19-2

SDIO Operation ...................................................................................................................................19-3

SDI Special Registers..........................................................................................................................19-4

SDI Control Register (SDICON) .....................................................................................................19-4

SDI Baud Rate Prescaler Register (SDIPRE).................................................................................19-4

SDI Command Argument Register (SDICmdArg).............................................................................19-5

SDI Command Control Register (SDICmdCon)................................................................................19-5

SDI Command Status Register (SDICmdSta).................................................................................19-6

SDI Response Register 0 (SDIRSP0) ............................................................................................19-6

SDI Response Register 1 (SDIRSP1) ............................................................................................19-6

SDI Response Register 2 (SDIRSP2) ............................................................................................19-7

SDI Response Register 3 (SDIRSP3) ............................................................................................19-7

SDI Data / Busy Timer Register (SDIDTimer)..................................................................................19-7

SDI Block Size Register (SDIBSize)..............................................................................................19-7

SDI Data Control Register (SDIDatCon) .........................................................................................19-8

SDI Data Remain Counter Register (ADIDatCnt) .............................................................................19-9

SDI Data Status Register (ADIDatSta) ...........................................................................................19-9

SDI FIFO Status Register (SDIFSTA) ............................................................................................19-10

SDI Interrupt Mask Register (SDIIntMsk)........................................................................................19-11

SDI Data Register (SDIDAT) .........................................................................................................19-12

Chapter 20 IIC-Bus Interface

Overview.............................................................................................................................................20-1

IIC-Bus Interface..........................................................................................................................20-3

Start and Stop Conditions ............................................................................................................20-3

Data Transfer Format ...................................................................................................................20-4

ACK Signal Transmission.............................................................................................................20-5

Read-Write Operation ..................................................................................................................20-6

Bus Arbitration Procedures ...........................................................................................................20-6

Abort Conditions ..........................................................................................................................20-6

Configuring IIC-Bus ......................................................................................................................20-6

Flowcharts of Operations in Each Mode.........................................................................................20-7

IIC-Bus Interface Special Registers .......................................................................................................20-11

Multi-Master IIC-Bus Control (IICCON) Register..............................................................................20-11

Multi-Master IIC-Bus Control/Status (IICSTAT) Register...................................................................20-12

Multi-Master IIC-Bus Address (IICADD) Register.............................................................................20-13

Multi-Master IIC-Bus Transmit/Receive Data Shift (IICDS) Register ...................................................20-13

Multi-Master IIC-Bus Line Contro l(IICLC) Register..........................................................................20-14

S3C2440A MICROCONTROLLER xvii

Table of Contents (Continued)

Chapter 21 IIS-Bus Interface

Overview.............................................................................................................................................21-1

Block Diagram ....................................................................................................................................21-2

Functional Descriptions ........................................................................................................................21-2

Transmit or Receive Only Mode ....................................................................................................21-2

Dma Transfer ..............................................................................................................................21-3

Transmit and Receive Mode..........................................................................................................21-3

Audio Serial Interface Format ................................................................................................................21-3

IIS-Bus Format............................................................................................................................21-3

MSB (Left) Justified .....................................................................................................................21-3

Sampling Frequency and Master Clock .........................................................................................21-4

IIS-Bus Interface Special Registers .......................................................................................................21-5

IIS Control (IISCON) Register ........................................................................................................21-5

IIS Mode Register (IISMOD) Register.............................................................................................21-6

IIS Prescaler (IISPSR) Register.....................................................................................................21-7

IIS FIFO Control (IISFCON) Register..............................................................................................21-8

IIS FIFO (IISFIFO) Register...........................................................................................................21-8

Chapter 22 SPI

Overview.............................................................................................................................................22-1

Features.....................................................................................................................................22-1

Block Diagram ............................................................................................................................22-2

SPI Operation .....................................................................................................................................22-3

Programming Procedure...............................................................................................................22-3

SPI Transfer Format .....................................................................................................................22-4

Transmitting Procedure for DMA ...................................................................................................22-5

Receiving Procedure for DMA .......................................................................................................22-5

SPI Special Registers..........................................................................................................................22-6

SPI Control Register....................................................................................................................22-6

SPI Status Register .....................................................................................................................22-7

SPI Pin Control Register ..............................................................................................................22-8

SPI Baud Rate Prescaler Register ................................................................................................22-9

SPI Tx Data Register...................................................................................................................22-9

SPI Rx Data Register...................................................................................................................22-9

xviii S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 23 Camera Interface

Overview.............................................................................................................................................23-1

Features.....................................................................................................................................23-1

Block Diagram ............................................................................................................................23-2

Timing Diagram...........................................................................................................................23-3

Camera Interface Operation..................................................................................................................23-5

Two DMA Paths ..........................................................................................................................23-5

Clock Domain .............................................................................................................................23-5

Frame Memory Hirerarchy............................................................................................................23-6

Memory Storing Method ...............................................................................................................23-8

Timing Diagram for Register Setting ..............................................................................................23-9

Timing Diagram for Last IRQ .........................................................................................................23-10

Camera Interface Special Registers .......................................................................................................23-11

Source Format Register...............................................................................................................23-11

Window Option Register...............................................................................................................23-12

Global Control Register................................................................................................................23-13

Y1 Start Address Register............................................................................................................23-13

Y2 Start Address Register............................................................................................................23-13

Y3 Start Address Register............................................................................................................23-14

Y4 Start Address Register............................................................................................................23-14

CB1 Start Address Register .........................................................................................................23-14

CB2 Start Address Register .........................................................................................................23-14

CB3 Start Address Register .........................................................................................................23-15

CB4 Start Address Register .........................................................................................................23-15

CR1 Start Address Register .........................................................................................................23-15

CR2 Start Address Register .........................................................................................................23-15

CR3 Start Address Register .........................................................................................................23-16

CR4 Start Address Register .........................................................................................................23-16

Codec Target Format Register......................................................................................................23-17

Codec Dma Control Register ........................................................................................................23-19

Register Setting Guide for Codec Scaler and Preview Scaler ...........................................................23-20

Codec Pre-Scaler Control Register 1 .............................................................................................23-21

Codec Pre-Scaler Control Register 2 .............................................................................................23-21

Codec Main-Scaler Control Register ..............................................................................................23-22

Codec Dma Target Area Register ..................................................................................................23-22

Codec Status Register .................................................................................................................23-23

RGB1 Start Address Register .......................................................................................................23-23

RGB2 Start Address Register .......................................................................................................23-23

RGB3 Start Address Register .......................................................................................................23-24

RGB4 Start Address Register .......................................................................................................23-24

Preview Target Format Register ....................................................................................................23-24

Preview DMA Control Register......................................................................................................23-25

S3C2440A MICROCONTROLLER xix

Table of Contents (Continued)

Chapter 23 Camera Interface (Continued)

Preview Pre-Scaler Control Register 1...........................................................................................23-25

Preview Pre-Scaler Control Register 2...........................................................................................23-26

Preview Main-Scaler Control Register............................................................................................23-26

Preview DMA Target Area Register................................................................................................23-26

Preview Status Register...............................................................................................................23-27

Image Capture Enable Register.....................................................................................................23-27

Chapter 24 AC97 Controller

Overview.............................................................................................................................................24-1

Features.....................................................................................................................................24-1

AC97 Controller Operation ....................................................................................................................24-2

Block Diagram ............................................................................................................................24-2

Internal Data Path........................................................................................................................24-3

Operation Flow Chart ...........................................................................................................................24-4

AC-Link Digital Interface Protocol ..........................................................................................................24-5

AC-Link Output Frame (SDATA_OUT) ...........................................................................................24-6

AC-Link Input Frame (SDATA_IN) .................................................................................................24-6

AC97 Powerdown................................................................................................................................24-7

AC97 Controller Special Registers ........................................................................................................24-9

AC97 Global Control Register (AC_GLBCTRL) ...............................................................................24-9

AC97 Global Status Register (AC_GLBSTAT) ................................................................................24-10

AC97 Codec Command Register (AC_CODEC_CMD) .....................................................................24-10

AC97 Codec Status Register (AC_CODEC_STAT) .........................................................................24-11

AC97 PCM Out/In Channel FIFO Address Register (AC_PCMADDR)...............................................24-11

AC97 MIC in Channel FIFO Address Register (AC_MICADDR) ........................................................24-12

AC97 PCM Out/In Channel FIFO Data Register (AC_PCMDATA).....................................................24-12

AC97 MIC in Channel FIFO Data Register (AC_MICDATA) ..............................................................24-12

xx S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 25 Bus Priorities

Overview.............................................................................................................................................25-1

Bus Priority Map .........................................................................................................................25-1

Chapter 26 Mechanical Data

Package Dimensions...........................................................................................................................26-1

Chapter 27 Electrical Data

Absolute Maximum Ratings ..................................................................................................................27-1

Recommended Operating Conditions .....................................................................................................27-2

D.C. Electrical Characteristics ..............................................................................................................27-3

A.C. Electrical Characteristics ..............................................................................................................27-8

S3C2440A MICROCONTROLLER xxi

List of Figures

Figure Title Page Number Number

1-1 S3C2440A Block Diagram ................................................................................................1-5

1-2 S3C2440A Pin Assignments (289-FBGA) ..........................................................................1-6

2-1 Big-Endian Addresses of Bytes within Words .....................................................................2-2

2-2 Little-Endian Addresses of Bytes within Words ..................................................................2-2

2-3 Register Organization in ARM State..................................................................................2-4

2-4 Register Organization in THUMB state..............................................................................2-5

2-5 Mapping of THUMB State Registers onto ARM State Registers ...........................................2-6

2-6 Program Status Register Format .......................................................................................2-7

3-1 ARM Instruction Set Format .............................................................................................3-1

3-2 Branch and Exchange Instructions....................................................................................3-5

3-3 Branch Instructions ..........................................................................................................3-7

3-4 Data Processing Instructions............................................................................................3-9

3-5 ARM Shift Operations ......................................................................................................3-12

3-6 Logical Shift Left ..............................................................................................................3-12

3-7 Logical Shift Right ...........................................................................................................3-13

3-8 Arithmetic Shift Right.......................................................................................................3-13

3-9 Rotate Right ....................................................................................................................3-14

3-10 Rotate Right Extended .....................................................................................................3-14

3-11 PSR Transfer ..................................................................................................................3-19

3-12 Multiply Instructions .........................................................................................................3-22

3-13 Multiply Long Instructions .................................................................................................3-25

3-14 Single Data Transfer Instructions .......................................................................................3-28

3-15 Little-Endian Offset Addressing .........................................................................................3-30

3-16 Halfword and Signed Data Transfer with Register Offset .......................................................3-34

3-17 Halfword and Signed Data Transfer with Immediate Offset and Auto-Indexing.........................3-35

3-18 Block Data Transfer Instructions .......................................................................................3-40

3-19 Post-Increment Addressing ..............................................................................................3-41

3-20 Pre-Increment Addressing................................................................................................3-42

3-21 Post-Decrement Addressing .............................................................................................3-42

3-22 Pre-Decrement Addressing...............................................................................................3-43

3-23 Swap Instruction..............................................................................................................3-47

3-24 Software Interrupt Instruction ............................................................................................3-49

3-25 Coprocessor Data Operation Instruction.............................................................................3-51

3-26 Coprocessor Data Transfer Instructions .............................................................................3-53

3-27 Coprocessor Register Transfer Instructions ........................................................................3-56

3-28 Undefined Instruction .......................................................................................................3-58

S3C2440A MICROCONTROLLER xxiii

List of Figures (Continued)

Figure Title Page Number Number

4-1 THUMB Instruction Set Formats .......................................................................................4-2

4-2 Format 1.........................................................................................................................4-5

4-3 Format 2.........................................................................................................................4-7

4-4 Format 3.........................................................................................................................4-9

4-5 Format 4.........................................................................................................................4-11

4-6 Format 5.........................................................................................................................4-13

4-7 Format 6.........................................................................................................................4-16

4-8 Format 7.........................................................................................................................4-18

4-9 Format 8.........................................................................................................................4-20

4-10 Format 9.........................................................................................................................4-22

4-11 Format 10 .......................................................................................................................4-24

4-12 Format 11 .......................................................................................................................4-26

4-13 Format 12 .......................................................................................................................4-28

4-14 Format 13 .......................................................................................................................4-30

4-15 Format 14 .......................................................................................................................4-31

4-16 Format 15 .......................................................................................................................4-33

4-17 Format 16 .......................................................................................................................4-34

4-18 Format 17 .......................................................................................................................4-36

4-19 Format 18 .......................................................................................................................4-37

4-20 Format 19 .......................................................................................................................4-38

5-1 S3C2440A Memory Map after Reset .................................................................................5-2

5-2 S3C2440A External nWAIT Timing Diagram (Tacc=4).........................................................5-6

5-3 S3C2440A nXBREQ/nXBACK Timing Diagram ...................................................................5-7

5-4 Memory Interface with 8-bit ROM......................................................................................5-8

5-5 Memory Interface with 8-bit ROM x 2.................................................................................5-8

5-6 Memory Interfac e with 8-bit ROM x 4.................................................................................5-9

5-7 Memory Interface with 16-bit ROM ....................................................................................5-9

5-8 Memory Interface with 16-bit SRAM ..................................................................................5-10

5-9 Memory Interface with 16-bit SRAM x 2.............................................................................5-10

5-10 Memory Interface with 16-bit SDRAM (4Mx16, 4banks).......................................................5-11

5-11 Memory Interface with 16-bit SDRAM (4Mx16x4Bank * 2ea) ................................................5-11

5-12 S3C2440A nGCS Timing Diagram .....................................................................................5-12

5-13 S3C2440A SDRAM Timing Diagram ..................................................................................5-13

xxiv S3C2440A MICROCONTROLLER

List of Figures (Continued)

Figure Title Page Number Number

6-1 NAND Flash Controller Block Diagram...............................................................................6-2

6-2 NAND Flash Controller Boot Loader Block Diagram............................................................6-2

6-3 CLE & ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0) ...................................................6-4

6-4 nWE & nRE Timing (TWRPH0=0, TWRPH1=0) ..................................................................6-4

6-5 NAND Flash Memory Mapping..........................................................................................6-9

6-6 A 8-bit NAND Flash Memory Interface ...............................................................................6-10

6-7 Two 8-bit NAND Flash Memory Interface............................................................................6-10

6-8 A 16-bit NAND Flash Memory Interface.............................................................................6-11

7-1 Clock Generator Block Diagram ........................................................................................7-3

7-2 PLL (Phase-Locked Loop) Block Diagram ..........................................................................7-5

7-3 Main Oscillator Circuit Examples ......................................................................................7-5

7-4 Power-On Reset Sequence (when the external clock source is a crystal oscillat or) ...............7-6

7-5 Changing Slow Clock by Setting PMS Value......................................................................7-7

7-6 Example of Internal Clock Change.....................................................................................7-8

7-7 The Clock Distribution Block Diagram................................................................................7-10

7-8 Power Management State Diagram...................................................................................7-11

7-9 Issuing Exit_from_Slow_mode Command in PLL on State...................................................7-13

7-10 Issuing Exit_from_Slow_mode Command After Lock Time...................................................7-13

7-11 Issuing Exit_from_Slow_mode Command and the Instant PLL_on

Command Simultaneously................................................................................................7-14

7-12 SLEEP Mode ..................................................................................................................7-17

8-1 Basic DMA Timing Diagram..............................................................................................8-3

8-2 Demand/Handshake Mode Comparison.............................................................................8-4

8-3 Burst 4 Transfer Size .......................................................................................................8-5

8-4 Single service in Demand Mode with Unit Transfer Size.......................................................8-6

8-5 Single service in Handshake Mode with Unit Transfer Size..................................................8-6

8-6 Whole service in Handshake Mode with Unit Transfer Size ..................................................8-6

10-1 16-bit PWM Timer Block Diagram.....................................................................................10-2

10-2 Timer Operations.............................................................................................................10-3

10-3 Example of Double Buffering Function ...............................................................................10-4

10-4 Example of a Timer Operation...........................................................................................10-6

10-5 Example of PWM ............................................................................................................10-7

10-6 Inverter On/Off.................................................................................................................10-8

10-7 The Wave Form When a Dead Zone Feature is Enabled ......................................................10-9

10-8 Timer4 DMA Mode Operation............................................................................................10-10

S3C2440A MICROCONTROLLER xxv

List of Figures (Continued)

Figure Title Page Number Number

11-1 UART Block Diagram (with FIFO) ......................................................................................11-2

11-2 UART AFC interface........................................................................................................11-4

11-3 Example showing UART Receiving 5 Characters with 2 Errors .............................................11-6

11-4 IrDA Function Block Diagram............................................................................................11-8

11-5 Serial I/O Frame Timing Diagram (Normal UART) ................................................................11-9

11-6 Infrared Transmit Mode Frame Timing Diagram ...................................................................11-9

11-7 Infrared Receive Mode Frame Timing Diagram....................................................................11-9

11-8 nCTS and Delta CTS Timing Diagram................................................................................11-19

12-1 USB Host Controller Block Diagram..................................................................................12-1

13-1 USB Device Controller Block Diagram ...............................................................................13-2

14-1 Interrupt Process Diagram ................................................................................................14-1

14-2 Priority Generating Block .................................................................................................14-5

15-1 LCD Controller Block Diagram ..........................................................................................15-3

15-2 Monochrome Display Types (STN)....................................................................................15-12

15-3 Color Display Types (STN) ...............................................................................................15-13

15-4 8-bit Single Scan Display Type STN LCD Timing................................................................15-15

15-5 16BPP Display Types (TFT) .............................................................................................15-22

15-6 TFT LCD Timing Example.................................................................................................15-23

15-7 Example of Scrolling in Virtual Display (Single Scan) ..........................................................15-25

15-8 Example of PWREN Function (PWREN=1, INVPWREN=0) ................................................15-26

16-1 ADC and Touch Screen Interface Functional Block Diagram................................................16-2

16-2 ADC and Touch Screen Operation signal...........................................................................16-4

17-1 Real Time Clock Block Diagram........................................................................................17-2

17-2 Main Oscillator Circuit Example ........................................................................................17-3

18-1 Watchdog Timer Block Diagram........................................................................................18-2

19-1 SD Interface Block Diagram..............................................................................................19-1

20-1 IIC-Bus Block Diagram .....................................................................................................20-2

20-2 Start and Stop Condition..................................................................................................20-3

20-3 IIC-Bus Interface Data Format...........................................................................................20-4

20-4 Data Transfer on the IIC-Bus.............................................................................................20-5

20-5 Acknowledge on the IIC-Bus.............................................................................................20-5

20-6 Operations for Master/Transmitter Mode............................................................................20-7

20-7 Operations for Master/Receiver Mode................................................................................20-8

20-8 Operations for Slave/Transmitter Mode ..............................................................................20-9

20-9 Operations for Slave/Receiver Mode ..................................................................................20-10

xxvi S3C2440A MICROCONTROLLER

List of Figures (Continued)

Figure Title Page Number Number

21-1 IIS-Bus Block Diagram .....................................................................................................21-2

21-2 IIS-Bus and MSB (Left)-justified Data Interface Formats ......................................................21-4

22-1 SPI Block Diagram..........................................................................................................22-2

22-2 SPI Transfer Format .........................................................................................................22-4

23-1 CAMIF Overview..............................................................................................................23-2

23-2 ITU-R BT 601 Input Timing Diagram ...................................................................................23-3

23-3 ITU-R BT 656 Input Timing Diagram ...................................................................................23-3

23-4 Two DMA Paths ..............................................................................................................23-5

23-5 CAMIF Clock Generation..................................................................................................23-6

23-6 Ping-Pong Memory Hierarchy ...........................................................................................23-7

23-7 Memory Storing Style......................................................................................................23-8

23-8 Timing Diagram for Register Setting ..................................................................................23-9

23-9 Timing diagram for last IRQ ..............................................................................................23-10

23-10 Window Offset Scheme....................................................................................................23-12

23-11 Image Mirror and Rotation ................................................................................................23-18

23-12 Scaling Scheme ..............................................................................................................23-20

24-1 AC97 Block Diagram .......................................................................................................24-2

24-2 Internal Data Path............................................................................................................24-3

24-3 AC97 Operation Flow Chart ..............................................................................................24-4

24-4 Bi-directional AC-link Frame with Slot Assignments............................................................24-5

24-5 AC-link Output Frame......................................................................................................24-6

24-6 AC-link Input Frame .........................................................................................................24-6

24-7 AC97 Powerdown Timing Diagram.....................................................................................24-7

24-8 AC97 Power down/Power up Flow .....................................................................................24-8

26-1 289-FBGA-1414 Package Dimension 1 (Top View) .............................................................26-1

26-2 289-FBGA-1414 Package Dimension 2 (Bottom View)........................................................26-2

27-1 Power Consumption Example Comparison when Applied DVS Scheme................................27-7

27-2 XTIpll Clock Timing Diagram .............................................................................................27-8

27-3 EXTCLK Clock Input Timing Diagram .................................................................................27-8

27-4 EXTCLK/HCLK in case when EXTCLK is used Without the PLL...........................................27-8

27-5 HCLK/CLKOUT/SCLK in case when EXTCLK is used .........................................................27-9

27-6 Manual Reset Input Timing Diagram..................................................................................27-9

27-7 Power-On Oscillation Setting Timing Diagram ....................................................................27-10

27-8 Sleep Mode Return Oscillation Setting Timing Diagram .......................................................27-11

27-9 ROM/SRAM Burst READ Timing Diagram (I)

(Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=0, DW=16bit)...............................27-12

27-10 ROM/SRAM Burst READ Timing Diagram (II)

(Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=1, DW=16bit)...............................27-13

S3C2440A MICROCONTROLLER xxvii

List of Figures (Continued)

Figure Title Page Number Number

27-11 External Bus Request in ROM/SRAM Cycle

(Tacs=0, Tcos=0, Tacc=8, Toch=0, Tcah=0, PMC=0, ST=0)...............................................27-14

27-12 ROM/SRAM READ Timing Diagram (I)

(Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=0)...............................................27-15

27-13 ROM/SRAM READ Timing Diagram (II)

(Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2cycle, PMC=0, ST=1) .......................................27-16

27-14 ROM/SRAM WRITE Timing Diagram (I)

(Tacs=2,Tcos=2,Tacc=4,Toch=2, Tcah=2, PMC=0, ST=0 ...................................................27-17

27-15 ROM/SRAM WRITE Timing Diagram (II)

(Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=1)...............................................27-18

27-16 External nWAIT READ Timing Diagram

(Tacs=0, Tcos=0, Tacc=6, Toch=0, Tcah=0, PMC=0, ST=0)...............................................27-19

27-17 External nWAIT WRITE Timing Diagram

(Tacs=0, Tcos=0, Tacc=4, Toch=0, Tcah=0, PMC=0, ST=0)...............................................27-19

27-18 Masked-ROM Single READ Timing Diagram (Tacs=2, Tcos=2, Tacc=8, PMC=01/10/11).......27-20

27-19 Masked-ROM Consecutive READ Timing Diagram

(Tacs=0, Tcos=0, Tacc=3, Tpac=2, PMC=01/10/11) ...........................................................27-20

27-20 SDRAM Single Burst READ Timing Diagram (Trp=2, Trcd=2, Tcl=2, DW=16bit)....................27-21

27-21 External Bus Request in SDRAM Timing Diagram (Trp=2, Trcd=2, Tcl=2) .............................27-22

27-22 SDRAM MRS Timing Diagram..........................................................................................27-23

27-23 SDRAM Single READ Timing Diagram (I) (Trp=2, Trcd=2, Tcl=2) .........................................27-24

27-24 SDRAM Single READ Timing Diagram (II) (Trp=2, Trcd=2, Tcl=3).........................................27-25

27-25 SDRAM Auto Refresh Timing Diagram (Trp=2, Trc=4).........................................................27-26

27-26 SDRAM Page Hit-Miss READ Timing Diagram (Trp=2, Trcd=2, Tcl=2)..................................27-27

27-27 SDRAM Self Refresh Timing Diagram (Trp=2, Trc=4) ..........................................................27-28

27-28 SDRAM Single Write Timing Diagram (Trp=2, Trcd=2) ........................................................27-29

27-29 SDRAM Page Hit-Miss Write Timing Diagram (Trp=2, Trcd=2, Tcl=2) ...................................27-30

27-30 External DMA Timing Diagram (Handshake, Single transfer) ................................................27-31

27-31 TFT LCD Controller Timing Diagram...................................................................................27-31

27-32 IIS Interface Timing Diagram.............................................................................................27-32

27-33 IIC Interface Timing Diagram.............................................................................................27-32

27-34 SD/MMC Interface Timing Diagram....................................................................................27-33

27-35 SPI Interface Timing Diagram (CPHA=1, CPOL=1) .............................................................27-33

27-36 NAND Flash Address/Command Timing Diagram ...............................................................27-34

27-37 NAND Flash Timing Diagram............................................................................................27-34

xxviii S3C2440A MICROCONTROLLER

List of Tables

Table Title Page Number Number

1-1 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 1 of 3).....................................1-7

1-2 S3C2440A 289-Pin FBGA Pin Assignments (Sheet 1 of 9) ..................................................1-10

1-3 S3C2440A Signal Descriptions (Sheet 1 of 6).....................................................................1-20

1-4 S3C2440A Special Registers (Sheet 1 of 14) .....................................................................1-26

2-1 PSR Mode Bit Values......................................................................................................2-9

2-2 Exception Entry/Exit........................................................................................................2-11

2-3 Exception Vectors...........................................................................................................2-13

3-1 The ARM Instruction Set ..................................................................................................3-2

3-2 Condition Code Summary .................................................................................................3-4

3-3 ARM Data Processing Instructions ....................................................................................3-11

3-4 Incremental Cycle Times..................................................................................................3-16

3-5 Assembler Syntax Descriptions........................................................................................3-27

3-6 Addressing Mode Names .................................................................................................3-45

4-1 THUMB Instruction Set Opcodes ......................................................................................4-3

4-2 Summary of Format 1 Instructions ....................................................................................4-5

4-3 Summary of Format 2 Instructions ....................................................................................4-7

4-4 Summary of Format 3 Instructions ....................................................................................4-9

4-5 Summary of Format 4 Instructions ....................................................................................4-11

4-6 Summary of Format 5 Instructions ....................................................................................4-13

4-7 Summary of PC-Relative Load Instruction ..........................................................................4-16

4-8 Summary of Format 7 Instructions ....................................................................................4-19

4-9 Summary of Format 8 Instructions ....................................................................................4-20

4-10 Summary of Format 9 Instructions ....................................................................................4-23

4-11 Halfword Data Transfer Instructions ...................................................................................4-24

4-12 SP-Relative Load/Store Instructions ..................................................................................4-26

4-13 Load Address..................................................................................................................4-28

4-14 The ADD SP Instruction...................................................................................................4-30

4-15 PUSH and POP Instructions .............................................................................................4-31

4-16 The Multiple Load/Store Instructions ..................................................................................4-33

4-17 The Conditional Branch Instructions ..................................................................................4-34

4-18 The SWI Instruction.........................................................................................................4-36

4-19 Summary of Branch Instruction .........................................................................................4-37

4-20 The BL Instruction ...........................................................................................................4-39

5-1 Bank 6/7 Addresses ........................................................................................................5-3

5-2 SDRAM Bank Address Configuration Example ...................................................................5-5

7-1 Clock Source Selection at Boot-Up...................................................................................7-2

7-2 Clock and Power State in Each Power Mode .....................................................................7-11

7-3 CLKSLOW and CLKDIVN Register Settings for SLOW Clock ex ample.................................7-12

7-4 Pin configuration table in Sleep mode ................................................................................7-16

S3C2440A MICROCONTROLLER xxix

List of Tables (Continued)

Table Title Page Number Number

8-1 DMA Request Sources for Each Channel...........................................................................8-2

9-1 S3C2440A Port Configuration (Sheet 1 of 5) .......................................................................9-2

11-1 Interrupts in Connection with FIFO ...................................................................................11-5

15-1 Relation Between VCLK and CLKVAL (STN, HCLK = 60MHz) .............................................15-5

15-2 Dither Duty Cycle Examples .............................................................................................15-7

15-3 Relation between VCLK and CLKVAL (TFT, HCLK = 60MHz)..............................................15-16

15-4 5:6:5 Format ...................................................................................................................15-21

15-5 5:5:5:1 Format ................................................................................................................15-21

15-6 MV Value for Each Display Mode......................................................................................15-41

21-1 CODEC clock (CODECLK = 256 or 384fs) .........................................................................21-4

21-2 Usable Serial Bit Clock Frequency (IISCLK = 16 or 32 or 48fs)............................................21-4

23-1 Camera Interface Signal Description ..................................................................................23-1

23-2 Video Timing Reference Codes of ITU-656 Format ..............................................................23-4

27-1 Absolute Maximum Rating ...............................................................................................27-1

27-2 Recommended Operating Conditions .................................................................................27-2

27-3 Normal I/O PAD DC Electrical Characteristics....................................................................27-3

27-4 USB DC Electrical Characteristics....................................................................................27-6

27-5 S3C2440 Power Supply Voltage and Current ......................................................................27-6

27-6 Typical Current Decrease by CLKCON Register .................................................................27-7

27-7 Clock Timing Constants...................................................................................................27-35

27-8 ROM/SRAM Bus Timing Constants...................................................................................27-36

27-9 Memory Interface Timing Constants ..................................................................................27-36

27-10 External Bus Request Timing Constants............................................................................27-37

27-11 DMA Controller Module Signal Timing Constants ................................................................27-37

27-12 TFT LCD Controller Module Signal Timing Constants ..........................................................27-38

27-13 IIS Controller Module Signal Timing Constants ...................................................................27-38

27-14 IIC BUS Controller Module Signal Timing ...........................................................................27-39

27-15 SD/MMC Interface Transmit/Receive Timing Constants.......................................................27-39

27-16 SPI Interface Transmit/Receive Timing Constants...............................................................27-40

27-17 USB Electrical Specifications ...........................................................................................27-40

27-18 USB Full Speed Output Buffer Electrical Characteristics .....................................................27-41

27-19 USB Low Speed Output Buffer Electrical Characteristics .....................................................27-41

27-20 NAND Flash Interface Timing Constants............................................................................27-42

xxx S3C2440A MICROCONTROLLER

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

INTRODUCTION

This user’s manual describes SAMSUNG's S3C2440A 16/32-bit RISC microprocessor. SAMSUNG’s S3C2440A is designed to provide hand-held devices and general applications with low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2440A includes the following components.

The S3C2440A is developed with ARM920T core, 0.13um CMOS standard cells and a memory complier. Its lowpower, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).

The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8-word line length.

By providing a complete set of common system peripherals, the S3C2440A minimizes overall system costs and eliminates the need to configure additional components. The integrated on-chip functions that are described in this document include:

• Around 1.2V internal, 1.8V/2.5V/3.3V memory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB D-

Cache/MMU

• External memory controller (SDRAM Control and Chip Select logic)

• LCD controller (up to 4K color STN and 256K color TFT) with LCD-dedicated DMA

• 4-ch DMA controllers with external request pins

• 3-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO)

• 2-ch SPls

• IIC bus interface (multi-master support)

• IIS Audio CODEC interface

• AC’97 CODEC interface

• SD Host interface version 1.0 & MMC Protocol version 2.11 compatible

• 2-ch USB Host controller / 1-ch USB Device controller (ver 1.1)

• 4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer

• 8-ch 10-bit ADC and Touch screen interface

• RTC with calendar function

• Camera interface (Max. 4096 x 4096 pixels input support. 2048 x 2048 pixel input support for scaling)

• 130 General Purpose I/O ports / 24-ch external interrupt source

• Power control: Normal, Slow, Idle and Sleep mode

• On-chip clock generator with PLL

1-1

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SAMSUNG S3C2440A User Guide

Specifications and Main Features

Frequently Asked Questions

User Manual