SAMSUNG S3C2440A User Guide

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S3C2440A

32-BIT CMOS

MICROCONTROLLER

USER'S MANUAL

Revision 1

Important Notice

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S3C2440A 32-Bit CMOS Microcontroller
User's Manual, Revision 1
Publication Number: 21-S3-C2440A-072004

© 2004 Samsung Electronics
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any

form or by any means, electric or mechanical, by photocopying, recording, or otherwise, without the prior written
consent of Samsung Electronics.

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certification (BVQ1 Certificate No. 9330). All semiconductor products are designed and
manufactured in accordance with the highest quality standards and objectives.

Samsung Electronics Co., Ltd.
San #24 Nongseo-Ri, Giheung- Eup
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Printed in the Republic of Korea

Table of Contents

Chapter 1 Product Overview

Introduction.........................................................................................................................................1-1

Features.............................................................................................................................................1-2

Block Diagram ....................................................................................................................................1-5

Pin Assignments .................................................................................................................................1-6

Signal Descriptions ..............................................................................................................................1-20

S3C2440A Special Registers ................................................................................................................1-26

Chapter 2 Programmer's Model

Overview.............................................................................................................................................2-1

Processor Operating States .........................................................................................................2-1

Switching State...........................................................................................................................2-1

Memory Formats .........................................................................................................................2-1

Big-Endian Format .......................................................................................................................2-2

Little-Endian Format ....................................................................................................................2-2

Instruction Length........................................................................................................................2-2

Operating Modes.........................................................................................................................2-3

Registers....................................................................................................................................2-3

The Program Status Registers......................................................................................................2-7

Exceptions .................................................................................................................................2-10

Interrupt Latencies.......................................................................................................................2-15

Reset .........................................................................................................................................2-15

S3C2440A MICROCONTROLLER iii

Table of Contents (Continued)

Chapter 3 ARM Instruction Set

Instruction Set Summay .......................................................................................................................3-1

Format Summary ........................................................................................................................3-1

Instruction Summary ....................................................................................................................3-2

The Condition Field ..............................................................................................................................3-4

Branch and Exchange (Bx)...................................................................................................................3-5

Instruction Cycle Times ................................................................................................................3-5

Assembler Syntax.......................................................................................................................3-5

Using R15 as an Operand ............................................................................................................3-5

Branch and Branch with Link (B, Bl) ......................................................................................................3-7

The Link Bit ................................................................................................................................3-7

Instruction Cycle Times ................................................................................................................3-7

Assembler Syntax.......................................................................................................................3-8

Data Processing..................................................................................................................................3-9

Cpsr Flags..................................................................................................................................3-11

Shifts .........................................................................................................................................3-12

Immediate Operand Rotates .........................................................................................................3-16

Writing to R15 .............................................................................................................................3-16

Using R15 as an Operandy ...........................................................................................................3-16

TEQ, TST, Cmp and Cmn Opcodes ...............................................................................................3-16

Instruction Cycle Times ................................................................................................................3-16

Assembler Syntax.......................................................................................................................3-17

Examples ...................................................................................................................................3-17

Psr Transfer (MRS, MSR).....................................................................................................................3-18

Operand Restrictions ...................................................................................................................3-18

Reserved Bits..............................................................................................................................3-20

Examples ...................................................................................................................................3-20

Instruction Cycle Times ................................................................................................................3-20

Assembly Syntax........................................................................................................................3-21

Examples ...................................................................................................................................3-21

Multiply And Multiply-Accumulate (MUL, MLA).......................................................................................3-22

Cpsr Flags..................................................................................................................................3-24

Instruction Cycle Times ................................................................................................................3-24

Assembler Syntax.......................................................................................................................3-24

Examples ...................................................................................................................................3-24

Multiply Long And Multiply-Accumulate Long (MULL, MLAL)...................................................................3-25

Operand Restrictions ...................................................................................................................3-26

Cpsr Flags..................................................................................................................................3-26

Instruction Cycle Times ................................................................................................................3-26

Assembler Syntax.......................................................................................................................3-27

Examples ...................................................................................................................................3-27

iv S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 3 ARM Instruction Set (Continued)

Single Data Transfer (LDR, STR) ...........................................................................................................3-28

Offsets and Auto-Indexing ............................................................................................................3-29

Shifted Register Offset .................................................................................................................3-29

Bytes and Words ........................................................................................................................3-29

Use of R15..................................................................................................................................3-31

Example.....................................................................................................................................3-31

Data Aborts ................................................................................................................................3-31

Instruction Cycle Times ................................................................................................................3-31

Assembler Syntax.......................................................................................................................3-32

Examples ...................................................................................................................................3-33

Halfword and Signed Data Transfer (LDRH/STRH/LDRSB/LDRSH) ...........................................................3-34

Offsets and Auto-Indexing ............................................................................................................3-35

Halfword Load and Stores .............................................................................................................3-36

Use of R15..................................................................................................................................3-37

Data Aborts ................................................................................................................................3-37

Instruction Cycle Times ................................................................................................................3-37

Assembler Syntax.......................................................................................................................3-38

Examples ...................................................................................................................................3-39

Block Data Transfer (LDM, STM)...........................................................................................................3-40

The Register List.........................................................................................................................3-40

Addressing Modes .......................................................................................................................3-41

Address Alignment ......................................................................................................................3-41

Use of the S Bit...........................................................................................................................3-43

Use of R15 as The Base..............................................................................................................3-43

Inclusion of the Base in the Register List.......................................................................................3-44

Data Aborts ................................................................................................................................3-44

Instruction Cycle Times ................................................................................................................3-44

Assembler Syntax.......................................................................................................................3-45

Examples ...................................................................................................................................3-46

Single Data Swap (SWP) .....................................................................................................................3-47

Bytes and Words ........................................................................................................................3-47

Use of R15..................................................................................................................................3-48

Data Aborts ................................................................................................................................3-48

Instruction Cycle Times ................................................................................................................3-48

Assembler Syntax.......................................................................................................................3-48

Software Interrupt (SWI).......................................................................................................................3-49

Return from the Supervisor ...........................................................................................................3-49

Comment Field............................................................................................................................3-49

Instruction Cycle Times ................................................................................................................3-49

Assembler Syntax.......................................................................................................................3-50

Coprocessor Data Operations (CDP) .....................................................................................................3-51

Coprocessor Instructions ..............................................................................................................3-51

Instruction Cycle Times ................................................................................................................3-52

Examples ...................................................................................................................................3-52

S3C2440A MICROCONTROLLER v

Table of Contents (Continued)

Chapter 3 ARM Instruction Set (Continued)

Coprocessor Data Transfers (LDC, STC) ................................................................................................3-53

The Coprocessor Fields ...............................................................................................................3-54

Addressing Modes .......................................................................................................................3-54

Address Alignment ......................................................................................................................3-54

Data Aborts ................................................................................................................................3-54

Assembler Syntax.......................................................................................................................3-55

Examples ...................................................................................................................................3-55

Coprocessor Register Transfers (MRC, MCR).................................................................................3-56

The Coprocessor Fields ...............................................................................................................3-56

Transfers to R15 ..........................................................................................................................3-57

Transfers from R15 ......................................................................................................................3-57

Instruction Cycle Times ................................................................................................................3-57

Assembler Syntax.......................................................................................................................3-57

Examples ...................................................................................................................................3-57

Undefined Instruction ...................................................................................................................3-58

Instruction Cycle Times ................................................................................................................3-58

Assembler Syntax.......................................................................................................................3-58

Instruction Set Examples .............................................................................................................3-59

Using the Conditional Instructions .................................................................................................3-59

Pseudo-Random Binary Sequence Generator.................................................................................3-61

Multiplication by Constant Using the Barrel Shifter..........................................................................3-61

Loading a Word from an Unknown Alignment .................................................................................3-63

Chapter 4 Thumb Instruction Set

Thumb Instruction Set Format ...............................................................................................................4-1

Format Summary ........................................................................................................................4-2

Opcode Summary .......................................................................................................................4-3

Format 1: Move Shifted Register...........................................................................................................4-5

Operation....................................................................................................................................4-5

Instruction Cycle Times ................................................................................................................4-6

Examples ...................................................................................................................................4-6

Format 2: Add/Subtract........................................................................................................................4-7

Operation....................................................................................................................................4-7

Instruction Cycle Times ................................................................................................................4-8

Examples ...................................................................................................................................4-8

Format 3: Move/Compare/Add/Subtract Immediate .................................................................................4-9

Operations..................................................................................................................................4-9

Instruction Cycle Times ................................................................................................................4-10

Examples ...................................................................................................................................4-10

vi S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 4 Thumb Instruction Set (Continued)

Format 4: ALU Operations ....................................................................................................................4-11

Operation....................................................................................................................................4-11

Instruction Cycle Times ................................................................................................................4-12

Examples ...................................................................................................................................4-12

Format 5: Hi-Register Operations/Branch Exchange...............................................................................4-13

Operation....................................................................................................................................4-13

Instruction Cycle Times ................................................................................................................4-14

The BX Instruction .......................................................................................................................4-14

Examples ...................................................................................................................................4-15

Using R15 As an Operand ............................................................................................................4-15

Format 6: PC-Relative Load ..................................................................................................................4-16

Operation....................................................................................................................................4-16

Instruction Cycle Times ................................................................................................................4-17

Examples ...................................................................................................................................4-17

Format 7: Load/Store With Register Offset .............................................................................................4-18

Operation....................................................................................................................................4-19

Instruction Cycle Times ................................................................................................................4-19

Examples ...................................................................................................................................4-19

Format 8: Load/Store Sign-Extended Byte/Halfword................................................................................4-20

Operation....................................................................................................................................4-20

Instruction Cycle Times ................................................................................................................4-21

Examples ...................................................................................................................................4-21

Format 9: Load/Store With Immediate Offset ..........................................................................................4-22

Operation....................................................................................................................................4-23

Instruction Cycle Times ................................................................................................................4-23

Examples ...................................................................................................................................4-23

Format 10: Load/Store Halfword ............................................................................................................4-24

Operation....................................................................................................................................4-24

Examples ...................................................................................................................................4-25

Format 11: SP-Relative Load/Store .......................................................................................................4-26

Operation....................................................................................................................................4-26

Instruction Cycle Times ................................................................................................................4-27

Examples ...................................................................................................................................4-27

Format 12: Load Address .....................................................................................................................4-28

Operation....................................................................................................................................4-28

Instruction Cycle Times ................................................................................................................4-29

Examples ...................................................................................................................................4-29

Format 13: Add Offset to Stack Pointer.................................................................................................4-30

Operation....................................................................................................................................4-30

Instruction Cycle Times ................................................................................................................4-30

Examples ...................................................................................................................................4-30

S3C2440A MICROCONTROLLER vii

Table of Contents (Continued)

Chapter 4 Thumb Instruction Set (Continued)

Format 14: Push/Pop Registers............................................................................................................4-31

Operation....................................................................................................................................4-31

Instruction Cycle Times ................................................................................................................4-32

Examples ...................................................................................................................................4-32

Format 15: Multiple Load/Store .............................................................................................................4-33

Operation....................................................................................................................................4-33

Instruction Cycle Times ................................................................................................................4-33

Examples ...................................................................................................................................4-33

Format 16: Conditional Branch..............................................................................................................4-34

Operation....................................................................................................................................4-34

Instruction Cycle Times ................................................................................................................4-35

Examples ...................................................................................................................................4-35

Format 17: Software Interrupt ................................................................................................................4-36

Operation....................................................................................................................................4-36

Instruction Cycle Times ................................................................................................................4-36

Examples ...................................................................................................................................4-36

Format 18: Unconditional Branch ..........................................................................................................4-37

Operation....................................................................................................................................4-37

Examples ...................................................................................................................................4-37

Format 19: long branch with link ...........................................................................................................4-38

Operation....................................................................................................................................4-38

Instruction Cycle Times ................................................................................................................4-39

Examples ...................................................................................................................................4-39

Instruction Set Examples .....................................................................................................................4-40

Multiplication by A Constant Using Shifts and Adds ........................................................................4-40

General Purpose Signed Divide .....................................................................................................4-41

Division by a Constant .................................................................................................................4-43

viii S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 5 Memory Controller

Overview.............................................................................................................................................5-1

Function Description ............................................................................................................................5-4

Bank0 Bus Width ........................................................................................................................5-4

Memory (SROM/SDRAM) Address Pin Connections .......................................................................5-4

Sdram Bank Address Pin Connection Example ..............................................................................5-5

nWAIT Pin Operation...................................................................................................................5-6

nXBREQ/nXBACK Pin Operation...................................................................................................5-7

Programmable Access Cycle .......................................................................................................5-12

Bus Width & Wait Control Register (Bwscon).................................................................................5-14

Bank Control Register (Bankconn: NGCS0-NGCS5) .......................................................................5-16

Bank Control Register (Bankconn: NGCS6-NGCS7) .......................................................................5-17

Refresh Control Register ..............................................................................................................5-18

Banksize Register.......................................................................................................................5-19

Sdram Mode Register Set Register (MRSR)...................................................................................5-20

Chapter 6 Nand Flash Contorller

Overview.............................................................................................................................................6-1

Features.....................................................................................................................................6-1

Block Diagram ............................................................................................................................6-2

Boot Loader Function...................................................................................................................6-2

Pin Configuration.........................................................................................................................6-3

Nand Flash Memory Configuration Table ........................................................................................6-3

Nand Flash Memory Timing ..........................................................................................................6-4

Software Mode....................................................................................................................................6-5

Steppingstone (4K-Byte SRAM)....................................................................................................6-6

Ecc (Error Correction Code)..................................................................................................................6-7

2048 Byte ECC Parity Code Assignment Table..............................................................................6-7

16 Byte ECC Parity Code Assignment Table..................................................................................6-7

ECC Module Features ..................................................................................................................6-8

ECC Programming Guide.............................................................................................................6-8

Nand Flash Memory Mapping.......................................................................................................6-9

Nand Flash Memory Configuration.................................................................................................6-10

Nand Flash Configuration Register ................................................................................................6-12

Control Register ..........................................................................................................................6-13

Command Register ......................................................................................................................6-15

Address Register.........................................................................................................................6-15

Data Register ..............................................................................................................................6-15

Main Data Area Register..............................................................................................................6-16

Spare Area Ecc Register.............................................................................................................6-17

NFCON Status Register ...............................................................................................................6-18

ECC0/1 Status Register ...............................................................................................................6-19

Main Data Area ECC0 Status Register..........................................................................................6-20

Spare Area ECC Status Register..................................................................................................6-20

Block Address Register ...............................................................................................................6-21

S3C2440A MICROCONTROLLER ix

Table of Contents (Continued)

Chapter 7 Clock & Power Management

Overview.............................................................................................................................................7-1

Functional Description .........................................................................................................................7-2

Clock Architecture .......................................................................................................................7-2

Clock Source Selection................................................................................................................7-2

Phase Locked Loop (PLL)............................................................................................................7-4

Clock Control Logic .....................................................................................................................7-6

Power Management.....................................................................................................................7-10

Clock Generator & Power Management Special Register ........................................................................7-20

Lock Time Count Register (LOCKTIME).........................................................................................7-20

PLL Control Register (MPLLCON & UPLLCON) ..............................................................................7-21

PLL Value Selection Table ...........................................................................................................7-21

Clock Control Register (CLKCON) .................................................................................................7-22

Clock Slow Control (CLKSLOW) Register......................................................................................7-23

Clock Divider Control (CLKDIVN) Register ......................................................................................7-24

Camera Clock Divider (CAMDIVN) Register ....................................................................................7-25

Chapter 8 DMA

Overview.............................................................................................................................................8-1

DMA Request Sources ........................................................................................................................8-2

DMA Operation ...................................................................................................................................8-2

External DMA DREQ/DACK Protocol............................................................................................8-3

Examples ...........................................................................................................................................8-6

DMA Special Registers........................................................................................................................8-7

DMA Initial Source (DISRC) Register .............................................................................................8-7

DMA Initial Source Control (DISRCC) Register ...............................................................................8-7

DMA Initial Destination (DIDST) Register .......................................................................................8-8

DMA Initial Destination Control (DIDSTC) Register ..........................................................................8-8

DMA Control (DCON) Register ......................................................................................................8-9

DMA Status (DSTAT) Register......................................................................................................8-12

DMA Current Source (DCSRC) Register ........................................................................................8-13

Current Destination (DCDST) Register...........................................................................................8-13

DMA Mask Trigger (DMASKTRIG) Register....................................................................................8-14

x S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 9 I/O PORTS

Overview.............................................................................................................................................9-1

Port Control Descriptions .....................................................................................................................9-7

Port Configuration Register (GPACON-GPJCON)............................................................................9-7

Port Data Register (GPADAT-GPJDAT) .........................................................................................9-7

Port Pull-Up Register (GPBUP-GPJUP).........................................................................................9-7

Miscellaneous Control Register.....................................................................................................9-7

External Interrupt Control Register.................................................................................................9-7

I/O Port Control Register......................................................................................................................9-8

Port A Control Registers (GPACON, GPADAT) ..............................................................................9-8

Port B Control Registers (GPBCON, GPBDAT, GPBUP).................................................................9-10

Port C Control Registers (GPCCON, GPCDAT, GPCUP).................................................................9-11

Port D Control Registers (GPDCON, GPDDAT, GPDUP).................................................................9-13

Port E Control Registers (GPECON, GPEDAT, GPEUP).................................................................9-15

Port F Control Registers (GPFCON, GPFDAT)...............................................................................9-17

Port G Control Registers (GPGCON, GPGDAT) .............................................................................9-18

Port H Control Registers (GPHCON, GPHDAT) ..............................................................................9-20

Port J Control Registers (GPJCON, GPJDAT) ................................................................................9-21

Miscellaneous Control Register (MISCCR).....................................................................................9-23

DCLK Control Registers (DCLKCON).............................................................................................9-25

EXTINTn (External Interrupt Control Register n)...............................................................................9-26

EINTFLTn (External Interrupt Filter Register n)................................................................................9-30

EINTMASK (External Interrupt Mask Register) ...............................................................................9-31

EINTPEND (External Interrupt Pending Register)............................................................................9-32

GSTATUSn (General Status Registers).........................................................................................9-33

DSCn (Drive Strength Control).......................................................................................................9-34

DSCn (Drive Strength Control).......................................................................................................9-35

MSLCON (Memory Sleep Control Register)....................................................................................9-36

S3C2440A MICROCONTROLLER xi

Table of Contents (Continued)

Chapter 10 Basic Timer

Overview.............................................................................................................................................10-1

Feature.......................................................................................................................................10-1

PWM Timer Operation .........................................................................................................................10-3

Prescaler & Divider......................................................................................................................10-3

Basic Timer Operation .................................................................................................................10-3

Auto Reload & Double Buffering....................................................................................................10-4

Timer Initialization Using Manual Update Bit and Inverter Bit............................................................10-5

Timer Operation...........................................................................................................................10-6

Pulse Width Modulation (PWM) ....................................................................................................10-7

Output Level Control ....................................................................................................................10-8

Dead Zone Generator ...................................................................................................................10-9

DMA Request Mode ....................................................................................................................10-10

PWM Timer Control Registers ..............................................................................................................10-11

Timer Configuration Register0 (TCFG0) ..........................................................................................10-11

Timer Configuration Register1 (TCFG1) ..........................................................................................10-12

Timer Control (TCON) Register......................................................................................................10-13

Timer 0 Count Buffer Register & Compare Buffer Register (TCNTB0/TCMPB0)...................................10-15

Timer 0 Count Observation Register (TCNTO0)...............................................................................10-15

Timer 1 Count Buffer Register & Compare Buffer Register (TCNTB1/TCMPB1)...................................10-16

Timer 1 Count Observation Register (TCNTO1)...............................................................................10-16

Timer 2 Count Buffer Register & Compare Buffer Register (TCNTB2/TCMPB2)...................................10-17

Timer 2 Count Observation Register (TCNTO2)...............................................................................10-17

Timer 3 Count Buffer Register & Compare Buffer Register (TCNTB3/TCMPB3)...................................10-18

Timer 3 Count Observation Register (TCNTO3)...............................................................................10-18

Timer 4 Count Buffer Register (TCNTB4)........................................................................................10-19

Timer 4 Count Observation Register (TCNTO4)...............................................................................10-19

xii S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 11 UART

Overview.............................................................................................................................................11-1

Features.....................................................................................................................................11-1

Block Diagram ....................................................................................................................................11-2

Uart Operation.............................................................................................................................11-3

Uart Special Registers .........................................................................................................................11-10

Uart Line Control Register ............................................................................................................11-10

Uart Control Register ...................................................................................................................11-11

Uart FIFO Control Register...........................................................................................................11-14

Uart Modem Control Register........................................................................................................11-15

Uart Tx/Rx Status Register...........................................................................................................11-16

Uart Error Status Register............................................................................................................11-17

Uart FIFO Status Register ............................................................................................................11-18

Uart Modem Status Register ........................................................................................................11-19

Uart Transmit Buffer Register (HOLDING Register & FIFO Register).................................................11-20

Uart Receive Buffer Register (HOLDING Register & FIFO Register) ..................................................11-20

Uart Baud Rate Divisor Register ....................................................................................................11-21

Chapter 12 USB HOST Controller

Overview.............................................................................................................................................12-1

Usb Host Controller Special Registers...................................................................................................12-2

OHCI Registers for Usb Host Controller .........................................................................................12-2

S3C2440A MICROCONTROLLER xiii

Table of Contents (Continued)

Chapter 13 USB Device Controller

Overview.............................................................................................................................................13-1

Feature.......................................................................................................................................13-1

Usb Device Controller Special Registers ................................................................................................13-3

Function Address Register (FUNC_ADDR_REG) ............................................................................13-5

Power Management Register (PWR_REG) ....................................................................................13-6

Interrupt Register (EP_INT_REG/USB_INT_REG)...........................................................................13-7

Interrupt Enable Register (EP_INT_EN_REG/USB_INT_EN_REG)....................................................13-9

Frame Number Register (FPAME_NUM1_REG/FRAME_NUM2_REG).............................................13-10

Index Register (INDEX_REG) ........................................................................................................13-11

MAX Packet Register (MAXP_REG) ..............................................................................................13-11

END Point0 Control Status Register (EP0_CSR)............................................................................13-12

END Point In Control Status Register (IN_CSR1_REG/IN_CSR2_REG)............................................13-13

END Point Out Control Status Register (OUT_CSR1_REG/OUT_CSR2_REG) ..................................13-15

END Point Out Write Count Register (OUT_FIFO_CNT1_REG/OUT_FIFO_CNT2_REG) .....................13-17

END Point FIFO Register (EPN_FIFO_REG)..................................................................................13-17

DMA Interface Control Register (EPN_DMA_CON) .........................................................................13-18

DMA Unit Counter Register (EPN_DMA_UNIT)...............................................................................13-19

DMA FIFO Counter Register (EPN_DMA_FIFO).............................................................................13-20

DMA Total Transfer Counter Register (EPn_DMA_TTC_L, M, H) ......................................................13-21

Chapter 14 Interrupt Controller

Overview.............................................................................................................................................14-1

Interrupt Controller Operation........................................................................................................14-2

Interrupt Sources.........................................................................................................................14-3

Interrupt Sub Sources ..................................................................................................................14-4

Interrupt Priority Generating Block.................................................................................................14-5

Interrupt Priority...........................................................................................................................14-6

Interrupt Controller Special Registers .....................................................................................................14-7

Source Pending (SRCPND) Register.............................................................................................14-7

Interrupt Mode (INTMOD) Register.................................................................................................14-9

Interrupt Mask (INTMSK) Register .................................................................................................14-11

Priority Register (PRIORITY).........................................................................................................14-13

Interrupt Pending (INTPND) Register..............................................................................................14-14

Interrupt Offset (INTOFFSET) Register ...........................................................................................14-16

Sub Source Pending (SUBSRCPND) Register................................................................................14-17

Interrupt Sub Mask (INTSUBMSK) Register ...................................................................................14-18

xiv S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 15 LCD Controller

Overview.............................................................................................................................................15-1

Features.....................................................................................................................................15-1

Common Features.......................................................................................................................15-2

External Interface Signal ..............................................................................................................15-2

Block Diagram ............................................................................................................................15-3

STN LCD Controller Operation ..............................................................................................................15-4

Timing Generator (TIMEGEN) .......................................................................................................15-4

Video Operation ..........................................................................................................................15-5

Dithering and Frame Rate Control .................................................................................................15-7

Memory Data Format (STN, BSWP = 0) ........................................................................................15-9

TFT LCD Controller Operation...............................................................................................................15-16

Video Operation ..........................................................................................................................15-16

Memory Data Format (TFT) ..........................................................................................................15-17

256 Palette Usage (TFT) ..............................................................................................................15-21

Samsung TFT LCD Panel

(3.5” PORTRAIT/256K COLOR/REFLECTIVE A-SI/TRANSFLECTIVE A-SI TFT LCD).........................15-24

Virtual Display (TFT/STN) .............................................................................................................15-25

LCD Power Enable (STN/TFT) .......................................................................................................15-26

LCD Controller Special Registers ..................................................................................................15-27

Frame Buffer Start Address 1 Register ..........................................................................................15-33

Chapter 16 ADC & Touch Screen Interface

Overview.............................................................................................................................................16-1

Features.....................................................................................................................................16-1

ADC & Touch Screen Interface Operation ..............................................................................................16-2

Block Diagram ............................................................................................................................16-2

Function Descriptions ..................................................................................................................16-3

ADC AND Touch Screen Interface Special Registers ..............................................................................16-5

ADC Control Register (ADCCON) ..................................................................................................16-5

ADC Touch Screen Control Register (ADCTSC)..............................................................................16-6

ADC Start Delay Register (ADCDLY).............................................................................................16-7

ADC Conversion Data Register (ADCDAT0)....................................................................................16-8

ADC Conversion Data Register (ADCDAT1)....................................................................................16-9

ADC Touch Screen Up-Down INT Check Register (ADCUPDN)........................................................16-9

S3C2440A MICROCONTROLLER xv

Table of Contents (Continued)

Chapter 17 Real Time Clock

Overview.............................................................................................................................................17-1

Features.....................................................................................................................................17-1

Real Time Clock Operation ...........................................................................................................17-2

Leap Year Generator....................................................................................................................17-2

Read/Write Registers ...................................................................................................................17-2

Backup Battery Operation............................................................................................................17-2

Alarm Function............................................................................................................................17-3

TICK Time Interrupt......................................................................................................................17-3

32.768kHz X-Tal Connection Example..........................................................................................17-3

Real Time Clock Special Registers .......................................................................................................17-4

Real Time Clock Control (RTCCON) Register .................................................................................17-4

TICK Time Count (TICNT) Register ................................................................................................17-4

RTC Alarm Control (RTCALM) Register..........................................................................................17-5

ALARM Second Data (ALMSEC) Register.....................................................................................17-6

ALARM Min Data (ALMMIN) Register ............................................................................................17-6

ALARM Hour Data (ALMHOUR) Register .......................................................................................17-6

ALARM Date Data (ALMDATE) Register........................................................................................17-7

ALARM Mon Data (ALMMON) Register.........................................................................................17-7

ALARM Year Data (ALMYEAR) Register.......................................................................................17-7

BCD Second (BCDSEC) Register .................................................................................................17-8

BCD Minute (BCDMIN) Register....................................................................................................17-8

BCD Hour (BCDHOUR) Register...................................................................................................17-8

BCD Date (BCDDATE) Register ....................................................................................................17-9

BCD Day (BCDDAY) Register.......................................................................................................17-9

BCD Month (BCDMON) Register...................................................................................................17-9

BCD Year (BCDYEAR) Register ...................................................................................................17-10

Chapter 18 Watchdog Timer

Overview.............................................................................................................................................18-1

Features.....................................................................................................................................18-1

Watchdog Timer Operation ...........................................................................................................18-2

Wtdat & Wtcnt............................................................................................................................18-2

Consideration of Debugging Environment .......................................................................................18-2

Watchdog Timer Special Registers .......................................................................................................18-3

Watchdog Timer Control (WTCON) Register...................................................................................18-3

Watchdog Timer Data (WTDAT) Register .......................................................................................18-4

Watchdog Timer Count (WTCNT) Register.....................................................................................18-4

xvi S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 19 MMC/SD/SDIO Controller

Features.............................................................................................................................................19-1

Block Diagram ....................................................................................................................................19-1

SD Operation......................................................................................................................................19-2

SDIO Operation ...................................................................................................................................19-3

SDI Special Registers..........................................................................................................................19-4

SDI Control Register (SDICON) .....................................................................................................19-4

SDI Baud Rate Prescaler Register (SDIPRE).................................................................................19-4

SDI Command Argument Register (SDICmdArg).............................................................................19-5

SDI Command Control Register (SDICmdCon)................................................................................19-5

SDI Command Status Register (SDICmdSta).................................................................................19-6

SDI Response Register 0 (SDIRSP0) ............................................................................................19-6

SDI Response Register 1 (SDIRSP1) ............................................................................................19-6

SDI Response Register 2 (SDIRSP2) ............................................................................................19-7

SDI Response Register 3 (SDIRSP3) ............................................................................................19-7

SDI Data / Busy Timer Register (SDIDTimer)..................................................................................19-7

SDI Block Size Register (SDIBSize)..............................................................................................19-7

SDI Data Control Register (SDIDatCon) .........................................................................................19-8

SDI Data Remain Counter Register (ADIDatCnt) .............................................................................19-9

SDI Data Status Register (ADIDatSta) ...........................................................................................19-9

SDI FIFO Status Register (SDIFSTA) ............................................................................................19-10

SDI Interrupt Mask Register (SDIIntMsk)........................................................................................19-11

SDI Data Register (SDIDAT) .........................................................................................................19-12

Chapter 20 IIC-Bus Interface

Overview.............................................................................................................................................20-1

IIC-Bus Interface..........................................................................................................................20-3

Start and Stop Conditions ............................................................................................................20-3

Data Transfer Format ...................................................................................................................20-4

ACK Signal Transmission.............................................................................................................20-5

Read-Write Operation ..................................................................................................................20-6

Bus Arbitration Procedures ...........................................................................................................20-6

Abort Conditions ..........................................................................................................................20-6

Configuring IIC-Bus ......................................................................................................................20-6

Flowcharts of Operations in Each Mode.........................................................................................20-7

IIC-Bus Interface Special Registers .......................................................................................................20-11

Multi-Master IIC-Bus Control (IICCON) Register..............................................................................20-11

Multi-Master IIC-Bus Control/Status (IICSTAT) Register...................................................................20-12

Multi-Master IIC-Bus Address (IICADD) Register.............................................................................20-13

Multi-Master IIC-Bus Transmit/Receive Data Shift (IICDS) Register ...................................................20-13

Multi-Master IIC-Bus Line Contro l(IICLC) Register..........................................................................20-14

S3C2440A MICROCONTROLLER xvii

Table of Contents (Continued)

Chapter 21 IIS-Bus Interface

Overview.............................................................................................................................................21-1

Block Diagram ....................................................................................................................................21-2

Functional Descriptions ........................................................................................................................21-2

Transmit or Receive Only Mode ....................................................................................................21-2

Dma Transfer ..............................................................................................................................21-3

Transmit and Receive Mode..........................................................................................................21-3

Audio Serial Interface Format ................................................................................................................21-3

IIS-Bus Format............................................................................................................................21-3

MSB (Left) Justified .....................................................................................................................21-3

Sampling Frequency and Master Clock .........................................................................................21-4

IIS-Bus Interface Special Registers .......................................................................................................21-5

IIS Control (IISCON) Register ........................................................................................................21-5

IIS Mode Register (IISMOD) Register.............................................................................................21-6

IIS Prescaler (IISPSR) Register.....................................................................................................21-7

IIS FIFO Control (IISFCON) Register..............................................................................................21-8

IIS FIFO (IISFIFO) Register...........................................................................................................21-8

Chapter 22 SPI

Overview.............................................................................................................................................22-1

Features.....................................................................................................................................22-1

Block Diagram ............................................................................................................................22-2

SPI Operation .....................................................................................................................................22-3

Programming Procedure...............................................................................................................22-3

SPI Transfer Format .....................................................................................................................22-4

Transmitting Procedure for DMA ...................................................................................................22-5

Receiving Procedure for DMA .......................................................................................................22-5

SPI Special Registers..........................................................................................................................22-6

SPI Control Register....................................................................................................................22-6

SPI Status Register .....................................................................................................................22-7

SPI Pin Control Register ..............................................................................................................22-8

SPI Baud Rate Prescaler Register ................................................................................................22-9

SPI Tx Data Register...................................................................................................................22-9

SPI Rx Data Register...................................................................................................................22-9

xviii S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 23 Camera Interface

Overview.............................................................................................................................................23-1

Features.....................................................................................................................................23-1

Block Diagram ............................................................................................................................23-2

Timing Diagram...........................................................................................................................23-3

Camera Interface Operation..................................................................................................................23-5

Two DMA Paths ..........................................................................................................................23-5

Clock Domain .............................................................................................................................23-5

Frame Memory Hirerarchy............................................................................................................23-6

Memory Storing Method ...............................................................................................................23-8

Timing Diagram for Register Setting ..............................................................................................23-9

Timing Diagram for Last IRQ .........................................................................................................23-10

Camera Interface Special Registers .......................................................................................................23-11

Source Format Register...............................................................................................................23-11

Window Option Register...............................................................................................................23-12

Global Control Register................................................................................................................23-13

Y1 Start Address Register............................................................................................................23-13

Y2 Start Address Register............................................................................................................23-13

Y3 Start Address Register............................................................................................................23-14

Y4 Start Address Register............................................................................................................23-14

CB1 Start Address Register .........................................................................................................23-14

CB2 Start Address Register .........................................................................................................23-14

CB3 Start Address Register .........................................................................................................23-15

CB4 Start Address Register .........................................................................................................23-15

CR1 Start Address Register .........................................................................................................23-15

CR2 Start Address Register .........................................................................................................23-15

CR3 Start Address Register .........................................................................................................23-16

CR4 Start Address Register .........................................................................................................23-16

Codec Target Format Register......................................................................................................23-17

Codec Dma Control Register ........................................................................................................23-19

Register Setting Guide for Codec Scaler and Preview Scaler ...........................................................23-20

Codec Pre-Scaler Control Register 1 .............................................................................................23-21

Codec Pre-Scaler Control Register 2 .............................................................................................23-21

Codec Main-Scaler Control Register ..............................................................................................23-22

Codec Dma Target Area Register ..................................................................................................23-22

Codec Status Register .................................................................................................................23-23

RGB1 Start Address Register .......................................................................................................23-23

RGB2 Start Address Register .......................................................................................................23-23

RGB3 Start Address Register .......................................................................................................23-24

RGB4 Start Address Register .......................................................................................................23-24

Preview Target Format Register ....................................................................................................23-24

Preview DMA Control Register......................................................................................................23-25

S3C2440A MICROCONTROLLER xix

Table of Contents (Continued)

Chapter 23 Camera Interface (Continued)

Preview Pre-Scaler Control Register 1...........................................................................................23-25

Preview Pre-Scaler Control Register 2...........................................................................................23-26

Preview Main-Scaler Control Register............................................................................................23-26

Preview DMA Target Area Register................................................................................................23-26

Preview Status Register...............................................................................................................23-27

Image Capture Enable Register.....................................................................................................23-27

Chapter 24 AC97 Controller

Overview.............................................................................................................................................24-1

Features.....................................................................................................................................24-1

AC97 Controller Operation ....................................................................................................................24-2

Block Diagram ............................................................................................................................24-2

Internal Data Path........................................................................................................................24-3

Operation Flow Chart ...........................................................................................................................24-4

AC-Link Digital Interface Protocol ..........................................................................................................24-5

AC-Link Output Frame (SDATA_OUT) ...........................................................................................24-6

AC-Link Input Frame (SDATA_IN) .................................................................................................24-6

AC97 Powerdown................................................................................................................................24-7

AC97 Controller Special Registers ........................................................................................................24-9

AC97 Global Control Register (AC_GLBCTRL) ...............................................................................24-9

AC97 Global Status Register (AC_GLBSTAT) ................................................................................24-10

AC97 Codec Command Register (AC_CODEC_CMD) .....................................................................24-10

AC97 Codec Status Register (AC_CODEC_STAT) .........................................................................24-11

AC97 PCM Out/In Channel FIFO Address Register (AC_PCMADDR)...............................................24-11

AC97 MIC in Channel FIFO Address Register (AC_MICADDR) ........................................................24-12

AC97 PCM Out/In Channel FIFO Data Register (AC_PCMDATA).....................................................24-12

AC97 MIC in Channel FIFO Data Register (AC_MICDATA) ..............................................................24-12

xx S3C2440A MICROCONTROLLER

Table of Contents (Continued)

Chapter 25 Bus Priorities

Overview.............................................................................................................................................25-1

Bus Priority Map .........................................................................................................................25-1

Chapter 26 Mechanical Data

Package Dimensions...........................................................................................................................26-1

Chapter 27 Electrical Data

Absolute Maximum Ratings ..................................................................................................................27-1

Recommended Operating Conditions .....................................................................................................27-2

D.C. Electrical Characteristics ..............................................................................................................27-3

A.C. Electrical Characteristics ..............................................................................................................27-8

S3C2440A MICROCONTROLLER xxi

List of Figures

Figure Title Page
Number Number

1-1 S3C2440A Block Diagram ................................................................................................1-5

1-2 S3C2440A Pin Assignments (289-FBGA) ..........................................................................1-6

2-1 Big-Endian Addresses of Bytes within Words .....................................................................2-2

2-2 Little-Endian Addresses of Bytes within Words ..................................................................2-2

2-3 Register Organization in ARM State..................................................................................2-4

2-4 Register Organization in THUMB state..............................................................................2-5

2-5 Mapping of THUMB State Registers onto ARM State Registers ...........................................2-6

2-6 Program Status Register Format .......................................................................................2-7

3-1 ARM Instruction Set Format .............................................................................................3-1

3-2 Branch and Exchange Instructions....................................................................................3-5

3-3 Branch Instructions ..........................................................................................................3-7

3-4 Data Processing Instructions............................................................................................3-9

3-5 ARM Shift Operations ......................................................................................................3-12

3-6 Logical Shift Left ..............................................................................................................3-12

3-7 Logical Shift Right ...........................................................................................................3-13

3-8 Arithmetic Shift Right.......................................................................................................3-13

3-9 Rotate Right ....................................................................................................................3-14

3-10 Rotate Right Extended .....................................................................................................3-14

3-11 PSR Transfer ..................................................................................................................3-19

3-12 Multiply Instructions .........................................................................................................3-22

3-13 Multiply Long Instructions .................................................................................................3-25

3-14 Single Data Transfer Instructions .......................................................................................3-28

3-15 Little-Endian Offset Addressing .........................................................................................3-30

3-16 Halfword and Signed Data Transfer with Register Offset .......................................................3-34

3-17 Halfword and Signed Data Transfer with Immediate Offset and Auto-Indexing.........................3-35

3-18 Block Data Transfer Instructions .......................................................................................3-40

3-19 Post-Increment Addressing ..............................................................................................3-41

3-20 Pre-Increment Addressing................................................................................................3-42

3-21 Post-Decrement Addressing .............................................................................................3-42

3-22 Pre-Decrement Addressing...............................................................................................3-43

3-23 Swap Instruction..............................................................................................................3-47

3-24 Software Interrupt Instruction ............................................................................................3-49

3-25 Coprocessor Data Operation Instruction.............................................................................3-51

3-26 Coprocessor Data Transfer Instructions .............................................................................3-53

3-27 Coprocessor Register Transfer Instructions ........................................................................3-56

3-28 Undefined Instruction .......................................................................................................3-58

S3C2440A MICROCONTROLLER xxiii

List of Figures (Continued)

Figure Title Page
Number Number

4-1 THUMB Instruction Set Formats .......................................................................................4-2

4-2 Format 1.........................................................................................................................4-5

4-3 Format 2.........................................................................................................................4-7

4-4 Format 3.........................................................................................................................4-9

4-5 Format 4.........................................................................................................................4-11

4-6 Format 5.........................................................................................................................4-13

4-7 Format 6.........................................................................................................................4-16

4-8 Format 7.........................................................................................................................4-18

4-9 Format 8.........................................................................................................................4-20

4-10 Format 9.........................................................................................................................4-22

4-11 Format 10 .......................................................................................................................4-24

4-12 Format 11 .......................................................................................................................4-26

4-13 Format 12 .......................................................................................................................4-28

4-14 Format 13 .......................................................................................................................4-30

4-15 Format 14 .......................................................................................................................4-31

4-16 Format 15 .......................................................................................................................4-33

4-17 Format 16 .......................................................................................................................4-34

4-18 Format 17 .......................................................................................................................4-36

4-19 Format 18 .......................................................................................................................4-37

4-20 Format 19 .......................................................................................................................4-38

5-1 S3C2440A Memory Map after Reset .................................................................................5-2

5-2 S3C2440A External nWAIT Timing Diagram (Tacc=4).........................................................5-6

5-3 S3C2440A nXBREQ/nXBACK Timing Diagram ...................................................................5-7

5-4 Memory Interface with 8-bit ROM......................................................................................5-8

5-5 Memory Interface with 8-bit ROM x 2.................................................................................5-8

5-6 Memory Interfac e with 8-bit ROM x 4.................................................................................5-9

5-7 Memory Interface with 16-bit ROM ....................................................................................5-9

5-8 Memory Interface with 16-bit SRAM ..................................................................................5-10

5-9 Memory Interface with 16-bit SRAM x 2.............................................................................5-10

5-10 Memory Interface with 16-bit SDRAM (4Mx16, 4banks).......................................................5-11

5-11 Memory Interface with 16-bit SDRAM (4Mx16x4Bank * 2ea) ................................................5-11

5-12 S3C2440A nGCS Timing Diagram .....................................................................................5-12

5-13 S3C2440A SDRAM Timing Diagram ..................................................................................5-13

xxiv S3C2440A MICROCONTROLLER

List of Figures (Continued)

Figure Title Page
Number Number

6-1 NAND Flash Controller Block Diagram...............................................................................6-2

6-2 NAND Flash Controller Boot Loader Block Diagram............................................................6-2

6-3 CLE & ALE Timing (TACLS=1, TWRPH0=0, TWRPH1=0) ...................................................6-4

6-4 nWE & nRE Timing (TWRPH0=0, TWRPH1=0) ..................................................................6-4

6-5 NAND Flash Memory Mapping..........................................................................................6-9

6-6 A 8-bit NAND Flash Memory Interface ...............................................................................6-10

6-7 Two 8-bit NAND Flash Memory Interface............................................................................6-10

6-8 A 16-bit NAND Flash Memory Interface.............................................................................6-11

7-1 Clock Generator Block Diagram ........................................................................................7-3

7-2 PLL (Phase-Locked Loop) Block Diagram ..........................................................................7-5

7-3 Main Oscillator Circuit Examples ......................................................................................7-5

7-4 Power-On Reset Sequence (when the external clock source is a crystal oscillat or) ...............7-6

7-5 Changing Slow Clock by Setting PMS Value......................................................................7-7

7-6 Example of Internal Clock Change.....................................................................................7-8

7-7 The Clock Distribution Block Diagram................................................................................7-10

7-8 Power Management State Diagram...................................................................................7-11

7-9 Issuing Exit_from_Slow_mode Command in PLL on State...................................................7-13

7-10 Issuing Exit_from_Slow_mode Command After Lock Time...................................................7-13

7-11 Issuing Exit_from_Slow_mode Command and the Instant PLL_on

Command Simultaneously................................................................................................7-14

7-12 SLEEP Mode ..................................................................................................................7-17

8-1 Basic DMA Timing Diagram..............................................................................................8-3

8-2 Demand/Handshake Mode Comparison.............................................................................8-4

8-3 Burst 4 Transfer Size .......................................................................................................8-5

8-4 Single service in Demand Mode with Unit Transfer Size.......................................................8-6

8-5 Single service in Handshake Mode with Unit Transfer Size..................................................8-6

8-6 Whole service in Handshake Mode with Unit Transfer Size ..................................................8-6

10-1 16-bit PWM Timer Block Diagram.....................................................................................10-2

10-2 Timer Operations.............................................................................................................10-3

10-3 Example of Double Buffering Function ...............................................................................10-4

10-4 Example of a Timer Operation...........................................................................................10-6

10-5 Example of PWM ............................................................................................................10-7

10-6 Inverter On/Off.................................................................................................................10-8

10-7 The Wave Form When a Dead Zone Feature is Enabled ......................................................10-9

10-8 Timer4 DMA Mode Operation............................................................................................10-10

S3C2440A MICROCONTROLLER xxv

List of Figures (Continued)

Figure Title Page
Number Number

11-1 UART Block Diagram (with FIFO) ......................................................................................11-2

11-2 UART AFC interface........................................................................................................11-4

11-3 Example showing UART Receiving 5 Characters with 2 Errors .............................................11-6

11-4 IrDA Function Block Diagram............................................................................................11-8

11-5 Serial I/O Frame Timing Diagram (Normal UART) ................................................................11-9

11-6 Infrared Transmit Mode Frame Timing Diagram ...................................................................11-9

11-7 Infrared Receive Mode Frame Timing Diagram....................................................................11-9

11-8 nCTS and Delta CTS Timing Diagram................................................................................11-19

12-1 USB Host Controller Block Diagram..................................................................................12-1

13-1 USB Device Controller Block Diagram ...............................................................................13-2

14-1 Interrupt Process Diagram ................................................................................................14-1

14-2 Priority Generating Block .................................................................................................14-5

15-1 LCD Controller Block Diagram ..........................................................................................15-3

15-2 Monochrome Display Types (STN)....................................................................................15-12

15-3 Color Display Types (STN) ...............................................................................................15-13

15-4 8-bit Single Scan Display Type STN LCD Timing................................................................15-15

15-5 16BPP Display Types (TFT) .............................................................................................15-22

15-6 TFT LCD Timing Example.................................................................................................15-23

15-7 Example of Scrolling in Virtual Display (Single Scan) ..........................................................15-25

15-8 Example of PWREN Function (PWREN=1, INVPWREN=0) ................................................15-26

16-1 ADC and Touch Screen Interface Functional Block Diagram................................................16-2

16-2 ADC and Touch Screen Operation signal...........................................................................16-4

17-1 Real Time Clock Block Diagram........................................................................................17-2

17-2 Main Oscillator Circuit Example ........................................................................................17-3

18-1 Watchdog Timer Block Diagram........................................................................................18-2

19-1 SD Interface Block Diagram..............................................................................................19-1

20-1 IIC-Bus Block Diagram .....................................................................................................20-2

20-2 Start and Stop Condition..................................................................................................20-3

20-3 IIC-Bus Interface Data Format...........................................................................................20-4

20-4 Data Transfer on the IIC-Bus.............................................................................................20-5

20-5 Acknowledge on the IIC-Bus.............................................................................................20-5

20-6 Operations for Master/Transmitter Mode............................................................................20-7

20-7 Operations for Master/Receiver Mode................................................................................20-8

20-8 Operations for Slave/Transmitter Mode ..............................................................................20-9

20-9 Operations for Slave/Receiver Mode ..................................................................................20-10

xxvi S3C2440A MICROCONTROLLER

List of Figures (Continued)

Figure Title Page
Number Number

21-1 IIS-Bus Block Diagram .....................................................................................................21-2

21-2 IIS-Bus and MSB (Left)-justified Data Interface Formats ......................................................21-4

22-1 SPI Block Diagram..........................................................................................................22-2

22-2 SPI Transfer Format .........................................................................................................22-4

23-1 CAMIF Overview..............................................................................................................23-2

23-2 ITU-R BT 601 Input Timing Diagram ...................................................................................23-3

23-3 ITU-R BT 656 Input Timing Diagram ...................................................................................23-3

23-4 Two DMA Paths ..............................................................................................................23-5

23-5 CAMIF Clock Generation..................................................................................................23-6

23-6 Ping-Pong Memory Hierarchy ...........................................................................................23-7

23-7 Memory Storing Style......................................................................................................23-8

23-8 Timing Diagram for Register Setting ..................................................................................23-9

23-9 Timing diagram for last IRQ ..............................................................................................23-10

23-10 Window Offset Scheme....................................................................................................23-12

23-11 Image Mirror and Rotation ................................................................................................23-18

23-12 Scaling Scheme ..............................................................................................................23-20

24-1 AC97 Block Diagram .......................................................................................................24-2

24-2 Internal Data Path............................................................................................................24-3

24-3 AC97 Operation Flow Chart ..............................................................................................24-4

24-4 Bi-directional AC-link Frame with Slot Assignments............................................................24-5

24-5 AC-link Output Frame......................................................................................................24-6

24-6 AC-link Input Frame .........................................................................................................24-6

24-7 AC97 Powerdown Timing Diagram.....................................................................................24-7

24-8 AC97 Power down/Power up Flow .....................................................................................24-8

26-1 289-FBGA-1414 Package Dimension 1 (Top View) .............................................................26-1

26-2 289-FBGA-1414 Package Dimension 2 (Bottom View)........................................................26-2

27-1 Power Consumption Example Comparison when Applied DVS Scheme................................27-7

27-2 XTIpll Clock Timing Diagram .............................................................................................27-8

27-3 EXTCLK Clock Input Timing Diagram .................................................................................27-8

27-4 EXTCLK/HCLK in case when EXTCLK is used Without the PLL...........................................27-8

27-5 HCLK/CLKOUT/SCLK in case when EXTCLK is used .........................................................27-9

27-6 Manual Reset Input Timing Diagram..................................................................................27-9

27-7 Power-On Oscillation Setting Timing Diagram ....................................................................27-10

27-8 Sleep Mode Return Oscillation Setting Timing Diagram .......................................................27-11

27-9 ROM/SRAM Burst READ Timing Diagram (I)

(Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=0, DW=16bit)...............................27-12

27-10 ROM/SRAM Burst READ Timing Diagram (II)

(Tacs=0, Tcos=0, Tacc=2, Toch=0, Tcah=0, PMC=0, ST=1, DW=16bit)...............................27-13

S3C2440A MICROCONTROLLER xxvii

List of Figures (Continued)

Figure Title Page
Number Number

27-11 External Bus Request in ROM/SRAM Cycle

(Tacs=0, Tcos=0, Tacc=8, Toch=0, Tcah=0, PMC=0, ST=0)...............................................27-14

27-12 ROM/SRAM READ Timing Diagram (I)

(Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=0)...............................................27-15

27-13 ROM/SRAM READ Timing Diagram (II)

(Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2cycle, PMC=0, ST=1) .......................................27-16

27-14 ROM/SRAM WRITE Timing Diagram (I)

(Tacs=2,Tcos=2,Tacc=4,Toch=2, Tcah=2, PMC=0, ST=0 ...................................................27-17

27-15 ROM/SRAM WRITE Timing Diagram (II)

(Tacs=2, Tcos=2, Tacc=4, Toch=2, Tcah=2, PMC=0, ST=1)...............................................27-18

27-16 External nWAIT READ Timing Diagram

(Tacs=0, Tcos=0, Tacc=6, Toch=0, Tcah=0, PMC=0, ST=0)...............................................27-19

27-17 External nWAIT WRITE Timing Diagram

(Tacs=0, Tcos=0, Tacc=4, Toch=0, Tcah=0, PMC=0, ST=0)...............................................27-19

27-18 Masked-ROM Single READ Timing Diagram (Tacs=2, Tcos=2, Tacc=8, PMC=01/10/11).......27-20

27-19 Masked-ROM Consecutive READ Timing Diagram

(Tacs=0, Tcos=0, Tacc=3, Tpac=2, PMC=01/10/11) ...........................................................27-20

27-20 SDRAM Single Burst READ Timing Diagram (Trp=2, Trcd=2, Tcl=2, DW=16bit)....................27-21

27-21 External Bus Request in SDRAM Timing Diagram (Trp=2, Trcd=2, Tcl=2) .............................27-22

27-22 SDRAM MRS Timing Diagram..........................................................................................27-23

27-23 SDRAM Single READ Timing Diagram (I) (Trp=2, Trcd=2, Tcl=2) .........................................27-24

27-24 SDRAM Single READ Timing Diagram (II) (Trp=2, Trcd=2, Tcl=3).........................................27-25

27-25 SDRAM Auto Refresh Timing Diagram (Trp=2, Trc=4).........................................................27-26

27-26 SDRAM Page Hit-Miss READ Timing Diagram (Trp=2, Trcd=2, Tcl=2)..................................27-27

27-27 SDRAM Self Refresh Timing Diagram (Trp=2, Trc=4) ..........................................................27-28

27-28 SDRAM Single Write Timing Diagram (Trp=2, Trcd=2) ........................................................27-29

27-29 SDRAM Page Hit-Miss Write Timing Diagram (Trp=2, Trcd=2, Tcl=2) ...................................27-30

27-30 External DMA Timing Diagram (Handshake, Single transfer) ................................................27-31

27-31 TFT LCD Controller Timing Diagram...................................................................................27-31

27-32 IIS Interface Timing Diagram.............................................................................................27-32

27-33 IIC Interface Timing Diagram.............................................................................................27-32

27-34 SD/MMC Interface Timing Diagram....................................................................................27-33

27-35 SPI Interface Timing Diagram (CPHA=1, CPOL=1) .............................................................27-33

27-36 NAND Flash Address/Command Timing Diagram ...............................................................27-34

27-37 NAND Flash Timing Diagram............................................................................................27-34

xxviii S3C2440A MICROCONTROLLER

List of Tables

Table Title Page
Number Number

1-1 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 1 of 3).....................................1-7

1-2 S3C2440A 289-Pin FBGA Pin Assignments (Sheet 1 of 9) ..................................................1-10

1-3 S3C2440A Signal Descriptions (Sheet 1 of 6).....................................................................1-20

1-4 S3C2440A Special Registers (Sheet 1 of 14) .....................................................................1-26

2-1 PSR Mode Bit Values......................................................................................................2-9

2-2 Exception Entry/Exit........................................................................................................2-11

2-3 Exception Vectors...........................................................................................................2-13

3-1 The ARM Instruction Set ..................................................................................................3-2

3-2 Condition Code Summary .................................................................................................3-4

3-3 ARM Data Processing Instructions ....................................................................................3-11

3-4 Incremental Cycle Times..................................................................................................3-16

3-5 Assembler Syntax Descriptions........................................................................................3-27

3-6 Addressing Mode Names .................................................................................................3-45

4-1 THUMB Instruction Set Opcodes ......................................................................................4-3

4-2 Summary of Format 1 Instructions ....................................................................................4-5

4-3 Summary of Format 2 Instructions ....................................................................................4-7

4-4 Summary of Format 3 Instructions ....................................................................................4-9

4-5 Summary of Format 4 Instructions ....................................................................................4-11

4-6 Summary of Format 5 Instructions ....................................................................................4-13

4-7 Summary of PC-Relative Load Instruction ..........................................................................4-16

4-8 Summary of Format 7 Instructions ....................................................................................4-19

4-9 Summary of Format 8 Instructions ....................................................................................4-20

4-10 Summary of Format 9 Instructions ....................................................................................4-23

4-11 Halfword Data Transfer Instructions ...................................................................................4-24

4-12 SP-Relative Load/Store Instructions ..................................................................................4-26

4-13 Load Address..................................................................................................................4-28

4-14 The ADD SP Instruction...................................................................................................4-30

4-15 PUSH and POP Instructions .............................................................................................4-31

4-16 The Multiple Load/Store Instructions ..................................................................................4-33

4-17 The Conditional Branch Instructions ..................................................................................4-34

4-18 The SWI Instruction.........................................................................................................4-36

4-19 Summary of Branch Instruction .........................................................................................4-37

4-20 The BL Instruction ...........................................................................................................4-39

5-1 Bank 6/7 Addresses ........................................................................................................5-3

5-2 SDRAM Bank Address Configuration Example ...................................................................5-5

7-1 Clock Source Selection at Boot-Up...................................................................................7-2

7-2 Clock and Power State in Each Power Mode .....................................................................7-11

7-3 CLKSLOW and CLKDIVN Register Settings for SLOW Clock ex ample.................................7-12

7-4 Pin configuration table in Sleep mode ................................................................................7-16

S3C2440A MICROCONTROLLER xxix

List of Tables (Continued)

Table Title Page
Number Number

8-1 DMA Request Sources for Each Channel...........................................................................8-2

9-1 S3C2440A Port Configuration (Sheet 1 of 5) .......................................................................9-2

11-1 Interrupts in Connection with FIFO ...................................................................................11-5

15-1 Relation Between VCLK and CLKVAL (STN, HCLK = 60MHz) .............................................15-5

15-2 Dither Duty Cycle Examples .............................................................................................15-7

15-3 Relation between VCLK and CLKVAL (TFT, HCLK = 60MHz)..............................................15-16

15-4 5:6:5 Format ...................................................................................................................15-21

15-5 5:5:5:1 Format ................................................................................................................15-21

15-6 MV Value for Each Display Mode......................................................................................15-41

21-1 CODEC clock (CODECLK = 256 or 384fs) .........................................................................21-4

21-2 Usable Serial Bit Clock Frequency (IISCLK = 16 or 32 or 48fs)............................................21-4

23-1 Camera Interface Signal Description ..................................................................................23-1

23-2 Video Timing Reference Codes of ITU-656 Format ..............................................................23-4

27-1 Absolute Maximum Rating ...............................................................................................27-1

27-2 Recommended Operating Conditions .................................................................................27-2

27-3 Normal I/O PAD DC Electrical Characteristics....................................................................27-3

27-4 USB DC Electrical Characteristics....................................................................................27-6

27-5 S3C2440 Power Supply Voltage and Current ......................................................................27-6

27-6 Typical Current Decrease by CLKCON Register .................................................................27-7

27-7 Clock Timing Constants...................................................................................................27-35

27-8 ROM/SRAM Bus Timing Constants...................................................................................27-36

27-9 Memory Interface Timing Constants ..................................................................................27-36

27-10 External Bus Request Timing Constants............................................................................27-37

27-11 DMA Controller Module Signal Timing Constants ................................................................27-37

27-12 TFT LCD Controller Module Signal Timing Constants ..........................................................27-38

27-13 IIS Controller Module Signal Timing Constants ...................................................................27-38

27-14 IIC BUS Controller Module Signal Timing ...........................................................................27-39

27-15 SD/MMC Interface Transmit/Receive Timing Constants.......................................................27-39

27-16 SPI Interface Transmit/Receive Timing Constants...............................................................27-40

27-17 USB Electrical Specifications ...........................................................................................27-40

27-18 USB Full Speed Output Buffer Electrical Characteristics .....................................................27-41

27-19 USB Low Speed Output Buffer Electrical Characteristics .....................................................27-41

27-20 NAND Flash Interface Timing Constants............................................................................27-42

xxx S3C2440A MICROCONTROLLER

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

1 PRODUCT OVERVIEW

INTRODUCTION

This user’s manual describes SAMSUNG's S3C2440A 16/32-bit RISC microprocessor. SAMSUNG’s S3C2440A is
designed to provide hand-held devices and general applications with low-power, and high-performance micro­controller solution in small die size. To reduce total system cost, the S3C2440A includes the following components.

The S3C2440A is developed with ARM920T core, 0.13um CMOS standard cells and a memory complier. Its low­power, simple, elegant and fully static design is particularly suitable for cost- and power-sensitive applications. It
adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA).

The S3C2440A offers outstanding features with its CPU core, a 16/32-bit ARM920T RISC processor designed by
Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with
separate 16KB instruction and 16KB data caches, each with an 8-word line length.

By providing a complete set of common system peripherals, the S3C2440A minimizes overall system costs and
eliminates the need to configure additional components. The integrated on-chip functions that are described in this
document include:

• Around 1.2V internal, 1.8V/2.5V/3.3V memory, 3.3V external I/O microprocessor with 16KB I-Cache/16KB D-

Cache/MMU

• External memory controller (SDRAM Control and Chip Select logic)

• LCD controller (up to 4K color STN and 256K color TFT) with LCD-dedicated DMA

• 4-ch DMA controllers with external request pins

• 3-ch UARTs (IrDA1.0, 64-Byte Tx FIFO, and 64-Byte Rx FIFO)

• 2-ch SPls

• IIC bus interface (multi-master support)

• IIS Audio CODEC interface

• AC’97 CODEC interface

• SD Host interface version 1.0 & MMC Protocol version 2.11 compatible

• 2-ch USB Host controller / 1-ch USB Device controller (ver 1.1)

• 4-ch PWM timers / 1-ch Internal timer / Watch Dog Timer

• 8-ch 10-bit ADC and Touch screen interface

• RTC with calendar function

• Camera interface (Max. 4096 x 4096 pixels input support. 2048 x 2048 pixel input support for scaling)

• 130 General Purpose I/O ports / 24-ch external interrupt source

• Power control: Normal, Slow, Idle and Sleep mode

• On-chip clock generator with PLL

1-1

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

FEATURES

Architecture

• Integrated system for hand-held devices and

general embedded applications.

• 16/32-Bit RISC architecture and powerful

instruction set with ARM920T CPU core.

• Enhanced ARM architecture MMU to support

WinCE, EPOC 32 and Linux.

• Instruction cache, data cache, write buffer and

Physical address TAG RAM to reduce the effect of
main memory bandwidth and latency on
performance.

• ARM920T CPU core supports the ARM debug

architecture.

• Internal Advanced Microcontroller Bus Architecture

(AMBA) (AMBA2.0, AHB/APB).

System Manager

• Little/Big Endian support.

• Support Fast bus mode and Asynchronous bus

mode.

• Address space: 128M bytes for each bank (total

1G bytes).

• Supports programmable 8/16/32-bit data bus width

for each bank.

• Fixed bank start address from bank 0 to bank 6.

• Programmable bank start address and bank size

for bank 7.

• Eight memory banks:

– Six memory banks for ROM, SRAM, and others.
– Two memory banks for ROM/SRAM/

Synchronous DRAM.

• Complete Programmable access cycles for all

memory banks.

• Supports external wait signals to expand the bus

cycle.

NAND Flash Boot Loader

• Supports booting from NAND flash memory.

• 4KB internal buffer for booting.

• Supports storage memory for NAND flash memory

after booting.

• Supports Advanced NAND flash

Cache Memory

• 64-way set-associative cache with I-Cache (16KB)

and D-Cache (16KB).

• 8words length per line with one valid bit and two

dirty bits per line.

• Pseudo random or round robin replacement

algorithm.

• Write-through or write-back cache operation to

update the main memory.

• The write buffer can hold 16 words of data and four

addresses.

Clock & Power Manager

• On-chip MPLL and UPLL:

UPLL generates the clock to operate USB
Host/Device.
MPLL generates the clock to operate MCU at
maximum 400Mhz @ 1.3V.

• Clock can be fed selectively to each function block

by software.

• Power mode : Normal, Slow, Idle, and Sleep

mode

Normal mode : Normal operating mode
Slow mode : Low frequency clock without PLL
Idle mode : The clock for only CPU is stopped.
Sleep mode : The Core power including all

peripherals is shut down.

• Woken up by EINT[15:0] or RTC alarm interrupt

from Sleep mode

• Supports self-refresh mode in SDRAM for power-

down.

• Supports various types of ROM for booting

(NOR/NAND Flash, EEPROM, and others).

1-2

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

FEATURES (Continued)

Interrupt Controller

• 60 Interrupt sources

(One Watch dog timer, 5 timers, 9 UARTs, 24
external interrupts, 4 DMA, 2 RTC, 2 ADC, 1 IIC, 2
SPI, 1 SDI, 2 USB, 1 LCD, 1 Battery Fault, 1
NAND and 2 Camera), 1 AC97

• Level/Edge mode on external interrupt source

• Programmable polarity of edge and level

• Supports Fast Interrupt request (FIQ) for very

urgent interrupt request

Timer with Pulse Width Modulation (PWM)

• 4-ch 16-bit Timer with PWM / 1-ch 16-bit internal

timer with DMA-based or interrupt-based operation

• Programmable duty cycle, frequency, and polarity

• Dead-zone generation

• Supports external clock sources

RTC (Real Time Clock)

• Full clock feature: msec, second, minute, hour,

date, day, month, and year

• 32.768 KHz operation

• Alarm interrupt

• Time tick interrupt

General Purpose Input/Output Ports

• 24 external interrupt ports

• 130 Multiplexed input/output ports

DMA Controller

• 4-ch DMA controller

• Supports memory to memory, IO to memory,

memory to IO, and IO to IO transfers

• Burst transfer mode to enhance the transfer rate

LCD Controller STN LCD Displays Feature

• Supports 3 types of STN LCD panels: 4-bit dual

scan, 4-bit single scan, 8-bit single scan display
type

• Supports monochrome mode, 4 gray levels, 16

gray levels, 256 colors and 4096 colors for STN
LCD

• Supports multiple screen size

– Typical actual screen size: 640x480, 320x240,
160x160, and others.
– Maximum frame buffer size is 4 Mbytes.
– Maximum virtual screen size in 256 color
mode: 4096x1024, 2048x2048, 1024x4096
and others

TFT(Thin Film Transistor) Color Displays Feature

• Supports 1, 2, 4 or 8 bpp (bit-per-pixel) palette

color displays for color TFT

• Supports 16, 24 bpp non-palette true-color

displays for color TFT

• Supports maximum 16M color TFT at 24 bpp mode

• LPC3600 Timing controller embedded for

LTS350Q1-PD1/2(SAMSUNG 3.5” Portrait / 256K­color/ Reflective a-Si TFT LCD)

• LCC3600 Timing controller embedded for

LTS350Q1-PE1/2(SAMSUNG 3.5” Portrait / 256K­color/ Transflective a-Si TFT LCD)

• Supports multiple screen size

– Typical actual screen size: 640x480, 320x240,
160x160, and others.
– Maximum frame buffer size is 4Mbytes.
– Maximum virtual screen size in 64K color
mode: 2048x1024, and others

UART

• 3-channel UART with DMA-based or interrupt-

based operation

• Supports 5-bit, 6-bit, 7-bit, or 8-bit serial data

transmit/receive (Tx/Rx)

• Supports external clocks for the UART operation

(UEXTCLK)

• Programmable baud rate

• Supports IrDA 1.0

• Loopback mode for testing

• Each channel has internal 64-byte Tx FIFO and

64-byte Rx FIFO.

1-3

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

FEATURES (Continued)

A/D Converter & Touch Screen Interface

• 8-ch multiplexed ADC

• Max. 500KSPS and 10-bit Resolution

• Internal FET for direct Touch screen interface

Watchdog Timer

• 16-bit Watchdog Timer

• Interrupt request or system reset at time-out

IIC-Bus Interface

• 1-ch Multi-Master IIC-Bus

• Serial, 8-bit oriented and bi-directional data

transfers can be made at up to 100 Kbit/s in
Standard mode or up to 400 Kbit/s in Fast mode.

IIS-Bus Interface

• 1-ch IIS-bus for audio interface with DMA-based

operation

• Serial, 8-/16-bit per channel data transfers

• 128 Bytes (64-Byte + 64-Byte) FIFO for Tx/Rx

• Supports IIS format and MSB-justified data format

AC97 Audio-CODEC Interface

• Support 16-bit samples

• 1-ch stereo PCM inputs/ 1-ch stereo PCM outputs

• DMA burst4 access support (only word transfer)

• Compatible with SD Memory Card Protocol version

1.0

• Compatible with SDIO Card Protocol version 1.0

• 64 Bytes FIFO for Tx/Rx

• Compatible with Multimedia Card Protocol version

2.11

SPI Interface

• Compatible with 2-ch Serial Peripheral Interface

Protocol version 2.11

• 2x8 bits Shift register for Tx/Rx

• DMA-based or interrupt-based operation

Camera Interface

• ITU-R BT 601/656 8-bit mode support

• DZI (Digital Zoom In) capability

• Programmable polarity of video sync signals

• Max. 4096 x 4096 pixels input support (2048 x

2048 pixel input support for scaling)

• Image mirror and rotation (X-axis mirror, Y-axis

mirror, and 180° rotation)

• Camera output format (RGB 16/24-bit and YCbCr

4:2:0/4:2:2 format)

1-ch MIC input

USB Host

• 2-port USB Host

• Complies with OHCI Rev. 1.0

• Compatible with USB Specification version 1.1

USB Device

• 1-port USB Device

• 5 Endpoints for USB Device

• Compatible with USB Specification version 1.1

SD Host Interface

• Normal, Interrupt and DMA data transfer mode

(byte, halfword, word transfer)

1-4

Operating Voltage Range

• Core: 1.20V for 300MHz

1.30V for 400MHz
Memory: 1.8V/ 2.5V/3.0V/3.3V

• I/O: 3.3V

Operating Frequency

• Fclk Up to 400MHz

• Hclk Up to 136MHz

• Pclk Up to 68MHz

Package

• 289-FBGA

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

BLOCK DIAGRAM

JTAG

ARM920T

Instruction

MMU

IVA[31:0]

ARM9TDMI

Processor core

(Internal Embedded ICE)

Data

MMU

LCD

CONT.

USB Host CONT.

NAND Ctrl.

NAND Flash Boot

C13

C13

ExtMaster

Loader

IPA[31:0]

DPA[31:0]

LCD

DMA

ID[31:0]

DD[31:0]

DVA[31:0]DVA[31:0]

InstructionC

ACHE

(16KB)

CP15

Data

CACHE

(16KB)

A
H
B

B
U
S

External

Coproc

Interface

Write

Buffer

WriteBack

PA Tag

RAM

BUS CONT.

Arbitor/Decode

Interrupt CONT.

Power

Management

Camera

Interface

Memory CONT.

SRAM/NOR/SDRAM

AMBA

Bus

I/F

WBPA[31:0]

Clock Generator

(MPLL)

Bridge & DMA (4Ch)

UART 0, 1, 2

USB Device

SDI/MMC

Watchdog

Timer

BUS CONT.

Arbitor/Decode Timer/PWM

SPI 0, 1

SPI

A
P
B

B
U
S

I2C

I2S

GPIO

RTC

ADC

0 ~ 3, 4(Internal)

AC97

Figure 1-1. S3C2440A Block Diagram

1-5

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

PIN ASSIGNMENTS

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

BOTTOM VIEW

Figure 1-2. S3C2440A Pin Assignments (289-FBGA)

1-6

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 1 of 3)

Pin

Number

Pin Name Pin

Number

Pin Name Pin

Number

Pin Name

A1 VDDi C1 VDDMOP E1 nFRE/GPA20
A2 SCKE C2 nGCS5/GPA16 E2 VSSMOP
A3 VSSi C3 nGCS2/GPA13 E3 nGCS7
A4 VSSi C4 nGCS3/GPA14 E4 nWAIT
A5 VSSMOP C5 nOE E5 nBE3
A6 VDDi C6 nSRAS E6 nWE
A7 VSSMOP C7 ADDR4 E7 ADDR1
A8 ADDR10 C8 ADDR11 E8 ADDR6

A9 VDDMOP C9 ADDR15 E9 ADDR14
A10 VDDi C10 ADDR21/GPA6 E10 ADDR23/GPA8
A11 VSSMOP C11 ADDR24/GPA9 E11 DATA2
A12 VSSi C12 DATA1 E12 DATA20
A13 DATA3 C13 DATA6 E13 DATA19
A14 DATA7 C14 DATA11 E14 DATA18
A15 VSSMOP C15 DATA13 E15 DATA17
A16 VDDi C16 DATA16 E16 DATA21
A17 DATA10 C17 VSSi E17 DATA24

B1 VSSMOP D1 ALE/GPA18 F1 VDDi

B2 nGCS1/GPA12 D2 nGCS6 F2 VSSi

B3 SCLK1 D3 nGCS4/GPA15 F3 nFWE/GPA19

B4 SCLK0 D4 nBE0 F4 nFCE/GPA22

B5 nBE1 D5 nBE2 F5 CLE/GPA17

B6 VDDMOP D6 nSCAS F6 nGCS0

B7 ADDR2 D7 ADDR7 F7 ADDR0/GPA0

B8 ADDR9 D8 ADDR5 F8 ADDR3

B9 ADDR12 D9 ADDR16/GPA1 F9 ADDR18/GPA3
B10 VSSi D10 ADDR20/GPA5 F10 DATA4
B11 VDDi D11 ADDR26/GPA11 F11 DATA5
B12 VDDMOP D12 DATA0 F12 DATA27
B13 VSSMOP D13 DATA8 F13 DATA31
B14 VDDMOP D14 DATA14 F14 DATA26
B15 DATA9 D15 DATA12 F15 DATA22
B16 VDDMOP D16 VSSMOP F16 VDDi
B17 DATA15 D17 VSSMOP F17 VDDMOP

1-7

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 2 of 3) (Continued)

Pin

Number

Pin Name Pin

Number

Pin Name Pin

Number

Pin Name

G1 VSSOP J1 VDDOP L1 LEND/GPC0
G2 CAMHREF/GPJ10 J2 VDDiarm L2 VDDiarm
G3 CAMDATA1/GPJ1 J3 CAMCLKOUT/GPJ11 L3 nXDACK0/GPB9
G4 VDDalive J4 CAMRESET/GPJ12 L4 VCLK/GPC1
G5 CAMPCLK/GPJ8 J5 TOUT1/GPB1 L5 nXBREQ/GPB6
G6 FRnB J6 TOUT0/GPB0 L6 VD1/GPC9
G7 CAMVSYNC/GPJ9 J7 TOUT2/GPB2 L7 VFRAME/GPC3
G8 ADDR8 J8 CAMDATA6/GPJ6 L8 I2SSDI/AC_SDATA_IN

G9 ADDR17/GPA2 J9 SDDAT3/GPE10 L9 SPICLK0/GPE13
G10 ADDR25/GPA10 J10 EINT10/nSS0/GPG2 L10 EINT15/SPICLK1/GPG7
G11 DATA28 J11 TXD2/nRTS1/GPH6 L11 EINT22/GPG14
G12 DATA25 J12 PWREN L12 Xtortc
G13 DATA23 J13 TCK L13 EINT2/GPF2
G14 XTIpll J14 TMS L14 EINT5/GPF5
G15 XTOpll J15 RXD2/nCTS1/GPH7 L15 EINT6/GPF6
G16 DATA29 J16 TDO L16 EINT7/GPF7
G17 VSSi J17 VDDalive L17 nRTS0/GPH1

H1 VSSiarm K1 VSSiarm M1 VLINE/GPC2

H2 CAMDATA7/GPJ7 K2 nXBACK/GPB5 M2 LCD_LPCREV/GPC6

H3 CAMDATA4/GPJ4 K3 TOUT3/GPB3 M3 LCD_LPCOE/GPC5

H4 CAMDATA3/GPJ3 K4 TCLK0/GPB4 M4 VM/GPC4

H5 CAMDATA2/GPJ2 K5 nXDREQ1/GPB8 M5 VD9/GPD1

H6 CAMDATA0/GPJ0 K6 nXDREQ0/GPB10 M6 VD6/GPC14

H7 CAMDATA5/GPJ5 K7 nXDACK1/GPB7 M7 VD16/SPIMISO1/GPD8

H8 ADDR13 K8 SDCMD/GPE6 M8 SDDAT1/GPE8

H9 ADDR19/GPA4 K9 SPIMISO0/GPE11 M9 IICSDA/GPE15

H10 ADDR22/GPA7 K10 EINT13/SPIMISO1/GPG5 M10 EINT20/GPG12
H11 VSSOP K11 nCTS0/GPH0 M11 EINT17/nRTS1/GPG9
H12 EXTCLK K12 VDDOP M12 VSSA_UPLL
H13 DATA30 K13 TXD0/GPH2 M13 VDDA_UPLL
H14 nBATT_FLT K14 RXD0/GPH3 M14 Xtirtc
H15 nTRST K15 UEXTCLK/GPH8 M15 EINT3/GPF3
H16 nRESET K16 TXD1/GPH4 M16 EINT1/GPF1
H17 TDI K17 RXD1/GPH5 M17 EINT4/GPF4

1-8

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-1. 289-Pin FBGA Pin Assignments – Pin Number Order (Sheet 3 of 3) (Continued)

Pin

Number

Pin Name Pin

Number

Pin Name Pin

Number

Pin Name

N1 VSSOP P15 AIN3 T12 VDDOP
N2 VD0/GPC8 P16 XP/AIN7 T13 OM3
N3 VD4/GPC12 P17 UPLLCAP T14 VSSA_ADC
N4 VD2/GPC10 R1 VD3/GPC11 T15 OM0
N5 VD10/GPD2 R2 VD8/GPD0 T16 YM/AIN4
N6 VD15/GPD7 R3 VD11/GPD3 T17 YP/AIN5
N7 VD22/nSS1/GPD14 R4 VD13/GPD5 U1 VDDiarm
N8 SDCLK/GPE5 R5 VD18/SPICLK1/GPD10 U2 VDDiarm

N9 EINT8/GPG0 R6 VD21 /GPD13 U3 VSSOP
N10 EINT18/nCTS1/GPG10 R7 I2SSCLK/AC_BIT_CLK U4 VSSiarm
N11 DP0 R8 SDDAT0/GPE7 U5 VD23/nSS0/GPD15
N12 DN1/PDN0 R9 CLKOUT0/GPH9 U6 I2SSDO/AC_SDATA_

OUT

N13 nRSTOUT/GPA21 R10 EINT11/nSS1/GPG3 U7 VSSiarm
N14 MPLLCAP R11 EINT14/SPIMOSI1/GPG6 U8 IICSCL/GPE14
N15 VDD_RTC R12 NCON U9 VSSOP
N16 VDDA_MPLL R13 OM1 U10 VSSiarm
N17 EINT0/GPF0 R14 AIN0 U11 VDDi

P1 LCD_LPCREVB/GPC7 R15 AIN2 U12 EINT19/TCLK1/GPG11

P2 VD5/GPC13 R16 XM/AIN6 U13 EINT23/GPG15

P3 VD7/GPC15 R17 VSSA_MPLL U14 DP1/PDP0

P4 VD12/GPD4 T1 VSSiarm U15 VSSOP

P5 VD14/GPD6 T2 VSSiarm U16 Vref

P6 VD20/GPD12 T3 VDDOP U17 AIN1

P7 I2SLRCK/AC_SYNC T4 VD17/SPIMOSI1/GPD9

P8 SDDAT2/GPE9 T5 VD19/GPD11

P9 SPIMOSI0/GPE12 T6 VDDiarm
P10 CLKOUT1/GPH10 T7 CDCLK/AC_nRESET
P11 EINT12/LCD_PWREN/

GPG4

T8 VDDiarm

P12 DN0 T9 EINT9/GPG1
P13 OM2 T10 EINT16/GPG8
P14 VDDA_ADC T11 EINT21/GPG13

1-9

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 1 of 9)

Pin

Number

Pin

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

F7 ADDR0/GPA0 ADDR0 Hi-z/– O(L)/– O(L) t10s
E7 ADDR1 ADDR1 Hi-z O(L) O(L) t10s
B7 ADDR2 ADDR2 Hi-z O(L) O(L) t10s

F8 ADDR3 ADDR3 Hi-z O(L) O(L) t10s
C7 ADDR4 ADDR4 Hi-z O(L) O(L) t10s
D8 ADDR5 ADDR5 Hi-z O(L) O(L) t10s
E8 ADDR6 ADDR6 Hi-z O(L) O(L) t10s
D7 ADDR7 ADDR7 Hi-z O(L) O(L) t10s
G8 ADDR8 ADDR8 Hi-z O(L) O(L) t10s
B8 ADDR9 ADDR9 Hi-z O(L) O(L) t10s
A8 ADDR10 ADDR10 Hi-z O(L) O(L) t10s
C8 ADDR11 ADDR11 Hi-z O(L) O(L) t10s
B9 ADDR12 ADDR12 Hi-z O(L) O(L) t10s
H8 ADDR13 ADDR13 Hi-z O(L) O(L) t10s
E9 ADDR14 ADDR14 Hi-z O(L) O(L) t10s
C9 ADDR15 ADDR15 Hi-z O(L) O(L) t10s

I/O

Type

D9 ADDR16/GPA1 ADDR16 Hi-z/– O(L)/– O(L) t10s
G9 ADDR17/GPA2 ADDR17 Hi-z/– O(L)/– O(L) t10s

F9 ADDR18/GPA3 ADDR18 Hi-z/– O(L)/– O(L) t10s
H9 ADDR19/GPA4 ADDR19 Hi-z/– O(L)/– O(L) t10s

D10 ADDR20/GPA5 ADDR20 Hi-z/– O(L)/– O(L) t10s
C10 ADDR21/GPA6 ADDR21 Hi-z/– O(L)/– O(L) t10s
H10 ADDR22/GPA7 ADDR22 Hi-z/– O(L)/– O(L) t10s
E10 ADDR23/GPA8 ADDR23 Hi-z/– O(L)/– O(L) t10s
C11 ADDR24/GPA9 ADDR24 Hi-z/– O(L)/– O(L) t10s

G10 ADDR25/GPA10 ADDR25 Hi-z/– O(L)/– O(L) t10s

D11 ADDR26/GPA11 ADDR26 Hi-z/– O(L)/– O(L) t10s
R14 AIN0 AIN0 – – AI r10
U17 AIN1 AIN1 – – AI r10
R15 AIN2 AIN2 – – AI r10
P15 AIN3 AIN3 – – AI r10

T16 YM/AIN4 AIN4 –/– –/– AI r10
T17 YP/AIN5 YP –/– –/– AI r10

R16 XM/AIN6 AIN6 –/– –/– AI r10

1-10

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 2 of 9) (Continued)

Pin

Number

Pin

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

P16 XP/AIN7 XP –/– –/– AI r10

H6 CAMDATA0/GPJ0 GPJ0 –/– Hi-z/– I t8
G3 CAMDATA1/GPJ1 GPJ1 –/– Hi-z/– I t8
H5 CAMDATA2/GPJ2 GPJ2 –/– Hi-z/– I t8
H4 CAMDATA3/GPJ3 GPJ3 –/– Hi-z/– I t8
H3 CAMDATA4/GPJ4 GPJ4 –/– Hi-z/– I t8
H7 CAMDATA5/GPJ5 GPJ5 –/– Hi-z/– I t8

J8 CAMDATA6/GPJ6 GPJ6 –/– Hi-z/– I t8
H2 CAMDATA7/GPJ7 GPJ7 –/– Hi-z/– I t8
G5 CAMPCLK/GPJ8 GPJ8 –/– Hi-z/– I t8
G7 CAMVSYNC/GPJ9 GPJ9 –/– Hi-z/– I t8
G2 CAMHREF/GPJ10 GPJ10 –/– Hi-z/– I t8

J3 CAMCLKOUT/GPJ11 GPJ11 –/– O(L)/– I t8

J4 CAMRESET/GPJ12 GPJ12 –/– O(L)/– I t8

D12 DATA0 DATA0 Hi-z Hi-z,O(L) I b12s
C12 DATA1 DATA1 Hi-z Hi-z,O(L) I b12s

I/O

Type

E11 DATA2 DATA2 Hi-z Hi-z,O(L) I b12s
A13 DATA3 DATA3 Hi-z Hi-z,O(L) I b12s
F10 DATA4 DATA4 Hi-z Hi-z,O(L) I b12s
F11 DATA5 DATA5 Hi-z Hi-z,O(L) I b12s
C13 DATA6 DATA6 Hi-z Hi-z,O(L) I b12s
A14 DATA7 DATA7 Hi-z Hi-z,O(L) I b12s
D13 DATA8 DATA8 Hi-z Hi-z,O(L) I b12s
B15 DATA9 DATA9 Hi-z Hi-z,O(L) I b12s
A17 DATA10 DATA10 Hi-z Hi-z,O(L) I b12s
C14 DATA11 DATA11 Hi-z Hi-z,O(L) I b12s
D15 DATA12 DATA12 Hi-z Hi-z,O(L) I b12s
C15 DATA13 DATA13 Hi-z Hi-z,O(L) I b12s
D14 DATA14 DATA14 Hi-z Hi-z,O(L) I b12s
B17 DATA15 DATA15 Hi-z Hi-z,O(L) I b12s
C16 DATA16 DATA16 Hi-z Hi-z,O(L) I b12s
E15 DATA17 DATA17 Hi-z Hi-z,O(L) I b12s
E14 DATA18 DATA18 Hi-z Hi-z,O(L) I b12s

1-11

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 3 of 9) (Continued)

Pin

Number

Pin

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

E13 DATA19 DATA19 Hi-z Hi-z,O(L) I b12s
E12 DATA20 DATA20 Hi-z Hi-z,O(L) I b12s
E16 DATA21 DATA21 Hi-z Hi-z,O(L) I b12s
F15 DATA22 DATA22 Hi-z Hi-z,O(L) I b12s

G13 DATA23 DATA23 Hi-z Hi-z,O(L) I b12s

E17 DATA24 DATA24 Hi-z Hi-z,O(L) I b12s

G12 DATA25 DATA25 Hi-z Hi-z,O(L) I b12s

F14 DATA26 DATA26 Hi-z Hi-z,O(L) I b12s

F12 DATA27 DATA27 Hi-z Hi-z,O(L) I b12s
G11 DATA28 DATA28 Hi-z Hi-z,O(L) I b12s
G16 DATA29 DATA29 Hi-z Hi-z,O(L) I b12s

H13 DATA30 DATA30 Hi-z Hi-z,O(L) I b12s

F13 DATA31 DATA31 Hi-z Hi-z,O(L) I b12s

P12 DN0 DN0 – – AI us

N11 DP0 DP0 – – AI us

N12 DN1/PDN0 DN1 –/– – AI us

I/O

Type

U14 DP1/PDP0 DP1 –/– – AI us

N17 EINT0/GPF0 GPF0 –/– Hi-z/– I t8
M16 EINT1/GPF1 GPF1 –/– Hi-z/– I t8

L13 EINT2/GPF2 GPF2 –/– Hi-z/– I t8
M15 EINT3/GPF3 GPF3 –/– Hi-z/– I t8
M17 EINT4/GPF4 GPF4 –/– Hi-z/– I t8

L14 EINT5/GPF5 GPF5 –/– Hi-z/– I t8

L15 EINT6/GPF6 GPF6 –/– Hi-z/– I t8

L16 EINT7/GPF7 GPF7 –/– Hi-z/– I t8

N9 EINT8/GPG0 GPG0 –/– Hi-z/– I t8

T9 EINT9/GPG1 GPG1 –/– Hi-z/– I t8

J10 EINT10/nSS0/GPG2 GPG2 –/–/– Hi-z/Hi-z/– I t8

R10 EINT11/nSS1/GPG3 GPG3 –/–/– Hi-z/Hi-z/– I t8
P11 EINT12/LCD_PWREN/GPG

GPG4 –/–/– Hi-z/O(L)/– I t8

4
K10 EINT13/SPIMISO1/GPG5 GPG5 –/–/– Hi-z/Hi-z/– I t8
R11 EINT14/SPIMOSI1/GPG6 GPG6 –/–/– Hi-z/Hi-z/– I t8

L10 EINT15/SPICLK1/GPG7 GPG7 –/–/– Hi-z/Hi-z/– I t8

1-12

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 4 of 9) (Continued)

Pin

Number

Pin

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

T10 EINT16/GPG8 GPG8 –/– Hi-z/– I t8

M11 EINT17/nRTS1/GPG9 GPG9 –/–/– Hi-z/O(H)/– I t8

N10 EINT18/nCTS1/GPG10 GPG10 –/–/– Hi-z/Hi-z/– I t8
U12 EINT19/TCLK1/GPG11 GPG11 –/–/– Hi-z/Hi-z/– I t12

M10 EINT20/GPG12 GPG12 –/– Hi-z/– I t12

T11 EINT21/GPG13 GPG13 –/– Hi-z/– I t12

L11 EINT22/GPG14 GPG14 –/– Hi-z/– I t12
U13 EINT23/GPG15 GPG15 –/– Hi-z/– I t12
H12 EXTCLK EXTCLK – – AI is
P17 UPLLCAP UPLLCAP – – AI r50
N14 MPLLCAP MPLLCAP – – AI r50
H14 nBATT_FLT nBATT_FLT – – I is

D4 nBE0 nBE0 Hi-z Hi-z,O(H) O(H) t10s
B5 nBE1 nBE1 Hi-z Hi-z,O(H) O(H) t10s
D5 nBE2 nBE2 Hi-z Hi-z,O(H) O(H) t10s
E5 nBE3 nBE3 Hi-z Hi-z,O(H) O(H) t10s

I/O

Type

R12 NCON NCON – – I is

G6 FRnB FRnB – Hi-z,O(L) I d2s

F3 nFWE/GPA19 GPA19 O(H)/– Hi-z,O(H)/– O(H) t10s

E1 nFRE/GPA20 GPA20 O(H)/– Hi-z,O(H)/– O(H) t10s

F4 nFCE/GPA22 GPA21 O(H)/– Hi-z,O(H)/– O(H) t10s
F5 CLE/GPA17 GPA17 O(L)/– Hi-z,O(L)/– O(L) t10s

D1 ALE/GPA18 GPA18 O(L)/– Hi-z,O(L)/– O(L) t10s

N13 nRSTOUT/GPA21 GPA21 –/– O(L)/– O(L) b8

C5 nOE nOE Hi-z Hi-z,O(H) O(H) t10s

H16 nRESET nRESET – – I is

F6 nGCS0 nGCS0 Hi-z Hi-z,O(H) O(H) t10s
B2 nGCS1/GPA12 GPA12 Hi-z/– Hi-z,O(H)/– O(H) t10s
C3 nGCS2/GPA13 GPA13 Hi-z/– Hi-z,O(H)/– O(H) t10s
C4 nGCS3/GPA14 GPA14 Hi-z/– Hi-z,O(H)/– O(H) t10s
D3 nGCS4/GPA15 GPA15 Hi-z/– Hi-z,O(H)/– O(H) t10s
C2 nGCS5/GPA16 GPA16 Hi-z/– Hi-z,O(H)/– O(H) t10s
D2 nGCS6 nGCS6 Hi-z Hi-z,O(H) O(H) t10s

1-13

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 5 of 9) (Continued)

Pin

Number

Pin

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

E3 nGCS7 nGCS7 Hi-z Hi-z,O(H) O(H) t10s
D6 nSCAS nSCAS Hi-z Hi-z,O(H) O(H) t10s
C6 nSRAS nSRAS Hi-z Hi-z,O(H) O(H) t10s

H15 nTRST nTRST I – I is

E4 nWAIT nWAIT – Hi-z,O(L) I d2s
E6 nWE nWE Hi-z Hi-z,O(H) O(H) t10s

J6 TOUT0/GPB0 GPB0 –/– O(L)/– I t8
J5 TOUT1/GPB1 GPB1 –/– O(L)/– I t8

J7 TOUT2/GPB2 GPB2 –/– O(L)/– I t8
K3 TOUT3/GPB3 GPB3 –/– O(L)/– I t8
K4 TCLK0/GPB4 GPB4 –/– –/– I t8
K2 nXBACK/GPB5 GPB5 –/– O(H)/– I t8

L5 nXBREQ/GPB6 GPB6 –/– –/– I t8
K7 nXDACK1/GPB7 GPB7 –/– O(H)/– I t8
K5 nXDREQ1/GPB8 GPB8 –/– –/– I t8

L3 nXDACK0/GPB9 GPB9 –/– O(H)/– I t8

I/O

Type

K6 nXDREQ0/GPB10 GPB10 –/– –/– I t8

T15 OM0 OM0 – – I is
R13 OM1 OM1 – – I is
P13 OM2 OM2 – – I is

T13 OM3 OM3 – – I is

J12 PWREN PWREN O(H) O(L) O(H) b8
K11 nCTS0/GPH0 GPH0 –/– –/– I t8

L17 nRTS0/GPH1 GPH1 –/– O(H)/– I t8
K13 TXD0/GPH2 GPH2 –/– O(H)/– I t8
K14 RXD0/GPH3 GPH3 –/– –/– I t8
K16 TXD1/GPH4 GPH4 –/– O(H)/– I t8
K17 RXD1/GPH5 GPH5 –/– –/– I t8

J11 TXD2/nRTS1/GPH6 GPH6 –/–/– O(H)/O(H)/– I t8

J15 RXD2/nCTS1/GPH7 GPH7 –/–/– Hi-z/Hi-z/– I t8
K15 UEXTCLK/GPH8 GPH8 –/– Hi-z/– I t8

R9 CLKOUT0/GPH9 GPH9 –/– O(L)/– I t12

P10 CLKOUT1/GPH10 GPH10 –/– O(L)/– I t12

1-14

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 6 of 9) (Continued)

Pin

Number

Pin

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

A2 SCKE SCKE Hi-z O(L) O(H) t10s
B4 SCLK0 SCLK0 Hi-z O(L) O(SCLK) t12s
B3 SCLK1 SCLK1 Hi-z O(L) O(SCLK) t12s
P7 I2SLRCK/AC_SYNC GPE0 –/– Hi-z/– I t8
R7 I2SSCLK/AC_BIT_CLK GPE1 –/– Hi-z/– I t8

T7 CDCLK/AC_nRESET GPE2 –/– Hi-z/– I t8

L8 I2SSDI/AC_SDATA_IN GPE3 –/–/– Hi-z/Hi-z/– I t8
U6 I2SSDO/AC_SDATA_OUT GPE4 –/–/– O(L)/Hi-z/– I t8
N8 SDCLK/GPE5 GPE5 –/– O(L)/– I t8
K8 SDCMD/GPE6 GPE6 –/– Hi-z/– I t8
R8 SDDAT0/GPE7 GPE7 –/– Hi-z/– I t8

M8 SDDAT1/GPE8 GPE8 –/– Hi-z/– I t8

P8 SDDAT2/GPE9 GPE9 –/– Hi-z/– I t8

J9 SDDAT3/GPE10 GPE10 –/– Hi-z/– I t8
K9 SPIMISO0/GPE11 GPE11 –/– Hi-z/– I t8
P9 SPIMOSI0/GPE12 GPE12 –/– Hi-z/– I t8

I/O

Type

L9 SPICLK0/GPE13 GPE13 –/– Hi-z/– I t8

U8 IICSCL/GPE14 GPE14 –/– Hi-z/– I d8

M9 IICSDA/GPE15 GPE15 –/– Hi-z/– I d8

J13 TCK TCK I – I is

H17 TDI TDI I – I is

J16 TDO TDO O O O ot
J14 TMS TMS I – I is

L1 LEND/GPC0 GPC0 –/– O(L)/– I t8
L4 VCLK/GPC1 GPC1 –/– O(L)/– I t8

M1 VLINE/GPC2 GPC2 –/– O(L)/– I t8

L7 VFRAME/GPC3 GPC3 –/– O(L)/– I t8
M4 VM/GPC4 GPC4 –/– O(L)/– I t8
M3 LCD_LPCOE/GPC5 GPC5 –/– O(L)/– I t8
M2 LCD_LPCREV/GPC6 GPC6 –/– O(L)/– I t8

P1 LCD_LPCREVB/GPC7 GPC7 –/– O(L)/– I t8
N2 VD0/GPC8 GPC8 –/– O(L)/– I t8

L6 VD1/GPC9 GPC9 –/– O(L)/– I t8

1-15

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 7 of 9) (Continued)

Pin

Number

Pin

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

N4 VD2/GPC10 GPC10 –/– O(L)/– I t8
R1 VD3/GPC11 GPC11 –/– O(L)/– I t8
N3 VD4/GPC12 GPC12 –/– O(L)/– I t8
P2 VD5/GPC13 GPC13 –/– O(L)/– I t8

M6 VD6/GPC14 GPC14 –/– O(L)/– I t8

P3 VD7/GPC15 GPC15 –/– O(L)/– I t8
R2 VD8/GPD0 GPD0 –/– O(L)/– I t8

M5 VD9/GPD1 GPD1 –/– O(L)/– I t8

N5 VD10/GPD2 GPD2 –/– O(L)/– I t8
R3 VD11/GPD3 GPD3 –/– O(L)/– I t8
P4 VD12/GPD4 GPD4 –/– O(L)/– I t8
R4 VD13/ GPD5 GPD5 –/–/– O(L)/O/– I t8
P5 VD14/GPD6 GPD6 –/–/– O(L)/O/– I t8
N6 VD15/GPD7 GPD7 –/–/– O(L)/O/– I t8

M7 VD16/SPIMISO1/GPD8 GPD8 –/–/– O(L)/Hi-z/– I t8

T4 VD17/SPIMOSI1/GPD9 GPD9 –/–/– O(L)/Hi-z/– I t8

I/O

Type

R5 VD18/SPICLK1/GPD10 GPD10 –/–/– O(L)/Hi-z/– I t8

T5 VD19//GPD11 GPD11 –/–/– O(L)/Hi-z/– I t8
P6 VD20/ GPD12 GPD12 –/–/– O(L)/Hi-z/– I t8
R6 VD21/ GPD13 GPD13 –/–/– O(L)/Hi-z/– I t8
N7 VD22/nSS1/GPD14 GPD14 –/–/– O(L)/Hi-z/– I t8
U5 VD23/nSS0/GPD15 GPD15 –/–/– O(L)/Hi-z/– I t8

U16 Vref Vref – – AI ia
G14 XTIpll XTIpll – – AI m26
M14 Xtirtc Xtirtc – – AI nc
G15 XTOpll XTOpll – – AO m26

L12 Xtortc Xtortc – – AO nc
N15 VDD_RTC VDD_RTC P P P drtc
P14 VDDA_ADC VDDA_ADC P P P d33th
N16 VDDA_MPLL VDDA_MPLL P P P d12t

M13 VDDA_UPLL VDDA_UPLL P P P d12t

G4 VDDalive VDDalive P P P d12i

J17 VDDalive VDDalive P P P d12i

1-16

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 8 of 9) (Continued)

Pin

Number

Pin

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

A1 VDDi VDDi P P P d12c
A10 VDDi VDDi P P P d12c
A16 VDDi VDDi P P P d12c

A6 VDDi VDDi P P P d12c
B11 VDDi VDDi P P P d12c

F1 VDDi VDDi P P P d12c
F16 VDDi VDDi P P P d12c
U11 VDDi VDDi P P P d12c

L2 VDDiarm VDDiarm P P P d12c

T6 VDDiarm VDDiarm P P P d12c

T8 VDDiarm VDDiarm P P P d12c

U1 VDDiarm VDDiarm P P P d12c

J2 VDDiarm VDDiarm P P P d12c
U2 VDDiarm VDDiarm P P P d12c
A9 VDDMOP VDDMOP P P P d33o

B12 VDDMOP VDDMOP P P P d33o

I/O

Type

B14 VDDMOP VDDMOP P P P d33o
B16 VDDMOP VDDMOP P P P d33o

B6 VDDMOP VDDMOP P P P d33o
C1 VDDMOP VDDMOP P P P d33o

F17 VDDMOP VDDMOP P P P d33o

J1 VDDOP VDDOP P P P d33o

T12 VDDOP VDDOP P P P d33o

T3 VDDOP VDDOP P P P d33o

K12 VDDOP VDDOP P P P d33o

T14 VSSA_ADC VSSA_ADC P P P sth

R17 VSSA_MPLL VSSA_MPLL P P P st

M12 VSSA_UPLL VSSA_UPLL P P P st

A12 VSSi VSSi P P P si

A3 VSSi VSSi P P P si
A4 VSSi VSSi P P P si

B10 VSSi VSSi P P P si
C17 VSSi VSSi P P P si

1-17

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-2. S3C2440A 289-Pin FBGA Pin Assignments (Sheet 9 of 9) (Continued)

Pin

Number

Pin

Name

Default

Function

I/O State

@BUS REQ

I/O State

@Sleep

I/O State

@nRESET

F2 VSSi VSSi P P P si

G17 VSSi VSSi P P P si

H1 VSSiarm VSSiarm P P P si
K1 VSSiarm VSSiarm P P P si

T1 VSSiarm VSSiarm P P P si
T2 VSSiarm VSSiarm P P P si

U10 VSSiarm VSSiarm P P P si

U4 VSSiarm VSSiarm P P P si

U7 VSSiarm VSSiarm P P P si
A11 VSSMOP VSSMOP P P P so
A15 VSSMOP VSSMOP P P P so

A5 VSSMOP VSSMOP P P P so

A7 VSSMOP VSSMOP P P P so

B1 VSSMOP VSSMOP P P P so
B13 VSSMOP VSSMOP P P P so
D16 VSSMOP VSSMOP P P P so

I/O

Type

D17 VSSMOP VSSMOP P P P so

E2 VSSMOP VSSMOP P P P so

G1 VSSOP VSSOP P P P so

N1 VSSOP VSSOP P P P so
U15 VSSOP VSSOP P P P so

U3 VSSOP VSSOP P P P so

U9 VSSOP VSSOP P P P so
H11 VSSOP VSSOP P P P so

NOTES:

1. The @BUS REQ. shows the pin state at the external bus, which is used by the other bus master.

2. ' – ‘ mark indicates the unchanged pin state at Bus Request mode.

3. Hi-z or Pre means Hi-z or early state and it is determined by the setting of MISCCR register.

4. AI/AO means analog input/analog output.

5. P, I, and O mean power, input and output respectively.

6. The I/O state @nRESET shows the pin status in the @nRESET duration below.

@nRESET4 OSCin

nRESET

1-18

FCLK

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

The table below shows I/O types and descriptions.

Input (I)/Output (O) Type Descriptions

d12i(vdd12ih) 1.2V VDD for alive power
d12c(vdd12ih_core), si(vssih) 1.2V VDD/VSS for internal logic
d33o(vdd33oph), so(vssoph) 3.3V VDD/VSS for external logic
d33th(vdd33th_abb),sth(vssbbh_abb) 3.3V VDD/VSS for analog circuitry
d12t(vdd12t_abb), st(vssbb_abb) 1.2V VDD/VSS for analog circuitry
drtc(vdd30th_rtc) 3.0V VDD for RTC power
t8(phbsu100ct8sm) Bi-directional pad, LVCMOS schmitt-trigger, 100k Ω pull-up resistor with

control, tri-state, Io = 8mA
is(phis) Input pad, LVCMOS schmitt-trigger level
us(pbusb0) USB pad
t10(phtot10cd) 5V tolerant output pad, tri-state.
ot(phot8) Output pad, tri-state, Io = 8mA
b8(phob8) Output pad, Io = 8mA
t16(phot16sm) Output pad, tri-state, medium slew rate, Io = 16mA
r10(phiar10_abb) Analog input pad with 10Ω resistor
ia(phia_abb) Analog input pad
gp(phgpad_option) Pad for analog pin
m26(phsoscm26_2440a) Oscillator cell with enable and feedback resistor
t12(phbsu100ct12sm) Bi-directional pad, LVCMOS schmitt-trigger, 100k Ω pull-up resistor with

control, tri-state, Io = 12mA
d8(phbsd8sm) Bi-directional pad, LVCMOS schmitt-trigger, open drain, Io = 8mA
t10s(phtot10cd_10_2440a) output pad, LVCMOS, tri -state, output drive strenth control, Io = 4, 6, 8,

10mA
b12s(phtbsu100ct12cd_12_2440a) Bi-directional pad, LVCMOS schmitt-trigger, 100k Ω pull-up resistor with

control, tri -state,output drive strenth control, Io = 6, 8, 10, 12mA
d2s(phtbsd2_2440a) Bi-directional pad, LVCMOS schmitt-trigger, open-drain, output drive

strenth ignore,
r50(phoar50_abb) Analog output pad, 50k Ω resistor, separated bulk-bias
t12s(phtot12cd_12_2440a) output pad, LVCMOS, tri -state, output drive strenth control, Io = 6, 8,

10, 12mA
nc(phnc) No connection pad

1-19

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

SIGNAL DESCRIPTIONS

Table 1-3. S3C2440A Signal Descriptions (Sheet 1 of 6)

Signal Input/Output Descriptions

Bus Controller

OM[1:0] I OM[1:0] sets S3C2440A in the TEST mode, which is used only at fabrication.

Also, it determines the bus width of nGCS0. The pull-up/down resistor
determines the logic level during RESET cycle.

00: Nand-boot 01: 16-bit 10: 32-bit 11: Test mode

ADDR[26:0] O ADDR[26:0] (Address Bus) outputs the memory address of the corresponding

bank .

DATA[31:0] IO DATA[31:0] (Data Bus) inputs data during memory read and outputs data during

memory write. The bus width is programmable among 8/16/32-bit.

nGCS[7:0] O nGCS[7:0] (General Chip Select) are activated when the address of a memory is

within the address region of each bank. The number of access cycles and the

bank size can be programmed.
nWE O nWE (Write Enable) indicates that the current bus cycle is a write cycle.
nOE O nOE (Output Enable) indicates that the current bus cycle is a read cycle.
nXBREQ I nXBREQ (Bus Hold Request) allows another bus master to request control of the

local bus. BACK active indicates that bus control has been granted.
nXBACK O nXBACK (Bus Hold Acknowledge) indicates that the S3C2440A has surrendered

control of the local bus to another bus master.
nWAIT I nWAIT requests to prolong a current bus cycle. As long as nWAIT is L, the

current bus cycle cannot be completed.

SDRAM/SRAM

nSRAS O SDRAM row address strobe
nSCAS O SDRAM column address strobe
nSCS[1:0] O SDRAM chip select
DQM[3:0] O SDRAM data mask
SCLK[1:0] O SDRAM clock
SCKE O SDRAM clock enable
nBE[3:0] O Upper byte/lower byte enable (In case of 16-bit SRAM)
nWBE[3:0] O Write byte enable

NAND Flash

CLE O Command latch enable
ALE O Address latch enable
nFCE O Nand flash chip enable
nFRE O Nand flash read enable
nFWE O Nand flash write enable
NCON I Nand flash configuration * If NAND flash controller isn’t used, it

has to be pull-up. (VDDMOP)

FRnB I Nand flash ready/busy

1-20

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-3. S3C2440A Signal Descriptions (Sheet 2 of 6) (Continued)

Signal Input/

Descriptions

Output

LCD Control Unit

VD[23:0] O STN/TFT/SEC TFT: LCD data bus
LCD_PWREN O STN/TFT/SEC TFT: LCD panel power enable control signal
VCLK O STN/TFT: LCD clock signal
VFRAME O STN: LCD frame signal
VLINE O STN: LCD line signal
VM O STN: VM alternates the polarity of the row and column voltage
VSYNC O TFT: Vertical synchronous signal
HSYNC O TFT: Horizontal synchronous signal
VDEN O TFT: Data enable signal
LEND O TFT: Line end signal
STV O SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal
CPV O SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal
LCD_HCLK O SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal
TP O SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal
STH O SEC TFT: SEC(Samsung Electronics Company) TFT LCD panel control signal
LCD_LPCOE O SEC TFT: Timing control signal for specific TFT LCD
LCD_LPCREV O SEC TFT: Timing control signal for specific TFT LCD
LCD_LPCREVB O SEC TFT: Timing control signal for specific TFT LCD

CAMERA Interface

CAMRESET O Software reset to the camera
CAMCLKOUT O Master clock to the camera
CAMPCLK I Pixel clock from camera
CAMHREF I Horizontal sync signal from camera
CAMVSYNC I Vertical sync signal from camera
CAMDATA[7:0] I Pixel data for YCbCr

Interrupt Control Unit

EINT[23:0] I External interrupt request

DMA

nXDREQ[1:0] I External DMA request
nXDACK[1:0] O External DMA acknowledge

1-21

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-3. S3C2440A Signal Descriptions (Sheet 3 of 6) (Continued)

Signal Input/Output Descriptions

UART

RxD[2:0] I UART receives data input
TxD[2:0] O UART transmits data output
nCTS[1:0] I UART clear to send input signal
nRTS[1:0] O UART request to send output signal
UEXTCLK I External clock input for UART

ADC

AIN[7:0] AI ADC input[7:0]. If it isn’t used pin, it has to be low (ground).
Vref AI ADC Vref

IIC-Bus

IICSDA IO IIC-bus data
IICSCL IO IIC-bus clock

IIS-Bus

I2SLRCK IO IIS-bus channel select clock
I2SSDO O IIS-bus serial data output
I2SSDI I IIS-bus serial data input
I2SSCLK IO IIS-bus serial clock
CDCLK O CODEC system clock

AC’97

AC_SYNC 48kHz fixed rate sample sync
AC_BIT_CLK IO 12.288MHz serial data clock
AC_nRESET O AC’97 Master H/W Reset
AC_SDATA_IN I Serial, time division multiplexed, AC’97 input stream
AC_SDATA_OUT O Serial, time division multiplexed, AC’97 output stream

Touch Screen

nXPON O Plus X-axis on-off control signal
XMON O Minus X-axis on-off control signal
nYPON O Plus Y-axis on-off control signal
YMON O Minus Y-axis on-off control signal

USB Host

DN[1:0] IO DATA(–) from USB host. (Need to 15k Ω pull-down)
DP[1:0] IO DATA(+) from USB host. (Need to 15k Ω pull-down)

USB Device

PDN0 IO DATA(–) for USB peripheral.

(Need to 470k Ω pull-down for power consumption in sleep mode)

PDP0 IO DATA(+) for USB peripheral. (Need to 1.5k Ω pull-up)

1-22

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-3. S3C2440A Signal Descriptions (Sheet 4 of 6) (Continued)

Signal Input/Output Description

SPI

SPIMISO[1:0] IO SPIMISO is the master data input line, when SPI is configured as a master.

When SPI is configured as a slave, these pins reverse its role.

SPIMOSI[1:0] IO SPIMOSI is the master data output line, when SPI is configured as a master.

When SPI is configured as a slave, these pins reverse its role.
SPICLK[1:0] IO SPI clock
nSS[1:0] I SPI chip select(only for slave mode)

SD

SDDAT[3:0] IO SD receive/transmit data
SDCMD IO SD receive response/ transmit command
SDCLK O SD clock

General Port

GPn[129:0] IO General input/output ports (some ports are output only)

TIMMER/PWM

TOUT[3:0] O Timer output[3:0]
TCLK[1:0] I External timer clock input

JTAG TEST LOGIC

nTRST I nTRST (TAP Controller Reset) resets the TAP controller at start.

If debugger is used, A 10K pull-up resistor has to be connected.

If debugger (black ICE) is not used, nTRST pin must be issued by a low active

pulse (Typically connected to nRESET).
TMS I TMS (TAP Controller Mode Select) controls the sequence of the TAP controller's

states. A 10K pull-up resistor has to be connected to TMS pin.
TCK I TCK (TAP Controller Clock) provides the clock input for the JTAG logic.

A 10K pull-up resistor must be connected to TCK pin.
TDI I TDI (TAP Controller Data Input) is the serial input for test instructions and data.

A 10K pull-up resistor must be connected to TDI pin.
TDO O TDO (TAP Controller Data Output) is the serial output for test instructions and

data.

1-23

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-3. S3C2440A Signal Descriptions (Sheet 5 of 6) (Continued)

Signal Input/Output Description

Reset, Clock & Power

XTOpll AO Crystal Output for internal osc circuit.

When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK
source.
When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only.
When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only.

If it isn't used, it has to be a floating pin.
MPLLCAP AI Loop filter capacitor for main clock.
UPLLCAP AI Loop filter capacitor for USB clock.
XTIrtc AI 32 kHz crystal input for RTC. If it isn’t used, it has to be High (VDDRTC).
XTOrtc AO 32 kHz crystal output for RTC. If it isn’t used, it has to be Float.
CLKOUT[1:0] O Clock output signal. The CLKSEL of MISCCR register configures the clock output

mode among the MPLL CLK, UPLL CLK, FCLK, HCLK, PCLK.
nRESET ST nRESET suspends any operation in progress and places S3C2440A into a

known reset state. For a reset, nRESET must be held to L level for at least 4

OSCin after the processor power has been stabilized.
nRSTOUT O For external device reset control (nRSTOUT = nRESET & nWDTRST &

SW_RESET)
PWREN O 1.2V/1.3V core power on-off control signal
nBATT_FLT I Probe for battery state(Does not wake up at Sleep mode in case of low battery

state). If it isn’t used, it has to be High (VDDOP).
OM[3:2] I OM[3:2] determines how the clock is made.

OM[3:2] = 00b, Crystal is used for MPLL CLK source and UPLL CLK source.

OM[3:2] = 01b, Crystal is used for MPLL CLK source and EXTCLK is used for

UPLL CLK source.

OM[3:2] = 10b, EXTCLK is used for MPLL CLK source and Crystal is used for

UPLL CLK source.

OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source.
EXTCLK I External clock source.

When OM[3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK

source.

When OM[3:2] = 10b, EXTCLK is used for MPLL CLK source only.

When OM[3:2] = 01b, EXTCLK is used for UPLL CLK source only.

If it isn't used, it has to be High (VDDOP).
XTIpll AI Crystal Input for internal osc circuit.

When OM[3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK

source.

When OM[3:2] = 01b, XTIpll is used for MPLL CLK source only.

When OM[3:2] = 10b, XTIpll is used for UPLL CLK source only.

If it isn't used, XTIpll has to be High (VDDOP).

1-24

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-3. S3C2440A Signal Descriptions (Sheet 6 of 6) (Continued)

Signal Input/Output Description

Power

VDDalive P S3C2440A reset block and port status register VDD.

It should be always supplied whether in normal mode or in Sleep mode.

VDDiarm P S3C2440A core logic VDD for ARM core.
VDDi P S3C2440A core logic VDD for Internal block.
VSSi/VSSiarm P S3C2440A core logic V

SS

VDDi_MPLL P S3C2440A MPLL analog and digital VDD.
VSSi_MPLL P S3C2440A MPLL analog and digital VSS.
VDDOP P S3C2440A I/O port VDD (3.3V)

VDDMOP P S3C2440A memory I/O V

DD

3.3V: SCLK up to 135 MHz

2.5V: SCLK up to 135 MHz

1.8V: SCLK up to 93 MHz
VSSOP P S3C2440A I/O port VSS
RTCVDD P RTC VDD (3.0V, Input range: 1.8 ~ 3.6V)

This pin must be connected to power properly if RTC isn't used.

VDDi_UPLL P S3C2440A UPLL analog and digital V
VSSi_UPLL P S3C2440A UPLL analog and digital V
VDDA_ADC P S3C2440A ADC VDD(3.3V)
VSSA_ADC P S3C2440A ADC V

NOTES:

1. I/O means Input/Output.

2. AI/AO means analog input/analog output.

3. ST means schmitt-trigger.

4. P means power.

SS

DD
SS

1-25

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

S3C2440A SPECIAL REGISTERS

Table 1-4. S3C2440A Special Registers (Sheet 1 of 14)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

Memory Controllers

BWSCON 0x48000000 W R/W Bus width & wait status control
BANKCON0 0x48000004 Boot ROM control
BANKCON1 0x48000008 BANK1 control
BANKCON2 0x4800000C BANK2 control
BANKCON3 0x48000010 BANK3 control
BANKCON4 0x48000014 BANK4 control
BANKCON5 0x48000018 BANK5 control
BANKCON6 0x4800001C BANK6 control
BANKCON7 0x48000020 BANK7 control
REFRESH 0x48000024 DRAM/SDRAM refresh control
BANKSIZE 0x48000028 Flexible bank size
MRSRB6 0x4800002C Mode register set for SDRAM BANK6
MRSRB7 0x48000030 Mode register set for SDRAM BANK7

1-26

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C2440A Special Registers (Sheet 2 of 14) (Continued)

Register Name Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

USB Host Controller

HcRevision 0x49000000 ← W Control and status group
HcControl 0x49000004
HcCommonStatus 0x49000008
HcInterruptStatus 0x4900000C
HcInterruptEnable 0x49000010
HcInterruptDisable 0x49000014
HcHCCA 0x49000018 Memory pointer group
HcPeriodCuttentED 0x4900001C
HcControlHeadED 0x49000020
HcControlCurrentED 0x49000024
HcBulkHeadED 0x49000028
HcBulkCurrentED 0x4900002C
HcDoneHead 0x49000030 Frame counter group
HcRmInterval 0x49000034
HcFmRemaining 0x49000038
HcFmNumber 0x4900003C
HcPeriodicStart 0x49000040
HcLSThreshold 0x49000044
HcRhDescriptorA 0x49000048 Root hub group
HcRhDescriptorB 0x4900004C
HcRhStatus 0x49000050
HcRhPortStatus1 0x49000054
HcRhPortStatus2 0x49000058

Interrupt Controller

SRCPND 0X4A000000 ← W R/W Interrupt request status
INTMOD 0X4A000004 W Interrupt mode control
INTMSK 0X4A000008 R/W Interrupt mask control
PRIORITY 0X4A00000C W IRQ priority control
INTPND 0X4A000010 R/W Interrupt request status
INTOFFSET 0X4A000014 R Interrupt request source offset
SUBSRCPND 0X4A000018 R/W Sub source pending
INTSUBMSK 0X4A00001C R/W Interrupt sub mask

1-27

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-4. S3C2440A Special Registers (Sheet 3 of 14) (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

DMA

DISRC0 0x4B000000 ← W R/W DMA 0 initial source
DISRCC0 0x4B000004 DMA 0 initial source control
DIDST0 0x4B000008 DMA 0 initial destination
DIDSTC0 0x4B00000C DMA 0 initial destination control
DCON0 0x4B000010 DMA 0 control
DSTAT0 0x4B000014 R DMA 0 count
DCSRC0 0x4B000018 DMA 0 current source
DCDST0 0x4B00001C DMA 0 current destination
DMASKTRIG0 0x4B000020 R/W DMA 0 mask trigger
DISRC1 0x4B000040 DMA 1 initial source
DISRCC1 0x4B000044 DMA 1 initial source control
DIDST1 0x4B000048 DMA 1 initial destination
DIDSTC1 0x4B00004C DMA 1 initial destination control
DCON1 0x4B000050 DMA 1 control
DSTAT1 0x4B000054 R DMA 1 count
DCSRC1 0x4B000058 DMA 1 current source
DCDST1 0x4B00005C DMA 1 current destination
DMASKTRIG1 0x4B000060 R/W DMA 1 mask trigger
DISRC2 0x4B000080 DMA 2 initial source
DISRCC2 0x4B000084 DMA 2 initial source control
DIDST2 0x4B000088 DMA 2 initial destination
DIDSTC2 0x4B00008C DMA 2 initial destination control
DCON2 0x4B000090 DMA 2 control
DSTAT2 0x4B000094 R DMA 2 count
DCSRC2 0x4B000098 DMA 2 current source
DCDST2 0x4B00009C DMA 2 current destination
DMASKTRIG2 0x4B0000A0 R/W DMA 2 mask trigger
DISRC3 0x4B0000C0 ← W R/W DMA 3 initial source
DISRCC3 0x4B0000C4 DMA 3 initial source control
DIDST3 0x4B0000C8 DMA 3 initial destination
DIDSTC3 0x4B0000CC DMA 3 initial destination control
DCON3 0x4B0000D0 DMA 3 control
DSTAT3 0x4B0000D4 R DMA 3 count
DCSRC3 0x4B0000D8 DMA 3 current source
DCDST3 0x4B0000DC DMA 3 current destination
DMASKTRIG3 0x4B0000E0 R/W DMA 3 mask trigger

1-28

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C2440A Special Registers (Sheet 4 of 14) (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

Clock & Power Management

LOCKTIME 0x4C000000 ← W R/W PLL lock time counter
MPLLCON 0x4C000004 MPLL control
UPLLCON 0x4C000008 UPLL control
CLKCON 0x4C00000C Clock generator control
CLKSLOW 0x4C000010 Slow clock control
CLKDIVN 0x4C000014 Clock divider control
CAMDIVN 0x4C000018 Camera clock divider control

LCD Controller

LCDCON1 0X4D000000 ← W R/W LCD control 1
LCDCON2 0X4D000004 LCD control 2
LCDCON3 0X4D000008 LCD control 3
LCDCON4 0X4D00000C LCD control 4
LCDCON5 0X4D000010 LCD control 5
LCDSADDR1 0X4D000014 STN/TFT: frame buffer start address 1
LCDSADDR2 0X4D000018 STN/TFT: frame buffer start address 2
LCDSADDR3 0X4D00001C STN/TFT: virtual screen address set
REDLUT 0X4D000020 STN: red lookup table
GREENLUT 0X4D000024 STN: green lookup table
BLUELUT 0X4D000028 STN: blue lookup table
DITHMODE 0X4D00004C STN: dithering mode
TPAL 0X4D000050 TFT: temporary palette
LCDINTPND 0X4D000054 LCD interrupt pending
LCDSRCPND 0X4D000058 LCD interrupt source
LCDINTMSK 0X4D00005C LCD interrupt mask
TCONSEL 0X4D000060 TCON(LPC3600/LCC3600) control

1-29

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-4. S3C2440A Special Registers (Sheet 5 of 14) (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

NAND Flash

NFCONF 0x4E000000 ← W R/W NAND flash configuration
NFCONT 0x4E000004 NAND flash control
NFCMD 0x4E000008 NAND flash command
NFADDR 0x4E00000C NAND flash address
NFDATA 0x4E000010 NAND flash data
NFMECC0 0x4E000014 NAND flash main area ECC0/1
NFMECC1 0x4E000018 NAND flash main area ECC2/3
NFSECC 0x4E00001C NAND flash spare area ECC
NFSTAT 0x4E000020 NAND flash operation status
NFESTAT0 0x4E000024 NAND flash ECC status for I/O[7:0]
NFESTAT1 0x4E000028 NAND flash ECC status for I/O[15:8]
NFMECC0 0x4E00002C R NAND flash main area ECC0 status
NFMECC1 0x4E000030 NAND flash main area ECC1 status
NFSECC 0x4E000034 NAND flash spare area ECC status
NFSBLK 0x4E000038 R/W NAND flash start block address
NFEBLK 0x4E00003C NAND flash end block address

1-30

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C2440A Special Registers (Sheet 6 of 14) (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

Camera Interface

CISRCFMT 0x4F000000 ← W RW Input source format
CIWDOFST 0x4F000004 Window offset register
CIGCTRL 0x4F000008 Global control register
CICOYSA1 0x4F000018

CICOYSA2 0x4F00001C
CICOYSA3 0x4F000020
CICOYSA4 0x4F000024
CICOCBSA1 0x4F000028
CICOCBSA2 0x4F00002C
CICOCBSA3 0x4F000030
CICOCBSA4 0x4F000034
CICOCRSA1 0x4F000038
CICOCRSA2 0x4F00003C
CICOCRSA3 0x4F000040
CICOCRSA4 0x4F000044

Y 1st frame start address for codec DMA
Y 2nd frame start address for codec DMA
Y 3nd frame start address for codec DMA
Y 4th frame start address for codec DMA
Cb 1st frame start address for codec DMA
Cb 2nd frame start address for codec DMA

nd

Cb 3
Cb 4
Cr 1

frame start address for codec DMA

th

frame start address for codec DMA

st

frame start address for codec DMA

Cr 2nd frame start address for codec DMA

nd

Cr 3

frame start address for codec DMA

th

Cr 4

frame start address for codec DMA
CICOTRGFMT 0x4F000048 Target image format of codec DMA
CICOCTRL 0x4F00004C Codec DMA control related
CICOSCPRERATIO 0x4F000050 Codec pre-scaler ratio control
CICOSCPREDST 0x4F000054 Codec pre-scaler destination format
CICOSCCTRL 0x4F000058 Codec main-scaler control
CICOTAREA 0x4F00005C Codec scaler target area
CICOSTATUS 0x4F000064 Codec path status
CIPRCLRSA1 0x4F00006C

CIPRCLRSA2 0x4F000070

RGB 1st frame start address for preview DMA
RGB 2nd frame start address for preview

DMA

CIPRCLRSA3 0x4F000074

RGB 3nd frame start address for preview
DMA

CIPRCLRSA4 0x4F000078

RGB 4th frame start address for preview DMA
CIPRTRGFMT 0x4F00007C Target image format of preview DMA
CIPRCTRL 0x4F000080 Preview DMA control related
CIPRSCPRERATIO 0x4F000084 Preview pre-scaler ratio control
CIPRSCPREDST 0x4F000088 Preview pre-scaler destination format
CIPRSCCTRL 0x4F00008C Preview main-scaler control
CIPRTAREA 0x4F000090 Preview scaler target area
CIPRSTATUS 0x4F000098 Preview path status
CIIMGCPT 0x4F0000A0 Image capture enable command

1-31

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-4. S3C2440A Special Registers (Sheet 7 of 14) (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc. Unit Read/

Write

Function

UART

ULCON0 0x50000000 ← W R/W UART 0 line control
UCON0 0x50000004 UART 0 control
UFCON0 0x50000008 UART 0 FIFO control
UMCON0 0x5000000C UART 0 modem control
UTRSTAT0 0x50000010 R UART 0 Tx/Rx status
UERSTAT0 0x50000014 UART 0 Rx error status
UFSTAT0 0x50000018 UART 0 FIFO status
UMSTAT0 0x5000001C UART 0 modem status
UTXH0 0x50000023 0x50000020 B W UART 0 transmission hold
URXH0 0x50000027 0x50000024 R UART 0 receive buffer
UBRDIV0 0x50000028 ← W R/W UART 0 baud rate divisor
ULCON1 0x50004000 UART 1 line control
UCON1 0x50004004 UART 1 control
UFCON1 0x50004008 UART 1 FIFO control
UMCON1 0x5000400C UART 1 modem control
UTRSTAT1 0x50004010 R UART 1 Tx/Rx status
UERSTAT1 0x50004014 UART 1 Rx error status
UFSTAT1 0x50004018 UART 1 FIFO status
UMSTAT1 0x5000401C UART 1 modem status
UTXH1 0x50004023 0x50004020 B W UART 1 transmission hold
URXH1 0x50004027 0x50004024 R UART 1 receive buffer
UBRDIV1 0x50004028 ← W R/W UART 1 baud rate divisor
ULCON2 0x50008000 UART 2 line control
UCON2 0x50008004 UART 2 control
UFCON2 0x50008008 UART 2 FIFO control
UTRSTAT2 0x50008010 R UART 2 Tx/Rx status
UERSTAT2 0x50008014 UART 2 Rx error status
UFSTAT2 0x50008018 UART 2 FIFO status
UTXH2 0x50008023 0x50008020 B W UART 2 transmission hold
URXH2 0x50008027 0x50008024 R UART 2 receive buffer
UBRDIV2 0x50008028 ← W R/W UART 2 baud rate divisor

1-32

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C2440A Special Registers (Sheet 8 of 14) (Continued)

Register Name Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

PWM Timer

TCFG0 0x51000000 ← W R/W Timer configuration
TCFG1 0x51000004 Timer configuration
TCON 0x51000008 Timer control
TCNTB0 0x5100000C Timer count buffer 0
TCMPB0 0x51000010 Timer compare buffer 0
TCNTO0 0x51000014 R Timer count observation 0
TCNTB1 0x51000018 R/W Timer count buffer 1
TCMPB1 0x5100001C Timer compare buffer 1
TCNTO1 0x51000020 R Timer count observation 1
TCNTB2 0x51000024 R/W Timer count buffer 2
TCMPB2 0x51000028 Timer compare buffer 2
TCNTO2 0x5100002C R Timer count observation 2
TCNTB3 0x51000030 R/W Timer count buffer 3
TCMPB3 0x51000034 Timer compare buffer 3
TCNTO3 0x51000038 R Timer count observation 3
TCNTB4 0x5100003C R/W Timer count buffer 4
TCNTO4 0x51000040 R Timer count observation 4

1-33

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-4. S3C2440A Special Registers (Sheet 9 of 14) (Continued)

Register Name Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

USB Device

FUNC_ADDR_REG 0x52000143 0x52000140 B R/W Function address
PWR_REG 0x52000147 0x52000144 Power management
EP_INT_REG 0x5200014B 0x52000148 EP interrupt pending and clear
USB_INT_REG 0x5200015B 0x52000158 USB interrupt pending and clear
EP_INT_EN_REG 0x5200015F 0x5200015C Interrupt enable
USB_INT_EN_REG 0x5200016F 0x5200016C Interrupt enable
FRAME_NUM1_REG 0x52000173 0x52000170 R Frame number lower byte
FRAME_NUM2_REG 0x52000177 0x52000174 Frame number higher byte
INDEX_REG 0x5200017B 0x52000178 R/W Register index
EP0_CSR 0x52000187 0x52000184 Endpoint 0 status
IN_CSR1_REG 0x52000187 0x52000184 In endpoint control status
IN_CSR2_REG 0x5200018B 0x52000188 In endpoint control status
MAXP_REG 0x52000183 0x52000180 Endpoint max packet
OUT_CSR1_REG 0x52000193 0x52000190 Out endpoint control status
OUT_CSR2_REG 0x52000197 0x52000194 Out endpoint control status
OUT_FIFO_CNT1_REG 0x5200019B 0x52000198 R Endpoint out write count
OUT_FIFO_CNT2_REG 0x5200019F 0x5200019C Endpoint out write count
EP0_FIFO 0x520001C3 0x520001C0 R/W Endpoint 0 FIFO
EP1_FIFO 0x520001C7 0x520001C4 Endpoint 1 FIFO
EP2_FIFO 0x520001CB 0x520001C8 Endpoint 2 FIFO
EP3_FIFO 0x520001CF 0x520001CC Endpoint 3 FIFO
EP4_FIFO 0x520001D3 0x520001D0 Endpoint 4 FIFO
EP1_DMA_CON 0x52000203 0x52000200 EP1 DMA Interface control
EP1_DMA_UNIT 0x52000207 0x52000204 EP1 DMA Tx unit counter
EP1_DMA_FIFO 0x5200020B 0x52000208 EP1 DMA Tx FIFO counter
EP1_DMA_TTC_L 0x5200020F 0x5200020C EP1 DMA Total Tx counter
EP1_DMA_TTC_M 0x52000213 0x52000210 EP1 DMA Total Tx counter
EP1_DMA_TTC_H 0x52000217 0x52000214 EP1 DMA Total Tx counter
EP2_DMA_CON 0x5200021B 0x52000218 B R/W EP2 DMA interface control
EP2_DMA_UNIT 0x5200021F 0x5200021C EP2 DMA Tx Unit counter
EP2_DMA_FIFO 0x52000223 0x52000220 EP2 DMA Tx FIFO counter
EP2_DMA_TTC_L 0x52000227 0x52000224 EP2 DMA total Tx counter
EP2_DMA_TTC_M 0x5200022B 0x52000228 EP2 DMA total Tx counter

1-34

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C2440A Special Registers (Sheet 10 of 14) (Continued)

Register Name Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

USB Device (Continued)

EP2_DMA_TTC_H 0x5200022F 0x5200022C EP2 DMA Total Tx counter
EP3_DMA_CON 0x52000243 0x52000240 EP3 DMA Interface control
EP3_DMA_UNIT 0x52000247 0x52000244 EP3 DMA Tx Unit counter
EP3_DMA_FIFO 0x5200024B 0x52000248 EP3 DMA Tx FIFO counter
EP3_DMA_TTC_L 0x5200024F 0x5200024C EP3 DMA Total Tx counter
EP3_DMA_TTC_M 0x52000253 0x52000250 EP3 DMA Total Tx counter
EP3_DMA_TTC_H 0x52000257 0x52000254 EP3 DMA Total Tx counter
EP4_DMA_CON 0x5200025B 0x52000258 EP4 DMA Interface control
EP4_DMA_UNIT 0x5200025F 0x5200025C EP4 DMA Tx Unit counter
EP4_DMA_FIFO 0x52000263 0x52000260 EP4 DMA Tx FIFO counter
EP4_DMA_TTC_L 0x52000267 0x52000264 EP4 DMA Total Tx counter
EP4_DMA_TTC_M 0x5200026B 0x52000268 EP4 DMA Total Tx counter
EP4_DMA_TTC_H 0x5200026F 0x5200026C EP4 DMA Total Tx counter

Watchdog Timer

WTCON 0x53000000 ← W R/W Watchdog timer mode
WTDAT 0x53000004 Watchdog timer data
WTCNT 0x53000008 Watchdog timer count

IIC

IICCON 0x54000000 ← W R/W IIC control
IICSTAT 0x54000004 IIC status
IICADD 0x54000008 IIC address
IICDS 0x5400000C IIC data shift
IICLC 0x54000010 IIC multi-master line control

IIS

IISCON 0x55000000,02 0x55000000 HW,W R/W IIS control
IISMOD 0x55000004,06 0x55000004 IIS mode
IISPSR 0x55000008,0A 0x55000008 IIS prescaler
IISFCON 0x5500000C,0E 0x5500000C IIS FIFO control
IISFIFO 0x55000012 0x55000010 HW IIS FIFO entry

1-35

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-4. S3C2440A Special Registers (Sheet 11 of 14) (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc. Unit Read/

Write

Function

I/O port

GPACON 0x56000000 ← W R/W Port A control
GPADAT 0x56000004 Port A data
GPBCON 0x56000010 Port B control
GPBDAT 0x56000014 Port B data
GPBUP 0x56000018 Pull-up control B
GPCCON 0x56000020 Port C control
GPCDAT 0x56000024 Port C data
GPCUP 0x56000028 Pull-up control C
GPDCON 0x56000030 Port D control
GPDDA1T 0x56000034 Port D data
GPDUP 0x56000038 Pull-up control D
GPECON 0x56000040 Port E control
GPEDAT 0x56000044 Port E data
GPEUP 0x56000048 Pull-up control E
GPFCON 0x56000050 Port F control
GPFDAT 0x56000054 Port F data
GPFUP 0x56000058 Pull-up control F
GPGCON 0x56000060 Port G control
GPGDAT 0x56000064 Port G data
GPGUP 0x56000068 Pull-up control G
GPHCON 0x56000070 Port H control
GPHDAT 0x56000074 Port H data
GPHUP 0x56000078 Pull-up control H
GPJCON 0x560000D0 Port J control
GPJDAT 0x560000D4 Port J data
GPJUP 0x560000D8 Pull-up control J
MISCCR 0x56000080 Miscellaneous control
DCLKCON 0x56000084 DCLK0/1 control
EXTINT0 0x56000088 External interrupt control register 0
EXTINT1 0x5600008C External interrupt control register 1
EXTINT2 0x56000090 External interrupt control register 2

1-36

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C2440A Special Registers (Sheet 12 of 14) (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc.

Unit

Read/

Write

Function

i/o port (continued)

EINTFLT0 0x56000094 ← W R/W Reserved
EINTFLT1 0x56000098 Reserved
EINTFLT2 0x5600009C External interrupt filter control register 2
EINTFLT3 0x560000A0 External interrupt filter control register 3
EINTMASK 0x560000A4 External interrupt mask
EINTPEND 0x560000A8 External interrupt pending
GSTATUS0 0x560000AC R External pin status
GSTATUS1 0x560000B0 R/W Chip ID
GSTATUS2 0x560000B4 Reset status
GSTATUS3 0x560000B8 Inform register
GSTATUS4 0x560000BC Inform register
MSLCON 0x560000CC Memory sleep control register

RTC

RTCCON 0x57000043 0x57000040 B R/W RTC control
TICNT 0x57000047 0x57000044 Tick time count
RTCALM 0x57000053 0x57000050 RTC alarm control
ALMSEC 0x57000057 0x57000054 Alarm second
ALMMIN 0x5700005B 0x57000058 Alarm minute
ALMHOUR 0x5700005F 0x5700005C Alarm hour
ALMDATE 0x57000063 0x57000060 alarm day
ALMMON 0x57000067 0x57000064 Alarm month
ALMYEAR 0x5700006B 0x57000068 Alarm year
BCDSEC 0x57000073 0x57000070 BCD second
BCDMIN 0x57000077 0x57000074 BCD minute
BCDHOUR 0x5700007B 0x57000078 BCD hour
BCDDATE 0x5700007F 0x5700007C BCD day
BCDDAY 0x57000083 0x57000080 BCD date
BCDMON 0x57000087 0x57000084 BCD month
BCDYEAR 0x5700008B 0x57000088 BCD year

1-37

PRODUCT OVERVIEW S3C2440A RISC MICROPROCESSOR

Table 1-4. S3C2440A Special Registers (Sheet 13 of 14) (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc. Unit Read/

Write

Function

A/D Converter

ADCCON 0x58000000 ← W R/W ADC control
ADCTSC 0x58000004 ADC touch screen control
ADCDLY 0x58000008 ADC start or interval delay
ADCDAT0 0x5800000C R ADC conversion data
ADCDAT1 0x58000010 ADC conversion data
ADCUPDN 0x58000014 R/W Stylus up or down interrupt status

SPI

SPCON0,1 0x59000000,20 ← W R/W SPI control
SPSTA0,1 0x59000004,24 R SPI status
SPPIN0,1 0x59000008,28 R/W SPI pin control
SPPRE0,1 0x5900000C,2C SPI baud rate prescaler
SPTDAT0,1 0x59000010,30 SPI Tx data
SPRDAT0,1 0x59000014,34 R SPI Rx data

SD Interface

SDICON 0x5A000000 ← W R/W SDI control
SDIPRE 0x5A000004 SDI baud rate prescaler
SDICARG 0x5A000008 SDI command argument
SDICCON 0x5A00000C SDI command control
SDICSTA 0x5A000010 R/(C) SDI command status
SDIRSP0 0x5A000014 R SDI response
SDIRSP1 0x5A000018 SDI response
SDIRSP2 0x5A00001C SDI response
SDIRSP3 0x5A000020 SDI response
SDIDTIMER 0x5A000024 R/W SDI data / busy timer
SDIBSIZE 0x5A000028 SDI block size
SDIDCON 0x5A00002C SDI data control
SDIDCNT 0x5A000030 R SDI data remain counter
SDIDSTA 0x5A000034 R/(C) SDI data status
SDIFSTA 0x5A000038 R SDI FIFO status
SDIIMSK 0x5A00003C ← W SDI interrupt mask
SDIDAT 0x5A000043 0x5A000040 B R/W SDI data

1-38

S3C2440A RISC MICROPROCESSOR PRODUCT OVERVIEW

Table 1-4. S3C2440A Special Registers (Sheet 14 of 14) (Continued)

Register

Name

Address

(B. Endian)

Address

(L. Endian)

Acc. Unit Read/

Write

Function

AC97 Audio-CODEC Interface

AC_GLBCTRL 0x5B000000 ← W R/W AC97 global control register
AC_GLBSTAT 0x5B000004 R AC97 global status register
AC_CODEC_CMD 0x5B000008 R/W AC97 codec command register
AC_CODEC_STAT 0x5B00000C R AC97 codec status register
AC_PCMADDR 0x5B000010 AC97 PCM out/in channel FIFO

address register

AC_MICADDR 0x5B000014 AC97 mic in channel FIFO address

register

AC_PCMDATA 0x5B000018 R/W AC97 PCM out/in channel FIFO data

register

AC_MICDATA 0x5B00001C AC97 MIC in channel FIFO data

register

Cautions on S3C2440A Special Registers

1. In the little endian mode ‘L’, endian address must be used. In the big endian mode ‘B’ endian address must be
used.

2. The special registers have to be accessed for each recommended access unit.

3. All registers except ADC registers, RTC registers and UART registers must be read/write in word unit (32-bit) in
little/big endian.

4. Make sure that the ADC registers, RTC registers and UART registers be read/write by the specified access unit
and the specified address. Moreover, one must carefully consider which endian mode is used.

5. W : 32-bit register, which must be accessed by LDR/STR or int type pointer (int *).

HW : 16-bit register, which must be accessed by LDRH/STRH or short int type pointer (short int *).
B : 8-bit register, which must be accessed by LDRB/STRB or char type pointer (char int *).

1-39

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL

2 PROGRAMMER'S MODEL

OVERVIEW

S3C2440A is developed using the advanced ARM920T core, which has been designed by Advanced RISC Machines,
Ltd.

PROCESSOR OPERATING STATES
From the programmer's point of view, the ARM920T can be in one of the two states:

• ARM state which executes 32-bit, word-aligned ARM instructions

• THUMB state is a state which can execute 16-bit, halfword-aligned THUMB instructions. In this state, the PC

uses bit 1 to select between alternate halfwords

NOTE

Transition between these two states does not affect the processor mode or the contents of the registers.

SWITCHING STATE
Entering THUMB State

Entry into THUMB state can be achieved by executing a BX instruction with the state bit (bit 0) set in the operand
register.

Transition to THUMB state will also occur automatically on return from an exception (IRQ, FIQ, UNDEF, ABORT,
SWI etc.), if the exception is entered with the processor in THUMB state.

Entering ARM State
Entry into ARM state can be done by the following methods:-

• On execution of the BX instruction with the state bit clear in the operand register.

• On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI etc.). In this case, the PC is

placed in the exception mode's link register, and execution commences at the exception's vector address.

MEMORY FORMATS

ARM920T views memory as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first
stored word, bytes 4 to 7 the second and so on. ARM920T can treat words in memory as being stored either in Big­Endian or Little-Endian format.

2-1

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR

Word Address

Word Address

BIG-ENDIAN FORMAT

In Big-Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least
significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31
through 24.

Higher Address

31 24

23 16

15 8 7 0

Lower Address

8
4
0

Most significant byte is at lowest address

Word is addressed by byte address of most significant byte

9
5
1

10
6
2

11
7
3

8
4
0

Figure 2-1. Big-Endian Addresses of Bytes within Words

LITTLE-ENDIAN FORMAT

In Little-Endian format, the lowest numbered byte in a word is considered the word's least significant byte, and the
highest numbered byte the most significant. Byte 0 of the memory system is therefore connected to data lines 7
through 0.

Higher Address

31 24

11
7

23 16
10
6

15 8 7 0
9
5

8
4

8
4

Lower Address

3

Least significant byte is at lowest address

Word is addressed by byte address of least significant byte

2

1

0

0

Figure 2-2. Little-Endian Addresses of Bytes within Words

INSTRUCTION LENGTH
Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state).
Data Types

ARM920T supports byte (8-bit), halfword (16-bit) and word (32-bit) data types. Words must be aligned to four-byte
boundaries and half words to two-byte boundaries.

2-2

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL

OPERATING MODES
ARM920T supports seven modes of operation:

• User (usr): The normal ARM program execution state

• FIQ (fiq): Designed to support a data transfer or channel process

• IRQ (irq): Used for general-purpose interrupt handling

• Supervisor (svc): Protected mode for the operating system

• Abort mode (abt): Entered after a data or instruction prefetch abort

• System (sys): A privileged user mode for the operating system

• Undefined (und): Entered when an undefined instruction is executed

Mode changes can be made using the control of software, or may be brought about by external interrupts or
exception processing. Most application programs will execute in User mode. The non-user modes' known as
privileged modes -are entered in order to service interrupts or exceptions, or to access protected resources.

REGISTERS

ARM920T has a total of 37 registers - 31 general-purpose 32-bit registers and six status registers - but these cannot
all be seen at once. The processor state and operating mode decides which registers are available to the
programmer.

The ARM State Register Set

In ARM state, 16 general registers and one or two status registers are visible at any one time. In privileged (non­User) modes, mode-specific banked registers are switched in. Figure 2-3 shows which register is available in each
mode: the banked registers are marked with a shaded triangle.

The ARM state register set contains 16 directly accessible registers: R0 to R15. All of these except R15 are general­purpose, and may be used to hold either data or address values. In addition to these, there is a seventeenth register
used to store status information.

Register 14 This register is used as the subroutine link register. This receives a copy of R15 when

a Branch and Link (BL) instruction is executed. Rest of the time it may be treated as a
general-purpose register. The corresponding banked registers R14_svc, R14_irq,
R14_fiq, R14_abt and R14_und are similarly used to hold the return values of R15
when interrupts and exceptions arise, or when Branch and Link instructions are
executed within interrupt or exception routines.

Register 15 This register holds the Program Counter (PC). In ARM state, bits [1:0] of R15 are zero

and bits [31:2] contain the PC. In THUMB state, bit [0] is zero and bits [31:1] contain
the PC.

Register 16 This register is the CPSR (Current Program Status Register). This contains condition

code flags and the current mode bits.

FIQ mode has seven banked registers mapped to R8-14 (R8_fiq-R14_fiq). In ARM state there are many FIQ handlers
which don’t require saving registers. User, IRQ, Supervisor, Abort and Undefined, each have two banked registers
mapped to R13 and R14, allowing each of these modes to have a private stack pointer and link registers.

2-3

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR

ARM State General Registers and Program Counter

System & User

r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13
r14

r15 (PC)

CPSR CPSR

FIQ

r0
r1
r2
r3
r4
r5
r6
r7
r8_

fiq

r9_

fiq

r10_

fiq

r11_

fiq

r12_

fiq

r13_

fiq

r14_

fiq

r15 (PC)

Supervisor IRQAbort Undefined

r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13_

svc

r14_

svc

r15 (PC)

r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13_
r14_

r15 (PC)

ARM State Program Status Registers

SPSR_

fiq

CPSR

SPSR_

svc

CPSR

SPSR_

abt
abt

abt

r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
r11
r12
r13_
r14_

r15 (PC)

CPSR

SPSR_

irq
irq

irq

r0
r1
r2
r3
r4
r5
r6
r7
r8
r9

r10
r11
r12
r13_
r14_
r15 (PC)

CPSR

SPSR_

und
und

und

= banked register

Figure 2-3. Register Organization in ARM State

2-4

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL

THUMB State General Registers and Program Counter

The THUMB State Register Set

The THUMB state register set is a subset of the ARM state set. The programmer has direct ac cess to eight general
registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the
CPSR. There are banked Stack Pointers, Link Registers and Saved Process Status Registers (SPSRs) for each
privileged mode. This is shown in Figure 2-4.

System & User

r0
r1
r2
r3
r4
r5
r6

r7
SP
LR
PC

CPSR CPSR

= banked register

FIQ

r0
r1
r2
r3
r4
r5
r6

r7
SP_
LR_
PC

fiq
fiq

Supervisor IRQAbort Undefined

r0
r1
r2
r3
r4
r5
r6

r7
SP_
LR_
PC

svc

svc

r0
r1
r2
r3
r4
r5
r6

r7
SP_
LR_
PC

abt
abt

r0
r1
r2
r3
r4
r5
r6

r7
SP_
LR_
PC

und

und

THUMB State Program Status Registers

SPSR_

fiq

CPSR

SPSR_

svc

CPSR

SPSR_

abt

CPSR

SPSR_

Figure 2-4. Register Organization in THUMB state

irq

r0
r1
r2
r3
r4
r5
r6

r7
SP_
LR_
PC

CPSR

SPSR_

fiq
fiq

und

2-5

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR

THUMB State

ARM State

The relationship between ARM and THUMB state registers
The relationship between ARM and THUMB state registers are as below: -

• THUMB state R0-R7 and ARM state R0-R7 are identical

• THUMB state CPSR and SPSRs and ARM state CPSR and SPSRs are identical

• THUMB state SP maps onto ARM state R13

• THUMB state LR maps onto ARM state R14

• The THUMB state Program Counter maps onto the ARM state Program Counter (R15)

This relationship is shown in Figure 2-5.

r0
r1
r2
r3
r4
r5
r6
r7

Stack Pointer (SP)

Link Register (LR)

Program Counter (PC)

(CPSR)
(SPSR)

Stack Pointer (r13)

Link Register (r14)

Program Counter (r15)

r0
r1
r2
r3
r4
r5
r6
r7
r8

r9
r10
r11
r12

(CPSR)
(SPSR)

Figure 2-5. Mapping of THUMB State Registers onto ARM State Registers

Lo-RegistersHi-Registers

2-6

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL

Condition Code Flags

(Resverved)

Control Bits

Accessing Hi -Registers in THUMB State

In THUMB state, registers R8-R15 ("Hi registers") are not part of the standard register set. However, the assembly
language programmer has limited access to them, and can use them for fast temporary storage.

A value may be transferred from a register in the range R0-R7 (a Lo register) to a Hi register and from a Hi register to
a Lo register, using special variants of the MOV instruction. Hi register values can also be compared against or
added to Lo register values with the CMP and ADD instructions. For more information, Please refer to Figure 3-34.

THE PROGRAM STATUS REGISTERS

The ARM920T contains a Current Program Status Register (CPSR), plus five Saved Program Status Registers
(SPSRs) for use by exception handlers. These register's functions are:

• Hold information about the most recently performed ALU operation

• Control the enabling and disabling of interrupts

• Set the processor operating mode

The arrangement of bits is shown in Figure 2-6.

31

30 29 2728 26 25 24 23 8 7 6 5 4 3 2 1 0

N Z C V I F T M4 M3 M2 M1 M0

Overflow
Carry/Borrow/Extend
Zero
Negative/Less Than

~

~

~

~

Mode bits
State bits
FIQ disable
IRQ disable

Figure 2-6. Program Status Register Format

2-7

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR

The Condition Code Flags

The N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical
operations, and may be tested to determine whether an instruction should be ex ecuted.

In ARM state, all instructions may be executed conditionally: see Table 3-2 for details.
In THUMB state, only the Branch instruction is capable of conditional execution: see Figure 3-46 for details.

The Control Bits

The bottom 8 bits of a PSR (incorporating I, F, T and M[4:0]) are known collectively as the control bits. These will be
changed when an exception arises. If the processor is operating in a privileged mode, they can also be manipulated
by software.

The T bit This reflects the operating state. When this bit is set, the processor is executed in

THUMB state, or otherwise it is executing in ARM state. This is reflected on the TBIT
external signal.

Note: That the software must never change the state of the TBIT in the CPSR. If this happens,
the processor will enter an unpredictable state.

Interrupt disable bits I and F bits are the interrupt disable bits. When set, these disable the IRQ and FIQ

interrupts respectively.

The mode bits The M4, M3, M2, M1 and M0 bits (M[4:0]) are the mode bits. These determine the

processor's operating mode, as shown in Table 2-1. Not all combinations of the mode
bits define a valid processor mode. Only those explicitly described shall be used. The
user should be aware that if any illegal value is programmed into the mode bits, M[4:0],
then the processor will enter an unrecoverable state. If this occurs, reset should be
applied.

Reserved bits

The remaining bits in the PSRs are reserved. When changing a PSR's flag or control bits,
you must ensure that these unused bits are not altered. Also, your program should not
rely on them containing specific values, since in future processors they may read as one
or zero.

2-8

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL

Table 2-1. PSR Mode Bit Values

M[4:0] Mode Visible THUMB state registers Visible ARM state registers

10000 User R7..R0,

LR, SP

R14..R0,
PC, CPSR

PC, CPSR

10001 FIQ R7..R0,

LR_fiq, SP_fiq
PC, CPSR, SPSR_fiq

10010 IRQ R7..R0,

LR_irq, SP_irq
PC, CPSR, SPSR_irq

10011 Supervisor R7..R0,

LR_svc, SP_svc,
PC, CPSR, SPSR_svc

10111 Abort R7..R0,

LR_abt, SP_abt,
PC, CPSR, SPSR_abt

11011 Undefined R7..R0

LR_und, SP_und,
PC, CPSR, SPSR_und

11111 System R7..R0,

LR, SP

R7..R0,
R14_fiq..R8_fiq,
PC, CPSR, SPSR_fiq

R12..R0,
R14_irq, R13_irq,
PC, CPSR, SPSR_irq

R12..R0,
R14_svc, R13_svc,
PC, CPSR, SPSR_svc

R12..R0,
R14_abt, R13_abt,
PC, CPSR, SPSR_abt

R12..R0,
R14_und, R13_und,
PC, CPSR

R14..R0,
PC, CPSR

PC, CPSR

Reserved bits The remaining bits in the PSR's are reserved. While changing a PSR's fl ag or control
bits, you must ensure that these unused bits are not altered. Also, your program should
not rely on them containing specific values, since in future processors they may read as
one or zero.

2-9

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR

EXCEPTIONS

Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an
interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so
that the original program can resume when the handler routine has finished.

It is possible for several exceptions to arise at the same time. If this happens, they are dealt with in a fixed order.
See Exception Priorities on page 2-14.

Action on Entering an Exception

While handling an exception, the ARM920T does following activities:

1. Preserves the address of the next instruction in the appropriate Link Register. If the exception has been entered
from ARM state, then the address of the next instruction is copied into the Link Register (that is, current PC + 4
or PC + 8 depending on the exception. See Table 2-2 on for details). If the exception has been entered from
THUMB state, then the value written into the Link Register is the current PC offset by a value such that the
program resumes from the correct place on return from the exception. This means that the exception handler
need not determine which state the exception was entered from. For example, in the case of SWI, MOVS PC,
R14_svc will always return to the next instruction regardless of whether the SWI was executed in ARM or
THUMB state.

2. Copies the CPSR into the appropriate SPSR

3. Forces the CPSR mode bits to a value which depends on the exception

4. Forces the PC to fetch the next instruction from the relevant exception vector

It may also set the interrupt disable flags to prevent otherwise unmanageable nestings of exceptions.
If the processor is in THUMB state when an exception occurs, it will automatically switch into ARM state when the

PC is loaded with the exception vector address.

Action on Leaving an Exception

On completion, the exception handler:

1. Moves the Link Register, minus an offset where appropriate, to the PC. (The offset will vary depending on the
type of exception.)

2. Copies the SPSR back to the CPSR

3. Clears the interrupt disable flags, if they were set on entry

NOTE

An explicit switch back to THUMB state is never needed, since restoring the CPSR from the SPSR
automatically sets the T bit to the value it held immediately prior to the exception.

2-10

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL

Exception Entry/Exit Summary

Table 2-2 summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended
instruction for exiting the exception handler.

Table 2-2. Exception Entry/Exit

Return Instruction Previous State Notes

ARM R14_x THUMB R14_x

BL MOV PC, R14 PC + 4 PC + 2
SWI MOVS PC, R14_svc PC + 4 PC + 2
UDEF MOVS PC, R14_und PC + 4 PC + 2
FIQ SUBS PC, R14_fiq, #4 PC + 4 PC + 4
IRQ SUBS PC, R14_irq, #4 PC + 4 PC + 4
PABT SUBS PC, R14_abt, #4 PC + 4 PC + 4
DABT SUBS PC, R14_abt, #8 PC + 8 PC + 8
RESET NA – –

(1)
(1)
(1)
(2)
(2)
(1)
(3)
(4)

NOTES:

1. Where PC is the address of the BL/SWI/Undefined Instruction fetch which had the prefetch abort.

2. Where PC is the address of the instruction which did not get executed since the FIQ or IRQ took priority.

3. Where PC is the address of the Load or Store instruction which generated the data abort.

4. The value saved in R14_svc upon reset is unpredictable.

FIQ

The FIQ (Fast Interrupt Request) exception is designed to support a data transfer or channel process, and in ARM
state has sufficient private registers to remove the need for register saving (thus minimizing the overhead of context
switching).

FIQ is externally generated by taking the nFIQ input LOW. This input can except either synchronous or
asynchronous transitions, depending on the state of the ISYNC input signal. When ISYNC is LOW, nFIQ and nIRQ
are considered asynchronous, and a cycle delay for synchronization is incurred before the interrupt can affect the
processor flow.

Irrespective of whether the exception was entered from ARM or Thumb state, a FIQ handler should leave the interrupt
by executing

SUBS PC,R14_fiq,#4

FIQ may be disabled by setting the CPSR's F flag (but note that this is not possible from User mode). If the F flag is
clear, ARM920T checks for a LOW level on the output of the FIQ synchronizer at the end of each instruction.

2-11

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR

IRQ

The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a
lower priority than FIQ and is masked out when a FIQ sequence is entered. It may be disabled at any time by setting
I bit in the CPSR, though this can only be done from a privileged (non-User) mode.

Irrespective of whether the exception was entered from ARM or Thumb state, an IRQ handler should return from the
interrupt by executing

SUBS PC,R14_irq,#4

Abort

An abort indicates that the current memory access cannot be completed. It can be signaled by the external ABORT
input. ARM920T checks for the abort exception during memory access cycles.

There are two types of abort:

• Prefetch Abort: occurs during an instruction prefetch.

• Data Abort: occurs during a data access.

If a prefetch abort occurs, the prefetched instruction is marked as invalid, but the exception will not be taken until the
instruction reaches the head of the pipeline. If the instruction is not executed – the abort doesn’t take place because
a branch occurs while it is in the pipeline -.

If a data abort occurs, the action taken depends on the instruction type:

• Single data transfer instruc tions (LDR, STR) write back modified base registers: the Abort handler must be aware
of this.

• The swap instruction (SWP) is aborted as though it had not been executed.

• Block data transfer instructions (LDM, STM) complete. If write-back is set, the base is updated. If the instruction

would have overwritten the base with data (ie it has the base in the transfer list), the overwriting is prevented. All
register overwriting is prevented after an abort is indicated, which means in particular that R15 (always the last
register to be transferred) is preserved in an aborted LDM instruction.

The abort mechanism allows the implementation of a demand paged virtual memory system. In such a system the
processor is allowed to generate arbitrary addresses. When the data at an address is unavailable, the Memory
Management Unit (MMU) signals an abort. The abort handler must then work out the cause of the abort, make the
requested data available, and retry the aborted instruction. The application program needs no knowledge of the
amount of memory available to it, nor is its state in any way affected by the abort.

After fixing the reason for the abort, the handler should execute the following irrespective of the state (ARM or
Thumb):

SUBS PC,R14_abt,#4 ; for a prefetch abort, or
SUBS PC,R14_abt,#8 ; for a data abort

This restores both the PC and the CPSR, and retries the aborted instruction.

2-12

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL

Software Interrupt

The Software Interrupt Instruction (SWI) is used for entering Supervisor mode, usually to request a particular
supervisor function. A SWI handler should return by executing the following irrespective of the state (ARM or Thumb):

MOV PC,R14_svc

This restores the PC and CPSR, and returns to the instruction following the SWI.

NOTE

nFIQ, nIRQ, ISYNC, LOCK, BIGEND, and ABORT pins exist only in the ARM920T CPU core.

Undefined Instruction

When ARM920T comes across an instruction which cannot be handled, it takes the undefined instruction trap. This
mechanism may be used to extend either the THUMB or ARM instruction set by software emulation.

After emulating the failed instruction, the trap handler should execute the following irrespective of the state (ARM or
Thumb):

MOVS PC,R14_und

This restores the CPSR and returns to the instruction following the undefined instruction.

Exception Vectors

The following table shows the exception vector addresses.

Table 2-3. Exception Vectors

Address Exception Mode in Entry

0x00000000 Reset Supervisor
0x00000004 Undefined instruction Undefined
0x00000008 Software Interrupt Supervisor

0x0000000C Abort (prefetch) Abort

0x00000010 Abort (data) Abort
0x00000014 Reserved Reserved
0x00000018 IRQ IRQ

0x0000001C FIQ FIQ

2-13

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR

Exception Priorities

When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are
handled:

Highest priority:

1. Reset

2. Data abort

3. FIQ

4. IRQ

5. Prefetch abort

Lowest priority:

6. Undefined Instruction, Software interrupt.

Not All Exceptions Can Occur at Once:

Undefined Instruction and Software Interrupt are mutually exclusive, since they each correspond to particular (non­overlapping) decodings of the current instruction.

If a data abort occurs at the same time as a FIQ, and FIQs are enabled (ie the CPSR's F flag is clear), ARM920T
enters the data abort handler and then immediately proceeds to the FIQ vector. A normal return from FIQ will cause
the data abort handler to resume execution. Placing data abort at a higher priority than FIQ is necessary to ensure
that the transfer error does not escape detection. The time for this exception entry should be added to worst-case
FIQ latency calculations.

2-14

S3C2440A RISC MICROPROCESSOR PROGRAMMER'S MODEL

INTERRUPT LATENCIES

The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to
pass through the synchronizer (Tsyncmax if asynchronous), plus the time for the longest instruction to complete
(Tldm, the longest instruction is an LDM which loads all the registers including the PC), plus the time for the data
abort entry (Texc), plus the time for FIQ entry (Tfiq). At the end of this time ARM920T will be executing the
instruction at 0x1C.

Tsyncmax is 3 processor cycles, Tldm is 20 cycles, Texc is 3 cycles, and Tfiq is 2 cycles. The total time is
therefore 28 processor cycles. This is just over 1.4 microseconds in a system which uses a continuous 20 MHz
processor clock. The maximum IRQ latency calculation is similar, but must allow for the fact that FIQ has higher
priority and could delay entry into the IRQ handling routine for an arbitrary length of time. The minimum latency for
FIQ or IRQ consists of the shortest time the request can take through the synchronizer (Tsyncmin) plus Tfiq. This is
4 processor cycles.

RESET

When the nRESET signal goes LOW, ARM920T abandons the executing instruction and then continues to fetch
instructions from incrementing word addresses.

When nRESET goes HIGH again, ARM920T:

1. Overwrites R14_svc and SPSR_svc by copying the current values of the PC and CPSR into them. The value of
the saved PC and SPSR is not defined.

2. Forces M[4:0] to 10011 (Supervisor mode), sets the I and F bits in the CPSR, and clears the CPSR's T bit.

3. Forces the PC to fetch the next instruction from address 0x00.

4. Execution resumes in ARM state.

2-15

PROGRAMMER'S MODEL S3C2440A RISC MICROPROCESSOR

NOTES

2-16

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

3 ARM INSTRUCTION SET

INSTRUCTION SET SUMMAY

This chapter describes the ARM instruction set in the ARM920T core.

FORMAT SUMMARY

The following figure shows the ARM instruction set.

2726252423222120191817161513 14121110 313029289876543210

Cond Rn Data/Processing/

Cond
Cond

Cond
Cond
Cond

Cond

Cond
Cond
Cond
Cond
Cond

Cond

Cond

Cond

0 0 I S

0 0 0 0 00 A S

0 0 0 0 0 01 B

0 0 0 P U 0 W L

0 0 0 P U 1 W L

0 1 I P U B W L
0 1 I
1 0 0 P U B W L
1 0 L1
1 1 0 P U B W L

1 1 01

1 1 01 L

1 1 11

Opcode

1 00 010 0 0

CP Opc

CP

Opc

Rd

Rd

A SU10 0 00

Rn

11 11 1 1 11

Rn

Rn

Rn

Rn Register List

Rn

CRn

CRn

Rn

Rd

Rd

Rd

Rd

Offset

CRd OffsetCP#

CRd

Rd

Ignored by processor

Operand2

Rs

RnRdHi RdLo

0

0

1

1

0

0

Offset Offset

CP#

CP#

1
1
1

0

0

0

1

1

1

0

0

1

0

0

0

0

0

0

0

0

H

S

H

S

Offset

CP

CP

1
1
1
1
1

1

1

CRm

0

CRm

1

Rm
Rm
Rm

Rn

Rm

PSR Transfer
Multiply
Multiply Long

Single Data Swap
Branch and Exchange
Halfword Data Transfer:

register offset
Halfword Data Transfer:

immendiate offset
Single Data Transfer

Undefined
Block Data Transfer
Branch
Coprocessor Data Transfer

Coprocessor Data Operation

Coprocessor Register Transfer

Software Interrupt

2726252423222120191817161513 14121110 313029289876543210

Figure 3-1. ARM Instruction Set Format

3-1

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

NOTES

Some instruction codes are not defined but does not cause Undefined instruction trap to be taken, for
instance a multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their
action may change in future ARM implementations.

INSTRUCTION SUMMARY

Table 3-1. The ARM Instruction Set

Mnemonic Instruction Action

ADC Add with carry Rd: = Rn + Op2 + Carry
ADD Add Rd: = Rn + Op2
AND AND Rd: = Rn AND Op2

B Branch R15: = address

BIC Bit clear Rd: = Rn AND NOT Op2

BL Branch with link R14: = R15, R15: = address
BX Branch and exchange R15: = Rn, T bit: = Rn[0]

CDP Coprocessor data processing (Coprocessor-specific)
CMN Compare Negative CPSR flags: = Rn + Op2
CMP Compare CPSR flags: = Rn - Op2
EOR Exclusive OR Rd: = (Rn AND NOT Op2)

OR (Op2 AND NOT Rn)

LDC Load coprocessor from memory Coprocessor load

LDM Load multiple registers Stack manipulation (Pop)

LDR Load register from memory Rd: = (address)

MCR Move CPU register to coprocessor

cRn: = rRn {<op>cRm}

register

MLA Multiply accumulate Rd: = (Rm × Rs) + Rn

MOV Move register or constant Rd: = Op2

3-2

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

Table 3-1. The ARM Instruction Set (Continued)

Mnemonic Instruction Action

MRC Move from coprocessor register to

Rn: = cRn {<op>cRm}

CPU register
MRS Move PSR status/flags to register Rn: = PSR
MSR Move register to PSR status/flags PSR: = Rm

MUL Multiply Rd: = Rm × Rs
MVN Move negative register Rd: = 0 × FFFFFFFF EOR Op2
ORR OR Rd: = Rn OR Op2

RSB Reverse subtract Rd: = Op2 - Rn

RSC Reverse subtract with Carry Rd: = Op2 - Rn - 1 + Carry

SBC Subtract with Carry Rd: = Rn - Op2 - 1 + Carry

STC Store coprocessor register to memory address: = CRn

STM Store Multiple Stack manipulation (Push)

STR Store register to memory <address>: = Rd

SUB Subtract Rd: = Rn - Op2

SWI Software Interrupt OS call

SWP Swap register with memory Rd: = [Rn], [Rn] := Rm

TEQ Test bitwise equality CPSR flags: = Rn EOR Op2

TST Test bits CPSR flags: = Rn AND Op2

3-3

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

THE CONDITION FIELD

In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the
instruction's condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be
executed. If the state of the C, N, Z and V flags fulfils the conditions encoded by the field, the instruction is
executed, otherwise it is ignored.

There are sixteen possible conditions, each represented by a two-character suffix that can be appended to the
instruction's mnemonic. For example, a Branch (B in assembly language) becomes BEQ for "Branch if Equal", which
means the Branch will only be taken if the Z flag is set.

In practice, fifteen different conditions may be used: these are listed in Table 3-2. The sixteenth (1111) is reserved,
and must not be used.

In the absence of a suffix, the condition field for most instructions is set to "Always" (suffix AL). This means the
instruction will always be executed regardless of the CPSR condition codes.

Table 3-2. Condition Code Summary

Code Suffix Flags Meaning

0000 EQ Z set equal
0001 NE Z clear not equal
0010 CS C set unsigned higher or same
0011 CC C clear unsigned lower
0100 MI N set negative
0101 PL N clear positive or zero
0110 VS V set overflow
0111 VC V clear no overflow
1000 HI C set and Z clear unsigned higher
1001 LS C clear or Z set unsigned lower or same
1010 GE N equals V greater or equal
1011 LT N not equal to V less than
1100 GT Z clear AND (N equals V) greater than
1101 LE Z set OR (N not equal to V) less than or equal
1110 AL (ignored) always

3-4

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

BRANCH AND EXCHANGE (BX)

This instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.
This instruction performs a branch by copying the contents of a general register, Rn, into the Program Counter, PC.

The branch causes a pipeline flush and refill from the address specified by Rn. This instruction also permits the
instruction set to be exchanged. When the instruction is executed, the value of Rn[0] determines whether the
instruction stream will be decoded as ARM or THUMB instructions.

31 2427 19 15 8 7 0

28 16 111223 20 4 3

00 0 1 10 0 0 11 1 1 11 1 1 11 1 1 00 0 1Cond Rn

[3:0] Operand Register

If bit0 of Rn = 1, subsequent instructions decoded as THUMB instructions
If bit0 of Rn =0, subsequent instructions decoded as ARM instructions

[31:28] Condition Field

Figure 3-2. Branch and Exchange Instructions

INSTRUCTION CYCLE TIMES

The BX instruction takes 2S + 1N cycles to execute, where S and N are defined as sequential (S-cycle) and non­sequential (N-cycle), respectively.

ASSEMBLER SYNTAX

BX - branch and exchange.
BX {cond} Rn

{cond} Two character condition mnemonic. See Table 3-2.
Rn is an expression evaluating to a valid register number.

USING R15 AS AN OPERAND

If R15 is used as an operand, the behavior is undefined.

3-5

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

Examples

ADR R0, Into_THUMB + 1 Generate branch target address and set bit 0 high – hence it comes in

THUMB state

BX R0 Branch and change to THUMB state.
CODE16 Assemble subsequent code as
Into_THUMB THUMB instructions
ADR R5, Back_to_ARM Generate branch target to word aligned address

hence bit 0 is low and so change back to ARM state.

BX R5 Branch and change back to ARM state.
ALIGN Word alignment
CODE32 Assemble subsequent code as ARM instructions
Back_to_ARM –

3-6

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

BRANCH AND BRANCH WITH LINK (B, BL)

The instruction is only executed if the condition is true. The various conditions are defined Table 3-2. The instruction
encoding is shown in Figure 3-3, below.

31 2427

28 23

Cond Offset

25

101 L

0

[24] Link bit

0 = Branch 1 = Branch with link

[31:28] Condition Field

Figure 3-3. Branch Instructions

Branch instruction contains a signed 2's complement 24 bit offset. This is shifted left two bits, sign extended to 32
bits, and added to the PC. The instruction can therefore specify a branch of +/- 32Mbytes. The branch offset must
take account of the prefetch operation, which causes the PC to be 2 words (8 bytes) ahead of the current instruction.

Branches beyond +/- 32Mbytes must use an offset or absolute destination which has been previously loaded into a
register. In this case the PC should be manually saved in R14 if a Branch with Link type operation is required.

THE LINK BIT

Branch with Link (BL) writes the old PC into the link register (R14) of the current bank. The PC value written into R14
is adjusted to allow for the prefetch, and contains the address of the instruction following the branch and link
instruction. Note that the CPSR is not saved with the PC and R14[1:0] are always cleared.

To return from a routine called by Branch with Link use MOV PC,R14 if the link register is still valid or LDM
Rn!,{..PC} if the link register has been saved onto a stack pointed to by Rn.

INSTRUCTION CYCLE TIMES

Branch and Branch with Link instructions take 2S + 1N incremental cycles, where S and N are defined as sequential
(S-cycle) and internal (I-cycle).

3-7

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

ASSEMBLER SYNTAX
Items in “{}” are optional. Items in “<>” must be present.
B{L}{cond} <expression>

{L}

Used to request the Branch with Link form of the instruction.
If absent, R14 will not be affected by the instruction.

{cond}

A two-character mnemonic as shown in Table 3-2.
If absent then AL (ALways) will be used.

<expression>

The destination. The assembler calculates the offset

Examples
here BAL here ; Assembles to 0xEAFFFFFE (note effect of PC offset).

B there ; Always condition used as default.
CMP R1,#0 ; Compare R1 with zero and branch to fred

if R1 was zero, otherwise continue.

BEQ fred ; Continue to next instruction.
BL sub+ROM ; Call subroutine at computed address.
ADDS R1,#1 ; Add 1 to register 1, setting CPSR flags

on the result then call subroutine if

BLCC sub ; the C flag is clear, which will be the

case unless R1 held 0xFFFFFFFF.

3-8

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

DATA PROCESSING

The data processing instruction is only executed if the condition is true. The conditions are defined in Table 3-2. The
instruction encoding is shown in Figure 3-4.

31 2427 19 15

28 16 111221

26 25

Cond Operand2

00 L20OpCode S Rn Rd

[15:12] Destination register

0 = Branch 1 = Branch with link

[19:16] 1st operand register

0 = Branch 1 = Branch with link

[20] Set condition codes

0 = Do not after condition codes 1 = Set condition codes

[24:21] Operation codes

0000 = AND-Rd: = Op1 AND Op2
0001 = EOR-Rd: = Op1 EOR Op2
0010 = SUB-Rd: = Op1-Op2
0011 = RSB-Rd: = Op2-Op1
0100 = ADD-Rd: = Op1+Op2
0101 = ADC-Rd: = Op1+Op2+C
0110 = SBC-Rd: = OP1-Op2+C-1
0111 = RSC-Rd: = Op2-Op1+C-1
1000 = TST-set condition codes on Op1 AND Op2
1001 = TEO-set condition codes on OP1 EOR Op2
1010 = CMP-set condition codes on Op1-Op2
1011 = SMN-set condition codes on Op1+Op2
1100 = ORR-Rd: = Op1 OR Op2
1101 = MOV-Rd: =Op2
1110 = BIC-Rd: = Op1 AND NOT Op2
1111 = MVN-Rd: = NOT Op2

0

[25] Immediate operand

0 = Operand 2 is a register 1 = Operand 2 is an immediate value

[11:0] Operand 2 type selection

311 04

Shift

[3:0] 2nd operand register [11:4] Shift applied to Rm

811 07

Rotate

[7:0] Unsigned 8 bit immediate value [11:8] Shift applied to Imm

Imm

Rm

[31:28] Condition field

Figure 3-4. Data Processing Instructions

3-9

ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands.
The first operand is always a register (Rn).

The second operand may be a shifted register (Rm) or a rotated 8 bit immediate value (Imm) according to the value of
the I bit in the instruction. The condition codes in the CPSR may be preserved or updated as a result of this
instruction, according to the value of the S bit in the instruction.

Certain operations (TST, TEQ, CMP, CMN) do not write the result to Rd. They are used only to perform tests and to
set the condition codes on the result and always have the S bit set. The instructions and their effects are listed in
Table 3-3.

3-10

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

CPSR FLAGS

The data processing operations can be classified as logical or arithmetic. The logical operations (AND, EOR, TST,
TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to
produce the result. If the S bit is set (and Rd is not R15, see below) the V flag in the CPSR will be unaffected. The C
flag will be set to the carry out from the barrel shifter (or preserved when the shift operation is LSL #0), the Z flag will
be set if and only if the result is all zeros, and the N flag will be set to the logical value of bit 31 of the result.

Table 3-3. ARM Data Processing Instructions

Assembler Mnemonic OP Code Action

AND 0000 Operand1 AND operand2
EOR 0001 Operand1 EOR operand2

WUB 0010 Operand1 - operand2

RSB 0011 Operand2 operand1

ADD 0100 Operand1 + operand2

ADC 0101 Operand1 + operand2 + carry

SBC 0110 Operand1 - operand2 + carry - 1

RSC 0111 Operand2 - operand1 + carry - 1

TST 1000 As AND, but result is not written

TEQ 1001 As EOR, but result is not written
CMP 1010 As SUB, but result is not written
CMN 1011 As ADD, but result is not written
ORR 1100 Operand1 OR operand2

MOV 1101 Operand2 (operand1 is ignored)

BIC 1110 Operand1 AND NOT operand2 (Bit clear)

MVN 1111 NOT operand2 (operand1 is ignored)

The arithmetic operations (SUB, RSB, ADD, ADC, SBC, RSC, CMP, CMN) treat each operand as a 32 bit integer
(either unsigned or 2's complement signed, the two are equivalent). If the S bit is set (and Rd is not R15) the V flag in
the CPSR will be set if an overflow occurs into bit 31 of the result; this may be ignored if the operands were
considered unsigned, but warns of a possible error if the operands were 2's complement signed. The C flag will be
set to the carry out of bit 31 of the ALU, the Z flag will be set if and only if the result was zero, and the N flag will be
set to the value of bit 31 of the result (indicating a negative result if the operands are considered to be 2's
complement signed).

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

SHIFTS

When the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the
Shift field in the instruction. This field indicates the type of shift to be performed (logical left or right, arithmetic right or
rotate right). The amount by which the register should be shifted may contain an immediate field in the instruction, or
in the bottom byte of another register (other than R15). The encoding for the different shift types is shown in Figure 3-

5.

456711

0

[6:5] Shift type

00 = logical left 01 = logical right
10 = arithmetic right 11 = rotate right

[11:7] Shift amount

5 bit unsigned integer

0RS

[6:5] Shift type

00 = logical left 01 = logical right
10 = arithmetic right 11 = rotate right

[11:8] Shift register

Shift amount specified in bottom-byte of Rs

456711 8

1

Figure 3-5. ARM Shift Operations

Instruction specified shift amount

When the shift amount is specified in the instruction, it is contained in a 5 bit field which can take any value from 0 to

31. A Logical Shift Left (LSL) takes the contents of Rm and moves each bit by the specified amount to a more
significant position. The least significant bits of the result are filled with zeros, and the high bits of Rm which do not
map into the result are discarded, except that the least significant discarded bit becomes the shifter carry output
which may be latched into the C bit of the CPSR when the ALU operation is in the logical class (see above). For
example, the effect of LSL #5 is shown in Figure 3-6.

31 27 26

Contents of Rm

carry out

Value of Operand 2

Figure 3-6. Logical Shift Left

NOTE

LSL #0 is a special case, where the shifter carries out is the old value of the CPSR C flag. The contents of
Rm are used directly as the second operand. A Logical Shift Right (LSR) is similar, but the contents of
Rm are moved to less significant positions in the result. LSR #5 has the effect shown in Figure 3-7.

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000000

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

31

45

Contents of Rm

00000

Value of Operand 2

0

carry out

Figure 3-7. Logical Shift Right

The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a
zero result with bit 31 of Rm as the carry output. Logical shift right zero is redundant as it is the same as logical shift
left zero, so the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL #0, and allow LSR #32 to be
specified.

An Arithmetic Shift Right (ASR) is similar to logical shift right, except that the high bits are filled with bit 31 of Rm
instead of zeros. This preserves the sign in 2's complement notation. For example, ASR #5 is shown in Figure
3-8.

31

4530

Contents of Rm

Value of Operand 2

0

carry out

Figure 3-8. Arithmetic Shift Right

The form of the shift field which might be expected to give ASR #0 is used to encode ASR #32. Bit 31 of Rm is again
used as the carry output, and each bit of operand 2 is also equal to bit 31 of Rm. The result is therefore all ones or
all zeros, according to the value of bit 31 of Rm.

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

Rotate right (ROR) operations reuse the bits which "overshoot" in a logical shift right operation by reintroducing them
at the high end of the result, in place of the zeros used to fill the high end in logical right operations. For example,
ROR #5 is shown in Figure 3-9.

31

45

Contents of Rm

Value of Operand 2

0

carry out

Figure 3-9. Rotate Right

The form of the shift field which might be expected to give ROR #0 is used to encode a special function of the barrel
shifter, rotate right extended (RRX). This is a rotate right by one bit position of the 33 bit quantity formed by
appending the CPSR C flag to the most significant end of the contents of Rm as shown in Figure 3-10.

31

Contents of Rm

C
in

01

carry out

3-14

Value of Operand 2

Figure 3-10. Rotate Right Extended

S3C2440A RISC MICROPROCESSOR ARM INSTRUCTION SET

Register Specified Shift Amount

Only the least significant byte of the contents of Rs is used to determine the shift amount. Rs can be any general
register other than R15.

If this byte is zero, the unchanged contents of Rm will be used as the second operand, and the old value of the
CPSR C flag will be passed on as the shifter carry output.

If the byte has a value between 1 and 31, the shifted result will exactly match that of an instruction specified shift
with the same value and shift operation.

If the value in the byte is 32 or more, the result will be a logical extension of the shift described above:

1. LSL by 32 has result zero, carry out equal to bit 0 of Rm.

2. LSL by more than 32 has result zero, carry out zero.

3. LSR by 32 has result zero, carry out equal to bit 31 of Rm.

4. LSR by more than 32 has result zero, carry out zero.

5. ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm.

6. ROR by 32 has result equal to Rm, carry out equal to bit 31 of Rm.

7. ROR by n where n is greater than 32 will give the same result and carry out as ROR by n-32; therefore
repeatedly subtract 32 from n until the amount is in the range 1 to 32 and see above.

NOTE

The zero in bit 7 of an instruction with a register controlled shift is compulsory; a one in this bit will cause
the instruction to be a multiply or undefined instruction.

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ARM INSTRUCTION SET S3C2440A RISC MICROPROCESSOR

IMMEDIATE OPERAND ROTATES

The immediate operand rotate field is a 4 bit unsigned integer which specifies a shift operation on the 8 bit immediate
value. This value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field.
This enables many common constants to be generated, for example all powers of 2.

WRITING TO R15

When Rd is a register other than R15, the condition code flags in the CPSR may be updated from the ALU flags as
described above.

When Rd is R15 and the S flag in the instruction is not set the result of the operation is placed in R15 and the CPSR
is unaffected.

When Rd is R15 and the S flag is set the result of the operation is placed in R15 and the SPSR corresponding to the
current mode is moved to the CPSR. This allows state changes which automatically restore both PC and CPSR.
This form of instruction should not be used in User mode.

USING R15 AS AN OPERANDY

If R15 (the PC) is used as an operand in a data processing instruction the register is used directly.
The PC value will be the address of the instruction, plus 8 or 12 bytes due to instruction prefetching. If the shift

amount is specified in the instruction, the PC will be 8 bytes ahead. If a register is used to specify the shift amount
the PC will be 12 bytes ahead.

TEQ, TST, CMP AND CMN OPCODES

NOTE

TEQ, TST, CMP and CMN do not write the result of their operation but do set flags in the CPSR. An
assembler should always set the S flag for these instructions even if this is not specified in the mnemonic.

The TEQP form of the TEQ instruction used in earlier ARM processors must not be used: the PSR transfer
operations should be used instead.

The action of TEQP in the ARM920T is to move SPSR_<mode> to the CPSR if the processor is in a privileged mode
and to do nothing if in User mode.

INSTRUCTION CYCLE TIMES

Data Processing instructions vary in the number of incremental cycles taken as follows:

Table 3-4. Incremental Cycle Times

Processing Type Cycles

Normal data processing 1S
Data processing with register specified shift 1S + 1I
Data processing with PC written 2S + 1N
Data processing with register specified shift and PC written 2S + 1N +1I

NOTE: S, N and I are as defined sequential (S-cycle), non-sequential (N-cycle), and internal (I-cycle) respectively.

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