Samsung KS8701 Datasheet

KS8701

DATA SHEET

FLEX

Roaming Decoder II

March, 2000

KS8701 Features

KS8701

FLEXTM ROAMING DECODER II DATA SHEET

FEATURES

l FLEX l 16 programmable user address words l 16 fixed temporary addresses l 16 operator messaging addresses l 1600,3200,and 6400bps(bits per second) decoding l Any-phase or single-phase decoding l Uses standard Serial Peripheral Interface (SPI) in slave mode l Allow low current STOP mode operation of host processor l Highly programmable receiver control l Real time clock time base l FLEX fragmentation and group messaging support l Real time clock over-the-air update support l Compatible with synthesized receivers l SSID and NID Roaming support l Low Battery Indication(External detector) l 28 used pins (32-pin package standard) l Backward compatible to the standard and roaming FLEX decoder ICs

paging protocol decoder

l Internal demodulator and data slicer l Improved battery savings via partial correlation and intermittent receiver clock l Full support for revision 1.9 of the FLEX protocol l 32-pin LQFP package

DESCRIPTION

This FLEXTM Roaming Decoder II date sheet describes the operation of the KS8701.

The KS8701 simplifies implementation of a FLEXTM paging device by interfacing with any of several off-theshelf paging receivers and any of several off-the-shelf host microcontroller/microprocessors. Its primary function is to process information received and demodulated from a FLEX radio paging channel, select messages addressed to the paging device and communicate the message information to the host.

The KS8701 also operates the paging receiver in an efficient power consumption mode and enables the host to operate in a low power mode when monitoring a signal channel for message information.

FLEXTM Roaming Decoder II 1

Ordering Information KS8701

ORDERING INFORMATION

Device

Name

KS8701 1.8V ~ 3.6V 76.8kHz or 160kHz

Supply

Voltage

Operating

Frequency

Operating

Temperature

-25¡É~ 85¡É

Package Type

32-LQFP-0707

Samsung Electronics reserves the right to make changes without notice.

Motorola, FLEX and FLEXstack are trademarks of Motorola Inc.

2 FLEXTM Roaming Decoder II

KS8701 Table Of Contents

Table Of Contents

Introduction ...........................................................................................................................5

System Block Diagram ............................................................................................................5

Functional Block Diagram .......................................................................................................7

Pin Description ........................................................................................................................8

Mechanical Specification..........................................................................................................10

SPI Packets ...........................................................................................................................11

Packet Communication Initiated by the Host ...........................................................................11

Packet Communication Initiated by the FLEX Decoder IC .......................................................12

Host-to-Decoder Packet Map ..................................................................................................13

Decoder-to-Host Packet Map ..................................................................................................15

Host-to-Decoder Packet Descriptions .................................................................................16

Checksum Packet ...................................................................................................................16

Configuration Packet ...............................................................................................................18

Control Packet ........................................................................................................................21

All Frame Mode Packet ...........................................................................................................23

Operator Messaging Address Enable Packet ..........................................................................24

Roaming Control Packet .........................................................................................................25

Timing Control Packet .............................................................................................................28

Receiver Line Control Packet ..................................................................................................29

Receiver Control Configuration Packets ..................................................................................30

Frame Assignment Packets ....................................................................................................35

User Address Enable Packet ..................................................................................................36

User Address Assignment Packets .........................................................................................37

Decoder-to-Host Packet Descriptions .................................................................................38

Block Information Word Packet ...............................................................................................39

Address Packet .......................................................................................................................41

Vector Packet .........................................................................................................................42

Message Packet ..................................................................................................................... 47

Roaming Status Packet ..........................................................................................................48

Receiver Shutdown Packet .....................................................................................................50

Status Packet ..........................................................................................................................51

Part ID Packet .........................................................................................................................53

FLEXTM Roaming Decoder II 3

Table Of Contents KS8701

Table Of Contents (continued)

Appendix A : Application Notes .......................................................................................... 55

Receiver Control .....................................................................................................................55

Message Building ...................................................................................................................59

Building a Fragmented Message ............................................................................................61

Operation of a Temporary Address .........................................................................................64

Using the Receiver Shutdown Packet .....................................................................................66

Appendix B : Specifications ................................................................................................ 68

Absolute Maximum Ratings ....................................................................................................68

DC Characteristics ..................................................................................................................68

AC Characteristics ..................................................................................................................69

4 FLEXTM Roaming Decoder II

KS8701 Introduction

Control

Detector

Synthesizer

KS8701

160

kHz 10MΩ

INTRODUCTION

SYSTEM BLOCK DIAGRAM

Programming Control

Receiver

Host

Microprocessor

User

Interface

S0/IFIN

38.4 or 40 kHz Clock

Receiver

15pF

Low Battery

LOBAT

15pF

Figure 1 : Example Block Diagram Using Internal Demodulator

When configured to use the internal demodulator, the KS8701 connects to a receiver capable of generating a limited (i.e. 1-bit digitized) 455 kHz or 140 kHz IF signal. In this mode, the KS8701 has 7 receiver control lines used for warming up and shutting down a receiver in stages. The KS8701 has the ability to detect a low battery signal during the receiver control sequences. It interfaces to a host MCU through a standard SPI. It has a 1minute timer that offers low power support for a time of day function on the host.

When using the internal demodulator, the oscillator frequency (or external clock) must be 160 kHz. The CLKOUT signal can be programmed to be either a 38.4 kHz signal created by fractionally dividing the oscillator clock, or a 40 kHz signal creating by dividing the oscillator clock by 4.

FLEXTM Roaming Decoder II 5

Introduction KS8701

Detector

Synthesizer

LOBAT

KS8701

76.8

kHz 10MΩ

Programming Control

Receiver

Control

Host

Microprocessor

User

Interface

Audio

Audio to

Digital

Converter

EXTS1 EXTS0

38.4 kHz Clock

10pF

Low Battery

10pF

Figure 2 : Example Block Diagram Using External Demodulator

The KS8701 can also be configured to connect to a receiver capable of converting a 4 level audio signal into a 2 bit digital signal. In this mode, the KS8701 has a 8 receiver control lines used for warming up and shutting down a receiver in stages. It also includes configuration setting for the two post detection filter bandwidths required to decode the two symbol rates of the FLEX signal. Also when using an external demodulator, the oscillator frequency (or external clock) must be 76.8 kHz and the CLKOUT signal (when enabled) is 38.4kHz clock output capable of driving other devices.

6 FLEXTM Roaming Decoder II

KS8701 Introduction

TEST2

TEST3

RESET

LOBAT

READY

S0 / IFIN

Detector

S0 – S7

EXTS1

EXTAL

VSS

FUNCTIONAL BLOCK DIAGRAM

EXTS0

SYMCLK

OSCPD

XTAL

CLKOUT

IFIN

76.8kHz

or 160kHz

Oscillator

Clock

Generator

S1-S7

Receiver

Control

Demodulator & Data Slicer

Symbol

Sync

Correlator

Deinterleaver

Internal Control

Unit

2 VDD

Noise

External

Control

Unit

Error

Corrector

Address

Comparator/

Correlator

Figure 3 : Block Diagram

FLEXTM Roaming Decoder II 7

Local

Message

Filter

SPI

Buffer

Control /

Status

Registers

SPI

4 SPI

Introduction KS8701

PIN DESCRIPTION

PIN NAME PIN TYPE DESCRIPTION

Power

LOBAT

RESET

EXTS1 EXTS0

SS SCK MOSI MISO READY

CLKOUT

3,13 Power 7,29 Ground

10 I Low battery detect input

Reset

24 I Active low reset to the KS8701.

External Symbol Input Signals

11 I MSb of the symbol currently being decoded 12 I LSb of the symbol currently being decoded

SPI Signals

27 I Slave Select for SPI communications 28 I Serial Clock for SPI communications 30 I Data input for SPI communications 31 O Three-state data output for SPI communications 26 O Driven low when the IC is ready for an SPI packet

Clock Signals

32 O 38.4 kHz or 40 kHz clock output(derived from oscillator)

SYMCLK EXTAL XTAL

14 O Recovered symbol clock

6 I 76.8 kHz or 160 kHz crystal input or external input 5 O 76.8 kHz or 160 kHz clock output

Internal oscillator power down.

OSCPD

2 I

Connected to VSS when using internal oscillator. Connected to VDD when using an external source.

Receiver Control Lines

S1 - S7

S0 / IFIN

22,21,20,19,

18,16,15

23 O / I

O Seven three-state receiver control output

S0 : Receiver control output when using external demodulator IFIN : Limited IF input when using internal demodulator

Test pins

TEST2, TEST3

8 FLEXTM Roaming Decoder II

4,8 I

1,9,17,25 O

IC manufacturing test mode pin. Normally connected to VSS.

IC manufacturing test mode pin. Normally connected to VSS. (Can be left unconnected.)

KS8701 Introduction

RESET

S0/IFINS1S2

S3 20

S4 19

S5 18

READY

SCK

MOSI

MISO

CLKOUT

KS8701

32 9

OSCPD

TEST2

XTAL

EXTAL

TEST3

SYMCLK

EXT0

EXT1

LOBAT

Figure 4 : KS8701 32-LQFP Top View

FLEXTM Roaming Decoder II 9

Introduction KS8701

MECHANICAL SPECIFICATION

PACKAGE DEMENSION

TOP VIEW

-D-

E1/2

-A3

SEE DETAIL "A"

N/4 TIPS

0.20 C A-B D 4X

D1/2

0.20 H A-B D

5 6

8 PLACES 11/13¡Æ

0.05

NOTES:

1. ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5-1982.

2. DATUM PLANE LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE.

3. DATUMS AND TO BE DETERMINED AT CENTERLINE BETWEEN LEADS WHERE LEADS EXIT PLASTIC BODY AT DATUM PLANE

4. TO BE DETERMINED AT SEATING PLANE

5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION, ALLOWABLE MOLD PROTRUSION IS 0.254mm ON D1 AND E1 DIMENSIONS.

6. THESE DIMENSIONS TO BE DETERMINED AT DATUM PLANE

7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION, ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.

8. CONTROLLING DIMENSION : MILLIMETER

9. A1 IS DEFINED AS THE DISTANCE FROM THE SEATING PLANE TO THE LOWEST POINT OF THE PACKAGE BODY.

- H -

- D -A - B

- H -

- C -

D/2

169

SEE DETAIL "C"

- H -

-B-

E/2

-H-

-CSEE DETAIL "B"

- 0.05 S

ccc

// 0.10 C

-A,B, OR D-

DETAIL "A"

DATUM PLANE

-H-

0.08 R. MIN.

0.20 MIN.

1.00 REF.

DETAIL "B"

ddd M C A-B S D S

0.09/0.20 0.09/0.16

DETAIL "C"

UNIT : mm

SYMBOL

ccc ddd

A A1 A2

D D1

E E1

b b1

MIN MAX

~ 1.60

0.05 0.15

1.35 1.45

9.00 BSC

7.00 BSC

9.00 BSC

7.00 BSC

0.45 0.75

0.80 BSC

0.30 0.45

0.30 0.40 ~ 0.10 ~ 0.20

e/2

0¡ÆMIN

0.08/0.20 R.

0.25

0-7¡Æ

WITH LEAD FINISH

BASE METAL

NOTE

4 6 4 6

Figure 5 : 32-LQFP-0707 Package Dimension

10 FLEXTM Roaming Decoder II

KS8701 SPI Packets

D0D1D31

D31

D31D1D0D0D1

D0D1D31

D31D0D1

D31

MOSI

SPI PACKETS

All data communicated between the KS8701 and the host MCU is transmitted on the SPI in 32-bit packets. Each packet consists of an 8-bit ID followed by 24 bits of information. The KS8701 uses the SPI bus in full duplex mode. In other words, whenever a packet communication occurs, the data in both directions is valid packet data.

The SPI interface consists of a READY pin and four SPI pins (SS, SCK, MOSI, and MISO). The SS is used as a chip select for the KS8701. The SCK is a clock supplied by the host MCU. The data from the host is transmitted on the MOSI(Master-Out-Slave-In) line. The data from the KS8701 is transmitted on the MISO(Master-In-Slave- Out) line.

Timing requirements for SPI communication are specified in “SPI Timing” on page 69.

PACKET COMMUNICATION INITIATED BY THE HOST

Refer to figure 6 on page 11. When the host sends a packet to the KS8701, it performs the following steps:

1. Select the KS8701 by driving the SS pin low.

2. Wait for the KS8701 to drive the READY pin low.

3. Send the 32-bit packet.

4. De-select the KS8701 by driving the SS pin high.

5. Repeat steps 1 through 4 for each additional packet.

READY

SCK

MISO

When the host sends a packet, it will also receive a valid packet from the KS8701. If the KS8701 is enabled (see “Checksum Packet” on page 16 for a definition of enabled) and has no other packets waiting to be sent, the KS8701 will send a status packet.

The host must transition the SS pin from high to low to begin each 32-bit packet. The KS8701 must see a negative transition on the SS pin in order for the host to initiate each packet communication.

Figure 6: Typical Multiple Packet Communications Initiated by the Host

High impedance state

FLEXTM Roaming Decoder II 11

SPI Packets KS8701

D31

READY

%"#

D31

PACKET COMMUNICATION INITIATED BY THE FLEX DECODER IC

Refer to figure 7 on page 12. When the KS8701 has a packet for the host to read, the following occurs:

1. The KS8701 drives the READY pin low.

2. If the KS8701 is not already selected, the host selects the KS8701 by driving the SS pin low.

3. The host receives (and sends) a 32-bit packet.

4. The host de-selects the KS8701 by driving the SS pin high (optional).

SCK

MOSI

MISO

Figure 7: Typical Multiple Packet Communications Initiated by the FLEX decoder IC

When the host is reading a packet from the KS8701, it must send a valid packet to the KS8701. If the host has no data to send, it is suggested that the host send a Checksum Packet with all of the data bits set to 0 in order to avoid disabling the KS8701. See “Checksum Packet” on page 16 for more details on enabling and disabling the KS8701.

The following figure illustrates that it is not necessary to de-select the KS8701 between packets then the packets are initiated by the KS8701.

READY

SCK

MOSI

D1 D1 D0

D1 D1

D31

High impedance state

D31D31 D31

D1 D1

MISO

Figure 8: Multiple Packet Communications Initiated by the FLEX decoder IC with No De-select

12 FLEXTM Roaming Decoder II

D31 D1 D0

D31

High-impedance state

KS8701 SPI Packets

HOST-TO-DECODER PACKET MAP

The upper 8 bits of a packet comprise the packet ID. The following table describes the packet id’s for all of the

packets that can be sent to the KS8701 from the host.

Table 1: Host-to-Decoder Packet ID Map

Packet ID

(Hexadecimal)

Packet Type Page

00 Checksum 16 01 Configuration 18 02 Control 21 03 All Frame Mode 23 04 Operator Message Address Enables 24 05 Roaming Control Packet 25 06 Timing Control Packet 28

07 - 0E Reserved (Host should never send)

0F Receiver Line Control 29 10 Receiver Control Configuration (Off setting) 30 11 Receiver Control Configuration (Warm Up 1 Setting) 31 12 Receiver Control Configuration (Warm Up 2 Setting) 31 13 Receiver Control Configuration (Warm Up 3 Setting) 31 14 Receiver Control Configuration (Warm Up 4 Setting) 31 15 Receiver Control Configuration (Warm Up 5 Setting) 31 16 Receiver Control Configuration (3200sps Sync Setting) 32 17 Receiver Control Configuration (1600sps Sync Setting) 33 18 Receiver Control Configuration (3200sps Data Setting) 33 19 Receiver Control Configuration (1600sps Data Setting) 33 1A Receiver Control Configuration (Shut Down 1 Setting) 34 1B Receiver Control Configuration (Shut Down 2 Setting) 34

1C - 1F Special (Ignored by KS8701)

20 Frame-Assignment (Frames 112 through 127) 35 21 Frame Assignment (Frames 96 through 111) 35 22 Frame Assignment (Frames 80 through 95) 35 23 Frame Assignment (Frames 64 through 79) 35

FLEXTM Roaming Decoder II 13

SPI Packets KS8701

Table 1: Host-to-Decoder Packet ID Map (Continued)

Packet ID

(Hexadecimal)

Packet type Page

24 Frame Assignment (Frames 48 through 63) 35 25 Frame Assignment (Frames 32 through 47) 35 26 Frame Assignment (Frames 16 through 31) 35 27 Frame Assignment (Frames 0 through 15) 35

28 – 77 Reserved (Host should never send)

78 User Address Enable 36

79 - 7F Reserved (Host should never send)

80 User Address Assignment (User address 0) 37 81 User Address Assignment (User address 1) 37 82 User Address Assignment (User address 2) 37 83 User Address Assignment (User address 3) 37 84 User Address Assignment (User address 4) 37 85 User Address Assignment (User address 5) 37 86 User Address Assignment (User address 6) 37 87 User Address Assignment (User address 7) 37 88 User Address Assignment (User address 8) 37

89 User Address Assignment (User address 9). 37 8A User Address Assignment (User address 10) 37 8B User Address Assignment (User address 11) 37 8C User Address Assignment (User address 12) 37 8D User Address Assignment (User address 13) 37 8E User Address Assignment (User address 14) 37 8F User Address Assignment (User address 15) 37

90 - FF Reserved (Host should never send)

14 FLEXTM Roaming Decoder II

KS8701 SPI Packets

DECODER-TO-HOST PACKET MAP

The following table describes the packet ID’ s for all of the packets that can be sent to the host from the

KS8701.

Table 2: Decoder-to-Host Packet ID Map

Packet ID

(Hexadecimal)

Packet Type Page

00 Block Information Word 39

01 Address 41 02 - 57 Vector or Message (ID is word number in frame) 42 58 - 5F Reserved

60 Roaming Status Packet 48

61 - 7D Reserved

7E Receiver Shutdown 50

7F Status 51

80 - FE Reserved

FF Part ID 53

FLEXTM Roaming Decoder II 15

Host-to-Decoder Packet Descriptions KS8701

HOST-TO-DECODER PACKET DESCRIPTIONS

The following sections describe the packets of information sent from the host to the KS8701. In all cases the

packets should be sent MSB first (bit 7 of byte 3 = bit 31 of the packet = MSB).

CHECKSUM PACKET

The Checksum Packet is used to insure proper communication between the host and the KS8701. The KS8701 exclusive-or’s the 24 data bits of every packet it receives (except the Checksum Packet and the special packet ID’ s 1C through 1F hexadecimal) with an internal checksum register. Upon reset and whenever the host writes a packet to the KS8701, the KS8701 is disabled from sending any information to the host processor until the host processor sends a Checksum Packet with the proper checksum value (CV) to the KS8701. When the KS8701 is disabled in this way, it prompts the host to read the Part ID Packet. Note that all other operation continues normally when the KS8701 is “disabled”. Disabled only implies that data cannot be read, all other internal operations continue to function.

When the KS8701 is reset, it is disabled and the internal checksum register is initialized to the 24 bit part ID defined in the Part ID Packet. See “Part ID Packet” on page 53 for a description of the Part ID. Every time a packet other than the Checksum Packet and the special packets 1C through 1F is sent to the KS8701, the value sent in the 24 information bits is exclusive-or’ed with the internal checksum register, the result is stored back to the checksum register, and the KS8701 is disabled. If a Checksum Packet is sent and the CV bits match the bits in the checksum register, the KS8701 is enabled. If a Checksum Packet is sent when the KS8701 is already enabled, the packet is ignored by the KS8701 in which case a null packet having the ID and data bits set to 0 is suggested. If a packet other than the Checksum Packet is sent when the KS8701 is enabled, the KS8701 will be disabled until a Checksum Packet is sent with the correct CV bits.

When the host reads a packet out of the KS8701 but has no data to send, the Checksum Packet should be sent so the KS8701 will not be disabled. The data in the Checksum Packet could be a null packet (32 bit stream of all zeros) since a Checksum Packet will not disable the KS8701. When the host re-configures the KS8701, the KS8701 will be disabled from sending any packets other than the Part ID Packet until the KS8701 is enabled with a Checksum Packet having the proper data. The ID of the Checksum Packet is 0.

Table 3: Checksum Packet Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Byte 3 0 0 0 0 0 0. 0 0 Byte 2 CV Byte 1 CV Byte 0 CV

CV CV

CV: Checksum Value.

16 FLEXTM Roaming Decoder II

KS8701 Host-to-Decoder Packet Descriptions

Decoder initializes

Packet data

bits

RESET

Decoder disables itself

checksum register to

Part ID value

Decoder initiates

Pare ID Packet

Decoder enabled?

matches checksum

Decoder enables itself

Decoder waits for

SPI packet from host

Checksum Packet?

Decoder disables itself

Decoder sets checksum

the packet data bits with

the checksum register

Figure 9: FLEX Decoder IC Checksum Flow Chart

FLEXTM Roaming Decoder II 17

Host-to-Decoder Packet Descriptions KS8701

EXTAL

w/DFC=1

w/DFC=0

CONFIGURATION PACKET

The Configuration Packet defines a number of different configuration options for the KS8701. Proper operation is not guaranteed if these settings are changed when decoding is enabled (i.e. the ON bit in the Control Packet is set). The ID of the Configuration Packet is 1.

Table 4: Configuration Packet Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Byte 3 0 0 0 0 0 0 0 1 Byte 2 0 DFC 0 0 0 IDE OFD Byte 1 0 0 0 0 0 PCE SP

OFD

Byte 0 SME MOT COD MTE LBP ICO 0 0

DFC: Disable Fractional Clock. When this bit is set and IDE is set, the CLKOUT signal will generate a 40 kHz

signal (EXTAL divided by 4). When this bit is cleared and IDE is set, the CLKOUT signal will generate

38.4 kHz signal (EXTAL fractionally divided by 25/6 see diagram below). This bit has no effect when

IDE is cleared. (value after reset=0)

CLKOUT

IDE: Internal Demodulator Enable. When this bit is set , the internal demodulator is enabled and clock

frequency at EXTAL is expected to be 160 kHz. When this bit is cleared, the internal demodulator is disabled and the clock frequency at EXTAL is expected to be 76.8 kHz.(value after reset=0)

18 FLEXTM Roaming Decoder II

KS8701 Host-to-Decoder Packet Descriptions

OFD: Oscillator Frequency Difference. These bits describe the maximum difference in the frequency of the

76.8 kHz oscillator crystal with respect to the frequency of the transmitter. These limits should be the worst case difference in frequency due to all conditions including but not limited to aging, temperature, and manufacturing tolerance. Using a smaller frequency difference in this packet will result in lower power consumption due to higher receiver battery save ratios. Note that this value is not the absolute error of the oscillator frequency provided to the KS8701. The absolute error of the clock used by the FLEX transmitter must be taken into account. (e.g. If the transmitter tolerance is +/- 25 ppm and the

76.8 kHz oscillator tolerance is +/-140 ppm, the oscillator frequency difference is +/- 165 ppm and OFD should be set to 0.)(value after reset=0)

OFD1 OFD0 Frequency Difference

0 0 +/- 300 ppm 0 1 +/-150 ppm 1 0 +/- 75 ppm 1 1 +/- 0 ppm

PCE: Partial Correlation Enable. When this bit is set, partial correlation of addresses is enabled. When

partial correlation is enabled, the KS8701 will shutdown the receiver before the end of the last FLEX block which contains addresses if it can determine that none of the addresses in that FLEX block will match any enabled address in the KS8701. When this bit is cleared, the receiver will be controlled as it was in previous versions of the IC.(value after reset=0)

SP: Signal Polarity. These bits set the polarity of EXTS1 and EXTS0 input signals. (value after reset=0)

The polarity of the EXTS0 and EXTS1 bits will be determined by the receiver design.

FSK Modulation @SP = 0, 0

EXTS1 EXTS0

SP1 SP0

Signal Polarity

EXTS1 EXTS0

0 0 Normal Normal +4800 Hz 1 0 0 1 Normal Inverted +1600 Hz 1 1 1 0 Inverted Normal -1600 Hz 0 1 1 1 Inverted Inverted -4800 Hz 0 0

SME: Synchronous Mode Enable. When this bit is set, a Status Packet will be automatically sent whenever

the SMU (synchronous mode update) bit in the Status Packet is set. The host can use the SM (synchronous mode) bit in the Status Packet as an in-range/out-of-range indication. (value after reset=0)

MOT: Maximum Off Time. This bit has no effect if AST in the Timing Control Packet is non-zero. When

AST=0 and MOT=0, asynchronous A-word searches will time-out in 4 minutes. When AST=0 and MOT=1, asynchronous A-word searches will time-out in 1 minute. (value after reset=0)

FLEXTM Roaming Decoder II 19

Host-to-Decoder Packet Descriptions KS8701

COD: Clock Output Disable. When this bit is clear, a 38.4 kHz or 40kHz(depending on IDE and DFC) signal

will be output on the CLKOUT pin. When this bit is set, the CLKOUT pin will be driven low. Note that setting and clearing this bit can cause pulses on the CLKOUT pin that are less than one half the clock period. Also note that when the clock output is enabled and not set for clock intermittent operation(see ICO in this packet), the CLKOUT pin will always output the clock signal even when the KS8701 is in reset (as long as the KS8701 oscillator is seeing clocks). Further note that the when the KS8701 is used in internal demodulator mode(i.e. uses a 160 kHz oscillator), the CLKOUT pin will be 80 kHz from reset until the time the IDE bit is set. This is because the KS8701 defaults to external demodulator mode at reset. (value after reset=0)

MTE: Minute Timer Enable. When this bit is set, a Status Packet will be sent at one minute intervals with the

MT (minute time-out) bit in the Status Packet set. When this bit is clear, the internal one-minute timer

stops counting. The internal one-minute timer is reset when this bit is changed from 0 to 1 or when the MTC (minute timer clear) bit in the Control Packet is set. Note that the minute timer will not be accurate using a 160 kHz oscillator until the IDE bit is set. (value after reset=0)

LBP: Low Battery Polarity. This bit defines the polarity of the KS8701’s LOBAT pin. The LB bit in the Status

Packet is initialized to the inverse value of this bit when the KS8701 is turned on (by setting the ON bit in the Control Packet). When the KS8701 is turned on, the first low battery update in the Status Packet will be sent to the host when a low battery condition is detected on the LOBAT pin. Setting this bit means that a high on the LOBAT pin indicates a low voltage condition. (value after reset=0)

ICO: Intermittent Clock Out. When this bit is clear and COD is clear, a 38.4 kHz or 40 kHz (depending on

the values of IDE and DFC) signal will be output on the CLKOUT pin. When this bit is set and COD is clear, the clock will only be output on the CLKOUT pin while the receiver is not in the Off state. The clock will be output for a few cycles before the receiver transitions from the off state and for a few cycles after the receiver transitions to the off state (this is to insure that the receiver receives enough clocks to detect and process the changes to and from the Off state). The CLKOUT pin will be driven low when it is not driving a clock. Note that when the clock is automatically enabled and disabled (i.e. when ICO is set), the CLKOUT signal transitions will be clean(i.e. no pulses less than half the clock period) when it transitions between no clock and clocked output. This bit has no effect when COD is set. (value after reset=0)

20 FLEXTM Roaming Decoder II

KS8701 Host-to-Decoder Packet Descriptions

CONTROL PACKET

The Control Packet defines a number of different control bits for the KS8701. The ID of the Control Packet is 2.

Table 5: Control Packet Bit Assignments

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Byte 3 0 0 0 0 0 0 1 0 Byte 2 FF

Byte 1 0 SPM PS

FF PS

0 0 0 0

Byte 0 0 SBI 0 MTC 0 0 EAE ON

FF: Force Frame 0-7. These bits enable and disable forcing the KS8701 to look in frames 0 through 7.

When an FF bit is set, the KS8701 will decode the corresponding frame. Unlike the AF bits in the Frame Assignment Packets, the system collapse of a FLEX system will not affect frames assigned using the FF bits (e.g. Where as setting AF0 to 1 when the system collapse is 5 will cause the KS8701 to decode frames 0, 32, 64, and 96, setting FF0 to 1 when the system collapse is 5 will only cause the KS8701 to decode frame 0.). This may be useful for acquiring transmitted time information or channel attributes (e.g. Local ID). (value after reset =0)

SPM: Single Phase Mode. When this bit is set, the KS8701 will decode only one phase of the transmitted

data. When this bit is clear, the KS8701 will decode all of the phases it receives. A change to this bit while the KS8701 is on, will not take affect until the next block 0 of the next decoded frame. (value after reset =0)

PS: Phase Select. When the SPM bit is set, these bits define what phase the KS8701 should decode

according to the following table. This value is determined by the service provider. A change to these bits while the KS8701 is on, will not take affect until the next block 0 of a frame. (value after reset =0)

PS Value

Phase Decoded

(based on FLEX Data Rate)

PS1 PS0 1600bps 3200bps 6400bps

0 0 a a a 0 1 a a b 1 0 a c c 1 1 a c d

SBI: Send Block Information words 2-4. When this bit is set, any errored or time related block information

words 2-4 will be sent to the host. See “Block Information Word Packet” on page39 for a description of the words sent. (value after reset=0)

MTC: Minute Timer Clear. Setting this bit will cause the one minute timer to restart from 0.

FLEXTM Roaming Decoder II 21

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