Samsung K4S281632D-TL75, K4S281632D-TL55, K4S281632D-TL1L, K4S281632D-TL1H, K4S281632D-TC7C Datasheet

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CMOS SDRAM
K4S281632D
Rev. 0.1 Sept. 2001
128Mbit SDRAM
2M x 16Bit x 4 Banks
Synchronous DRAM
LVTTL
Rev. 0.1
Sept. 2001
CMOS SDRAM
K4S281632D
Rev. 0.1 Sept. 2001
Revision History Revision 0.0 (Mar. 06, 2001)
Revision 0.1 (Sep. 06, 2001)
Redefined IDD1 & IDD4 in DC Characteristics
Changed the Notes in Operating AC Parameter. < Before >
5. For 1H/1L, tRDL=1CLK and tDAL=1CLK+tRP is also supported . SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP. < After >
5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
CMOS SDRAM
K4S281632D
Rev. 0.1 Sept. 2001
The K4S281632D is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programma­ble burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high perfor­mance memory system applications.
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
GENERAL DESCRIPTIONFEATURES
FUNCTIONAL BLOCK DIAGRAM
2M x 16Bit x 4 Banks Synchronous DRAM
Bank Select
Data Input Register
2M x 16 2M x 16
Sense AMP
Output BufferI/O Control
Column Decoder
Latency & Burst Length
Programming Register
Address Register
Row Buffer
Refresh Counter
Row Decoder Col. Buffer
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS RAS CAS WE LDQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
2M x 16 2M x 16
Timing Register
UDQM
* Samsung Electronics reserves the right to change products or specification without notice.
ORDERING INFORMATION
Part No. Max Freq. Interface Package
K4S281632D-TC/L55 183MHz(CL=3)
LVTTL
54
TSOP(II)
K4S281632D-TC/L60 166MHz(CL=3) K4S281632D-TC/L7C 133MHz(CL=2) K4S281632D-TC/L75 133MHz(CL=3) K4S281632D-TC/L1H 100MHz(CL=2) K4S281632D-TC/L1L 100MHz(CL=3)
CMOS SDRAM
K4S281632D
Rev. 0.1 Sept. 2001
VDD
DQ0
VDDQ
DQ1 DQ2
VSSQ
DQ3 DQ4
VDDQ
DQ5 DQ6
VSSQ
DQ7
VDD
LDQM
WE CAS RAS
CS BA0 BA1
A10/AP
A0 A1 A2 A3
VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28
PIN CONFIGURATION (Top view)
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS N.C/RFU UDQM CLK CKE N.C A11 A9 A8 A7 A6 A5 A4 VSS
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs. CS Chip select
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM
CKE Clock enable
Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby.
A0 ~ A11 Address
Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8
BA0 ~ BA1 Bank select address
Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time.
RAS Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge.
CAS Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access.
WE Write enable
Enables write operation and row precharge. Latches data in starting from CAS, WE active.
L(U)DQM Data input/output mask
Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active.
DQ0 ~ 15 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
VDDQ/VSSQ Data output power/ground
Isolated power supply and ground for the output buffers to provide improved noise immunity.
N.C/RFU
No connection /reserved for future use
This pin is recommended to be left No Connection on the device.
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