SAMSUNG K4S280832B Technical data

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K4S280832B CMOS SDRAM

PIN CONFIGURATION (Top view)

VDD

A10/AP

PIN FUNCTION DESCRIPTION

DQ0

VDDQ

N.C

DQ1

VSSQ

N.C

DQ2

VDDQ

N.C

DQ3

VSSQ

N.C
VDD
N.C

WE
CAS
RAS

CS
BA0
BA1

A0
A1
A2
A3

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

VSS
DQ7
VSSQ
N.C
DQ6
VDDQ
N.C
DQ5
VSSQ
N.C
DQ4
VDDQ
N.C
VSS
N.C/RFU
DQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
VSS

54Pin TSOP (II)

(400mil x 875mil)

(0.8 mm Pin pitch)

Pin Name Input Function

CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select

CKE Clock enable

A0 ~ A11 Address

BA0 ~ BA1 Bank select address

RAS Row address strobe

CAS Column address strobe

WE Write enable

DQM Data input/output mask

DQ0 ~ 7 Data input/output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.

VDDQ/VSSQ Data output power/ground

N.C/RFU

No connection
/reserved for future use

Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.

Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11, Column address : CA0 ~ CA9

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.

Enables write operation and row precharge.
Latches data in starting from CAS, WE active.

Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.

Isolated power supply and ground for the output buffers to provide improved noise
immunity.

This pin is recommended to be left No Connection on the device.

Rev. 0.0 Aug. 1999