Samsung K4S281632F-TCL60, K4S281632F-TC75, K4S281632F-TC60, K4S280432F-TCL75, K4S280832F-TCL75 Datasheet
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Preliminary
SDRAM 128Mb F-die (x4, x8, x16)
128Mb F-die SDRAM Specification
CMOS SDRAM
Revision 0.2
November. 2003
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.2 November. 2003
Preliminary
SDRAM 128Mb F-die (x4, x8, x16)
Revision History
Revision 0.0 (Agust, 2003)
- First release.
Revision 0.1 (November, 2003)
- completed DC characteristics.
Revision 0.2 (November, 2003)
- Preliminary spec release.
CMOS SDRAM
Rev. 0.2 November. 2003
Preliminary
SDRAM 128Mb F-die (x4, x8, x16)
CMOS SDRAM
8M x 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K Cycle)
GENERAL DESCRIPTION
The K4S280432F / K4S280832F / K4S281632F is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x
8,388,608 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
Ordering Information
Part No. Orgainization Max Freq. Interface Package
K4S280432F-TC(L)75 32M x 4 133MHz LVTTL 54pin TSOP
K4S280832F-TC(L)75 16M x 8 133MHz LVTTL 54pin TSOP
K4S281632F-TC(L)60/75 8M x 16 166MHz LVTTL 54pin TSOP
Organization Row Address Column Address
32Mx4 A0~A11 A0-A9, A11
16Mx8 A0~A11 A0-A9
8Mx16 A0~A11 A0-A8
Row & Column address configuration
Rev. 0.2 November. 2003
Preliminary
SDRAM 128Mb F-die (x4, x8, x16)
Package Physical Dimension
#54
#1
22.62
MAX
0.891
22.22
± 0.10
± 0.004
0.875
0.10
MAX
0.004
0.71
( )
0.028
0.30
0.012
+0.10
-0.05
+0.004
-0.002
0.80
0.0315
#28
#27
0.21
0.008
CMOS SDRAM
MAX
0.05
0.002
0~8°C
0.45~0.75
0.50
MIN
0.018~0.030
)
0.020
(
0.25
TYP
0.010
0.400
± 0.10
± 0.004
10.16
0.125
0.005
0.047
1.20
+0.075
-0.035
+0.003
-0.001
11.76±0.20
0.463±0.008
± 0.05
1.00
± 0.002
0.039
54Pin TSOP Package Dimension
Rev. 0.2 November. 2003
Preliminary
SDRAM 128Mb F-die (x4, x8, x16)
FUNCTIONAL BLOCK DIAGRAM
Bank Select
CLK
ADD
Address Register
Refresh Counter
LRAS
Row Buffer
LCBR
Row Decoder Col. Buffer
Data Input Register
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
Column Decoder
Latency & Burst Length
Sense AMP
CMOS SDRAM
LWE
LDQM
Output BufferI/O Control
DQi
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS
* Samsung Electronics reserves the right to change products or specification without notice.
LCAS LWCBR
Timing Register
RAS CAS WE L(U)DQM
Programming Register
Rev. 0.2 November. 2003
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