SAMSUNG K4M56323LE Technical data
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K4M56323LE - M(E)E/N/S/C/L/R
2M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA
FEATURES
• 2.5V power supply.
• LVCMOS compatible with multiplexed address.
• Four banks operation.
• MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• Extended Temperature Operation (-25°C ~ 85°C).
• 2Chips DDP 90Balls FBGA with 0.8mm ball pitch
( -MXXX : Leaded, -EXXX : Lead Free).
Mobile-SDRAM
GENERAL DESCRIPTION
The K4M56323LE is 268,435,456 bits synchronous high data
rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits,
fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high performance memory system applications.
ORDERING INFORMATION
Part No. Max Freq. Interface Package
K4M56323LE-M(E)E/N/S/C/L/R80 125MHz(CL=3)
K4M56323LE-M(E)E/N/S/C/L/R1H 105MHz(CL=2)
K4M56323LE-M(E)E/N/S/C/L/R1L
- M(E)E/N/S : Normal / Low / Super Low Power, Extended Temperature(-25°C ~ 85°C)
- M(E)C/L/R : Normal / Low / Super Low Power, Commercial Temperature(-25°C ~ 70°C)
NOTES :
1. In case of 40MHz Frequency , CL1 can be supported.
2. Samsung shall not offer for sale or sell either directly or through and third-party proxy, and DRAM memory products that include "Multi-Die Plastic
DRAM" for use as components in general and scientific computers such as, by way of example, mainframes, servers, work stations or desk top
computers for the first three years of five year term of this license. Nothing herein limits the rights of Samsung to use Multi-Die Plastic DRAM in other
products or other applications under paragrangh such as mob ile, telecom or non-computer application(which include by way of example laptop or
notebook computers, cell phones, televisions or visual monitors)
Violation may subject the customer to legal claims and also excludes any warranty against infringement from Samsung." .
3. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific
purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
105MHz(CL=3)
*1
LVCMOS
90 FBGA
Leaded (Lead Free)
February 2004
K4M56323LE - M(E)E/N/S/C/L/R
FUNCTIONAL BLOCK DIAGRAM
Bank Select
Mobile-SDRAM
LWE
Data Input Register
LDQM
CLK
ADD
LCKE
Refresh Counter
Row Buffer
Address Register
LRAS
LCBR
LRAS LCBR LWE LDQM
CLK CKE CS
Row Decoder Col. Buffer
LCAS LWCBR
Timing Register
RAS CAS WE DQM
2M x 32
2M x 32
2M x 32
2M x 32
Column Decoder
Latency & Burst Length
Programming Register
Sense AMP
Output BufferI/O Control
DQi
February 2004
K4M56323LE - M(E)E/N/S/C/L/R
Package Dimension and Pin Configuration
1
D
Substrate(2Layer)
< Bottom View*1 >
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
#A1 Ball Origin Indicator
E
1
521634897
E
< Top View*2 >
E/2
e
z
b
SAMSUNG Week
K4M56323LE-XXXX
A1
Mobile-SDRAM
*2
< Top View
90Ball(6x15) FBGA
123789
A DQ26 DQ24 V
BDQ28V
SSQ DQ27 DQ25 DQ22 DQ20 VDDQ
CV
D
DVSSQ DQ29 DQ30 DQ17 DQ18 VDDQ
EVDDQ DQ31 NC NC DQ16 VSSQ
FVSS DQM3 A3 A2 DQM2 VDD
GA4A5A6A10A0A1
H A7 A8 NC NC BA1 A11
J CLK CKE A9 BA0 CS
KDQM1 NC NC CAS WE DQM0
D/2
DDQ DQ8 VSS VDD DQ7 VSSQ
LV
MVSSQ DQ10 DQ9 DQ6 DQ5 VDDQ
NVSSQ DQ12 DQ14 DQ1 DQ3 VDDQ
PDQ11VDDQ VSSQ VDDQ VSSQ DQ4
R DQ13 DQ15 V
Pin Name Pin Function
CLK System Clock
A
CS
CKE Clock Enable
A
0 ~ A11 Address
BA
0 ~ BA1 Bank Select Address
RAS
CAS
WE
DQM
0 ~ DQM3 Data Input/Output Mask
0 ~ 31 Data Input/Output
DQ
V
DD/VSS Power Supply/Ground
V
DDQ/VSSQ Data Output Power/Ground
DDQ VSSQ VDDQ VSSQ DQ19
>
SS VDD DQ23 DQ21
RAS
SS VDD DQ0 DQ2
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
[Unit:mm]
Symbol Min Typ Max
A - 1.30 1.40
A
1
E-11.00-
E
1
D - 13.00 -
D
1
e-0.80b 0.40 0.45 0.50
z--0.10
0.30 0.35 0.40
-6.40-
-11.20-
February 2004
K4M56323LE - M(E)E/N/S/C/L/R
Mobile-SDRAM
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on any pin relative to V
Voltage on V
DD supply relative to Vss VDD, VDDQ -1.0 ~ 3.6 V
ss VIN, VOUT -1.0 ~ 3.6 V
Storage temperature T
Power dissipation P
Short circuit current I
NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
STG -55 ~ +150 °C
D 1.0 W
OS 50 mA
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)
Parameter Symbol Min Typ Max Unit Note
VDD 2.3 2.5 2.7 V
Supply voltage
Input logic high voltage VIH 0.8 x VDDQ - VDDQ + 0.3 V 2
Input logic low voltage VIL -0.3 0 0.3 V 3
Output logic high voltage VOH VDDQ -0.2 - - V IOH = -0.1mA
Output logic low voltage VOL - - 0.2 V IOL = 0.1mA
Input leakage current ILI -10 - 10 uA 4
NOTES :
1. Samsung can support VDDQ 2.5V(in general case) and 1.8V(in specific case) for VDD 2.5V products.
Please contact to the memory marketing team in Samsung Electronics when considering the use of VDDQ 1.8V(Min 1.65V).
2. VIH (max) = 3.0V AC.The overshoot voltage duration is ≤ 3ns.
3. VIL (min) = -1.0V AC. The undershoot voltage duration is ≤ 3ns.
4. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
VDDQ
2.3 2.5 2.7 V
1.65 - 2.7 V 1
CAPACITANCE (VDD = 2.5V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)
Pin Symbol Min Max Unit Note
Clock CCLK 3.0 8.0 pF
RAS, CAS, WE, CS, CKE CIN 3.0 8.0 pF
DQM CIN 1.5 4.0 pF
Address CADD 3.0 8.0 pF
DQ0 ~ DQ31 COUT 3.0 6.5 pF
February 2004
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