The RT8202/A/B PWM controller provides high efficiency ,
excellent transient response, a nd high DC output a ccuracy
needed for stepping down high voltage batteries to
generate low voltage CPU core, I/O, and chipset RAM
supplies in notebook computers.
The constant on-time PWM control sche me handles wide
input/output voltage ratios with ea se and provides 100ns
“instant-on” response to load tran sients while maintaining
a relatively constant switching frequency .
The RT8202/A/B achieves high efficiency at a reduced
cost by eliminating the current sense resistor found in
traditional current mode PWMs. Efficiency is further
enhanced by its ability to drive very large synchronous
rectifier MOSFET s. The buck conversion allows this device
to directly step down high voltage batteries for the highest
possible efficiency . The RT8202/A/B is intended f or CPU
core, chipset, DRAM, or other low voltage supplies as
low as 0.75V. RT8202 is available in WQFN-16L 4x4,
RT8202A is available in WQF N-16L 3x3 and R T8202B is
available in WQF N-14L 3.5x3.5 pack ages.
Features
Ultra-High Efficiency
Resistor Programmable Current Limit by Low Side
R
Sense (Lossless Limit) or Sense Resistor
DS(ON)
(High Accuracy)
Quick Load Step Response within 100ns
1% V
Adjustable 0.75V to 3.3V Output Range
4.5V to 26V Battery Input Range
Resistor Programmable Frequency
Over/Under Voltage Protection
2 Steps Current Limit During Soft-Start
Drives Large Synchronous-Rectifier FET s
Power Good Indicator
RoHS Compliant and 100% Lead (Pb)-Free
Accuracy over Line and Load
OUT
Applications
Notebook Computers
CPU Core Supply
Chipset/RAM Supply a s Low as 0.75V
VOUT Sense Input. Connect to the output of PW M converter. VOUT
is an input of the PWM controller.
Analog Supply Voltage Input for the internal analog integrated circuit.
Bypass to GND with a 1F ceramic capacitor.
VOUT Feedback Input. Connect FB to a resistor voltage divider from
VOUT to GND to adjust the output from 0.75V to 3.3V.
Power Good Signal Open-Drain Output of PWM Converter. This pin
will be pulled high when the output voltage is within the target range.
GND
Ground for Analog Circuitry. The exposed pad must be soldered to a
large PCB and connected to GND for maximum power dissipation.
Low side N-MOSFET Gate-Drive Output for PWM. This pin swings
between GND and VDDP.
VDDP is the gate driver supply for the external MOSFETs. Bypass to
GND with a 1F ceramic capacitor.
PWM Current Limit Setting and sense. Connect a resistor between
OC to PHASE for current limit setting.
Inductor Connection. This pin is not only the zero-current-sense input
for the PWM converter, but also the UGATE high side gate driver
return.
High Side N-MOSFET Floating Gate-Driver Output for the PWM
converter. This pin swings between PHASE and BOOT.
Boost Capacitor Connection for PWM Converter. Connect an external
ceramic capacitor to PHASE and an external diode to VDDP.
PWM Enable and Operation Mode Selection Input. Connect to VDD
for diode-emulation mode, connect to GND for shutdown mode and
floating the pin for CCM mode.
VIN Sense Input. Connect to VIN through a resistor. TON is an input
of the PWM controller.
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Input V oltage, TON to GN D ---------------------------------------------------------------------------------------------- −0.3V to 32V
BOOT to GND -------------------------------------------------------------------------------------------------------------- −0.3V to 38V
PHASE to BOOT ---------------------------------------------------------------------------------------------------------- −6V to 0.3V
V DD, V DDP, VOUT, EN/DEM, FB, PGOOD to GND -------------------------------------------------------------- −0.3V to 6V
UGA TE to PHASE -------------------------------------------------------------------------------------------------------- −0.3V to 6V
OC to GND ------------------------------------------------------------------------------------------------------------------ −0.3V to 32V
LGA TE t o G ND ------------------------------------------------------------------------------------------------------------- −0.3V to 6V
PGND to GND -------------------------------------------------------------------------------------------------------------- −0.3V to 0.3V
Power Dissipation, P
Lead T e mperature (Soldering, 10 sec.)------------------------------------------------------------------------------- 26 0°C
Junction T e mperature ---------------------------------------------------------------------------------------------------- 150°C
Storage T emperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Mode) ---------------------------------------------------------------------------------------------- 2kV
MM (Ma chine Mode)------------------------------------------------------------------------------------------------------ 200V
@ TA = 25°C
D
Recommended Operating Conditions (Note 4)
Input V oltage, V
Supply Voltage, V
Junction T emperature Range--------------------------------------------------------------------------------------------
Ambient T emperature Range--------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------- 4.5V to 26V
IN
, V
DD
---------------------------------------------------------------------------------------------- 4.5V to 5.5V
DDP
−40°C to 125°C
−40°C to 85°C
Electrical Characteristics
(V
= V
DD
PWM Controller
Quiescent Supply Current VDD + VDDP, FB = 0.8V -- -- 1250 A
TON Operating Current R
Shutdown Current I
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
EN/DEM Logic Low Voltage -- -- 0.8 V
EN/DEM Logic High Voltage 2.9 -- -- V
EN/DEM Floating Voltage
Logic Input Current
PGOOD (upper side threshold decide by OV threshold)
Trip Threshold (Falling)
Fault Propagation Delay
Output Low Voltage I
Leakage Current High state, forced to 5.0V -- -- 1 A
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θ
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of
JA
JEDEC 51-7 thermal measurement standard. The case point of θ
EN/DEM Open -- 2 -- V
EN/DEM = VDD -- 1 5
A
EN/DEM = 0 5 1 --
Measured at FB, with respect to
reference, no load.
13 10 7 %
Hysteresis = 3%
Falling edge, FB forced below
PGOOD trip threshold
= 1mA -- -- 0.4 V
SINK
is on the expose pad of the package.
JC
-- 2.5 -- s
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
The RT8202/A/B PWM controller provides high efficiency ,
excellent transient response, a nd high DC output a ccuracy
needed for stepping down high voltage batteries to
generate low voltage CPU core, I/O, and chipset RAM
supplies in notebook computers. Richtek Mach
ResponseTM technology is specifically designed for
providing 100ns “instant-on” response to load steps while
maintaining a relatively constant operating frequency a nd
inductor operating point over a wide range of input voltages.
The topology circumvents the poor load tran sient ti ming
problems of fixed-frequency current mode PWMs while
avoiding the problems caused by widely varying switching
frequencies in conventional constant-on-ti me and constantoff-time PWM schemes. The DRVTM mode PWM
modulator is specifically designed to have better noise
immunity for such a single output application.
PWM Operation
The Mach Response
TM
DRVTM mode controller relies on
,
the output filter capacitor's effective series resistance
(ESR) to act as a current sense resistor, so the output
ripple voltage provides the PWM ra mp signal. Refer to the
function diagra ms of RT8202/A/B, the synchronous high
side MOSFET is turned on at the beginning of each cycle.
After the internal one-shot timer expires, the MOSFET is
turned off. The pulse width of this one shot is determined
by the converter's input and output voltages to keep the
frequency fairly constant over the input voltage range.
Another one-shot sets a minimum off-time (400ns typ.).
On-Time Control (TON)
The on-time one-shot comparator has two inputs. One
input monitors the output voltage, while the other input
samples the input voltage and converts it to a current.
This input voltage proportional current is used to charge
an internal on-time capacitor. The on-time is the time
required for the voltage on this capacitor to charge from
zero volts to V
, thereby making the on-time of the high
OUT
side switch directly proportional to output voltage and
inversely proportional to input voltage. The implementation
results in a nearly constant switching frequency without
the need a clock generator.
And then the switching frequency is :
Frequency = V
R
is a resistor connected from the input supply (VIN)
TON
/ (VIN x TON)
OUT
to TON pin.
Mode Selection (EN/DEM) Operation
The EN/DEM pin enables the supply. When EN/DEM is
tied to VDD, the controller is enabled and operates in
diode-emulation mode. When the EN/DEM pin is floating,
the RT8202/A/B will operate in forced-CCM mode.
Diode-Emulation Mode (EN/DEM = High)
In diode-emulation mode, RT8202/A/B automatically
reduces switching frequency at light-load conditions to
maintain high efficiency. This reduction of frequency is
achieved smoothly a nd without increasing V
ripple or
OUT
load regulation. As the output current decreases from
heavy-load condition, the inductor current is also reduced,
and eventually comes to the point that its valley touches
zero current, which is the boundary between continuous
conduction and discontinuous conduction modes. By
emulation the behavior of diodes, the low-side MOSFET
allows only partial of negative current when the inductor
freewheeling current reach negative. As the loa d current
is further decrea sed, it takes longer and longer to discharge
the output capacitor to the level than requires the next
“ON” cycle. The on-time is kept the same as that in the
heavy-load condition. In reverse, when the output current
increases from light load to heavy load, the switching
frequency increases to the preset value as the inductor
current reaches the continuous condition. The transition
load point to the light load operation ca n be calculated as
follows (Figure 3) :
(V V)
IT
LOADON
INOUT
2L
where TON is On-time.
TON = 3.85p x R
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
The switching waveforms may appear noisy and
asynchronous when light loa ding causes diode-emulation
operation, but this is a normal operating condition that
results in high light-load efficiency . T rade-offs in DEM noise
vs. light-load efficiency are made by varying the inductor
value. Generally, low inductor values produce a broader
efficiency vs. load curve, while higher values result in higher
full-load efficiency (assuming that the coil resistance
remains fixed) and less output voltage ripple. The
disadvantages for using higher inductor values include
larger physical size and degrades loa d-transient response
(especially at low input voltage levels).
Forced-CCM Mode (EN/DEM = floating)
The low noise, forced-CCM mode (EN/DEM = floating)
disables the zero-crossing comparator, which controls the
low-side switch on-time. This causes the low side gatedrive waveform to become the complement of the high
side gate-drive waveform. This in turn causes the inductor
current to reverse at light loads as the PWM loop to
maintain a duty ratio V
OUT/VIN
. The benefit of forced-CCM
mode is to keep the switching frequency fairly constant,
but it comes at a cost : The no-load battery current can
be up to 10mA to 40mA, depending on the external
MOSFETs.
Current Limit Setting (OCP)
RT8202/A/B has cycle-by-cycle current limiting control.
The current limit circuit employs a unique “valley” current
sensing algorithm. If the magnitude of the current-sense
signal at OC is above the current limit threshold, the PWM
is not allowed to initiate a new cycle (Figure 4).
0
t
Figure 4. V alley Current-Limit
Current sensing of the RT8202/A/B can be a ccomplished
in two ways. Users can either use a current sense resistor
or the on-state of the low side MOSFET (R
DS(ON)
). For
resistor sensing, a sense resistor is pla ced between the
source of low-side MOSFET and PGND (Figure 5(a)).
R
sensing is more efficient a nd less expensive (Figure
DS(ON)
5(b)). There is a compromise between current-limit
accura cy a nd sense resistor power dissi pation.
PHASE
PHASE
LGATE
OC
R
ILIM
LGATE
OC
R
ILIM
(a)(b)
Figure 5. Current-Sense Methods
In both case s, the R
resistor between the OC pin and
ILIM
PHASE pin sets the over current threshold. This resistor
R
is connected to a 20μA current source within the
ILIM
RT8202/A/B which is turned on when the low side
MOSFET turns on. When the voltage drop across the
sense resistor or low side MOSFET equals the voltage
across the R
resistor, positive current li mit will activate.
ILIM
The high side MOSFET will not be turned on until the
voltage drop across the sense element (resistor or
MOSFET) falls below the voltage across the R
resistor.
ILIM
Choose a current limit resistor by following Equation :
R
= I
ILIM
x R
LIMIT
SENSE
/ 20μA
Carefully observe the PC board layout guidelines to ensure
that noise and DC errors do not corrupt the current-sense
signal seen by OC and PGND. Mount the IC close to the
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
low-side MOSFET and sense resistor with short, direct
traces, making a Kelvin sense connection to the sense
resistor.
MOSFET Gate Driver (UGATE, LGA TE)
The high side driver is designed to drive high current, low
R
N-MOSFET(s). When configured as a floating
DS(ON)
driver, 5V bia s voltage is delivered from V DDP supply . The
average drive current is proportional to the gate charge at
VGS = 5V times switching frequency. The instantaneous
drive current is supplied by the flying cap acitor between
BOOT and PHASE pins.
A dead time to prevent shoot through is internally
generated between high side MOSFET off to low side
MOSFET on, and low side MOSFET off to high side
MOSFET on.
The low side driver is designed to drive high current, low
R
N-MOSFET(s). The internal pull-down transistor
DS(ON)
that drives LGATE low is robust, with a 0.6Ω typical onresistance. A 5V bias voltage is delivered form VDDP
supply . The instanta neous drive current is supplied by the
flying cap acitor between V DDP and PGND.
For high current application s, some combinations of high
and low side MOSFETs might be encountered that will
cause excessive gate-drain coupling, which can lead to
efficiency killing, EMI producing shoot through currents.
This is often remedied by adding a resistor in series with
BOOT, which increases the turn-on time of the high side
MOSFET without degrading the turn-off time (Figure 6).
V
IN
+5V
tolerances once more. In soft start, PGOOD is actively
held low and is allowed to tra nsition high until soft start is
over and the output rea ches 93% of its set voltage. There
is a 2.5μs delay built into PGOOD circuitry to prevent
false transition.
POR, UVLO and Soft-Start
Power on reset (POR) occurs when VDD rises above to
approximately 4.3V, the RT8202/A/B will reset the fault
latch and preparing the PWM for operation. Below
4.1V
, the V DD under voltage-lockout (UVLO) circuitry
(MIN)
inhibits switching by keeping UGA TE and LGATE low.
A built-in soft-start is used to prevent surge current from
power supply input after EN/DEM is enabled. It clamps
the ramping of intern al reference voltage which is compared
with FB signal. The typical soft-start duration is 1.35ms.
Furthermore, the maximum allowed current limit is
segment in 2 steps during 1.35ms period.
Output Over Voltage Protection (OVP)
The output voltage can be continuously monitored for over
voltage protection. When the output voltage exceeds 15%
of the its set voltage threshold, over voltage protection is
triggered and the low side MOSFET is latched on. This
activates the low side MOSFET to discharge the output
cap acitor.
RT8202/A/B is latched once OVP is triggered and can
only be relea sed by V DD or EN/DEM power on reset. There
is 20us delay built into the over voltage protection circuit
to prevent false transitions.
BOOT
R
Output Under Voltage Protection (UVP)
The output voltage can be continuously monitored for under
UGATE
PHASE
voltage protection. When the output voltage is less than
70% of its set voltage threshold, under voltage protection
is triggered and then both UGA TE and LGA TE gate drivers
Figure 6. Reducing the UGA TE Rise T ime
are forced low . In order to remove the residual charge on
the output capacitor during the under voltage period, if
Power Good Output (PGOOD)
The power good output is an open-drain output and requires
a pull up resistor. When the output voltage is 15% above
or 10% below its set voltage, PGOOD gets pulled low. It
is held low until the output voltage returns to within these
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
PHASE is greater than 1V, the LGA TE is forced high until
PHASE is lower than 1V. There is 2.5us delay built into
the under voltage protection circuit to prevent false
transitions. During soft-start, the UVP will be blanked
around 3.1ms.
13
RT8202/A/B
Output V oltage Setting (FB)
V
IN
The output voltage can be adjusted from 0.75V to 3.3V by
setting the feedback resistor R1 a nd R2 (Figure 7). Choose
R2 to be approxi mately 10kΩ, and solve f or R1 using the
equation:
R1
V = V 1
OUTFB
R2
where VFB is 0.75V.
Note that in order for the device to regulate in a controlled
manner , the ripple content at the feedba ck pin, VFB, should
be approxi mately 15mV at minimum V
no smaller than 10mV. If V
at minimum V
ripple
, and worst ca se
BAT
BAT
is less
than 15mV, the above component values should be
revisited in order to improve this. Quite often a small
cap acitor , C1, is required in parallel with the top feedback
For application that output voltage is higher than 3.3V,
user can also use a voltage divider to keep VOUT pin
voltage within 0.75V to 2.8V as shown in Figure 8. For
this case, T
If R < 2M then T = 3.85p
TONON
resistor, R1, in order to ensure that VFB is large enough.
The value of C1 can be calculated a s follows, where R2 is
If R 2M then T = 3.55p
TONON
the bottom feedback resistor .
Where R
Firstly calculating the value of Z1 required :
Z1 = V0.015
R2
0.015
ripple_VBAT(MIN)
output signal of resistor divider. Since the switching
frequency is
F =
S
Secondly calculating the value of C1 required to achieve
this :
11
C1 = F
Z1 R1
2f
SW_VBAT(MIN)
For a given switching frequency , we can obtain the R
a s below
If R < 2M then
TON
R =
TON
Finally using the equation as follows to verify the value of
If R 2M then
V
:
FB
V = V
FB_VBAT(MIN)ripple_VBAT(MIN)
TON
R =
TON
V
R2+
1
where V
minimum V
f
sw_VBAT(MIN)
V
FB_VBAT(MIN)
V
.
BAT
R1
ripple_VBAT(MIN)
;
BAT
is the switching frequency in minimum V
is the ripple voltage into FB pin in minimum
R2
1
2fC1
SW_VBAT(MIN)
is the output ripple voltage in
BAT
;
Figure 8. Output Voltage Setting for V
UGATE
PHASE
BOOT
VOUT
FB
GND
R1
R2
Figure 7. Setting The Output Voltage
can be determined as below :
ON
is TON set resistor and the V
TON
V
OUT
VT
INON
RV
R V
V0.5V
OUTOUT
VVF3.85p
INOUT_FBS
V0.4V
OUTOUT
VVF3.55p
VIN
UGATE
PHASE
BOOT
VOUT
FB
GND
INOUT_FBS
V
IN
R
TON
V
OUT_FB
R3
R4
Application
V
OUT
Z1
C1
TONOUT_FB
TONOUT_FB
C2
V0.5
IN
V0.4
IN
is the
OUT_FB
1
1
V
OUT
R1
C2
R2
> 3.3V
OUT
TON
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The switching frequency (on-time) and operating point (%
ripple or LIR) determine the inductor value as f ollows :
T(V - V)
ONINOUT
L =
LI
IRLOAD(MAX)
Find a low pass inductor having the lowest possible DC
resistance that fits in the allowed dimen sions. Ferrite cores
are often the best choice, although powdered iron is
inexpensive and ca n work well at 200kHz. The core must
be large enough and not to saturate at the pea k inductor
current (I
I
= I
PEAK
) :
PEAK
LOAD(MAX)
+ [(LIR / 2) x I
LOAD(MAX)
]
Output Capacitor Selection
The output filter ca pacitor must have ESR low enough to
meet output ripple and loa d transient requirement, yet have
high enough ESR to satisfy stability requirements. Also,
the cap acitance value must be high enough to a bsorb the
inductor energy going from a full load to no load condition
without tripping the OVP circuit.
Do not put high value ceramic capacitors directly across
the outputs without taking precautions to ensure sta bility .
Large ceramic capacitors can have a high ESR zero
frequency and cause erratic and unstable operation.
However, it is easy to add sufficient series resistance by
placing the ca pacitors a couple of inche s downstream from
the inductor and connecting V
or FB divider close to
OUT
the inductor.
There are two related but distinct ways including double
pulsing and feedback loop instability to identify the
unstable operation.
Double-pulsing occurs due to noise on the output or
because the ESR is too low that there is not enough
voltage ramp in the output voltage sign al. The “fools” the
error comparator into triggering a new cycle immediately
after 400ns minimum off-time period ha s expired. Doublepulsing is more annoying tha n harmful, resulting in nothing
worse than increased output ripple. However, it may
indicate the possible presence of loop instability, which
is caused by insufficient ESR.
For CPU core voltage converters and other applications
where the output is subject to violent load transient, the
output capacitor's size depends on how much ESR is
needed to prevent the output from dipping too low under a
load transient. Ignoring the sag due to f inite cap acita nce :
V
ESR
P-P
I
LOAD(MAX)
In non-CPU applications, the output capacitor's size
depends on how much ESR is needed to maintain at an
accepta ble level of output voltage ripple :
V
ESR
LI
P-P
IRLOAD(MAX)
Organic semiconductor ca pa citor(s) or specially polymer
ca pacitor(s) are recommended.
Output Capacitor Stability
Stability is determined by the value of the ESR zero relative
to the switching frequency . The point of instability is given
by the following equation :
f =
ESR
1
2ESR C4
OUT
f
SW
Loop instability ca n result in oscillation at the output after
line or load perturbations that can trip the over voltage
protection latch or cause the output voltage to fall below
the tolerance limit.
The easiest method for stability checking is to apply a
very zero-to-max load tran sient and carefully observe the
output-voltage-ripple envelope for overshoot a nd ringing. It
helps to simultaneously monitor the inductor current with
AC probe. Do not allow more tha n one ringing cycle after
the initial step-response under- or over-shoot.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum operation junction temperature.
The maximum power dissipation depends on the thermal
resistance of IC package, PCB layout, the rate of
surroundings airflow and temperature difference between
junction to ambient. The maximum power dissipation ca n
be calculated by following formula :
P
D(MAX)
= ( T
J(MAX)
− TA ) / θ
JA
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
temperature 125°C, TA is the ambient temperature and
the θ
is the junction to ambient thermal resistance.
JA
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal re sistance, θJA, is layout dependent. The
junction to ambient thermal resistance θ
is layout
JA
dependent. For WQFN-16L 3x3 packages, the thermal
resistance θJA is 68°C/W on the standard JEDEC 51-7
four layers thermal test board. For WQFN-14L 3.5x3.5
package, the thermal resistance θ
is 60°C/W on the
JA
standard JEDEC 51-7 four layers thermal test board. The
maximum power dissipation at TA = 25°C can be calculated
by following formula :
P
= (125°C − 2°C) / (68°C/W) = 1.471W for
D(MAX)
WQF N-16L 3x3 pa ckages
P
= (125°C − 25°C) / (54°C/W) = 1.852W for
D(MAX)
WQF N-16L 4x4 pa ckages
P
= (125°C − 25°C) / (60°C/W) = 1.667W for
D(MAX)
WQF N-14L 3.5x3.5 packages
The maximum power dissipation depends on the operating
ambient temperature for fixed T
and thermal
J(MAX)
resistance, θJA. The derating curve in Figure 9 of derating
curves allows the designer to see the effect of rising
ambient te mperature on the maximum power allowed.
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
Maximum Power Dissipation (W)
0.0
0255075100125
WQFN -16L 3x3
WQFN -16L 4x4
Ambient Temperatur e (°C)
Four Layer PCB
WQFN -14L 3.5x3.5
Layout Considerations
Layout is very important in high frequency switching
converter design. If designed improperly , the PCB could
radiate excessive noise and contribute to the converter
instability. Certain points must be considered before
starting a layout for RT8202/A/B.
Connect RC low pa ss filter from V DDP to V DD, 1uF a nd
10Ω are recommended. Place the filter ca pa citor close
to the IC.
Keep current li mit setting network a s close as possible
to the IC. Routing of the network should avoid coupling
to high voltage switching node.
Connections from the drivers to the respective gate of
the high side or the low side MOSFET should be as
short as possible to reduce stray inductance.
All sensitive analog traces and components such as
VOUT, FB, GND, EN/DEM, PGOOD, OC, VDD, and
TON should be placed away from high voltage switching
nodes such as PHASE, LGATE, UGATE, or BOOT
nodes to avoid coupling. Use internal layer(s) a s ground
plane(s) and shield the feedba ck trace from power tra ces
and components.
Current sense connections must always be made using
Kelvin connections to ensure an accurate signal, with
the current limit resistor located at the device.
Power sections should connect directly to ground
plane(s) using multiple vias as required for current
handling (including the chip power ground connection s).
Power components should be placed to minimize loops
and reduce losses.
Figure 9. Derating Curve of Maxi mum Power Dissi pation
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
D 3.400 3.600 0.134 0.142
D2 1.950 2.150 0.077 0.085
E 3.400 3.600 0.134 0.142
1
2
E2 1.950 2.150 0.077 0.085
e 0.500 0.020
e1 1.500 0.060
L 0.300 0.500
0.012 0.020
W-Type 14L QFN 3.5x3.5 Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS8202/A/B-07 April 2014www.richtek.com
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