Richtek RT8166BZQW Schematic

®

RT8166B

Dual Single-Phase PWM Controller for CPU and GPU Core Power Supply

General Description

The RT8166B is a dual single-pha se PWM controller with integrated MOSFET drivers, compliant with Intel IMVP7 Pulse Width Modulation Specification to support both CPU core and GPU core power. This part a dopts G-NA VP (Green-Native A VP), which is a Richtek proprietary topology derived from finite DC gain compen sator in consta nt ontime control mode. G-NAVPTM makes this part an easy setting PWM controller to meet all Intel AVP (Active V oltage Positioning) mobile CPU/GPU requirements. The RT8166B uses SVID interface to control a n 8-bit DAC for

output voltage programming. The built-in high accuracy DAC converts the received VID code into a voltage value ranging from 0V to 1.52V with 5mV step voltage. The system accuracy of the controller can reach 0.8%. The RT8166B operates in continuous conduction mode or diode emulation mode, according to the SVID command. The maximum efficiency ca n reach up to 90% in dif ferent operating modes according to different load conditions. The droop function (load line) can be ea sily progra mmed by setting the DC gain of the error amplifier. With proper compensation, the load transient response can achieve optimized A VP performance.

The output voltage transition slew rate is set vi a the SVID interface. The RT8166B supports both DCR and sense resistor current sensing. The RT8166B provides VR_READY and thermal throttling output signals for

IMVP7 CPU and GPU core. This part also features complete fault protection functions including over voltage, under voltage, negative voltage, over current and thermal shutdown.

TM

Features



 Dual Single-Phase PWM Controller for CPU Core



and GPU Core Power



 IMVP7 Compatible Power Management States



 Serial VID Interface



 G-NAV P



 A V P f or CPU VR Only



 0.5% DAC Accuracy



 0.8% System Accuracy



 Differential Remote Voltage Sensing



 Built-in ADC for Platform Programming



 SETINI/SETINIA for CPU/GPU Core VR Initial

TM

T opology

Startup Voltage

 TMPMAX to Set Platform Maximum Temperature  ICCMAX/ICCMAXA for CPU/GPU Core VR

Maximum Current



 Power Good Indicator : VR_READY/VRA_READY for



CPU/GPU Core Power



 Thermal Throttling Indicator : VRHOT



 Diode Emulation Mode at Light Load Condition



 Fast Line/Load Transient Response



 Switching Frequency up to 1MHz per Phase



 OVP, UVP, NVP, OTP, UVLO, OCP



 Small 40-Lead WQFN Package



 RoHS Compliant and Halogen Free



Applications

 IMVP7 Intel CPU/GPU Core Power Supply  Laptop Computers  A VP Step-Down Converter

The RT8166B is available in a WQFN-40L 5x5 small footprint pack age.

Marking Information

RT8166BZQW : Product Number

RT8166B ZQW YMDNN

DS8166B-03 November 2013 www.richtek.com

©

YMDNN : Date Code

1

RT8166B

Ordering Information

RT8166B

Package Type QW : WQFN-40L 5x5 (W-Type)

Lead Plating System Z : ECO (Ecological Element with Halogen Free and Pb free)

Note :

Richtek products are :

 RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

 Suitable for use in SnPb or Pb-free soldering processes.

Pin Configurations

(TOP VIEW)

UGATE1

PHASE1

LGATE1

PVCC

LGATEA

PHASEA

FB

VCC

10

1 2 3 4 5 6 7 8 9

SETINI

ICCMAX

TMPMAX

ICCMAXA

WQFN-40L 5x5

GND

TSEN

OCSET

BOOT1

TONSET

ISEN1P ISEN1N

COMP

RGND

GFXPS2 SETINIA

UGATEA

BOOTAENTONSETA

41

TSENA

OCSETA

31323334353637383940

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IBIAS

VRHOT

30

ISENAP

29

ISENAN

28

COMPA

27

FBA

26

RGNDA

25

VCLK

24

VDIO

23

ALERT

22

VRA_READY

21

VR_READY

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DS8166B-03 November 2013www.richtek.com

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Typical Application Circuit

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DS8166B-03 November 2013 www.richtek.com

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RT8166B

Table 1. IMVP7/VR12 Compliant VID Table

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 VDAC Voltage

0 0 0 0 0 0 0 0 0 0 0.000 0 0 0 0 0 0 0 1 0 1 0.250 0 0 0 0 0 0 1 0 0 2 0.255 0 0 0 0 0 0 1 1 0 3 0.260 0 0 0 0 0 1 0 0 0 4 0.265 0 0 0 0 0 1 0 1 0 5 0.270 0 0 0 0 0 1 1 0 0 6 0.275 0 0 0 0 0 1 1 1 0 7 0.280 0 0 0 0 1 0 0 0 0 8 0.285 0 0 0 0 1 0 0 1 0 9 0.290 0 0 0 0 1 0 1 0 0 A 0.295 0 0 0 0 1 0 1 1 0 B 0.300 0 0 0 0 1 1 0 0 0 C 0.305 0 0 0 0 1 1 0 1 0 D 0.310 0 0 0 0 1 1 1 0 0 E 0.315 0 0 0 0 1 1 1 1 0 F 0.320 0 0 0 1 0 0 0 0 1 0 0.325 0 0 0 1 0 0 0 1 1 1 0.330 0 0 0 1 0 0 1 0 1 2 0.335 0 0 0 1 0 0 1 1 1 3 0.340 0 0 0 1 0 1 0 0 1 4 0.345 0 0 0 1 0 1 0 1 1 5 0.350 0 0 0 1 0 1 1 0 1 6 0.355 0 0 0 1 0 1 1 1 1 7 0.360 0 0 0 1 1 0 0 0 1 8 0.365 0 0 0 1 1 0 0 1 1 9 0.370 0 0 0 1 1 0 1 0 1 A 0.375 0 0 0 1 1 0 1 1 1 B 0.380 0 0 0 1 1 1 0 0 1 C 0.385 0 0 0 1 1 1 0 1 1 D 0.390 0 0 0 1 1 1 1 0 1 E 0.395 0 0 0 1 1 1 1 1 1 F 0.400 0 0 1 0 0 0 0 0 2 0 0.405 0 0 1 0 0 0 0 1 2 1 0.410 0 0 1 0 0 0 1 0 2 2 0.415

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RT8166B

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

0 0 1 0 0 0 1 1 2 3 0.420 0 0 1 0 0 1 0 0 2 4 0.425 0 0 1 0 0 1 0 1 2 5 0.430 0 0 1 0 0 1 1 0 2 6 0.435 0 0 1 0 0 1 1 1 2 7 0.440 0 0 1 0 1 0 0 0 2 8 0.445 0 0 1 0 1 0 0 1 2 9 0.450 0 0 1 0 1 0 1 0 2 A 0.455 0 0 1 0 1 0 1 1 2 B 0.460 0 0 1 0 1 1 0 0 2 C 0.465 0 0 1 0 1 1 0 1 2 D 0.470 0 0 1 0 1 1 1 0 2 E 0.475 0 0 1 0 1 1 1 1 2 F 0.480 0 0 1 1 0 0 0 0 3 0 0.485 0 0 1 1 0 0 0 1 3 1 0.490 0 0 1 1 0 0 1 0 3 2 0.495 0 0 1 1 0 0 1 1 3 3 0.500 0 0 1 1 0 1 0 0 3 4 0.505 0 0 1 1 0 1 0 1 3 5 0.510 0 0 1 1 0 1 1 0 3 6 0.515 0 0 1 1 0 1 1 1 3 7 0.520 0 0 1 1 1 0 0 0 3 8 0.525 0 0 1 1 1 0 0 1 3 9 0.530 0 0 1 1 1 0 1 0 3 A 0.535 0 0 1 1 1 0 1 1 3 B 0.540 0 0 1 1 1 1 0 0 3 C 0.545 0 0 1 1 1 1 0 1 3 D 0.550 0 0 1 1 1 1 1 0 3 E 0.555 0 0 1 1 1 1 1 1 3 F 0.560 0 1 0 0 0 0 0 0 4 0 0.565 0 1 0 0 0 0 0 1 4 1 0.570 0 1 0 0 0 0 1 0 4 2 0.575 0 1 0 0 0 0 1 1 4 3 0.580 0 1 0 0 0 1 0 0 4 4 0.585 0 1 0 0 0 1 0 1 4 5 0.590

DS8166B-03 November 2013 www.richtek.com

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RT8166B

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

0 1 0 0 0 1 1 0 4 6 0.595 0 1 0 0 0 1 1 1 4 7 0.600 0 1 0 0 1 0 0 0 4 8 0.605 0 1 0 0 1 0 0 1 4 9 0.610 0 1 0 0 1 0 1 0 4 A 0.615 0 1 0 0 1 0 1 1 4 B 0.620 0 1 0 0 1 1 0 0 4 C 0.625 0 1 0 0 1 1 0 1 4 D 0.630 0 1 0 0 1 1 1 0 4 E 0.635 0 1 0 0 1 1 1 1 4 F 0.640 0 1 0 1 0 0 0 0 5 0 0.645 0 1 0 1 0 0 0 1 5 1 0.650 0 1 0 1 0 0 1 0 5 2 0.655 0 1 0 1 0 0 1 1 5 3 0.660 0 1 0 1 0 1 0 0 5 4 0.665 0 1 0 1 0 1 0 1 5 5 0.670 0 1 0 1 0 1 1 0 5 6 0.675 0 1 0 1 0 1 1 1 5 7 0.680 0 1 0 1 1 0 0 0 5 8 0.685 0 1 0 1 1 0 0 1 5 9 0.690 0 1 0 1 1 0 1 0 5 A 0.695 0 1 0 1 1 0 1 1 5 B 0.700 0 1 0 1 1 1 0 0 5 C 0.705 0 1 0 1 1 1 0 1 5 D 0.710 0 1 0 1 1 1 1 0 5 E 0.715 0 1 0 1 1 1 1 1 5 F 0.720 0 1 1 0 0 0 0 0 6 0 0.725 0 1 1 0 0 0 0 1 6 1 0.730 0 1 1 0 0 0 1 0 6 2 0.735 0 1 1 0 0 0 1 1 6 3 0.740 0 1 1 0 0 1 0 0 6 4 0.745 0 1 1 0 0 1 0 1 6 5 0.750 0 1 1 0 0 1 1 0 6 6 0.755 0 1 1 0 0 1 1 1 6 7 0.760 0 1 1 0 1 0 0 0 6 8 0.765 0 1 1 0 1 0 0 1 6 9 0.770

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RT8166B

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

0 1 1 0 1 0 1 0 6 A 0.775 0 1 1 0 1 0 1 1 6 B 0.780 0 1 1 0 1 1 0 0 6 C 0.785 0 1 1 0 1 1 0 1 6 D 0.790 0 1 1 0 1 1 1 0 6 E 0.795 0 1 1 0 1 1 1 1 6 F 0.800 0 1 1 1 0 0 0 0 7 0 0.805 0 1 1 1 0 0 0 1 7 1 0.810 0 1 1 1 0 0 1 0 7 2 0.815 0 1 1 1 0 0 1 1 7 3 0.820 0 1 1 1 0 1 0 0 7 4 0.825 0 1 1 1 0 1 0 1 7 5 0.830 0 1 1 1 0 1 1 0 7 6 0.835 0 1 1 1 0 1 1 1 7 7 0.840 0 1 1 1 1 0 0 0 7 8 0.845 0 1 1 1 1 0 0 1 7 9 0.850 0 1 1 1 1 0 1 0 7 A 0.855 0 1 1 1 1 0 1 1 7 B 0.860 0 1 1 1 1 1 0 0 7 C 0.865 0 1 1 1 1 1 0 1 7 D 0.870 0 1 1 1 1 1 1 0 7 E 0.875 0 1 1 1 1 1 1 1 7 F 0.880 1 0 0 0 0 0 0 0 8 0 0.885 1 0 0 0 0 0 0 1 8 1 0.890 1 0 0 0 0 0 1 0 8 2 0.895 1 0 0 0 0 0 1 1 8 3 0.900 1 0 0 0 0 1 0 0 8 4 0.905 1 0 0 0 0 1 0 1 8 5 0.910 1 0 0 0 0 1 1 0 8 6 0.915 1 0 0 0 0 1 1 1 8 7 0.920 1 0 0 0 1 0 0 0 8 8 0.925 1 0 0 0 1 0 0 1 8 9 0.930 1 0 0 0 1 0 1 0 8 A 0.935 1 0 0 0 1 0 1 1 8 B 0.940 1 0 0 0 1 1 0 0 8 C 0.945 1 0 0 0 1 1 0 1 8 D 0.950

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RT8166B

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

1 0 0 0 1 1 1 0 8 E 0.955 1 0 0 0 1 1 1 1 8 F 0.960 1 0 0 1 0 0 0 0 9 0 0.965 1 0 0 1 0 0 0 1 9 1 0.970 1 0 0 1 0 0 1 0 9 2 0.975 1 0 0 1 0 0 1 1 9 3 0.980 1 0 0 1 0 1 0 0 9 4 0.985 1 0 0 1 0 1 0 1 9 5 0.990 1 0 0 1 0 1 1 0 9 6 0.995 1 0 0 1 0 1 1 1 9 7 1.000 1 0 0 1 1 0 0 0 9 8 1.005 1 0 0 1 1 0 0 1 9 9 1.010 1 0 0 1 1 0 1 0 9 A 1.015 1 0 0 1 1 0 1 1 9 B 1.020 1 0 0 1 1 1 0 0 9 C 1.025 1 0 0 1 1 1 0 1 9 D 1.030 1 0 0 1 1 1 1 0 9 E 1.035 1 0 0 1 1 1 1 1 9 F 1.040 1 0 1 0 0 0 0 0 A 0 1.045 1 0 1 0 0 0 0 1 A 1 1.050 1 0 1 0 0 0 1 0 A 2 1.055 1 0 1 0 0 0 1 1 A 3 1.060 1 0 1 0 0 1 0 0 A 4 1.065 1 0 1 0 0 1 0 1 A 5 1.070 1 0 1 0 0 1 1 0 A 6 1.075 1 0 1 0 0 1 1 1 A 7 1.080 1 0 1 0 1 0 0 0 A 8 1.085 1 0 1 0 1 0 0 1 A 9 1.090 1 0 1 0 1 0 1 0 A A 1.095 1 0 1 0 1 0 1 1 A B 1.100 1 0 1 0 1 1 0 0 A C 1.105 1 0 1 0 1 1 0 1 A D 1.110 1 0 1 0 1 1 1 0 A E 1.115 1 0 1 0 1 1 1 1 A F 1.120 1 0 1 1 0 0 0 0 B 0 1.125 1 0 1 1 0 0 0 1 B 1 1.130

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RT8166B

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

1 0 1 1 0 0 1 0 B 2 1.135 1 0 1 1 0 0 1 1 B 3 1.140 1 0 1 1 0 1 0 0 B 4 1.145 1 0 1 1 0 1 0 1 B 5 1.150 1 0 1 1 0 1 1 0 B 6 1.155 1 0 1 1 0 1 1 1 B 7 1.160 1 0 1 1 1 0 0 0 B 8 1.165 1 0 1 1 1 0 0 1 B 9 1.170 1 0 1 1 1 0 1 0 B A 1.175 1 0 1 1 1 0 1 1 B B 1.180 1 0 1 1 1 1 0 0 B C 1.185 1 0 1 1 1 1 0 1 B D 1.190 1 0 1 1 1 1 1 0 B E 1.195 1 0 1 1 1 1 1 1 B F 1.200 1 1 0 0 0 0 0 0 C 0 1.205 1 1 0 0 0 0 0 1 C 1 1.210 1 1 0 0 0 0 1 0 C 2 1.215 1 1 0 0 0 0 1 1 C 3 1.220 1 1 0 0 0 1 0 0 C 4 1.225 1 1 0 0 0 1 0 1 C 5 1.230 1 1 0 0 0 1 1 0 C 6 1.235 1 1 0 0 0 1 1 1 C 7 1.240 1 1 0 0 1 0 0 0 C 8 1.245 1 1 0 0 1 0 0 1 C 9 1.250 1 1 0 0 1 0 1 0 C A 1.255 1 1 0 0 1 0 1 1 C B 1.260 1 1 0 0 1 1 0 0 C C 1.265 1 1 0 0 1 1 0 1 C D 1.270 1 1 0 0 1 1 1 0 C E 1.275 1 1 0 0 1 1 1 1 C F 1.280 1 1 0 1 0 0 0 0 D 0 1.285 1 1 0 1 0 0 0 1 D 1 1.290 1 1 0 1 0 0 1 0 D 2 1.295 1 1 0 1 0 0 1 1 D 3 1.300 1 1 0 1 0 1 0 0 D 4 1.305 1 1 0 1 0 1 0 1 D 5 1.310

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RT8166B

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

1 1 0 1 0 1 1 0 D 6 1.315 1 1 0 1 0 1 1 1 D 7 1.320 1 1 0 1 1 0 0 0 D 8 1.325 1 1 0 1 1 0 0 1 D 9 1.330 1 1 0 1 1 0 1 0 D A 1.335 1 1 0 1 1 0 1 1 D B 1.340 1 1 0 1 1 1 0 0 D C 1.345 1 1 0 1 1 1 0 1 D D 1.350 1 1 0 1 1 1 1 0 D E 1.355 1 1 0 1 1 1 1 1 D F 1.360 1 1 1 0 0 0 0 0 E 0 1.365 1 1 1 0 0 0 0 1 E 1 1.370 1 1 1 0 0 0 1 0 E 2 1.375 1 1 1 0 0 0 1 1 E 3 1.380 1 1 1 0 0 1 0 0 E 4 1.385 1 1 1 0 0 1 0 1 E 5 1.390 1 1 1 0 0 1 1 0 E 6 1.395 1 1 1 0 0 1 1 1 E 7 1.400 1 1 1 0 1 0 0 0 E 8 1.405 1 1 1 0 1 0 0 1 E 9 1.410 1 1 1 0 1 0 1 0 E A 1.415 1 1 1 0 1 0 1 1 E B 1.420 1 1 1 0 1 1 0 0 E C 1.425 1 1 1 0 1 1 0 1 E D 1.430 1 1 1 0 1 1 1 0 E E 1.435

1 1 1 0 1 1 1 1 E F 1.440 1 1 1 1 0 0 0 0 F 0 1.445 1 1 1 1 0 0 0 1 F 1 1.450 1 1 1 1 0 0 1 0 F 2 1.455 1 1 1 1 0 0 1 1 F 3 1.460 1 1 1 1 0 1 0 0 1 1 1 1 0 1 0 1 F 5 1.470 1 1 1 1 0 1 1 0 F 6 1.475 1 1 1 1 0 1 1 1 F 7 1.480 1 1 1 1 1 0 0 0

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F 4

F 8

DS8166B-03 November 2013www.richtek.com

1.465

1.485

RT8166B

VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 H1 H0 DAC Voltage

1 1 1 1 1 0 0 1 F 9 1.490 1 1 1 1 1 0 1 0 F A 1.495 1 1 1 1 1 0 1 1 F B 1.500 1 1 1 1 1 1 0 0 F C 1.505 1 1 1 1 1 1 0 1 F D 1.510 1 1 1 1 1 1 1 0 F E 1.515 1 1 1 1 1 1 1 1 F F 1.520

DS8166B-03 November 2013 www.richtek.com

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11

RT8166B

Functional Pin Description

Pin No. Pin Name Pin Function

1 BOOT1

2 TONSET 3 ISEN1P Positive Current Sense Input Pin of CPU VR.

4 ISEN1N Negative Current Sense Input Pin of CPU VR. 5 COMP CPU VR Compensation Pin. This pin is the output of the error amplifier. 6 FB CPU VR Feedback Pin. This pin is the inverting input node of the error amplifier.

7 RGND

8 GFXPS2

9 VCC

10 SETINIA ADC Input for Single-Phase GPU VR VBOOT Voltage Setting. 11 SETINI ADC Input for Single-Phase CPU VR VBOOT Voltage Setting. 12 TMPMAX ADC Input for Single-Phase CPU VR Maximum Temperature Setting. 13 ICCMAX ADC Input for Single-Phase CPU VR Maximum Current Setting. 14 ICCMAXA ADC Input for Single-Phase GPU VR Max imum Current Setting. 15 TSEN Thermal Monitor Sense Input Pin for CPU VR.

16 OCSET

17 TSENA Thermal Monitor Sense Input for GPU VR.

18 OCSETA

19 IBIAS 20

VRHOT 21 VR_READY CPU VR Voltage Ready Indicator. This pin has an open drain output. 22 VRA_READY GPU VR Voltage Ready Indicator. This pin has an open drain output. 23

ALERT 24 VDIO Data Transmission Line of SVID Interface. 25 VCLK Clock Signal Line of SVID Interface.

26 RGNDA 27 FBA GPU VR Feedback Pin. This pin is the inverting input node of the error amplifier. 28 COMPA 29 ISENAN Negative Current Sense Input Pin of Single- Phase GPU VR.

30 ISENAP Positive Current Sense Input Pin of Single-Phase GPU VR. 31 TONSETA

CPU VR Bootstrap Power Pin. Thi s pin powers the high side MOSFET drivers. Connect this pin to the PHASE1 pin with a bootstrap capacitor.

Single-Phase CPU VR On-Time Setting Pin. Connect this pin to V resistor to set ripple size in PWM mode.

Return Ground for CPU VR. This pin is the inverti ng input node for dif ferential remote voltage sens ing.

Set Pin for GPU VR Operation Mode. Logic-high on this pin will force the GPU V R to enter DCM.

Controller Power Supply Pin. Connect this pi n to GND via a ceramic capacitor larger than 1F.

Set Pin for Single-Phase CPU VR Over Current Protection Threshold. Connect a resistive voltage divider from VCC to ground, and connect the joint of the voltage divider to the OCSET pin. The voltage, V over current threshold, I

, for CPU VR.

LIMIT

, at this pin sets the

OCSET

Set Pin for Single-Phase GPU VR Over Current Protection Threshold. Connect a resistive voltage divider from VCC to ground, and connect the joint of the voltage divider to the OCSETA pin. The voltage, V over current threshold, I

, for GPU VR.

LIMIT

OCSETA

, at this pin sets the

Internal Bias Current Setting. Connect a 53.6k resistor from t his pin to GND to set the internal bias current.

Therm al Monitor Output Pin (active low).

Alert Line of SVID Interface (active low). This pin has an open drain output.

Return Ground for Single-Phase GPU VR. This pin is the inverting input node for differential remote voltage sensing.

Single-Phase GPU VR Compensation Pin. This pin is the output of the error amplifier.

Single-Phase GPU VR On-Time Setting Pin. Connect this pin to VIN with a resistor to set ripple size in PWM mode.

with a

IN

12

©

DS8166B-03 November 2013www.richtek.com

Pin No. Pin Name Pin Function

32 E N Voltage Regulator Enable Signal Input Pin. 33 BOOTA

34 UGATEA

35 PHASEA

36 LGATEA

37 PVCC

38 LGATE1

39 PHASE1

40 UGATE1

41 (Exp osed Pad) GND

GPU VR Bootstrap Power Pi n. This pin powers the high side MOSFET drivers. Connect thi s pin to the PHASEA pin with a bootstrap capaci tor. Upper Gate Driver of GPU VR. Thi s pi n drives the high side MOSFET of GPU VR.

Switc h Node of GPU VR. This pin i s the return node of the high side MOSF ET driver for GPU VR. Connect this pin to the joint of the source of high side MOSFET, drain of the low side MOSFET, and the output inductor.

Lowe r G ate Driv e r of GPU VR. Thi s pi n dri ves th e low s ide M OS FET of G PU VR.

MOSFET Driver Power Supply Pin. Connect this pin to GND via a ceramic capacitor larger than 1F.

Lower G ate Drive r of C PU VR. Th is pi n driv es th e low si de MOSF ET of CPU VR.

Switc h Node of CPU VR. This pin is the retur n node of the high side driver f or CPU VR. Connect this pin to the joint of the sour ce of high side MOSFET, drain of the low side MOSFET, and the output inductor. Upper Gate Driver of CPU VR. This pin drives the high side MOSFET of CPU VR.

Ground of Low Side MOSFET Driver. T he exposed pad m ust be soldered to a large PCB and connected to GND for maximum power dissipation.

RT8166B

DS8166B-03 November 2013 www.richtek.com

©

13

RT8166B

Function Block Diagram

VDIO

VCLK

ICCMAX

ICCMAXA

TMPMAX

ALERT

SETINIA

TSEN

SETINI

TSENA

EN

VR_READY

VCC

VRHOT

VRA_READY

RGNDA

FBA

COMPA

IBIAS

RGND

FB

COMP

ISEN1P

ISEN1N

From Control Logic

DAC

Soft-Start & Slew

Rate Control

From Control Logic

DAC

Soft-Start & Slew

Rate Control

SVID XCVR

V

REFA

+

-

V

REF

+

-

ERROR

AMP

ERROR

AMP

MUX

ADC

Offset

Cancellation

To Protection Logic

OCPOVP/UVP/NVP

Offset

Cancellation

UVLO

Control & Protection Logic

TON Time

PWM CMP

+

-

+

10

-

PWM CMP

+

-

To Protection Logic

+

10

-

OCP OVP/UVP/NVP

Generator

Driver Logic

Control

TON Time Generator

Driver Logic

Control

GFXPS2

TONSETA

BOOTA UGATEA

PHASEA PVCC

LGATEA

ISENAP ISENAN

OCSETA

TONSET

BOOT1 UGATE1

PHASE1

LGATE1

OCSET

©

DS8166B-03 November 2013www.richtek.com

14

RT8166B

Absolute Maximum Ratings (Note 1)

 PVCC, VCC to GND ------------------------------------------------------------------------------------- −0.3V to 6.5V  RGNDx to GND ------------------------------------------------------------------------------------------- −0.3V to 0.3V  TONSETx to GND ---------------------------------------------------------------------------------------- −0.3V to 28V  Others------------------------------------------------------------------------------------------------------- −0.3V to (V  BOOTx to PHASEx-------------------------------------------------------------------------------------- −0.3V to 6.5V  PHASEx to GND

DC------------------------------------------------------------------------------------------------------------ −3V to 28V <20ns ------------------------------------------------------------------------------------------------------- −8V to 32V

 UGATEx to PHASEx

DC------------------------------------------------------------------------------------------------------------ −0.3V to (BOOTx − PHASEx) <20ns ------------------------------------------------------------------------------------------------------- −5V to 7.5V

 LGA TEx to GND

DC------------------------------------------------------------------------------------------------------------ −0.3V to (PVCC + 0.3V) <20ns ------------------------------------------------------------------------------------------------------- −2.5V to 7.5V

 Power Dissipation, P

@ T

D

= 25°C

A

WQFN−40L 5x5------------------------------------------------------------------------------------------- 2.778W

 Package Thermal Resistance (Note 2)

WQFN−40L 5x5, θJA------------------------------------------------------------------------------------- 36°C/W WQFN−40L 5x5, θJC------------------------------------------------------------------------------------- 6°C/W

 Junction T emperature------------------------------------------------------------------------------------ 150°C  Lead T e mperature (Soldering, 10 sec.)-------------------------------------------------------------- 26 0°C  Storage T emperature Range --------------------------------------------------------------------------- −65°C to 150°C  ESD Susceptibility (Note 3)

HBM (Human Body Mode) ----------------------------------------------------------------------------- 2kV MM (Ma chine Mode)------------------------------------------------------------------------------------- 200V

+ 0.3V)

CC

Recommended Operating Conditions (Note 4)

 Supply Voltage, V  Input V oltage, V

 Junction T emperature Range--------------------------------------------------------------------------- −40°C to 125°C  Ambient T emperature Range--------------------------------------------------------------------------- −40°C to 85°C

------------------------------------------------------------------------------------- 4.5V to 5.5V

CC

----------------------------------------------------------------------------------------- 5V to 25V

IN

Electrical Characteristics

(V

= 5V, T

CC

Supply Input

Input Voltage Range Supply Curr ent

+ PVCC)

(V

CC

Supply Curr ent (TONSETx)

DS8166B-03 November 2013 www.richtek.com

= 25°C, unless otherwise specified)

A

Parameter Symbol Test Conditions Min Typ Max Unit

VCC/V V

Battery Input Voltage 5 -- 25 V

IN

I

+ I

VCC

I

TONSETx

©

VEN = 1.05V, Not Switching 4.5 5 5.5 V

PVCC

VEN = 1.05V, Not Switching -- 12 20 mA

PVCC

VFB =1 V, VIN = 12V, R

= 100k -- 110 -- A

TON

15

RT8166B

Parameter Symbol Test Conditions Min Typ Max Unit

Shutdown Current (PVCC + V

CC

)

Shutdown Current (TONSETx )

I

VCC_SHDN

+ I

PVCC_SHDN

I

TONSETx_SHDN

= 0V -- -- 5 A

V

EN

VEN = 0V -- -- 5 A

TON Setting

TONSETx Voltage V

TONSETx

On-Time tON I TONSETx Input

Current Range Mini mum Off-Time T

I

RTON

OFF_MIN

I

V

= 80A, V

RTON

= 80A, V

RTON

= 1.1V 2 5 -- 28 0 A

FBx

-- 350 -- ns

GFX VR Forced DEM

GFXPS2x Enable Threshol d G FXPS2x Disable Threshol d

V

4.3 -- -- V

GFXPS

-- -- 0.7 V

GFXPS

References and System Output Voltage

DAC Accuracy (PS0/PS1)

SETINIx Voltage V

IBIAS Pin Voltage V Dynamic VID Slew

Rate

V

FBx

SETINIx

R

IBIAS

DVID

SR

VID OFS

V V V V

SetVID Slow 2.5 3.125 3.75 SetVID Fast 10 12.5 15

Setting = 1.000V~1.520V

SVID

Set ting = 0V

SVID

Setting = 0.800V~1.000V

SVID

Set ting = 0V

SVID

Setting = 0.500V~0.800V

SVID

Set ting = 0V

SVID

Setting = 0.250V~0.500V

SVID

Set ting = 0V

SVID

Setting = 1.100V

SVID

Set ting = 0.640V~0.635V

SVID INI_CORE INI_CORE INI_CORE INI_CORE

IBIAS

= 0V, V = 0.9V, V = 1V, V = 1.1V, V

= 53.6k 2.09 2.14 2.19 V

= 1V 0.95 1.075 1.2 0V

FBx

= 1V 315 350 385 ns

FBx

0.5 0 0.5 %VID

5 0 5

8 0 8

mV

8 0 8

10 0 10

INI_GFX

= 0V 0 0.3125 0.5125

= 0.9V 0.7375 0.9375 1.1375

INI_GFX

= 1V 1.3625 1.5625 1.7625

= 1.1V 2.6125 -- 5

INI_GFX

mV/s

V

Error Amplifier

DC Gain ADC R Gain-Bandwidth

Product

Slew Rate SR

Output Voltage Range

MAX Source/Sink Current

Impedance of F Bx R

16

©

GBW C

COMP

V

I

R

COMP

V

COMP

1 -- -- M

FBx

= 47k (Note5) 70 80 -- dB

L

= 5pF (Note5) -- 10 -- MHz

LOAD

= 10pF ( Gain = 4,

C

LOAD

R

LOAD_COMP

V

COMPx

= 47k 0.5 -- 3.6 V

L

COMP

= 47k,

= 0.5V to 3V)

= 2V -- 250 -- A

-- 5 -- V/s

DS8166B-03 November 2013www.richtek.com

Current Sense Amplifier

RT8166B

Parameter Symbol Test Conditions Min Typ Max Unit

Input Offset Voltage V Impedance of Ne g. Input R Impedance of Pos. Input R Current Sense

Diffe re nti al Inpu t Ra nge Current Sense D C Gain

(Loop) V

Linear ity V

ISEN

V

A

Gate Driver

Upper Driver Sour ce R Upper Driver Sink R

Lower Driver Sour ce R L o wer Dri v e r Sink R Internal Boot Charging

Switch On - R esis ta n ce Zero Current Det ection

Threshold

R

V

Protection Under Vol tage Lock-out

Threshold Under Vol tage Lock-out

Hysteresis Over Voltage Protection

Threshold Under Vol tage Protection

Threshold Negat ive Voltage

Pro te cti on Threshold Curre nt Sense Ga in for

Over Current Protection

V

V

V

A

Logic Inputs

OFS_CSA

ISENxN ISENxP

CSDIx

V

I

ISEN_ACC

UGATEx_sr

UGATEx_sk LGATEx_sr LGATEx_sk

BOOTx

ZCD_TH

UVLO

OVP

UVP

NVP

OC

1 -- 1 mV

1 -- -- M

V

= 1.1V,

FBx

V

CSDIx

FBx

V

DAC

V

BOOTx

V

BOOTx

V

UGATEx

= V

ISENxP

= 1.1V, 30mV < V

= 1.1V 30mV < V

 V

PHASEx

 V

UGATEx

= 0.1V -- 1 -- 

PVCC = 5V, PVCC  V

V

LGATEx

= 0.1V -- 0.5 -- 

 V

= 5V

= 0.1V

ISENxN

CSDIx

ISEN_IN

LGATEx

< 50mV -- 10 -- V/ V

< 50mV 1 -- 1 %

= 0.1V - - 1 -- 

50 -- 100 mV

-- 1 -- 

PVCC to BOOTx -- 30 -- 

V

ZCD_TH

= GN D  V

PHASEx

-- 10 -- mV

VCC Falling edge 4.04 4.24 -- V

-- 100 -- mV

V

Respect to VOUT_MAX filte r time

V

= V

UVP

<1. 52V, with 3s filter time

= V

NVP

V

OCSET

V

ISENxP

ISENxN

= 2.4V  V

ISENxN

 V

REFx

 GND 100 50 -- mV

= 50mV

, with 1s

SVID

, 0.8V < V

100 150 200 mV

REFx

350 300 250 mV

-- 48 -- V/V

EN Input Threshold Voltage

Logic-High VIH With respe c t to 1V, 70% 0.7 -- --

Logic-Low V

With respe c t to 1V, 30% -- -- 0.3

IL

V

Leakage Current of EN 1 -- 1 A VCLK,VDIO Input

Threshold Vol tage Leakage Current of

VC L K, VDI O

DS8166B-03 November 2013 www.richtek.com

©

VIH With respect to Intel Spec. 0.65 -- --

With respect to Intel Spec. -- -- 0.45

V

IL

I

LEAK_IN

1 -- 1 A

V

17

RT8166B

Parameter Symbol Test Conditions Min Typ Max Unit

ALERT

A LERT Low Vo ltage

VR Ready

VRx_READY Low Voltage V VRx_READY D elay t

Ther ma l Throttling

VRHOT Output Voltage V

High Impedance Output

V

ALERT

VRx_READY IVRx_READY_ SINK

VRx_READY

VRHOT

I

ALERT_ SINK

V

ISENxN

I

VRHOT_SINK

= V

= 4mA

BOOT

= 40mA

-- -- 0.4 V

= 4mA -- -- 0.4 V to V

VRx_RE ADY

high 70 100 160 s

-- 0.4 -- V

ALERT, VRx_READY, VRHOT

Temperature Zone

TSEN Threshold for Tmp_Zone [7] transition

TSEN Threshold for Tmp_Zone [6] transition

TSEN Threshold for Tmp_Zone [5] transition

TSEN Threshold for Tmp_Zone [4] transition

TSEN Threshold for Tmp_Zone [3] transition

TSEN Threshold for Tmp_Zone [2] transition

TSEN Threshold for Tmp_Zone [1] transition

TSEN Threshold for Tmp_Zone [0] transition

Update Period t

ADC

I

LEAK_OUT

1 -- 1 A

100°C -- 1.8725 -- V

97°C -- 1.8175 -- V

V

TSENx

94°C -- 1.7625 -- V

91°C -- 1.7075 -- V

88°C -- 1.6525 -- V

85°C -- 1.5975 -- V

V

TSENx

82°C -- 1.5425 -- V

75°C -- 1.4875 -- V

-- 1600 -- s

TSEN

Latency t

Digital Code of ICCMAX

Digital Code of ICCMAXA

Digital Code of TMPMAX

18

©

-- -- 400 s

LAT

C

ICCMAX1

C

ICCMAX2

C

ICCMAX3

C

ICCMAXA1

C

ICCMAXA2

C

ICCMAXA3

C

TMPMAX1

C

TMPMAX2

C

TMPMAX3

V

ICCMAX

V

ICCMAX

V

ICCMAX

V

ICCMAXA

V

ICCMAXA

V

ICCMAXA

V

TMPMAX

V

TMPMAX

V

TMPMAX

= 0.637V 29 32 35 decimal = 1.2642V 61 64 67 decimal = 2.5186V 125 128 131 decimal

= 0.1666V 5 8 11 decimal = 0.3234V 13 16 19 decimal

= 0.637V 29 32 35 decimal = 1.6758V 82 85 88 decimal = 1.9698V 97 100 103 decimal = 2.4598V 122 125 128 decimal

DS8166B-03 November 2013www.richtek.com

RT8166B

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability.

Note 2. θ

is measured at T

JA

measured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guaranteed by design.

= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is

A

©

DS8166B-03 November 2013 www.richtek.com

19

RT8166B

Typical Operating Characteristics

V

CORE

(500mV/Div)

EN

(2V/Div)

VR_READY

(2V/Div)

UGATE

(20V/Div)

V

CORE

(1V/Div)

CORE VR Power On from EN

Boot VID = 1V

Time (100μs/Div)

CORE VR OCP

V

CORE

(500mV/Div)

EN

(2V/Div)

VR_READY

(2V/Div)

UGATE

(20V/Div)

V

CORE

(1V/Div)

CORE VR Power Off from EN

Boot VID = 1V

Time (100μs/Div)

CORE VR OVP and NVP

I

LOAD

(10A/Div)

VR_READY

(1V/Div)

UGATE

(20V/Div)

V

CORE

(500mV/Div)

VCLK

(2V/Div)

VDIO

(2V/Div) ALERT

(2V/Div)

VID = 1.1V

Time (100μs/Div)

CORE VR Dynamic VID Up

0.7V to 1.2V, Slew Rate = Slow, I

LOAD =

4A

LGATE

(10V/Div)

VR_READY

(1V/Div)

UGATE

(20V/Div)

V

CORE

(500mV/Div)

VCLK

(2V/Div)

VDIO

(2V/Div) ALERT

(2V/Div)

VID = 1.1V

Time (40μs/Div)

CORE VR Dynamic VID Down

1.2V to 0.7V, Slew Rate = Slow, I

LOAD =

4A

Time (40μs/Div)

©

Time (40μs/Div)

DS8166B-03 November 2013www.richtek.com

20

RT8166B

V

CORE

(500mV/Div)

VCLK

(2V/Div)

VDIO

(2V/Div) ALERT

(2V/Div)

V

CORE

(20mV/Div)

CORE VR Dynamic VID Up

0.7V to 1.2V, Slew Rate = Fast, I

Time (10μs/Div)

CORE VR Load Transient

LOAD =

4A

V

CORE

(500mV/Div)

VCLK

(2V/Div)

VDIO

(2V/Div) ALERT

(2V/Div)

V

CORE

(20mV/Div)

CORE VR Dynamic VID Down

1.2V to 0.7V, Slew Rate = Fast, I

Time (10μs/Div)

LOAD =

CORE VR Load Transient

4A

I

LOAD

(A/Div)

V

CORE

(20mV/Div)

VCLK

(1V/Div)

LGATE

(10V/Div)

UGATE

(20V/Div)

8 1

VID = 1.1V, I

1A to 8A, Slew Time = 150ns

LOAD =

Time (100μs/Div)

CORE VR Mode Transition

VID = 1.1V , PS0 to PS2, I

Time (100μs/Div)

LOAD =

0.2A

I

LOAD

(A/Div)

V

CORE

(20mV/Div)

VCLK

(1V/Div) LGATE

(10V/Div)

UGATE

(20V/Div)

8 1

VID = 1.1V, I

8A to 1A, Slew Time = 150ns

LOAD =

Time (100μs/Div)

CORE VR Mode Transition

VID = 1.1V , PS2 to PS0, I

Time (100μs/Div)

LOAD =

0.2A

©

DS8166B-03 November 2013 www.richtek.com

21

RT8166B

1.9

TSEN

(V/Div)

1.7

VRHOT

(500mV/Div)

V

GFX

(500mV/Div)

EN

(2V/Div)

VRA_READY

(2V/Div)

CORE VR Thermal Monitoring

TSEN Sweep from 1.7V to 1.9V

Time (10ms/Div)

GFX VR Power On from EN

1.006

1.004

1.002

1.000

(V)

0.998

REF

V

0.996

0.994

0.992

0.990

V

GFX

(500mV/Div)

EN

(2V/Div)

VRA_READY

(2V/Div)

CORE VR V

-50 -25 0 25 50 75 100 125

vs. Tem perature

REF

Temperature (°C)

GFX VR Power Off from EN

UGATEA

(20V/Div)

V

GFX

(1V/Div)

I

LOAD

(5A/Div)

VRA_READY

(1V/Div)

UGATEA

(20V/Div)

Time (100μs/Div)

GFX VR OCP

Time (100μs/Div)

Boot VID = 1V

UGATEA

(20V/Div)

V

GFX

(1V/Div)

VRA_READY

(1V/Div)

LGATEA

(10V/Div)

UGATEA

(20V/Div)

Boot VID = 1V

Time (100μs/Div)

GFX VR OVP and NVP

VID = 1.1V

Time (40μs/Div)

©

DS8166B-03 November 2013www.richtek.com

22

RT8166B

V

GFX

(500mV/Div)

VCLK

(2V/Div)

VDIO

(2V/Div) ALERT

(2V/Div)

V

GFX

(500mV/Div)

GFX VR Dynamic VID

0.7V to 1.2V, Slew Rate = Slow, I

Time (40μs/Div)

GFX VR Dynamic VID

LOAD =

1.25A

V

GFX

(500mV/Div)

VCLK

(2V/Div)

VDIO

(2V/Div) ALERT

(2V/Div)

V

GFX

(500mV/Div)

GFX VR Dynamic VID

1.2V to 0.7V, Slew Rate = Slow, I

Time (40μs/Div)

GFX VR Dynamic VID

LOAD =

1.25A

VCLK

(2V/Div)

VDIO

(2V/Div) ALERT

(2V/Div)

V

GFX

(20mV/Div)

I

LOAD

(A/Div)

4 1

0.7V to 1.2V, Slew Rate = Fast, I

Time (10μs/Div)

GFX VR Load Transient

VID = 1.1V, I

1A to 4A, Slew Time = 150ns

LOAD =

1.25A

VCLK

(2V/Div)

VDIO

(2V/Div) ALERT

(2V/Div)

V

GFX

(20mV/Div)

I

LOAD

(A/Div)

4 1

1.2V to 0.7V, Slew Rate = Fast, I

Time (10μs/Div)

GFX VR Load Transient

VID = 1.1V, I

4A to 1A, Slew Time = 150ns

LOAD =

1.25A

Time (100μs/Div)

©

Time (100μs/Div)

DS8166B-03 November 2013 www.richtek.com

23

RT8166B

V

GFX

(20mV/Div)

VCLK

(1V/Div)

LGATEA

(10V/Div)

UGATEA

(20V/Div)

1.9

TSENA

(V/Div)

1.7

GFX VR Mode Transition

VID = 1.1V , PS0 to PS2, I

Time (100μs/Div)

LOAD =

GFX VR Thermal Monitoring

0.1A

V

GFX

(20mV/Div)

VCLK

(1V/Div)

LGATEA

(10V/Div)

UGATEA

(20V/Div)

1.006

1.004

1.002

1.000

0.998

(V)

0.996

REF

V

0.994

GFX VR Mode Transition

VID = 1.1V , PS2 to PS0, I

Time (100μs/Div)

GFX VR V

vs. Temperature

REF

LOAD =

0.1A

VRHOT

(500mV/Div)

TSENA Sweep from 1.7V to 1.9V

Time (10ms/Div)

0.992

0.990

0.988

-50-250 255075100125

Temperatur e (°C)

©

DS8166B-03 November 2013www.richtek.com

24

Application Information

RT8166B

The RT8166B is a VR12/IMVP7 compliant, dual singlephase synchronous Buck PWM controller for the CPU CORE VR a nd GFX VR. The gate drivers are embedded to facilitate PCB design a nd reduce the total BOM cost. A Serial VID (SVID) interface is built-in in the RT8166B to communicate with Intel VR12/IMVP7 complia nt CPU.

The RT8166B adopts G-NAVPTM (Green Native AVP), which is Richtek's proprietary topology derived from finite DC gain compensator, making it an easy setting PWM controller to meet AVP requirements. The load line can be ea sily progra mmed by setting the DC gain of the error amplif ier. The RT8166B has fast transient response due to the G-NAVPTM commanding variable switching frequency .

G-NAVPTM topology also represents a high efficiency system with green power concept. With G-NAVP topology , the RT8166B becomes a green power controller with high efficiency under heavy load, light load, a nd very light load conditions. The RT8166B supports mode transition function between CCM a nd DEM. These dif ferent operating states allow the overall power system to have low power loss. By utilizing the G-NAVPTM topology , the operating frequency of RT8166B varies with output voltage, load and VIN to further enhance the eff iciency even in CCM.

The built-in high accuracy DAC converts the SVID code ranging from 0.25V to 1.52V with 5mV per step. The differential remote output voltage sense a nd high accura cy DAC allow the system to have high output voltage accura cy.

TM

The RT8166B supports VR12/IMVP7 compatible power management states a nd VID on-the-fly function. The power management states include DEM in PS2/PS3 and ForcedCCM in PS1/PS0. The VID on-the-fly function has three different slew rates : Fa st, Slow and Decay . The RT8166B integrates a high accuracy ADC for platform setting functions, such as no-load offset and over current level. The controller supports both DCR and sense resistor current sensing. The RT8166B provides VR ready output signals of both CORE VR and GFX VR. It also features complete fault protection functions including over voltage, under voltage, negative voltage, over current and under voltage lockout. The RT8166B is available in a WQFN40L 5x5 small foot print package.

Design Tool

T o help users reduce eff orts and errors caused by ma nual calculations, a user-friendly design tool is now available on request. This design tool calculates all necessary design parameters by entering user's requirements. Plea se conta ct Richtek's representatives for details.

Serial VID (SVID) Interface

SVID is a three-wire seri al synchronous interface defined by Intel. The three wire bus includes VDIO, VCLK and ALERT signals. The master (Intel's VR12/IMVP7 CPU) initiates and termin ates SVID tra nsa ctions a nd drives the V DIO, VCLK, and ALERT during a transa ction. The slave (RT8166B) receives the SVID transactions and acts accordingly.

DS8166B-03 November 2013 www.richtek.com

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25

RT8166B

Standard Serial VID Command

Code Commands

00h not supported N/A N/A N/A

01h SetVID_Fast VID code N/A

02h SetVID_Slow VID code N/A

03h SetVID_Decay VID code N/A

04h SetPS

05h SetRegADR

06h SetReg DAT

07h GetReg

08h

-

1Fh

not supported N/A N/A N/A

Master Payload

Contents

Byte indicating

po wer st ates

Pointer of registers

in data table

New data regis ter

content

Pointer of registers

in data table

Slave Payload

Contents

Set new tar get VID code, VR jumps t o new VID target with controlled default “fast” slew rate

12.5mV/s. Set new tar get VID code, VR jumps t o new VID

target with controlled default “slow” slew rate

3.125m V/s. Set new tar get VID code, VR jumps t o new VID target, but does not control the slew rate. The output voltage decays at a rate proportional to the load current

N/A Set power state

N/A Set the pointer of the data register

N/A Write t he contents to the data register

Specified

Register

Contents

Slave returns the contents of the specified register as the payload

Description

26

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DS8166B-03 November 2013www.richtek.com

RT8166B

Data and Configuration Register

Index Register Name Description Access Default

00h Vendor ID Vendor ID, default 1Eh. RO, Vendor 1Eh 01h Product ID Product ID. RO, Vendor 65h 02h Product Revision Product Revision. RO, Vendor 01h 05h Protocol ID SVID Protocol ID. RO, Vendor 01h

Bit mapped register, identifies the SVID VR capabilities

06h VR_Capability

10h St a tus _1 Data regis t er co ntai nin g t he stat us of VR. R-M , W-PW M 00 h 11h Status -2 Data reg is ter co ntai ning the status of t ran smi ss ion . R- M , W-PW M 00h

12h

Temperature Zone

15h Output_Current

1Ch Status_2_lastread The register contains a copy of the status_2. R-M, W-PWM 00h

21h ICC_Max

22h Temp_Max

24h SR-Fast

and which of the optional telemetry register are supported.

Data reg is ter sho wi ng temp er at ure zo ne that have been entered.

Data register showing direct ADC conversion of averaged output current.

Data register containing the maximum ICC of platform supports. Binary format in Amp, IE 64h = 100A. Data register containing the temperature max the platform supports. Binary format in °C, IE 64h = 100°C Only fo r CORE VR

Data register containing the capability of fast slew rate the platform can sustains. Binary format in mV/s, IE 0Ah = 10mV/s.

RO, Vendor 81h

R-M, W-PWM 00h

RO, Platform --

RO 0Ah

25h SR-Slow

30h VOUT_Max

Data reg is ter co ntainin g t he capability of slow slew rat e. Binary format in mV/s IE 02h = 2.5mV/s.

The register is programmed by the master and sets the maximum VID.

RO 02h

RW, Master FBh

31h VID Set ti ng Data reg is ter co nt ai nin g currently prog r amm e d VID. RW, Maste r 00 h 32h Power Stat e Regis ter co ntai ni ng the cu r rent pr og ramm ed pow er state. RW, Maste r 00 h 33h Offset Set offset in VID steps. RW, Master 00h

34h Multi VR Config

35h Pointer

Notes : RO = Read Only RW = Read/Write R-M = Read by Master W -PWM = Write by PWM only

Vendor = hard coded by VR vendor Platform = programmed by platform Master = programmed by the master PWM = programmed by the VR control IC

Bit mapped data register which configures multiple VRs behavior on the same bus.

Scratch pa d registe r for temporary s torage o f the Se tR egA DR poi nter regis ter .

RW, Master 00h

RW, Master 30h

DS8166B-03 November 2013 www.richtek.com

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27

RT8166B

Power Ready Detection and Power On Reset (POR)

During start-up, the RT8166B detects the voltage on the voltage input pins : VCC and EN. When VCC > V

UVLO

the RT8166B will recognize the power state of system to be ready (POR = high) and wait for enable command at EN pin. After POR = high and EN > V

, the RT8166B

ENTH

will enter start-up sequence for both CORE VR a nd GFX VR. If the voltage on any voltage pin drops below POR threshold (POR = low), the RT8166B will enter power down sequence and all the functions will be disa bled. SVID will be invalid within 300μs after chip becomes enabled. All the protection latches (OVP, OCP, UVP, OTP) will be cleared only after POR = low. EN = low will not clear these latches.

VCC

EN

V

U

V

E

N

+

L

O

-

+

-

T

H

POR

Chip EN

ICCMAX, ICCMAXA and TMPMAX

The RT8166B provides ICCMAX, ICCMAXA a nd TMPMAX pins for platform users to set the maximum level of output

,

current or VR temperature: ICCMAX for CORE VR maximum current, ICCMAXA for GFX VR maximum current, and TMPMAX for CORE VR maximum temperature.

To set ICCMAX, ICCMAXA and TMPMAX, platform designers should use resistive voltage dividers on these three pins. The current of the divider should be several milli-Amps to avoid noise effect. The three items share the same algorithms : the ADC divides 5V into 255 levels. Therefore, LSB = 5/255 = 19.6mV , which mea ns 19.6mV applied to ICCMAX pin equals to 1A setting. For exa mple, if a platform designer wants to set TMPMAX to 120°C, the voltage applied to TMPMAX should be 120 x 19.6mV =

2.352V. The ADC circuit inside these three pins will decode the voltage a pplied and store the maximum current/ temperature setting into ICC_MAX and Temp_Max

Figure 1. Power Ready Detection and Power On Reset

(POR)

Precise Reference Current Generation

The RT8166B includes extensive analog circuits inside the controller. These analog circuits need very precise reference voltage/current to drive these analog devices. The RT8166B will auto-generate a 2.14V voltage source at IBIAS pin, and a 53.6kΩ resistor is required to be connected between IBIAS and analog ground. Through this connection, the RT8166B generates a 40μA current

registers. The ADC monitors a nd decodes the voltage at these three pins only after EN = high. If EN = low, the RT8166B will not take a ny action even when the V R output current or temperature exceeds its maximum setting at these ADC pins. The maximum level settings at these ADC pins are different from over current protection or over temperature protection. That mea ns, these maximum level setting pins are only for platform users to define their system operating conditions and these messages will only be utilized by the CPU.

V

CC

from IBIAS pin to analog ground a nd this 40μA current will be mirrored inside the RT8166B for internal use. Other types of connection or other values of resistance a pplied at the IBIAS pin may cause failure of the RT8166B's analog

A/D

Converter

ICCMAX

ICCMAXA

TMPMAX

circuits. Thus a 53.6kΩ resistor is the only recommended component to be connected to the IBIAS pin. The resistance accuracy of this resistor is recommended to be at least 1%.

Current

2.14V

-

Mirror

+

-

IBIAS

53.6k

V

INI_CORE

The initial start up voltage (V RT8166B can be set by platform users through SETINI and SETINIA pins. V oltage divider circuit is recommended to be applied to SETINI a nd SETINIA pins. The V V

relate to SETINI/SETINIA pin voltage setting as

INI_GFX

Figure 3. ADC Pins Setting

and V

INI_GFX

Setting

INI_CORE

, V

INI_GFX

shown in Figure 4. Recommended voltage setting at SETINI

Figure 2. IBIAS Setting

28

©

and SETINIA pins are also shown in Figure 4.

DS8166B-03 November 2013www.richtek.com

) of the

INI_CORE

/

RT8166B

V

(

C

5

V

)

V

N

I

V

N

I

V

=

1

.

1

I

_

C

O

I

_

I

G

N

_

I

C

N

I

V

I

N

I

_

O

I

C

I

_

I

G

N

_

I

C

N

I

V

I

N

I

V

E

R

=

1

.

V

F

X

2

1

/

V

C

1

=

V

O

E

R

1

=

V

_

G

F

X

4

1

/

V

C

=

0

.

9

V

R

E

=

0

.

9

V

F

X

0

=

V

O

E

R

=

0

V

_

G

F

X

C

8

1

/

V

C

D

G

N

Figure 4. SETINI and SETINIA Pin Voltage Setting

Start Up Sequence

The RT8166B utilizes internal soft-start sequence which strictly follows Intel VR12/IMVP7 start up sequence specifications. After POR = high a nd EN = high, a 300μs delay is needed for the controller to determine whether all the power inputs are ready for entering start up sequence. If pin voltage of SETINI/SETINIA is zero, the output voltage of CORE/GFX VR is programmed to stay at 0V. If pin voltage of SETINI/SETINIA is not zero, VR output voltage will ramp up to initi al boot voltage (V

INI_CORE

, V

INI_GFX

) after both POR = high and EN = high. After the output voltage of CORE/GFX VR rea ches target initial boot voltage, the controller will keep the output voltage at the initial boot voltage and wait for the next SVID commands. After the RT8166B receives valid VID code (typically SetVID_Slow command), the output voltage will ramp up/down to the target voltage with specified slew rate. After the output voltage reaches the target voltage, the RT8166B will send out VR_READY signal to indicate the power state of the RT8166B is ready. The VR_READY circuit is an opendrain structure so a pull-up resistor is recommended for connecting to a voltage source.

V

INI_CORE

V

INI_GFX

1.1V

0.9V

1V

0V

SETINI/SETINIA Pin Voltage

Recommended

5

x VCC≒3.125V or VCC

8

3

x VCC≒1.875V

8

3

x VCC≒0.9375V

16

1

x VCC≒0.3125V or GND

16

Power Down Sequence

Similar to the start up sequence, the RT8166B also utilizes a soft shutdown mechanism during turn-off. After POR = low, the internal reference voltage (positive terminal of compensation EA) starts ramping down with 3.125mV/μs slew rate, and output voltage will follow the reference voltage to 0V . After output voltage drops below 0.2V, the RT8166B shuts down and all functions are disa bled. The VR_READY will be pulled down immediately after POR = low.

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DS8166B-03 November 2013 www.richtek.com

29

RT8166B

VCC

POR

EN Chip

(Internal Signal)

EN

SVID

V

CORE

CORE VR

Operation Mode

V

GFX

GFX VR

Operation Mode

VR_READY

VRA_READY

VCC

POR

EN Chip

(Internal Signal)

XX

Off

300µs

CCM CCM

CCM

100µs

Valid xx

SVID defined

Figure 5 (a). Power sequence for RT8166B (V

EN

300µs

SVID defined

100µs

INI_CORE

= V

CCM

INI_GFX

0.2V Off

= 0V)

SVID

V

CORE

CORE VR

Operation Mode

VR_READY

V

GFX

GFX VR

Operation Mode

VRA_READY

XX

250µs

50µs

V

INI_CORE

CCM CCMOff

100µs

V

INI_GFX

CCMOff

100µs

Figure 5 (b). Power sequence for RT8166B (V

©

Valid

SVID define d

INI_CORE

CCM

0, V

 

INI_GFX

0V)

xx

0.2V Off

DS8166B-03 November 2013www.richtek.com

30

RT8166B

Disable GFX VR : Before EN = High

GFX VR enable or disable is determined by the internal circuitry that monitors the ISENAN voltage during start up. Before EN = high, GFX V R detects whether the voltage of ISENAN is higher than “VCC − 1V” to disable GFX VR. The unused driver pins ca n be connected to GND or left floating.

GFX VR Forced-DEM Function Enable : After VRA_Ready = High

The GFX VR's forced-DEM function can be enabled or disabled with GFXPS2 pin. The RT8166B detects the voltage of GFXPS2 f or forced-DEM function. If the voltage at GFXPS2 pin is higher tha n 4.3V , the GFX V R operates in forced-DEM. If this voltage is lower than 0.7V, the G FX VR follows SVID power state comma nd.

Loop Control

Both CORE and GFX VR adopt Richtek's proprietary GNAVPTM topology . G-NAVPTM is based on the f inite-gain valley current mode with CCRCOT (Constant Current Ripple Constant On T ime) topology. The output voltage, V

CORE

or V

, will decrea se with incre asing output load

GFX

current. The control loop consists of PWM modulator with power stage, current sense amplifier and error amplifier a s shown in Figure 6.

Similar to the valley current mode control with finite compensator gain, the high side MOSFET on-time is determined by the CCRCOT PWM generator. When load current increas es, VCS increa ses, the steady state COMP voltage also increases which makes the output voltage decrea se, thus a chieving AVP.

Droop Setting (with Temperature Compensation)

It's very easy to achieve the Active Voltage Positioning (AVP) by properly setting the error amplifier gain due to the native droop characteristics. The target is to have

V

= V

OUT

Then solving the switching condition V

REFx

− I

LOAD

x R

(1)

DROOP

COMPx

= V

CSx

in

Figure 6 yields the desired error amplif ier gain a s

R2



A

V

R1 R

I SENSE

DROOP

(2)



AR

where AI is the internal current sense amplifier gain and R

is the current sense resistance. If no external sens e

SENSE

resistor is present, the DCR of the inductor will act as R

SENSE

. R

is the resistive slope value of the converter

DROOP

output and is the desired static output impedance.

V

OUT

A

> A

V2

V1

A

V2

A

V1

OUT

GFX/CORE VR

CCRCOT

PWM Generator

CMP

+

-

V

CSx

Driver

Logic

Control

+

Ai

-

UGATEx PHASEx

LGATEx

ISENxP

ISENxN

COMPx

FBx

C

Byp

V

IN

High Side MOSFET

Low Side MOSFET

C2 C1

R2

R1

R

X

(V

L

C

X

CORE/GFX VR V

CC_SENSE

V

OUT

CORE/VGFX

R

C

)

0

Load Current

Figure 7. Error Amplifier Gain (AV) Influence on V

Accuracy

Since the DCR of inductor is temperature dependent, it affects the output accura cy in high temperature conditions. Temperature compensation is recommended for the lossless inductor DCR current sense method. Figure 8 shows a simple but effective way of compensating the temperature variations of the sense resistor using a n N TC

-

EA

+

VREFx

RGNDx

-

+

CORE/GFX VR V

SS_SENSE

thermistor placed in the feedba ck path.

Figure 6. Simplified Schematic for Droop a nd Remote

Sense in CCM

DS8166B-03 November 2013 www.richtek.com

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31

RT8166B





C2 C1

EA

FBx

R2

V

SS_SENSE

COMPx

-

+

-

+

RGNDx

VREFx

R1b

R1a

NTC

V

CC_SENSE

Figure 8. Loop Setting with T emperature Compen sation

Usually, R1a is set to equal R

(25°C), while R1b is

NTC

selected to linearize the NTC's temperature chara cteristic. For a given NTC, the design would be to obtain R1b a nd R2 and then C1 a nd C2. According to (2), to compensate the temperature variations of the sense resistor , the error amplifier gain (AV) should have the same temperature coefficient with R

AR

V, HOT SENSE, HOT

AR

V, COLD SENSE, COLD



SENSE

. Hence

(3)

From (2), we can have Av at a ny temperature (T) a s

A



V, T

R1 a / /R R1 b

R2

NTC, T



(4)

The standard formula f or the resistance of NTC thermistor as a function of te mperature is given by :



11









T+273 298

RR e

where R



NTC, T NTC, 25

is the thermistor's nominal resistance at

NTC, 25



(5)

room temperature, β (beta) is the thermistor's material constant in Kelvins, and T is the thermistor's actual temperature in Celsius.

The DCR value at different te mperatures can be calculated

R1 b



R

SENSE, HOT

R

SENSE, COLD

(R1a //R ) (R1a//R )



NTC, HOT NT C, COLD

R



SENSE, HOT

1





R

SENSE, COLD



Loop Compensation

Optimized compensation of the CORE VR allows for best possible load step response of the regulator's output. A type-I compensator with one pole and one zero is adequate for a proper compensation. Figure 8 shows the compensation circuit. It wa s previously mentioned that to determine the resistive feedback components of error amplifier gain, C1 and C2 must be calculated for the compensation. The target is to a chieve constant resistive output impedance over the widest possible frequency range.

The pole frequency of the compensator must be set to compensate the output ca p acitor ESR zero :

f



P

1

2CR

 

C

where C is the cap acita nce of the output capa citor and R is the ESR of the output cap acitor. C2 can be calculated as follows :

CR



C2



C

R2

The zero of compensator has to be placed at half of the switching frequency to filter the switching-related noise. Such that,

C1



R1 b R1 a//R f





1

NTC, 25 C S W



using the equation below :

TON Setting

DCRT = DCR25 x [1+0.00393 x (T-25)] (6) where 0.00393 is the temperature coefficient of copper.

For a given NTC thermistor , solving (4) at room temperature (25°C) yields

R2 = A where A

x (R1b + R1a // R

V, 25

is the error amplif ier gain at room temperature

V, 25°C

) (7)

NTC, 25

obtained from (2). R1b can be obtained by substituting (7) to (3),

32

©

High frequency operation optimizes the application by trading off efficiency due to higher switching losses with smaller component size. This may be acceptable in ultraportable devices where the load currents are lower and the controller is powered from a lower voltage supply . Low frequency operation offers the best overall efficiency at the expense of component size and board spa ce. Figure 9 shows the on-time setting circuit. Connect a resistor (R

TONSETx

of UGA TEx :

t (V 1.2V)

ONx REFx

) between VIN and T ONSETx to set the on-time

-12





28 10 R

DS8166B-03 November 2013www.richtek.com

VV

IN REFx

TONSETx



(8)

(9)

C

(10)

(11)

(12)

RT8166B

where t voltage of converter, and V voltage.

When V frequency may be over the maximum design range, ma king it unaccepta ble. Therefore, the VR i mplements a pseudoconstant-frequency technology to avoid this disadva ntage of CCRCOT topology. When V the on-time equation will be modified to :

t (V 1.2V)

ONx REFx

is the UGA TEx turn on period, VIN is the input

ONx

is the internal reference

REFx

is larger than 1.2V, the equivalent switching

REFx

is larger than 1.2V,

REFx



-12

 

23.33 10 R V



TONSETx REFx



VV

IN REFx

(13)

Differential Remote Sense Setting

The CORE/GFX VR includes differential, remote-sense inputs to eliminate the effects of voltage drops along the PC board traces, CPU internal power routes and socket contacts. The CPU contains on-die sense pins CORE/ GFX V GFX V

CC_SENSE

SS_SENSE

and V

SS_SENSE

. Connect RGNDx to CORE/

. Connect FBx to CORE/GFX V

CC_SENSE

with a resistor to build the negative input path of the error a mplifier. The precision voltage reference V

is referred

REFx

to RGND f or a ccurate remote sensing.

Current Sense Setting

The current sense topology of the CORE/GFX VR is

On-time tran slates roughly to switching frequencies. The on-times guara nteed in the Electrical Characteristics are influenced by switching delays in external high side MOSFET . Also, the dead-time effect increa ses the effective on-time, reducing the switching frequency . It occurs only in CCM during dynamic output voltage transitions when

continuous inductor current sensing. Therefore, the controller can be less noise sensitive. Low of fset amplif iers are used for loop control and over current detection. The internal current sense a mplifier gain (AI) is fixed to be 10. The ISENxP and ISENxN denote the positive and negative input of the current sense a mplifier .

the inductor current reverses at light or negative load currents. With reversed inductor current, PHASEx goes high earlier than normal, extending the on-time by a period equal to the high side MOSFET rising dead time.

For better efficiency of the given load ra nge, the maximum switching frequency is suggested to be :

f(kHz)

S(MAX)

VI R DCRR

REFx(MAX) LOAD(MAX) ON_LS FET DROOP

VI R R

IN(MAX) LOAD(MAX) ON_LS FET ON_HS FET



tt

   

1



ON HS Delay



 





(14)

where f

is the turn on delay of high side MOSFET , V

Delay

is the maximum switching frequency, t

S(MAX)

HS-

REFx(MAX)

is the maximum application DAC voltage of application, V

IN(MAX)

I

LOAD(MAX)

is the low side MOSFET R side MOSFET R R

DROOP

is the maximum application input voltage,

is the maximum load of a pplication, R

, R

DS(ON)

, DCRL is the inductor DCR, and

DS(ON)

ON_HS-FET

ON_LS-FET

is the high

is the load line setting.

GFX/CORE

VR CCRCOT

PWM

Generator

TONSETx

VREFx

R

TONSETx

C1

R1

V

IN

Users can either use a current sense resistor or the inductor's DCR f or current sensing. Using inductor's DCR allows higher efficiency a s shown in Figure 10. To let

L

DCR

RC



X

(15)

then the transient performance will be optimum. For example, choose L = 0.36μH with 1mΩ DCR and C

= 100nF, to yields for R

X

0.36 H

V



CSx



PHASEx

+

A

I

-

R3.6k



X

1m 100nF

ISENxP

ISENxN

:

X

(16)

V

OUT

(V

CORE/VGFX

L

DCR

C

R

X

)

C

Byp

Figure 10. Lossless Inductor Sensing

Considering the inductance tolera nce, the resistor RX has to be tuned on board by examining the tra nsient voltage. If the output voltage transient has an initial dip below the minimum load line requirement with a slow recovery, R is too small. Vice versa, if the resista nce is too large the

On-Time

Figure 9. On-Time Setting with RC Filter

DS8166B-03 November 2013 www.richtek.com

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output voltage transient will only have a small initial dip and the recovery will be too fast, causing a ring-back.

33

X

RT8166B

Using current-sense resistor in series with the inductor can have better a ccuracy , but the ef ficiency is a trade-off. Considering the equivalent inductance (L

) of the current

ESL

sense resistor, a RC f ilter is recommended. The RC filter calculation method is similar to the above-mentioned inductor DCR sensing method.

Operation Mode Transition

The RT8166B supports operation mode transition function in CORE/GFX VR for the SetPS comma nd of Intel's VR12/ IMVP7 CPU. The default operation mode of the RT8166B's CORE/GFX VR is PS0, which is CCM operation. The other operation mode is PS2 (DEM operation).

After receiving SetPS command, the CORE/GFX V R will immediately change to the new operation state. When VR receives SetPS command of PS2 operation mode, the VR operates as a DEM controller.

If VR receives dyna mic VID change command (SetVID), VR will automatically enter PS0 operation mode. After output voltage reaches target voltage, V R will stay at PS0 state and ignore former SetPS command. Only by re-sending SetPS command after SetVID command will VR be forced into PS2 operation state again.

Thermal Monitoring and Temperature Reporting

CORE/GFX VR provides thermal monitoring function via sensing TSEN pin voltage. Through the voltage divider resistors R1, R2, R3 and R

, the voltage of TSEN will

NTC

be proportional to VR temperature. When VR temperature rises, the TSENx voltage also rises. The ADC circuit of VR monitors the voltage variation at TSENx pin from 1.47V to 1.89V with 55mV resolution, and this voltage is decoded into digital format and stored into the Temperature Zone register.

V

CC

TSENx

R

1

R

NTC

R

2

R

3

T o meet Intel's V R12/IMVP7 specification, platform users have to set the TSEN voltage to meet the temperature variation of VR from 75% to 100% VR max temperature. For example, if the VR max temperature is 100°C, platform

users have to set the TSEN voltage to be 1.4875V when VR temperature reaches 75°C and 1.8725V when VR temperature reaches 100°C. Detailed voltage setting versus temperature variation is shown in Table 2. Thermometer code is implemented in the Temperature Zone register.

Table 2. Temperature Zone Register

Compar at or Tr ip Poin t s

VRHOT

SVID

Thermal

Alert

Temperatur es Scal ed to maximum = 100% Voltage Represents Assert bit Minimu m L evel

b7 b6 b5 b4 b3 b2 b1 b0

100% 97% 94% 91% 88% 85% 82% 75%

1.855V 1.8V

TSE N Pin V o lt age

1.855  V

1.800  V

1.745  V

1.690  V

1.635  V

1.580  V

1.525  V

1.470  V V

TSEN

 1.835 0 111_111 1

TSEN

 1.780 001 1_1111

TSEN

 1.725 0001_1111

TSEN

 1.670 0000_1111

TSEN

 1.615 0000_0111

TSEN

 1.560 0000_001 1

TSEN

 1.505 0000_000 1

TSEN

 1.470 0000_0000

1.745V 1.69V 1.635V 1.58V 1.52

Temperature_Zone

Register Content

1111_1111

5V

1.47 V

The RT8166B supports two temperature reporting, VRHOT (hardware reporting) and ALERT(software reporting), to fulfill VR12/IMVP7 specif ication. VRHOT is a n open-drain structure which sends out active-low VRHOT signals. When TSEN voltage rises above 1.855V (100% of VR temperature), the VRHOT signal will be set to low . When TSEN voltage drops below 1.8V (97% of VR temperature), the VRHOT signal will be reset to high. When TSEN voltage rises above 1.8V (97% of VR temperature), The RT8166B will update the bit1 data from 0 to 1 in the Status_1 register and assert ALERT. When TSEN voltage drops below

1.745V (94% of VR temperature), VR will update the bit1 data from 1 to 0 in the Status_1 register and a ssert ALER T .

Figure 1 1. Thermal Monitoring Circuit

34

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The temperature reporting function for the GFX VR can be

DS8166B-03 November 2013www.richtek.com

RT8166B

disabled by pulling TSENA pin to VCC in case the temperature reporting function for the GFX VR is not used or the GFX VR is disabled. When the GFX VR's temperature reporting function is disabled, the RT8166B will reject the SVID command of getting the

then temperature compensation is recommended for protection under all conditions. Figure 13 shows a typical OCP setting with temperature compensation.

R

OC1a

V

CC

NTC

Temperature_Zone register content of the GFX VR. However, note that the temperature reporting function f or the CORE VR is always a ctive. CORE VR's temperature reporting function can not be disabled by pulling TSEN

OCSETx

R

OC1b

OC2

pin to VCC.

Over Current Protection

The CORE/GFX VR compares a programmable current limit set point to the voltage from the current sense a mplifier output for Over Current Protection (OCP). The voltage applied to OCSETx pin def ines the desired peak current limit threshold I

V

= 48 x I

OCSET

LIMIT

:

x R

SENSE

(17)

Connect a resistive voltage divider from VCC to GND, with the joint of the resistive divider connected to OCSET pin a s shown in Figure 12. For a given R

V



RR 1

 

OC1 OC2

CC



V

OCSET



V

CC

OCSETx

, then

OC2

(18)

R

OC1

R

OC2

Figure 12. OCP Setting without Temperature

Figure 13. OCP Setting with Temperature Compensation

Usually , R nominal resistance at room temperature. Ideally, V

is selected to be equal to the thermistor's

OC1a

OCSET

is assumed to have the same temperature coefficient as R

According to the basic circuit calculation, V

(Inductor DCR) :

SENSE

VR

OCSET, HOT SENSE, HOT

VR

OCSET, COLD SENSE, COLD



OCSET

(19)

can be

obtained at any temperature :

R

VV

OCSET, T CC



R//R R R

OC1a NTC, T OC1b OC2

OC2



(20)

Re-write (19) from (20), to get V

R//R R R R

OC1a NTC, COLD OC1b OC2 SENSE, HOT

R//R R R R

OC1a NT C, HOT OC1b OC2 SENSE, COLD



at room temperature

OCSET



(21)

V

OCSET, 25

V

CC



R



R//R R R

OC1a NTC, 25 OC1b OC 2

OC2



(22)

Compensation

The current limit is triggered when inductor current exceeds the current limit threshold I V

. The driver will be forced to turn off UGATE until

OCSET

, defined by

LIMIT

the over current condition is cleared. If the over current condition remains valid for 15 PWM cycles, VR will trigger OCP latch. Latched OCP forces both UGA TE a nd LGA TE to go low. When OCP is triggered in one of VRs, the

Solving (21) and (22) yields R

R



OC2

RR (1)R

    

R

EQU, HOT EQU, COLD EQU, 25

V

CC

V

OCSET, 25



OC1b

(1)R2 R R

   

EQU, HOT EQU, COLD

(1 )



and R

OC1b

(1 )



OC2

(23)

(24)

other VR will enter into soft shutdown sequence. The OCP latch mechanism will be masked when VRx_READY = low, which mea ns that only the current li mit will be a ctive when V

is ramping up to initi al voltage (or V

OUT

REFx

).

If inductor DCR is used a s the current sense component,

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where



R

SENSE, HOT

R DCR [1 0.00393 (T 25)]

SENSE, COLD 25 COLD

DCR [1 0.00393 ( T 25)]



  

25 HOT

  

(25)

35

RT8166B

R

EQU, T

= R

OC1a

// R

(26)

NTC, T

where tON is the UGA TE turn on period.

Over Voltage Protection (OVP)

The over voltage protection circuit of CORE/GFX VR monitors the output voltage via the ISENxN pin. The supported maximum operating VID of VR (V in the V out_Max register. Once V

ISENxN

exceeds “V

(MAX)

) is stored

(MAX)

+ 200mV”, OVP is triggered and latched. VR will try to turn on low side MOSFETs and turn off high side MOSFETs to protect CPU. When OVP is triggered by the one of the VRs, the other VR will enter soft shutdown sequence. A 1μs delay is used in OVP detection circuit to prevent false trigger.

Negative Voltage Protection (NVP)

During OVP latch state, both CORE/GFX VRs also monitor ISENxN pin for negative voltage protection. Since the OVP latch will continuously turn on low side MOSFET of VR, VR may suffer negative output voltage. Therefore, when the voltage of ISENxN drops below −0.05V after triggering OVP, VR will turn off low side MOSFETs while high side MOSFET s remain off. The N VP function will be a ctive only after OVP is triggered.

Under Voltage Protection (UVP)

Both CORE/GFX VR implement U nder V oltage Protection (UVP). If ISENxN is less tha n V

by 300mV + V

REFx

OFFSET

VR will trigger UVP latch. The UVP latch will turn off both high side and low side MOSFET s. When UVP is triggered by one of the VRs, the other VR will enter into soft shutdown sequence. The UVP mechanism is masked when VRx_READY = low .

Under Voltage Lock Out (UVLO)

During normal operation, if the voltage at the VCC pin drops below UVLO falling edge threshold, both VR will trigger UVLO. The UVLO protection forces all high side MOSFETs and low side MOSFET s of f to turn off.

Inductor Selection

The switching frequency and ripple current determine the inductor value as f ollows :

VV



Lt

MIN ON

IN OUT



I

Ripple(MAX)

(27)

Higher inductance induces less ripple current a nd hence higher efficiency . However, the tra deoff is a slower transient response of the power stage to load tra nsients. This might increase the need f or more output ca pacitors, thus driving up the cost. Find a low-loss inductor having the lowest possible DC resista nce that fits in the allotted dimensions. The core must be large enough not to be saturated at the peak inductor current.

Output Capacitor Selection

Output capacitors are used to obtain high bandwidth for the output voltage beyond the bandwidth of the converter itself. Usually, the CPU manufacturer recommends a capacitor configuration. Two different kinds of output capacitors can be found, bulk capacitors closely located to the inductors and ceramic output capacitors in close proximity to the load. Latter ones are for mid-frequency decoupling with very small ESR and ESL values while the bulk ca pacitors have to provide enough stored energy to overcome the low-frequency bandwidth ga p between the regulator and the CPU.

Thermal Considerations

For continuous operation, do not exceed absolute maximum junction temperature. The maximum power

,

dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and a mbient temperature. The maximum power dissipation can be calculated by the following formula :

P where T

the ambient temperature, a nd θ

D(MAX)

= (T

J(MAX)

− TA) / θ

J(MAX)

JA

is the maximum junction temperature, T

is the junction to ambient

JA

thermal resistance. For recommended operating condition specifications of

the RT8166B, the maximum junction temperature is 125°C and TA is the ambient temperature. The junction to ambient thermal resistance, θJA, is layout dependent. For WQF N40L 5x5 packages, the thermal resistance, θJA, is 36°C/ W on a standard JEDEC 51-7 f our-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula :

is

A

36

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RT8166B

P

= (125°C − 25°C) / (36°C/W) = 2.778W for

D(MAX)

WQF N-40L 5x5 pa ckage The maximum power dissipation depends on the operating

ambient temperature for fixed T

and thermal

J(MAX)

resistance, θJA. For the RT8166B package, the derating curve in Figure 14 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.

3.20

2.80

2.40

2.00

1.60

1.20

0.80

0.40

Maximum Pow er Dissipat ion (W) 1

0.00 0255075100125

Ambient Tempera ture ( °C )

Four-Layer PCB

Figure 14. Derating Curves f or RT8166B Package

accura cy . The PCB tra ce from the sense nodes should be parallel to the controller.

 Route high-speed switching nodes away from sensitive

analog areas (COMPx, FBx, ISENxP, ISENxN, etc...)

 Special attention should be paid in placing the DCR

current sensing components. The DCR current sensing capacitor and resistors must be placed close to the controller.

 The ca pacitor connected to the ISEN1N/ISENAN for noise

decoupling is optional and it should also be pla ced close to the ISEN1N/ISENAN pin.

 The NTC thermistor should be pla ced physically close

to the inductor for better DCR thermal compensation.

Layout Consideration

Careful PC board layout is critical to achieving low switching losses and clean, stable operation. The switching power stage requires particular attention. If possible, mount all of the power components on the top side of the board with their ground terminals flushed against one another . Follow these guidelines for optimum PC board layout :

 Keep the high current paths short, especially at the

ground terminals.

 Keep the power tra ces and load connections short. This

is essential for high efficiency.

 When trade-offs in trace lengths must be made, it's

preferable to allow the inductor charging path to be made longer than the discharging path.

 Place the current sense component close to the

controller. ISENxP a nd ISENxN connections for current limit and voltage positioning must be made using Kelvin sense connections to guarantee the current sense

DS8166B-03 November 2013 www.richtek.com

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37

RT8166B

Outline Dimension

D

E

e

A

A3

A1

D2

SEE DETAIL A

1

b

L

E2

1 2

DETAIL A

Pin #1 ID a nd T ie Bar Mark Option s

Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated.

Dimensions In Millimeters Dim e nsions In Inches

Symbol

Min Max Min Max

A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010

b 0.150 0.250 0.006 0.010

D 4.950 5.050 0.195 0.199 D2 3.250 3.500 0.128 0.138

E 4.950 5.050 0.195 0.199 E2 3.250 3.500 0.128 0.138

e 0.400 0.016 L 0.350 0.450

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789

0.014 0.018

W-Type 40L QFN 5x5 Package

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

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Richtek RT8166BZQW Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual