To our customers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas
companies.
Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry
Electronics Corporation took over all the business of both
Renesas Electronics website: http://www.renesas.com
st
, 2010
April 1
Renesas Electronics Corporation
.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
additional and different inform ation to be disclosed by Renesas Electronics such as that disclosed through our website.
2. Renesas Electronics does not assume any liability for infringement of patents, copyrig hts, or other intellectual property rights
of third parties by or arising from the use of Renesa s Electronics products or technical information described in this document.
No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights
of Renesas Electronics or others.
3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, w hether in whole or in part.
4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsi bility for any losses incurred by
you or third parties arising from the use of these circuits, software, or information.
5. When exporting the products or technology described in this document, you should comply with the applicable export control
laws and regulations and follow the procedures required by such laws and regulations. You sho uld not use Renesas
Electronics products or the technolog y described in this document for any purpose relating to military applications or use by
the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and
technology may not be used for or incorporate d into any products or systems whose manufac ture, use, or sale is prohibited
under any applicable domestic or foreign laws or regulations.
6. Renesas Electronics has used reasonable ca re in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
7. Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and
“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as
indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular
application. You may not use any Renesa s Electronics product for any application categorized as “Specific” without the prior
written consent of Renesas Electronic s. Further, you may not use any Renesas Electronics product for any application for
which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way
liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an
application categorized as “Spec ific” or for which the product is not intended where you have failed t o obtain the prior written
consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise
expressly specified in a Renesas Electronics data sheets or data books, etc.
“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-
“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or
8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and othe r product characteristics. Renesas Elec tronics shall have no liability for malfunctions or
damages arising out of the use of Renesa s Electronics products beyond such specified ranges.
9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, se miconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measure s to
guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a
Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire
control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because
the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system
manufactured by you.
10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental
compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable
laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with
applicable laws and regulations.
11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas
Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this
document or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-
owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
equipment; home electronic applianc es; machine tools; personal electronic equipment; and industrial robots.
crime systems; safety equipment; and medical equipment not specifically designed for life support.
systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare
intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.
User’s Manual
SH-2A, SH-2 E200F Emulator
Additional Document for User’s Manual
Supplementary Information on Using the
SH7286, SH7285, and SH7243
Renesas Microcomputer Development
Environment System
SuperH™ Family / SH7280 Group
E200F for SH7280 Group R0E572800EMU00E
Rev.4.00 2009.02
Rev. 4.00 Feb. 18, 2009 Page ii of vi
REJ10J1662-0400
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for dama
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
ges arising out of the uses set forth above.
Rev. 4.00 Feb. 18, 2009 Page iii of vi
REJ10J1662-0400
Rev. 4.00 Feb. 18, 2009 Page iv of vi
REJ10J1662-0400
Contents
Section 1 System Configuration .........................................................................1
1.1 Components of the Emulator ............................................................................................ 1
1.2 System Configuration ....................................................................................................... 5
Section 2 Connecting the Emulator to the User System.....................................7
2.1 Connecting the Emulator to the User System ................................................................... 7
2.2 Connecting the Emulator to the User System by Using the EV-chip Unit........................ 7
2.2.1 Connecting the EV-chip Unit to the Emulator ....................................................... 7
2.2.2 Connecting the E200F External Bus Trace Unit to the EV-chip Unit.................... 10
2.2.3 Connecting the H-UDI/AUD Probe to the EV-chip Unit....................................... 12
2.2.4 Connecting the E200F Emulation Memory Unit to the EV-chip Unit................... 13
2.2.5 Connecting the E200F External Bus Trace Unit, Emulation Memory Unit,
and EV-chip Unit ................................................................................................... 15
2.2.6 Connecting the EV-chip Unit to the User System Interface Board ........................ 16
2.2.7 Using the E200F Emulator as a Stand-Alone Unit................................................. 17
2.3 Connecting the Emulator to the User System by Using the H-UDI Port Connector......... 18
2.4 Installing the H-UDI Port Connector on the User System................................................ 19
2.5 Pin Assignments of the H-UDI Port Connector................................................................ 19
2.6 Recommended Circuit between the H-UDI Port Connector and the MCU ...................... 21
2.6.1 Recommended Circuit (36-Pin Type) .................................................................... 21
2.7 Using the IC Socket to Mount an MCU on the User System............................................ 24
Section 3 Software Specifications when Using the SH7286, SH7285, and
SH7243 ................................................................................................27
3.1 Differences between the MCU and the Emulator ............................................................. 27
3.2 Specific Functions for the Emulator when Using the SH7286, SH7285, and SH7243..... 34
3.2.1 Event Condition Functions..................................................................................... 34
3.2.2 Trace Functions...................................................................................................... 41
3.2.3 Notes on Using the JTAG (H-UDI) Clock (TCK) and AUD Clock (AUDCK)..... 52
3.2.4 Notes on Setting the [Breakpoint] Dialog Box.......................................................52
3.2.5 Notes on Setting the [Event Condition] Dialog Box and
the BREAKCONDITION_ SET Command........................................................... 53
3.2.6 Performance Measurement Function...................................................................... 53
Section 4 User System Interface Circuits ............................................................59
4.1 User System Interface Circuits .........................................................................................59
Rev. 4.00 Feb. 18, 2009 Page v of vi
REJ10J1662-0400
4.2 Delay Time for the User System Interface........................................................................ 64
Rev. 4.00 Feb. 18, 2009 Page vi of vi
REJ10J1662-0400
Section 1 System Configuration
Section 1 System Configuration
1.1 Components of the Emulator
The E200F emulator supports the SH7285 group (SH7285), SH7286 group (SH7286), and
SH7243 group (SH7243). Table 1.1 lists the components of the emulator.
Table 1.1 Components of the Emulator
Classification Component
Hardware
AC adapter E200F serial numbers: 0001 to 0113
1 Input: 100 to 240 V
Emulator main unit
Appearance
Quantity Remarks
1 R0E0200F1EMU00:
Depth: 185.0 mm, Width: 130.0
mm,
Height: 45.0 mm, Mass: 321.0 g
Output: 12 V 4.0 A
Depth: 120.0 mm, Width: 72.0 mm,
Height: 27.0 mm, Mass: 400.0 g
E200F serial numbers: 0114 or later
1 Input: 100 to 240 V
Output: 12 V 3.0 A
Depth: 99.0 mm, Width: 62.0 mm,
Height: 26.0 mm, Mass: 270.0 g
AC cable 1 Length: 2000 mm
Rev. 4.00 Feb. 18, 2009 Page 1 of 64
REJ10J1662-0400
Section 1 System Configuration
Table 1.1 Components of the Emulator (cont)
Classification Component
Hard-
USB cable
Appearance
Quantity Remarks
1 Length: 1500 mm, Mass: 50.6 g
ware
(cont)
External probe E200F serial numbers: 0001 to 0113
1 Length: 500 mm,
Pins 1 to 4: probe input pins,
T: trigger output pin,
G: GND pin
E200F serial numbers: 0114 or later
1 Length: 500 mm,
Pins 1 to 4: probe input pins,
T: trigger output pin,
G: GND pin
Software
E200F emulator setup
program,
SH-2A, SH-2 E200F
Emulator User’s Manual,
and
Supplementary
Information on Using the
SH7286, SH7285, and
1 R0E0200F1EMU00S,
R0E0200F1EMU00J,
R0E0200F1EMU00E,
R0E572800EMU00J, and
R0E572800EMU00E
(provided on a CD-R)
SH7243*
Note: Additional document for the MCUs supported by the emulator is included. Check the target
MCU and refer to its additional document.
Rev. 4.00 Feb. 18, 2009 Page 2 of 64
REJ10J1662-0400
Table 1.2 Optional Components of the Emulator
Section 1 System Configuration
Classification Component
Hardware
Emulation memory unit
EV-chip unit 1 R0E572800VKK00:
Trace cable 1 R0E0200F0ACC00:
External bus trace unit
(Memory capacity:
8 Mbytes or 16 Mbytes)
Appearance
Quantity Remarks
1 R0E0200F1ETU00:
Depth: 90.0 mm, Width: 125.0 mm,
Height: 15.2 mm, Mass: 100 g
1 R0E0200F1MSR00 (8 Mbytes),
R0E0200F1MSR01 (16 Mbytes):
Depth: 90.0 mm, Width: 125.0 mm,
Height: 15.2 mm,
Mass: 81 g (R0E0200F1MSR00),
85 g (R0E0200F1MSR01)
Note that it is not possible to
connect these emulation memory
units at the same time.
Depth: 110.0 mm, Width: 125.0
mm, Height: 15.2 mm, Mass: 110 g
Length: 300 mm, Mass: 65 g
SH7243 (PLQP0100KB-
A) user system interface
board
SH7285 (PLQP0144KA-
A) user system interface
board
1 R0E572430CFK00:
Depth: 60.0 mm, Width: 90.0 mm,
Height: 26.0 mm, Mass: 45 g
1 R0E572850CFK00:
Depth: 60.0 mm, Width: 90.0 mm,
Height: 26.0 mm, Mass: 45 g
Rev. 4.00 Feb. 18, 2009 Page 3 of 64
REJ10J1662-0400
Section 1 System Configuration
Table 1.2 Optional Components of the Emulator (cont)
Classification Component
Hardware
(cont)
SH7286 (PLQP0176KBA) user system interface
board
SH7286 (PLQP0176LB-A)
user system interface
board
Appearance
Quan-
tity Remarks
1 R0E572860CFK00:
Depth: 60.0 mm, Width: 90.0 mm,
Height: 26.0 mm, Mass: 45 g
1 R0E572860CFL00:
Depth: 60.0 mm, Width: 90.0 mm,
Height: 26.0 mm, Mass: 45 g
Expansion profiling unit 1 R0E0200F0EPU00:
Depth: 98.0 mm, Width: 115.0 mm,
Height: 15.2 mm, Mass: 52 g
Rev. 4.00 Feb. 18, 2009 Page 4 of 64
REJ10J1662-0400
1.2 System Configuration
Figure 1.1 shows an example of the emulator system configuration.
- When the EV-chip unit is not used:
Expansion profiling unit
High-performance
Embedded Workshop
USB 2.0/1.1
E200F
Section 1 System Configuration
H-UDI port connector
IC socket
User system
H-UDI and AUD
External bus
trace unit
Emulation
memory unit
EV-chip unit
User system
interface board
User system
PC
- When the EV-chip unit is not used:
High-performance
Embedded Workshop
USB 2.0/1.1
PC
E200F
Expanded profilling unit
Trace cable
Figure 1.1 System Configuration Using the Emulator
(1) System Configuration of the SH7280 Series and the SH7243 Series
Table 1.3 shows the system configuration supported by the SH7280 series and the SH7243
series.
Rev. 4.00 Feb. 18, 2009 Page 5 of 64
REJ10J1662-0400
Section 1 System Configuration
Table 1.3 System Configuration Supported by the SH7280 Series and SH7243 Series
E200F Emulator EV-chip Unit
R0E0200F1EMU00
System configu-
ration 1
System configu-
ration 2
System configu-
ration 3
System configu-
ration 4
System configu-
ration 5
System configu-
ration 6
System configu-
ration 7
System configu-
ration 8
System configu-
ration 9
System configu-
ration 10
Supported Not supported Not supported Not supported Not supported Not supported Not supported
*1
Supported Supported Not supported Not supported Not supported Supported Supported*2
Supported Supported Not supported Supported Not supported Supported Supported*2
Supported Supported Supported Not supported Not suppor ted Supported Supported*2
Supported Supported Supported Supported Not supported Supported Supported*2
Supported Not supported Not supported Not supported Supported Not supported Not supported
*1
Supported Supported Not supported Not supported Supported Suppor ted Supported*2
Supported Supported Not supported Supported Supported Supported Supported*2
Supported Supported Supported Not supported S upported Supported Supported*2
Supported Supported Supported Supported S upported Supported Supported*2
R0E572800VKK00
External Bus
Trace Unit
R0E0200F1ETU00
Emulation Memory Unit Expansion Profiling
Unit
R0E0200F1MSR00
R0E0200F1MSR01
R0E0200F0EPU00
Trace Cable
R0E0200F0ACC00
User System Interface
Board
R0E572430CFK00
R0E572850CFK00
R0E572860CFK00
R0E572860CFL00
Notes: 1. When the EV-chip unit is not used, the H-UDI port connector must be installed on the
user system. When designing the user system, refer to section 2.3, Connecting the
Emulator to the User System by Using the H-UDI Port Connector. For this system
configuration, note that the H-UDI and AUD pins of the MCU are occupied by the
emulator.
2. The user system interface board is only used when the emulator is connected to the
user system; it is not required when the emulator system operates alone.
Rev. 4.00 Feb. 18, 2009 Page 6 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
Section 2 Connecting the Emulator to the User System
2.1 Connecting the Emulator to the User System
When the emulator is connected to the user system, use the optional EV-chip unit, user system
interface board, and trace cable.
2.2 Connecting the Emulator to the User System by Using the EV-chip
Unit
The following describes how to connect the emulator to the EV-chip unit, external bus trace unit,
emulation memory unit, trace cable, and user system interface board.
2.2.1 Connecting the EV-chip Unit to the Emulator
• Open the cover of TRACE I/F on the side of the main unit case.
• Connect the trace cable to the EV-chip unit as shown in figure 2.1.
Rev. 4.00 Feb. 18, 2009 Page 7 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
Figure 2.1 Connecting the Trace Cable to E200F when Using the EV-chip Unit
Rev. 4.00 Feb. 18, 2009 Page 8 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
• Connect the EV-chip unit to the trace cable (CN1 side).
Figure 2.2 Connecting the Trace Cable to the EV-chip Unit
CAUTION
Check the orientation of pin 1 before connecting parts.
Rev. 4.00 Feb. 18, 2009 Page 9 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
2.2.2 Connecting the E200F External Bus Trace Unit to the EV-chip Unit
• When the external bus trace unit is used with the EV-chip unit, connect the external bus trace
unit to the EV-chip unit as shown in figure 2.3.
Figure 2.3 Connecting the External Bus Trace Unit to the EV-chip Unit
Rev. 4.00 Feb. 18, 2009 Page 10 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
• After checking the location of pin 1, connect the EV-chip unit, external bus trace unit, and
trace cable.
Figure 2.4 Connecting the EV-chip Unit, External Bus Trace Unit, and Trace Cable
CAUTION
Check the orientation of pin 1 before connecting parts.
Rev. 4.00 Feb. 18, 2009 Page 11 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
2.2.3 Connecting the H-UDI/AUD Probe to the EV-chip Unit
• Connect the H-UDI/AUD probe to the EV-chip unit as shown in figure 2.5.
Figure 2.5 Connecting the H-UDI/AUD Probe to the EV-chip Unit
CAUTION
Check the orientation of pin 1 before connecting parts.
Rev. 4.00 Feb. 18, 2009 Page 12 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
2.2.4 Connecting the E200F Emulation Memory Unit to the EV-chip Unit
• When the emulation memory unit is used with the EV-chip unit, connect the emulation
memory unit to the EV-chip unit (figure 2.6).
Figure 2.6 Connecting the Emulation Memory Unit to the EV-chip Unit
Rev. 4.00 Feb. 18, 2009 Page 13 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
• After checking the location of pin 1, connect the EV-chip unit, emulation memory unit, and
trace cable.
Figure 2.7 Connecting the Emulation Memory Unit, EV-chip Unit, and Trace Cable
CAUTION
Check the orientation of pin 1 before connecting parts.
Rev. 4.00 Feb. 18, 2009 Page 14 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
2.2.5 Connecting the E200F External Bus Trace Unit, Emulation Memory Unit, and EV-
chip Unit
• When the external bus trace unit is used with the emulation memory unit and EV-chip unit, as
shown in figure 2.8, connect them in the positions of (a), (b), and (c) for the external bus trace
unit, emulation memory unit, and EV-chip unit, respectively.
• After checking the location of pin 1, connect the external bus trace unit, emulation memory
unit, and EV-chip unit.
Figure 2.8 Connecting the External Bus Trace Unit, Emulation Memory Unit, and EV-chip
Unit
CAUTION
Check the orientation of pin 1 and the position of each
unit before connecting parts.
Rev. 4.00 Feb. 18, 2009 Page 15 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
2.2.6 Connecting the EV-chip Unit to the User System Interface Board
• After checking the location of pin 1, connect the EV-chip unit to the user system interface
board.
EV-chip unit
Connector No.
EV-Chip Unit
Connector No.
User I/F Connector 1
(CN3)
User I/F Connector 2
(CN4)
Board
Spacer
Board
Connector No.
UCN1
UCN2
User system
Figure 2.9 Connecting the User System Interface Board to the EV-chip Unit
CAUTION
Check the orientation of pin 1 before connecting parts.
Notes: 1. Connection of the signals differs depending on the MCU used.
2. For the method to connect the user system interface board to the user system, refer to
the user system interface board user’s manual for each MCU.
Rev. 4.00 Feb. 18, 2009 Page 16 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
2.2.7 Using the E200F Emulator as a Stand-Alone Unit
• If you are using the E200F emulator unit without connecting it to a user system, refer to table
1.3 in section 1.2, System Configuration, and make connections as shown in figure 2.10 until
the EV-chip unit becomes available.
EV-chip unit
When using the emulator as a
stand-alone unit
When connecting the emulator to
the user system
User system
interface board
User system
Figure 2.10 Connecting the E200F Emulator as a Stand-Alone Unit
Rev. 4.00 Feb. 18, 2009 Page 17 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
2.3 Connecting the Emulator to the User System by Using the H-UDI
Port Connector
To connect the E200F emulator (hereinafter referred to as the emulator), the H-UDI port connector
must be installed on the user system to connect the user system interface cable. When designing
the user system, refer to the recommended circuit between the H-UDI port connector and the
MCU.
It is impossible to connect the emulator to the 14-pin type connector that is recommended for the
E10A-USB emulator. The 36-pin type connector is the same as that of the E10A-USB emulator.
When designing the user system, read the E200F emulator user's manual and hardware manual for
the related device.
Table 2.1 shows the type number of the emulator, the corresponding connector type, and the use of
AUD function.
Table 2.1 Type Number, AUD Function, and Connector Type
Type Number Connector AUD Function
R0E200F1EMU00 14-pin connector Not available
R0E200F1EMU00 36-pin connector Available
The H-UDI port connector has the 36-pin and 14-pin types as described below. Use the 36-pin
connector when using the emulator.
1. 36-pin type (with AUD function)
The AUD trace function is supported. A large amount of trace information can be acquired in
realtime. The window trace function is also supported for acquiring memory access in the
specified range (memory access address or memory access data) by tracing.
2. 14-pin type (without AUD function)
The AUD trace function cannot be used because only the H-UDI function is supported. This
connector type is not available for the emulator. Use the E10A-USB emulator.
Rev. 4.00 Feb. 18, 2009 Page 18 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
2.4 Installing the H-UDI Port Connector on the User System
Table 2.2 shows the recommended H-UDI port connectors for the emulator.
Table 2.2 Recommended H-UDI Port Connectors
Connector Type Number Manufacturer Specifications
36-pin connector
DX10M-36S Screw type
DX10M-36SE,
DX10G1M-36SE
Hirose Electric Co., Ltd.
Lock-pin type
Note: When designing the 36-pin connector layout on the user board, do not connect any
components under the H-UDI connector.
2.5 Pin Assignments of the H-UDI Port Connector
Figure 2.11 shows the pin assignments of the 36-pin H-UDI port connectors.
Note: Note that the pin number assignments of the H-UDI port connector shown on the
following page differ from those of the connector manufacturer.
Rev. 4.00 Feb. 18, 2009 Page 19 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
Pin
Signal
No.
AUDCK
1
2
GND
3
AU D ATA0
4
GND
5
AU D ATA1
6
GND
AU D ATA2
7
8
GND
AU D ATA3
9
10
GND
_AUDSYNC
11
12
GND
13
N.C.
14
GND
15
N.C.
16
GND
17
TCK
18
GND
Notes:
1. Input to or output from the user system.
Input/
*1
Output
Output
Output
Output
Output
Output
*2
Output Output
Input
Note
Pin
No.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Signal
TMS
GND
*2
_TRST
*4
(GND)
TDI
GND
TDO
GND
_ASEBRKAK
/_ASEBRK
GND
UVCC
GND
*2
_RES
GND
*3
GND
GND
N.C.
GND
Input/
*1
Output
Note
Input
Input
Input
Output
Input/
*2
output
Output
User reset
Output
2. The symbol (_) means that the signal is active-low.
3. The emulator monitors the GND signal of the user system and detects whether or not the user system is connected.
4.
When the H-UDI/AUD probe is connected to this pin and the ASEMD0# pin is set to 0, do not connect to GND but to
the ASEMD0# pin directly.
Edge of the board
(connected to the connector)
4
+0.1
2
φ
2.8
0
+0.1
36
φ
0.7
0
4.5
H-UDI port connector
(top view)
1.1
9.0
1.905
35
H-UDI port connector (front view)
4.09
3
1
: Pattern inhibited area
H-UDI port connector (top view)
21.59
37.61
43.51
1.27
Figure 2.11 Pin Assignments of the H-UDI Port Connector (36 Pins)
Rev. 4.00 Feb. 18, 2009 Page 20 of 64
REJ10J1662-0400
(Pin 1 mark)
M2.6 x 0.45
3.9
Unit: mm
9.0
0.3
4.8
Section 2 Connecting the Emulator to the User System
2.6 Recommended Circuit between the H-UDI Port Connector and the
MCU
2.6.1 Recommended Circuit (36-Pin Type)
Figures 2.12 and 2.13 show recommended circuits for connection between the H-UDI and AUD
port connectors (36 pins) and the MCU when the emulator is in use.
Notes: 1. Do not connect anything to the N.C. pins of the H-UDI port connector.
2. The ASEMD0# pin must be 0 when the emulator is connected and 1 when the emulator
is not connected, respectively.
(1) When the emulator is used: ASEMD0# = 0
(2) When the emulator is not used: ASEMD0# = 1
Figures 2.12 and 2.13 show examples of circuits that allow the ASEMD0# pin to be
GND (0) whenever the emulator is connected by using the H-UDI/AUD probe. When
the ASEMD0# pin is changed by switches, etc., ground pin 22. Do not connect this pin
to the ASEMD0# pin.
3. When a network resistance is used for pull-up, it may be affected by a noise. Separate
TCK from other resistances.
4. The pattern between the H-UDI port connector and the MCU must be as short as
possible. Do not connect the signal lines to other components on the board.
5. The AUD signals (AUDCK, AUDATA3 to AUDATA0, and _AUDSYNC) operate in
high speed. Isometric connection is needed if possible. Do not separate connection nor
connect other signal lines adjacently.
6. Supply the operating voltages of the H-UDI and AUD of the MCU to the UVCC pin.
7. The resistance values shown in figures 2.12 and 2.13 are for reference.
8. For the AUDCK pin, guard the pattern between the H-UDI port connector and the
MCU at GND level.
9. For the pin processing in cases where the emulator is not used, refer to the hardware
manual of the related MCU.
Rev. 4.00 Feb. 18, 2009 Page 21 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
All pulled-up at 4.7 kΩ or more
VCC
VCC
VCC
H-UDI port connector
(36-pin type)
2
GND
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
GND
GND
GND
GND
GND
GND
GND
GND
GND
(GND)
GND
GND
GND
GND
GND
GND
GND
AUDATA0
AUDATA1
AUDATA2
AUDATA3
AUDSYNC
ASEBRKAK
/ASEBRK
AUDCK
N.C.
N.C.
TCK
TMS
TRST
TDI
TDO
UVCC
RES
GND
N.C.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
1 kΩ
VCC = I/O power supply
VCC
SH7286
AUDCK
AUDATA0
AUDATA1
AUDATA2
AUDATA3
AUDSYNC
TCK
TMS
TRST
TDI
TDO
ASEBRKAK
/ASEBRK *
RES
ASEMD0
Reset signal
User system
Note:
The ASEBRKAK#/ASEBRK# pin (I/O pin) is multiplexed with the FWE pin (input pin). For the pin processing when the
emulator is used and the user system is independently in operation, pins must be pulled up at 4.7 kΩ or more or pulled
down at 100 kΩ. For the pin processing when the emulator is not used, refer to the hardware manual of the related MCU.
Figure 2.12 Recommended Circuit for Connection between the H-UDI Port Connector and
MCU when the Emulator is in Use (36-Pin Type) (1)
Rev. 4.00 Feb. 18, 2009 Page 22 of 64
REJ10J1662-0400
H-UDI port connector
(36-pin type)
2
GND
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
GND
GND
GND
GND
GND
GND
GND
GND
GND
(GND)
GND
GND
GND
GND
GND
GND
GND
AUDATA0
AUDATA1
AUDATA2
AUDATA3
AUDSYNC
ASEBRKAK
/ASEBRK
AUDCK
N.C.
N.C.
TCK
TMS
TRST
TDI
TDO
UVCC
RES
GND
N.C.
Section 2 Connecting the Emulator to the User System
VCC = I/O power supply
All pulled-up at 4.7 kΩ or more
VCC
VCC
VCC
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
VCC
SH7285 or SH7243
AUDCK
AUDATA0
AUDATA1
AUDATA2
AUDATA3
AUDSYNC
TCK
TMS
TRST
TDI
TDO
ASEBRKAK
/ASEBRK
RES
ASEMD0
Reset signal
User system
Note:
The ASEBRKAK#/ASEBRK# pin (I/O pin) is multiplexed with the FWE pin (input pin). For the pin processing when the
emulator is used and the user system is independently in operation, pins must be pulled up at 4.7 kΩ or more or pulled
down at 100 kΩ. For the pin processing when the emulator is not used, refer to the hardware manual of the related MCU.
Figure 2.13 Recommended Circuit for Connection between the H-UDI Port Connector and
MCU when the Emulator is in Use (36-Pin Type) (2)
Rev. 4.00 Feb. 18, 2009 Page 23 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
2.7 Using the IC Socket to Mount an MCU on the User System
Figure 2.14 shows an example of the external appearance of the configuration when the IC socket
is used to mount an MCU on the user system using and the E200F emulator is connected in onchip debugging mode.
(1) External appearance of the configuration of the on-chip connection when the IC socket is used
for the SH7286, SH7285, or SH7243
Screws
Top cover for IC socket
MCU
User system
H-UDI/AUD probe
Figure 2.14 External Appearance of the Configuration of the On-Chip Connection when
the IC Socket is Used for the SH7286, SH7285, or SH7243
Rev. 4.00 Feb. 18, 2009 Page 24 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
CAUTION
1. Check the orientation of pin 1 before connecting parts.
2. As the IC socket and IC top cover for mounting on the
user system, we recommend the following products.
⎯ IC socket for SH7286
(package: PLQP0176KB-A, former package: FP-176EV)
IC socket: NQPACK176SD-ND socket
(manufactured by Tokyo Eletech Corporation)
Top cover for IC socket: HQPACK176SD cover
(manufactured by Tokyo Eletech Corporation)
⎯ IC socket for SH7286
(package: PLQP0176LB-A, former package: FP-176AV)
IC socket: NQPACK176SE socket
(manufactured by Tokyo Eletech Corporation)
Top cover for IC socket: HQPACK176SE cover
(manufactured by Tokyo Eletech Corporation)
⎯ IC socket for SH7285
(package: PLQP0144KA-A, former package: FP-144LV)
IC socket: NQPACK144SD-ND socket
(manufactured by Tokyo Eletech Corporation)
Top cover for IC socket: HQPACK144SD cover
(manufactured by Tokyo Eletech Corporation)
⎯ IC socket for SH7243
(package: PLQP0100KB-A, former package: FP-100UV)
IC socket: NQPACK100SD-ND socket
(manufactured by Tokyo Eletech Corporation)
Top cover for IC socket: HQPACK100SD cover
(manufactured by Tokyo Eletech Corporation)
Rev. 4.00 Feb. 18, 2009 Page 25 of 64
REJ10J1662-0400
Section 2 Connecting the Emulator to the User System
Rev. 4.00 Feb. 18, 2009 Page 26 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
Section 3 Software Specifications when Using the SH7286,
SH7285, and SH7243
3.1 Differences between the MCU and the Emulator
1. When the emulator system is initiated, it initializes the general registers and part of the control
registers as shown in table 3.1. The initial values of the MCU are undefined. When the
emulator is initiated from the workspace, a value to be entered is saved in a session.
Table 3.1 Register Initial Values at Emulator Link Up
Register Emulator at Link Up
R0 to R14 H'00000000
R15 (SP) Value of the SP in the power-on reset vector table
PC Value of the PC in the power-on reset vector table
SR H'000000F0
GBR H'00000000
VBR H'00000000
TBR H'00000000
MACH H'00000000
MACL H'00000000
PR H'00000000
Note: When a value of the interrupt mask bit in the SR register is changed in the [Registers]
window, it is actually reflected in that register immediately before execution of the user
program is started. It also applies when the value is changed by the REGISTER_SET
command.
2. The emulator uses the H-UDI; do not access the H-UDI.
3. Low-Power States (Sleep, Software Standby, and Module Standby)
⎯ When the emulator is used, the sleep state can be cleared with either the clearing function
or with the [STOP] button, and a break will occur.
⎯ The memory must not be accessed or modified in software standby state.
⎯ Do not stop inputting the clock to the H-UDI module by using the module standby
function.
Rev. 4.00 Feb. 18, 2009 Page 27 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
4. Reset Signals
The MCU reset signals are only valid during emulation started with clicking the GO or STEPtype button. If these signals are enabled on the user system in command input wait state, they
are not sent to the MCU.
Note: Do not break the user program when the _RES, _BREQ, or _WAIT signal is being low. A
TIMEOUT error will occur. If the _BREQ or _WAIT signal is fixed to low during break,
a TIMEOUT error will occur at memory access.
5. Direct Memory Access Controller (DMAC)
The DMAC operates even when the emulator is used. When a data transfer request is
generated, the DMAC executes DMA transfer.
6. Memory Access during User Program Execution
During execution of the user program, memory is accessed by the following two methods, as
shown in table 3.2.
Table 3.2 Memory Access during User Program Execution
Method Description
H-UDI read/write The stopping time of the user program is short because memory is
accessed by the dedicated bus master.
Short break This function is not available in this emulator. (Do not set)
The method for accessing memory during execution of the user program is specified by using
the [Configuration] dialog box.
Table 3.3 Stopping Time by Memory Access (Reference)
Method Condition Stopping Time
H-UDI read/write Reading of one longword for the
internal RAM
Writing of one longword for the
internal RAM
Rev. 4.00 Feb. 18, 2009 Page 28 of 64
REJ10J1662-0400
Reading: Maximum three bus clock
cycles (Bφ)
Writing: Maximum two bus clock
cycles (Bφ)
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
7. Memory Access to the External Flash Memory Area
The emulator can download the load module to the external flash memory area (for details,
refer to section 6.21, Download Function to the Flash Memory Area, in the SH-2A, SH-2
E200F Emulator User’s Manual). Neither memory write nor BREAKPOINT setting is enabled
for the external flash memory area. To set the break condition for the program on the external
flash memory, use the Event Condition function. Some MCUs will incorporate no external
flash memory area.
8. ROM Cache
For ROM cache in the MCU, the emulator operates as shown in table 3.4.
Table 3.4 Operation for ROM Cache
Function Operation
Write and erase Writes or erases all contents of ROM cache.
Memory read Accesses the disabled cache area to read the content of internal flash
memory.
9. Multiplexing the AUD Pins in On-Chip Debugging Mode
The AUD pins are multiplexed as shown in table 3.5.
Rev. 4.00 Feb. 18, 2009 Page 29 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
Table 3.5 Multiplexed Functions
MCU Function 1 Function 2
SH7286 FWE _ASEBRKAK/_ASEBRK
PD16/D16/IRQ0/_CS3 AUDATA0
PD17/D17/IRQ1/_POE5/SCK3/_CS2/WRxD AUDATA1
PD18/D18/IRQ2/_POE6/TXD3/_CS1/WTxD AUDATA2
PD19/D19/IRQ3/_POE7/RXD3/_CS0/WSCK AUDATA3
PD24/D24/DREQ0/TIOC4DS AUDCK
PD22/D22/IRQ6/TIC5US/RXD4 _AUDSYNC
SH7285 PA3/RXD1/SSI/_CS3 TMS
PA4/TXD1/SSO/_CS4 _TRST
PA0/RXD0/_CS0 TDI
PA1/TXD0/_CS1 TDO
PA2/SCK0/_SCS/_CS2 TCK
FWE _ASEBRKAK/_ASEBRK
PD16/IRQ0/_CS3 AUDATA0
PD17/IRQ1/_POE5/SCK3/_CS2/WRxD AUDATA1
PD18/IRQ2/_POE6/TXD3/_CS1/WTxD AUDATA2
PD19/IRQ3/_POE7/RXD3/_CS0/WSCK AUDATA3
PD24/DREQ0/TIOC4DS AUDCK
PD22/IRQ6/TIC5US/RXD4 _AUDSYNC
SH7243 PC3/A3 TMS
PC4/A4 _TRST
PC0/A0/_POE0 TDI
PC1/A1 TDO
PC2/A2 TCK
FWE _ASEBRKAK/_ASEBRK
PD4/D4/TIC5W AUDATA0
PD5/D5/TIC5US AUDATA1
PD6/D6/TIC5VS AUDATA2
PD7/D7/TIC5WS AUDATA3
PD8/D8/TIOC3AS AUDCK
PD3/D3/TIC5V _AUDSYNC
Rev. 4.00 Feb. 18, 2009 Page 30 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
Note: Function 1 can be used when the AUD pins of the device are not connected to the
emulator.
The AUD pins are multiplexed with other pins. When the AUD function is used by the
SH7286, SH7285, and SH7243 E200F emulator, AUD pins are used regardless of the settings
of the pin function controller (PFC).
Note that the AUD function can be used regardless of the above AUD pin settings in EV-chip unit
debugging mode.
10. Using the Watchdog Timer (WDT)
The WDT does not operate during a break.
11. Loading Sessions
Information in [JTAG clock] of the [Configuration] dialog box cannot be recovered by loading
sessions. Thus the TCK value will be 5 MHz.
12. [IO] Window
⎯ Display and modification
For each watchdog timer register, there are two registers to be separately used for write and
read operations.
Table 3.6 Watchdog Timer Register
Register Name Usage Register
WTCSR(W) Write Watchdog timer control/status register
WTCNT(W) Write Watchdog timer counter
WTCSR(R) Read Watchdog timer control/status register
WTCNT(R) Read Watchdog timer counter
WRCSR(W) Write Watchdog reset control/status register
WRCSR(R) Read Watchdog reset control/status register
Rev. 4.00 Feb. 18, 2009 Page 31 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
⎯ Customization of the I/O-register definition file
The internal I/O registers can be accessed from the [IO] window. However, note the following
when accessing the SDMR register of the bus state controller. Before accessing the SDMR
register, specify addresses to be accessed in the I/O-register definition file (SH7285.IO or
SH7243.IO) and then activate the High-performance Embedded Workshop. After the I/Oregister definition file is created, the MCU’s specifications may be changed. If each I/O
register in the I/O-register definition file differs from addresses described in the hardware
manual, change the I/O-register definition file according to the description in the hardware
manual. The I/O-register definition file can be customized in accordance to its format.
However, the emulator does not support the bit-field function.
⎯ Verification
In the [IO] window, the input values cannot be verified.
13. Illegal Instructions
Do not execute illegal instructions with STEP-type commands.
14. Reset Input
During execution of the user program, the emulator may not operate correctly if a contention
occurs between the following operations for the emulator and the reset input to the target
device:
⎯ Setting an Event Condition
⎯ Setting an internal trace
⎯ Displaying the content acquired by an internal trace
⎯ Reading or writing of a memory
Note that those operations should not contend with the reset input to the target device.
15. Contention between the Change of the FRQCR Register and the Debugging Functions
The following notes are required for the user program for changing the multiplication rate of
PLL circuit 1 to change the frequency:
⎯ Avoid contention between the change of the FRQCR register in the user program and the
memory access from the [Memory] window, etc.
⎯ When the automatic updating function is used in the [Monitor] window or [Watch]
window, generate and set a break of Event Condition for an instruction immediately before
changing the FRQCR register. Contention will be avoided by generating a break and
executing the user program again.
For the change of the multiplication rate of PLL circuit 1 and the FRQCR register, refer to the
hardware manual for the MCU.
Rev. 4.00 Feb. 18, 2009 Page 32 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
16. MCU operation mode
Boot or the User boot mode is not supported in this emulator.
Rev. 4.00 Feb. 18, 2009 Page 33 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
3.2 Specific Functions for the Emulator when Using the SH7286,
SH7285, and SH7243
In on-chip debugging mode, a reset must be input when the emulator is activated.
3.2.1 Event Condition Functions
The emulator is used to set event conditions for the following three functions:
• Break of the user program
• Internal trace
• Start or end of performance measurement
Table 3.7 lists the types of Event Condition.
Table 3.7 Types of Event Condition
Event Condition Type Description
Address bus condition (Address) Sets a condition when the address bus (data access) value
or the program counter value (before or after execution of
instructions) is matched.
Data bus condition (Data) Sets a condition when the data bus value is matched. Byte,
word, or longword can be specified as the access data size.
Bus state condition
(Bus State)
Count Sets a condition when the other specified conditions are
Reset point A reset point is set when the count and the sequential
Action Selects the operation when a condition (such as a break, a
Use the [Combination action(Sequential or PtoP)] dialog box to specify the sequential condition,
the point-to-point operation of the internal trace, and the start or end of performance measurement.
There are two bus state condition settings:
Bus state condition: Sets a condition when the data bus
value is matched.
Read/write condition: Sets a condition when the read/write
condition is matched.
satisfied for the specified counts.
condition are specified.
trace halt condition, a trace acquisition condition, or a trigger
output) is matched.
Rev. 4.00 Feb. 18, 2009 Page 34 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
Table 3.8 lists the combinations of conditions that can be set under Ch1 to Ch11 and the software
trace.
Table 3.8 Dialog Boxes for Setting Event Conditions
Function
Dialog Box
[Event
Condition 1]
[Event
Condition 2]
[Event
Condition 3]
[Event
Condition 4]
[Event
Condition 5]
[Event
Condition 6]
[Event
Condition 7]
[Event
Condition 8]
[Event
Condition 9]
[Event
Condition 10]
[Event
Condition 11]
Notes: 1. O: Can be set in the dialog box.
X: Cannot be set in the dialog box.
2. For the Action item,
B: Setting a break is enabled.
T1: Setting the trace halt and acquisition conditions are enabled for the internal trace.
T2: Setting the trace halt is enabled for the internal trace.
T3: Setting the trace halt and point-to-point is enabled for the internal trace.
P: Setting a performance-measurement start or end condition is enabled.
Address Bus
Condition
(Address)
Ch1 O O O O O
Ch2 O O O X O
Ch3 O X X X O
Ch4 O X X X O
Ch5 O X X X O
Ch6 O X X X O
Ch7 O X X X O
Ch8 O X X X O
Ch9 O X X X O
Ch10 O X X X O
Ch11 O
(reset point)
Data Bus
Condition
(Data)
X X X X
Bus State
Condition (Bus
Status)
Count
Condition
(Count)
Action
(B, T1, and P)
(B, T1, and P)
(B and T2)
(B and T3)
(B and T3)
(B and T2)
(B and T2)
(B and T2)
(B and T2)
(B and T2)
Rev. 4.00 Feb. 18, 2009 Page 35 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
The [Event Condition 11] dialog box is used to specify the count of [Event Condition 1] and
becomes a reset point when the sequential condition is specified.
Sequential Setting: Use the [Combination action(Sequential or PtoP)] dialog box to specify the
sequential condition and the start or end of performance measurement.
Table 3.9 Conditions to Be Set
Classification Item Description
[Ch1, 2, 3] list box Sets the sequential condition and the start or end of performance
measurement using Event Conditions 1 to 3 and 11.
Don’t care Sets no sequential condition or the start or end of
performance measurement.
Break: Ch3-2-1 Breaks when a condition is satisfied in the order of
Event Condition 3, 2, 1.
Break: Ch3-2-1,
Reset point
Break: Ch2-1 Breaks when a condition is satisfied in the order of
Break: Ch2-1,
Reset point
I-Trace stop: Ch3-2-1 Halts acquisition of an internal trace when a
I-Trace stop: Ch3-2-1,
Reset point
I-Trace stop: Ch2-1 Halts acquisition of an internal trace when a
I-Trace stop: Ch2-1,
Reset point
Breaks when a condition is satisfied in the order of
Event Condition 3, 2, 1.
Enables the reset point of Event Condition 11.
Event Condition 2, 1.
Breaks when a condition is satisfied in the order of
Event Condition 2, 1.
Enables the reset point.
condition is satisfied in the order of Event Condition
3, 2, 1.
Halts acquisition of an internal trace when a
condition is satisfied in the order of Event Condition
3, 2, 1.
Enables the reset point.
condition is satisfied in the order of Event Condition
2, 1.
Halts acquisition of an internal trace when a
condition is satisfied in the order of Event Condition
2, 1.
Enables the reset point.
Rev. 4.00 Feb. 18, 2009 Page 36 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
Table 3.9 Conditions to Be Set (cont)
Classification Item Description
[Ch1, 2, 3] list box
(cont)
Ch1 to Ch2 PA Sets the performance measurement period during
[Ch4, 5] list box Sets the point-to-point of the internal trace (the start or end condition of
Don’t care Sets no start or end condition of trace acquisition.
I-Trace: Ch5 to Ch4
I-Trace: Ch5 to Ch4
Notes: 1. After the sequential condition and the count specification condition of Event Condition 1
have been set, break and trace acquisition will be halted if the sequential condition is
satisfied for the specified count.
2. If a reset point is satisfied, the satisfaction of the condition set in Event Condition will be
disabled. For example, if the condition is satisfied in the order of Event Condition 3, 2,
reset point, 1, the break or trace acquisition will not be halted. If the condition is
satisfied in the order of Event Condition 3, 2, reset point, 3, 2, 1, the break and trace
acquisition will be halted.
3. If the start condition is satisfied after the end condition of the performance
measurement has been satisfied, performance measurement will be restarted. For the
measurement result after a break, the measurement results during performance
measurement are added.
4. If the start condition is satisfied after the end condition has been satisfied by the point-
to-point of the internal trace, trace acquisition will be restarted.
Ch2 to Ch1 PA Sets the performance measurement period during
the time from the satisfaction of the condition set in
Event Condition 2 (start condition) to the
satisfaction of the condition set in Event Condition
1 (end condition).
the time from the satisfaction of the condition set in
Event Condition 1 (start condition) to the
satisfaction of the condition set in Event Condition
2 (end condition).
trace acquisition) using Event Conditions 4 and 5.
Sets the acquisition period during the time from the
PtoP
PtoP, Power-on reset
satisfaction of the condition set in Event Condition
5 (start condition) to the satisfaction of the
condition set in Event Condition 4 (end condition).
Sets the acquisition period during the time from the
satisfaction of the condition set in Event Condition
5 (start condition) to the satisfaction of the
condition set in Event Condition 4 (end condition)
or the power-on reset.
Rev. 4.00 Feb. 18, 2009 Page 37 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
Usage Example of Sequential Break Extension Setting: A tutorial program provided for the
product is used as an example. For the tutorial program, refer to section 6, Tutorial, in the SH-2A,
SH-2 E200F Emulator User’s Manual.
The conditions of Event Condition are set as follows:
1. Ch1
Breaks address H’00001086 when the condition [Prefetch address break after executing] is
satisfied.
2. Ch2
Breaks address H’00001068 when the condition [Prefetch address break after executing] is
satisfied.
3. Ch3
Breaks address H’00001058 when the condition [Prefetch address break after executing] is
satisfied.
Note: Do not set other channels.
4. Sets the contents of the [Ch1,2,3] list box to [Break: Ch 3-2-1] in the [Combination action]
dialog box.
Then, set the program counter and stack pointer (PC = H’00000800, R15 = H’FFF9F000) in the
[Registers] window and click the [Go] button. If this does not execute normally, issue a reset and
execute the above procedures.
The program is executed up to the condition of Ch1 and halted. Here, the condition is satisfied in
the order of Ch3 -> 2 -> 1.
Rev. 4.00 Feb. 18, 2009 Page 38 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
Figure 3.1 [Source] Window at Execution Halt (Sequential Break)
If the sequential condition, performance measurement start/end, or point-to-point for the internal
trace is set, conditions of Event Condition to be used will be disabled. Such conditions must be
enabled from the popup menu by clicking the right mouse button on the [Event Condition] sheet.
Notes: 1. If the Event condition is set for the slot in the delayed branch instruction by the
program counter (after execution of the instruction), the condition is satisfied before
executing the instruction in the branch destination (when a break has been set, it occurs
before executing the instruction in the branch destination).
2. Do not set the Event condition for the SLEEP instruction by the program counter (after
execution of the instruction).
3. When the Event condition is set for the 32-bit instruction by the program counter, set
that condition in the upper 16 bits of the instruction.
4. If the power-on reset and the Event condition are matched simultaneously, no condition
will be satisfied.
5. Do not set the Event condition for the DIVU or DIVS instruction by the program
counter (after execution of the instruction).
Rev. 4.00 Feb. 18, 2009 Page 39 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
6. If a condition of which intervals are satisfied closely is set, no sequential condition will
be satisfied.
• Set the Event conditions, which are satisfied closely, by the program counter with
intervals of two or more instructions.
• After the Event condition has been matched by accessing data, set the event
condition by the program counter with intervals of 17 or more instructions.
7. If the settings of the Event condition or the sequential conditions are changed during
execution of the program, execution will be suspended. (The number of clock cycles to
be suspended during execution of the program is a maximum of about 102 bus clock
cycles (Bφ). If the bus clock (Bφ) is 20 MHz, the program will be suspended for 5.1
μs.)
8. If the settings of Event conditions or the sequential conditions are changed during
execution of the program, the emulator temporarily disables all Event conditions to
change the settings. During this period, no Event conditions will be satisfied.
9. If the break condition before executing an instruction is set to the instruction followed
by DIVU and DIVS, the factor for halting a break will be incorrect under the following
condition:
If a break occurs during execution of the above DIVU and DIVS instructions, the break
condition before executing an instruction, which has been set to the next instruction,
may be displayed as the factor for halting a break.
10. If the break conditions before and after executing instructions are set to the same
address, the factor for halting a break will be incorrectly displayed. The factor for
halting a break due to the break condition after executing an instruction will be
displayed even if a break is halted by the break condition before executing an
instruction.
11. Do not set the break condition after executing instructions and BREAKPOINT
(software break) to the same address.
12. When the emulator is being connected, the user break controller (UBC) function is not
available.
Rev. 4.00 Feb. 18, 2009 Page 40 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
3.2.2 Trace Functions
The emulator supports the trace functions listed in table 3.10.
Table 3.10 Trace Functions
Function Internal Trace AUD Trace
Branch trace Supported Supported
Memory access trace Supported Supported
Software trace Not supported Supported
The internal and AUD traces are set in the [I-Trace/AUD-Trace acquisition] dialog box of the
[Trace] window.
Rev. 4.00 Feb. 18, 2009 Page 41 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
Internal Trace Function: When [I-Trace] is selected for [Trace type] on the [Trace mode] page
of the [I-Trace/AUD-Trace acquisition] dialog box, the internal trace can be used.
Figure 3.2 [I-Trace/AUD-Trace acquisition] Dialog Box (Internal Trace Function)
Rev. 4.00 Feb. 18, 2009 Page 42 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
The following three items can be selected as the internal trace from [Type] of [I-Trace mode].
Table 3.11 Information on Acquiring the Internal Trace
Item Acquisition Information
[M-Bus & Branch] Acquires the data and branch information on the M-bus.
• Data access (read/write)
• PC-relative access
• Branch information
[I-Bus] Acquires the data on the I-bus.
• Data access (read/write)
• Selection of the bus master on the I-bus (CPU/DMA/A-DMA)
• Instruction fetch
[I-Bus, M-Bus & Branch] Acquires the contents of [M-Bus & Branch] and [I-Bus].
After selecting [Type] of [I-Trace mode], select the contents to be acquired from [Acquisition].
Typical examples are described below (note that items disabled for [Acquisition] are not
acquired).
• Example of acquiring branch information only:
Select [M-Bus & Branch] from [Type] and enable [Branch] on [Acquisition].
• Example of acquiring the read or write access (M-bus) only by the user program:
Select [M-Bus & Branch] from [Type] and enable [Read], [Write], and [Data access] on
[Acquisition].
• Example of acquiring the read access only by DMAC (I-bus):
Select [I-Bus] from [Type] and enable [Read], [DMA], and [Data access] on [Acquisition].
Rev. 4.00 Feb. 18, 2009 Page 43 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
Using the Event Condition restricts the condition; the following three items are set as the internal
trace conditions.
Table 3.12 Trace Conditions of the Internal Trace
Item Acquisition Information
Trace halt Acquires the internal trace until the Event Condition is satisfied. (The
trace content is displayed in the [Trace] window after a trace has been
halted. No break occurs in the user program.)
Trace acquisition Acquires only the data access where the Event Condition is satisfied.
Point-to-point Traces the period from the satisfaction of Event Condition 5 to the
satisfaction of Event Condition 4.
To restrict trace acquisition to access only a specific address or specific function of a program, an
Event Condition can be used. Typical examples are described below.
• Example of halting a trace with a write access (M-bus) to H’FFF80000 by the user program as
a condition (trace halt):
Set the condition to be acquired on [I-Trace mode].
Set the following in the [Event Condition 1] or [Event Condition 2] dialog box:
Address condition: Set [Address] and H’FFF80000.
Bus state condition: Set [M-Bus] and [Write].
Action condition: Disable [Acquire Break] and set [Acquire Trace] for [Stop].
• Example of acquiring the write access (M-bus) only to H’FFF80000 by the user program (trace
acquisition condition):
Select [M-Bus & Branch] from [Type] and enable [Write] and [Data access] on [Acquisition].
Set the following in the [Event Condition 1] or [Event Condition 2] dialog box:
Address condition: Set [Address] and H’FFF80000.
Bus state condition: Set [M-Bus] and [Write].
Action condition: Disable [Acquire Break] and set [Acquire Trace] for [Condition].
For the trace acquisition condition, the condition to be acquired by the Event Condition should be
acquired by setting the [I-Trace mode].
• Example of acquiring a trace for the period while the program passes H’1000 through H’2000
(point-to-point):
Set the condition to be acquired on [I-Trace mode].
Set the address condition as H’1000 in the [Event Condition 4] dialog box.
Set the address condition as H’2000 in the [Event Condition 5] dialog box.
Rev. 4.00 Feb. 18, 2009 Page 44 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
Set [I-Trace] as [Ch4 to Ch5 PtoP] in the [Combination action (Sequential or PtoP)] dialog
box.
When point-to-point and trace acquisition condition are set simultaneously, they are ANDed.
Notes on Internal Trace:
• Timestamp
The timestamp is the clock counts of Bφ (48-bit counter). Table 3.13 shows the timing for
acquiring the timestamp.
Table 3.13 Timing for the Timestamp Acquisition
Item Acquisition Information Counter Value Stored in the Trace Memory
M-bus data access Counter value when data access (read or write) has
been completed
Branch Counter value when the next bus cycle has been
completed after a branch
I-bus Fetch Counter value when a fetch has been completed
Data access Counter value when data access has been completed
• Point-to-point
The trace-start condition is satisfied when the specified instruction has been fetched.
Accordingly, if the trace-start condition has been set for the overrun-fetched instruction (an
instruction that is not executed although it has been fetched at a branch or transition to an
interrupt), tracing is started during overrun-fetching of the instruction. However, when
overrun-fetching is achieved (a branch is completed), tracing is automatically suspended.
If the start and end conditions are satisfied closely, trace information will not be acquired
correctly.
The execution cycle of the instruction fetched before the start condition is satisfied may be
traced.
When the I-bus is acquired, do not specify point-to-point.
Memory access may not be acquired by the internal trace if it occurs at several instructions
immediately before satisfaction of the point-to-point end condition.
• Halting a trace
Do not set the trace-end condition for the SLEEP instruction and the branch instruction that the
delay slot becomes the SLEEP instruction.
Rev. 4.00 Feb. 18, 2009 Page 45 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
• Trace acquisition condition
Do not set the trace-end condition for the SLEEP instruction and the branch instruction
according to which the delay slot becomes the SLEEP instruction.
When [I-BUS, M-Bus & Branch] is selected and the trace acquisition condition is set for the
M-bus and I-bus with the Event Condition, set the M-bus condition and the I-bus condition for
[Event Condition 1] and [Event Condition 2], respectively.
If the settings of [I-Trace mode] are changed during execution of the program, execution will
be suspended. (The number of clock cycles to be suspended during execution of the program is
66 bus clock cycles (Bφ). If the bus clock (Bφ) is 20 MHz, the program will be suspended for
3.3 μs.)
• Displaying a trace
If a trace is displayed during execution of the program, execution will be suspended to acquire
the trace information. (The number of clock cycles to be suspended during execution of the
program is 24576 bus clock cycles (Bφ). If the bus clock (Bφ) is 20 MHz, the program will be
suspended for 1228.8 μs.)
• Branch trace
If breaks occur immediately after executing non-delayed branch and TRAPA instructions and
generating a branch due to exception or interrupt, a trace for one branch will not be acquired
immediately before such breaks.
However, this does not affect on generation of breaks caused by a BREAKPOINT and a break
before executing instructions of Event Condition.
• Writing memory immediately before generating a break
If an instruction is executed to write memory immediately before generating a break, trace
acquisition may not be performed.
Rev. 4.00 Feb. 18, 2009 Page 46 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
AUD Trace Functions: This function is operational when the AUD pins of the MCU are
connected to the emulator. Table 3.14 shows the AUD trace acquisition mode that can be set in
each trace function.
Table 3.14 AUD Trace Acquisition Mode
Type Mode Description
Continuous
trace occurs
Non realtime trace When the next branching occurs while the trace information
Trace buffer
full
Trace stop After the trace buffer becomes full, the trace information is no
Break A break occurs when the trace buffer becomes full.
AUD trace
function used
Time stamp clock The resolution of the timer for timestamps can be specified.
Realtime trace When the next branching occurs while the trace information
is being output, all the information may not be output. The
user program can be executed in realtime, but some trace
information will be lost.
is being output, the CPU stops operations until the
information is output. The user program is not executed in
realtime.
Trace continue This function writes the latest trace information on the oldest
information to store the latest trace information.
longer acquired. The user program is continuously executed.
Enable free trace When this box is checked, the emulator ignores the AUD
eventpoint setting and acquires all trace information.
Select 20 ns, 100 ns, 400 ns, or 1.6 μs.
To set the AUD trace acquisition mode, click the [Trace] window with the right mouse button and
select [Setting] from the pop-up menu to display the [I-Trace/AUD-Trace acquisition] dialog box.
The AUD trace acquisition mode can be set in the [AUD mode1], [AUD mode2], or [AUD
mode3] group box in the [Trace mode] page of the [I-Trace/AUD-Trace acquisition] dialog box.
Rev. 4.00 Feb. 18, 2009 Page 47 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
Figure 3.3 [Trace mode] Page
When the AUD trace function is used, select the [AUD function] radio button in the [Trace type]
group box of the [Trace mode] page.
Rev. 4.00 Feb. 18, 2009 Page 48 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
(a) Branch Trace Function
The branch source and destination addresses and their source lines are displayed.
Branch trace can be acquired by selecting the [Branch trace] check box in the [AUD function]
group box of the [Trace mode] page.
The branch type can be selected in the [AUD Branch trace] page.
Figure 3.4 [AUD Branch trace] Page
Rev. 4.00 Feb. 18, 2009 Page 49 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
(b) Window Trace Function
Memory access in the specified range can be acquired by trace.
Two memory ranges can be specified for channels A and B. The read, write, or read/write
cycle can be selected as the bus cycle for trace acquisition.
Setting Method:
(i) Select the [Channel A] and [Channel B] check boxes in the [AUD function] group
box of the [Trace mode] page. Each channel will become valid.
(ii) Open the [Window trace] page and specify the bus cycle and memory range that are to be
set for each channel.
Figure 3.5 [Window trace] Page
Rev. 4.00 Feb. 18, 2009 Page 50 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
Note: When [M-BUS] or [I-BUS] is selected, the following bus cycles will be traced.
• M-BUS: A bus cycle generated by the CPU is acquired.
• I-BUS: A bus cycle generated by the CPU or DMA is acquired.
(c) Software Trace Function
Note: This function can be supported with SuperH C/C++ compiler (manufactured by Renesas
Technology Corp.; including OEM and bundle products) V7.0 or later.
When a specific instruction is executed, the PC value at execution and the contents of one
general register are acquired by trace. Describe the Trace(x) function (x is a variable name) to
be compiled and linked beforehand. For details, refer to the SuperH
TM
RISC engine C/C++
Compiler, Assembler, Optimizing Linkage Editor User’s Manual.
When the load module is downloaded on the emulator and is executed while a software trace
function is valid, the PC value that has executed the Trace(x) function, the general register
value for x, and the source lines are displayed.
To activate the software trace function, select the [Software trace] check box in the [AUD
function] group box of the [Trace mode] page.
Notes on AUD Trace:
1. When the trace display is performed during user program execution, the mnemonics, operands,
or source is not displayed.
2. The AUD trace function outputs the differences between newly output branch source addresses
and previously output branch source addresses. The window trace function outputs the
differences between newly output addresses and previously output addresses. If the previous
branch source address is the same for the upper 16 bits, the lower 16 bits are output. If it
matches the upper 24 bits, the lower 8 bits are output. If it matches the upper 28 bits, the lower
4 bits are output.
The emulator regenerates the 32-bit address from these differences and displays it in the
[Trace] window. If the emulator cannot display the 32-bit address, it displays the difference
from the previously displayed 32-bit address.
3. If the 32-bit address cannot be displayed, the source line is not displayed.
4. In the emulator, when multiple loops are performed to reduce the number of AUD trace
displays, only the IP counts up.
5. In the emulator, the maximum number of trace displays is 262144 lines (131072 branches).
However, the maximum number of trace displays differs according to the AUD trace
information to be output. Therefore, the above pointers cannot always be acquired.
6. If a completion-type exception occurs during exception branch acquisition, the next address to
the address in which an exception occurs is acquired.
Rev. 4.00 Feb. 18, 2009 Page 51 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
7. The AUD trace is disabled while the profiling function is used.
8. If breaks occur immediately after executing non-delayed branch and TRAPA instructions and
generating a branch due to exception or interrupt, a trace for one branch will not be acquired
immediately before such breaks.
However, this does not affect on generation of breaks caused by a BREAKPOINT and a break
before executing instructions of Event Condition.
9. The value of [Data] is not appropriate in the trace result by the software trace (that value is
appropriate in the window trace result.).
3.2.3 Notes on Using the JTAG (H-UDI) Clock (TCK) and AUD Clock (AUDCK)
1. Set the JTAG clock (TCK) frequency to less than the frequency of the SH7286, SH7285, and
SH7243 peripheral module clock (CKP) and 25 MHz or lower.
2. The initial value of the JTAG clock (TCK) is 5 MHz.
3. A value to be set for the JTAG clock (TCK) is initialized after executing [Reset CPU] or
[Reset Go]. Thus the TCK value will be 5 MHz.
4. When debugging is performed without connecting the EV-chip unit, set the AUD clock
(AUDCK) frequency to 25 MHz or lower. When debugging is performed with the EV-chip
unit connected, set the AUD clock (AUDCK) frequency to 50 MHz or lower. If the higher
frequency is input, the emulator will not operate normally.
3.2.4 Notes on Setting the [Breakpoint] Dialog Box
1. When an odd address is set, the next lowest even address is used.
2. A BREAKPOINT is accomplished by replacing instructions of the specified address.
It cannot be set to the following addresses:
⎯ An area other than CS and the internal RAM
⎯ An instruction in which Event Condition 2 is satisfied
⎯ A slot instruction of a delayed branch instruction
3. During step operation, the specified BREAKPOINT and Event Condition breaks are disabled.
4. When execution resumes from the address where a BREAKPOINT is specified and a break
occurs before the Event Condition execution, single-step operation is performed at the address
before execution resumes. Therefore, realtime operation cannot be performed.
5. When a BREAKPOINT is set to the slot instruction of a delayed branch instruction, the PC
value becomes an illegal value. Accordingly, do not set a BREAKPOINT to the slot
instruction of a delayed branch instruction.
Rev. 4.00 Feb. 18, 2009 Page 52 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
6. If a BREAKPOINT cannot be correctly set to an address in the ROM or flash memory area, a
mark z will be displayed in the [BP] area of the address on the [Source] or [Disassembly]
window by refreshing the [Memory] window, etc. after Go execution. However, no break will
occur at this address. When the program halts with the break condition, the mark z
disappears.
7. If you wish to use a BREAKPOINT (software break), specify the SH2A_SBSTK command to
enable use of a user stack before setting a PC break. While enabled, extra four bytes of a user
stack are used when a break occurs. The value of the stack pointer (R15) must be correctly set
in advance because a user stack is to be used. By default, use of a user stack is disabled. For
details on the command, refer to the help file.
• Example
To enable use of a user stack:
>SH2A_SBSTK enable
3.2.5 Notes on Setting the [Event Condition] Dialog Box and the BREAKCONDITION_
SET Command
1. When [Go to cursor], [Step In], [Step Over], or [Step Out] is selected, the settings of Event
Condition 3 are disabled.
2. When an Event Condition is satisfied, emulation may stop after two or more instructions have
been executed.
3.2.6 Performance Measurement Function
The emulator supports the performance measurement function.
1. Setting the performance measurement conditions
To set the performance measurement conditions, use the [Performance Analysis] dialog box or
the PERFORMANCE_SET command. When any line in the [Performance Analysis] window
is clicked with the right mouse button, a popup menu is displayed and the [Performance
Analysis] dialog box can be displayed by selecting [Setting].
Note: For the command line syntax, refer to the online help.
Rev. 4.00 Feb. 18, 2009 Page 53 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
(a) Specifying the measurement start/end conditions
The measurement start/end conditions are specified by using Event Condition 1,2. The
[Ch1,2,3] list box of the [Combination action] dialog box can be used.
Table 3.15 Measurement Period
Classification Item Description
Selection in
the [Ch1, 2, 3]
list box
Ch1 to Ch2
Other than
Ch2 to Ch1
PA
PA
above
The period from the satisfaction of the condition set in Event
Condition 2 (start condition) to the satisfaction of the condition set
in Event Condition 1 (end condition) is set as the performance
measurement period.
The period from the satisfaction of the condition set in Event
Condition 1 (start condition) to the satisfaction of the condition set
in Event Condition 2 (end condition) is set as the performance
measurement period.
The period from the start of execution of the user program to the
occurrence of a break is measured.
Figure 3.6 [Performance Analysis] Dialog Box
Rev. 4.00 Feb. 18, 2009 Page 54 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
For measurement tolerance,
• The measured value includes tolerance.
• Tolerance will be generated before or after a break.
Note: When [Ch2 to Ch1 PA] or [Ch1 to Ch2 PA] is selected, to execute the user program,
specify conditions set in Event Condition 2 and Event Condition 1 and one or more items
for performance measurement.
(b) Measurement item
Items are measured with [Channel 1 to 4] in the [Performance Analysis] dialog box.
Maximum four conditions can be specified at the same time. Table 3.16 shows the
measurement items (Options in table 3.16 are parameters for <mode> of the
PERFORMANCE_SET command. They are displayed for CONDITION in the [Performance
Analysis] window).
Rev. 4.00 Feb. 18, 2009 Page 55 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
Table 3.16 Measurement Item
Selected Name Option
Disabled None
Elapsed time AC
Branch instruction counts BT
Number of execution instructions I
Number of execution 32bit-instructions I32
Exception/interrupt counts EA
Interrupt counts INT
Data cache-miss counts DC
Instruction cache-miss counts IC
All area access counts ARN
All area instruction access counts ARIN
All area data access counts ARND
Cacheable area access counts CDN (data access)
Cacheable area instruction access counts CIN
Non cacheable area data access counts NCN
URAM area access counts UN
URAM area instruction access counts UIN
URAM area data access counts UDN
Internal I/O area data access counts IODN
Internal ROM area access counts RN
Internal ROM area instruction access counts RIN
Internal ROM area data access counts RDN
All area access cycle ARC
All area instruction access cycle ARIC
All area data access cycle ARDC
All area access stall ARS
All area instruction access stall ARIS
All area data access stall ARDS
Rev. 4.00 Feb. 18, 2009 Page 56 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
Notes: 1. In the non-realtime trace mode of the AUD trace, normal counting cannot be performed
because the generation state of the stall or the execution cycle is changed.
2. If the internal ROM is not installed on the product, do not set the measurement item for
the internal ROM area.
3. For SH7286, SH7285, and SH7243, do not set measurement items for the cache-miss
counts, cacheable area, or non-cacheable area.
2. Displaying the measured result
The measured result is displayed in the [Performance Analysis] window or the
PERFORMANCE_ANALYSIS command in hexadecimal (32 bits).
Note: If a performance counter overflows as a result of measurement, “********” will be
displayed.
3. Initializing the measured result
To initialize the measured result, select [Initialize] from the popup menu in the [Performance
Analysis] window or specify INIT with the PERFORMANCE_ANALYSIS command.
Rev. 4.00 Feb. 18, 2009 Page 57 of 64
REJ10J1662-0400
Section 3 Software Specifications when Using the SH7286, SH7285, and SH7243
Rev. 4.00 Feb. 18, 2009 Page 58 of 64
REJ10J1662-0400
Section 4 User System Interface Circuits
Section 4 User System Interface Circuits
4.1 User System Interface Circuits
Figures 4.1 through 4.6 show user system interface circuits. Use them as a reference to determine
the value of the pull-up resistance.
SH7280
MD1
MD0
FWE
SH7280
HD151015
HD151015 EP1S10
EP1S10
EP1S10
EP1S10
CB3T16211
CB3T16211
Figure 4.1 User System Interface Circuits
User system
Vcc
100 kΩ
MD1
MD0
Vcc
100 kΩ
FWE
User system
_WDTOVF_WDTOVF
Figure 4.2 User System Interface Circuits
Rev. 4.00 Feb. 18, 2009 Page 59 of 64
REJ10J1662-0400
Section 4 User System Interface Circuits
SH7280
HD151015
NMI NMI
HD151015
_RES
CN2
EP1S10
AHC14 AHC14
EP1S10LVC08
AHC14 AHC14
Figure 4.3 User System Interface Circuits
User system
Vcc
100 kΩ
Vcc
100 kΩ
_RES
Rev. 4.00 Feb. 18, 2009 Page 60 of 64
REJ10J1662-0400
Section 4 User System Interface Circuits
SH7280
XTAL
EXTAL EXTAL
VCC
VSS
PLLVSS
PVCC
AVCC
AVSS
AVREFVSS
AVREF
VCL
N.C.
HD151015
0.01
μF
0.01
μF
0.01
μF
0.01
μF
0.1 μF
3.3 V
2200
pF
2200
pF
2200
pF
2200
pF
EP1S10
1 μF
1 μF
1 μF
LVTH16244
3.3
μF
3.3
μF
3.3
μF
Vcc
100 kΩ
G6K_2G_DC3V
G6K_2G_DC3V
G6K_2G_DC3V
3.3 V
3.3 V
3.3 V
N.C.
1 μF
N.C.
1 μF
1 μF
N.C.
N.C.
N.C.
User system
XTAL
VSS
VCC
PLLVSS
AVCC
AVREF
AVSS
AVREFVSS
VCL
Figure 4.4 User System Interface Circuits
Rev. 4.00 Feb. 18, 2009 Page 61 of 64
REJ10J1662-0400
Section 4 User System Interface Circuits
SH7280
PF(11:0) PF(11:0)
DA1, DA0 DA1, DA0
ASEBCK
ASEBRK
AVcc
DALC112S1
EP1S10
LVTH16244
N.C.
User system
Figure 4.5 User System Interface Circuits
ASEBRK
Rev. 4.00 Feb. 18, 2009 Page 62 of 64
REJ10J1662-0400
Section 4 User System Interface Circuits
SH7280
PA23-PA21, PA14-PA10
PA8-PA6, PB19-PB15
PB9, PB6, PB3-PB0
PC15-0, PD31-PD20
PD15-PD0, PE15-PE13
PE7
PA5-PA0, PB12, PB11
PB8, PB7, PD19-PD16
PE15-PE13
PA15, PA9, PB14, PB13
PB10, PE12-PE8
PE6-0
EP1S10
EP1S10
Vcc
100 kΩ
CB3T16211
100 kΩ
CB3T16211
Vcc
100 kΩ
74V2G66
User system
PA23-PA21, PA14-PA10
PA8-PA6, PB19-PB15
PB9, PB6, PB3-PB0
PC15-0, PD31-PD20
PD15-PD0, PE15-PE13
PE7
VccVcc
100 kΩ
PA5-PA0, PB12, PB11
PB8, PB7, PD19-PD16
PE15-PE13
PA15, PA9, PB14, PB13
PB10, PE12-PE8
PE6-0
Figure 4.6 User System Interface Circuits
Note: A part of port pin names shown in figure 4.6 may not be included in the pin assignment
diagram of the SH7286, SH7285, and SH7243. These pins are not connected to the user
system.
Rev. 4.00 Feb. 18, 2009 Page 63 of 64
REJ10J1662-0400
Section 4 User System Interface Circuits
SH7280
DrVCC
DrVSS
USBXTAL
USBEXTAL
USD+
USD-
VBUS
3.3 V
EP1S10
48 MHz
CB3T16211
MAX709R
N.C.
N.C.
N.C.
220 Ω
Figure 4.7 User System Interface Circuits
4.2 Delay Time for the User System Interface
47 Ω
User system
DrVCC
DrVSS
USBXTAL
USBEXTAL
USD+
USD-
VBUS
100 kΩ
Since the _RES and NMI signals are connected to the user system via the logic on the EV-chip
unit, a delay time shown in table 4.1 will be generated until the signal is input from the user
system to the MCU.
Table 4.1 Delay Time for Signals via the EV-chip Unit
No. Signal Name Delay Time (ns)
1 _RES 24
2 NMI 21
Rev. 4.00 Feb. 18, 2009 Page 64 of 64
REJ10J1662-0400
SH-2A, SH-2 E200F Emulator
Additional Document for User's Manual
Supplementary Information on Using the SH7286, SH7285,
and SH7243
Publication Date: Rev.1.00, June 12, 2007
Rev.4.00, February 18, 2009
Published by: Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by: Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
© 2009. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
http://www.renesas.com
Colophon 6.2
SH-2A, SH-2 E200F Emulator
Additional Document for User’s Manual
Supplementary Information on Using the
SH7286, SH7285, and SH7243
1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan
REJ10J1662-0400
Loading...