Renesas 4514, 4513 User Manual

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To all our customers

Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.

The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself.

Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

MITSUBISHI 4-BIT SINGLE-CHIP MICROCOMPUTER

4500 SERIES

4513/4514

Group

User’s Manual

keep safety first in your circuit designs !

Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.

Notes regarding these materials

These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.

Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials.

All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein.

Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.

The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.

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Any diversion or reexport contrary to the export control laws and regulations of JAPAN and/or the country of destination is prohibited.

Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.

Preface

This user’s manual describes the hardware and instructions of Mitsubishi’s 4513/4514 Group CMOS 4-bit microcomputer.

After reading this manual, the user should have a through knowledge of the functions and features of the 4513/4514 Group and should be able to fully utilize the product. The manual starts with specifications and ends with application examples.

In this manual, the 4514 Group is mainly described. The differences from the 4513 Group are described at the related points.

BEFORE USING THIS USER’S MANUAL

This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development.

1. Organization

CHAPTER 1 HARDWARE

This chapter describes features of the microcomputer and operation of each peripheral function.

CHAPTER 2 APPLICATION

This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers.

CHAPTER 3 APPENDIX

This chapter includes precautions for systems development using the microcomputer, the mask ROM confirmation forms (mask ROM version), and mark specification forms which are to be submitted when ordering.

Be sure to refer to this chapter because this chapter also includes necessary information for systems development.

Note: In this manual, the 4514 Group is mainly described. The differences from the 4513 Group are described at the related points.

 

 

Table of contents

 

 

 

Table of contents

 

CHAPTER 1 HARDWARE

 

 

 

 

 

 

DESCRIPTION ................................................................................................................................

1-3

FEATURES ......................................................................................................................................

1-3

APPLICATION ................................................................................................................................

1-3

PIN CONFIGURATION ..................................................................................................................

1-4

BLOCK DIAGRAM .........................................................................................................................

1-6

PERFORMANCE OVERVIEW .......................................................................................................

1-8

PIN DESCRIPTION ........................................................................................................................

1-9

MULTIFUNCTION ...................................................................................................................

1-10

CONNECTIONS OF UNUSED PINS ...................................................................................

1-10

PORT FUNCTION ..................................................................................................................

1-11

DEFINITION OF CLOCK AND CYCLE ...............................................................................

1-11

PORT BLOCK DIAGRAMS ...................................................................................................

1-12

FUNCTION BLOCK OPERATIONS ...........................................................................................

1-17

CPU ..........................................................................................................................................

1-17

PROGRAM MEMOY (ROM) ..................................................................................................

1-20

DATA MEMORY (RAM) .........................................................................................................

1-21

INTERRUPT FUNCTION .......................................................................................................

1-22

EXTERNAL INTERRUPTS ....................................................................................................

1-26

TIMERS ...................................................................................................................................

1-29

WATCHDOG TIMER ..............................................................................................................

1-35

SERIAL I/O..............................................................................................................................

1-36

A-D CONVERTER ..................................................................................................................

1-41

VOLTAGE COMPARATOR....................................................................................................

1-47

RESET FUNCTION ................................................................................................................

1-49

VOLTAGE DROP DETECTION CIRCUIT ...........................................................................

1-52

RAM BACK-UP MODE ..........................................................................................................

1-53

CLOCK CONTROL .................................................................................................................

1-57

ROM ORDERING METHOD .......................................................................................................

1-58

LIST OF PRECAUTIONS ............................................................................................................

1-59

SYMBOL ........................................................................................................................................

1-62

LIST OF INSTRUCTION FUNCTION ........................................................................................

1-63

INSTRUCTION CODE TABLE....................................................................................................

1-66

MACHINE INSTRUCTIONS ........................................................................................................

1-70

CONTROL REGISTERS ..............................................................................................................

1-84

BUILT-IN PROM VERSION ........................................................................................................

1-88

4513/4514 Group User’s Manual

i

 

 

 

Table of contents

 

 

 

CHAPTER 2 APPLICATION

 

 

 

 

 

 

2.1

I/O pins ....................................................................................................................................

2-2

 

2.1.1 I/O ports ..........................................................................................................................

2-2

 

2.1.2 Related registers ............................................................................................................

2-4

 

2.1.3 Port application examples .............................................................................................

2-7

 

2.1.4 Notes on use ..................................................................................................................

2-9

2.2

Interrupts ...............................................................................................................................

2-11

 

2.2.1 Interrupt functions ........................................................................................................

2-11

 

2.2.2 Related registers ..........................................................................................................

2-13

 

2.2.3 Interrupt application examples....................................................................................

2-16

 

2.2.4 Notes on use ................................................................................................................

2-25

2.3

Timers ....................................................................................................................................

2-26

 

2.3.1 Timer functions .............................................................................................................

2-26

 

2.3.2 Related registers ..........................................................................................................

2-27

 

2.3.3 Timer application examples ........................................................................................

2-30

 

2.3.4 Notes on use ................................................................................................................

2-39

2.4

Serial I/O ................................................................................................................................

2-40

 

2.4.1 Carrier functions ...........................................................................................................

2-40

 

2.4.2 Related registers ..........................................................................................................

2-41

 

2.4.3 Operation description ...................................................................................................

2-42

 

2.4.4 Serial I/O application example ...................................................................................

2-45

 

2.4.5 Notes on use ................................................................................................................

2-48

2.5

A-D converter .......................................................................................................................

2-49

 

2.5.1 Related registers ..........................................................................................................

2-50

 

2.5.2 A-D converter application examples ..........................................................................

2-51

 

2.5.3 Notes on use ................................................................................................................

2-52

2.6

Voltage comparator .............................................................................................................

2-54

 

2.6.1 Voltage comparator function .......................................................................................

2-54

 

2.6.2 Related registers ..........................................................................................................

2-54

 

2.6.3 Notes on use ................................................................................................................

2-55

2.7

Reset.......................................................................................................................................

2-56

 

2.7.1 Reset circuit ..................................................................................................................

2-56

 

2.7.2 Internal state at reset ..................................................................................................

2-57

2.8

Voltage drop detection circuit..........................................................................................

2-58

2.9

RAM back-up ........................................................................................................................

2-59

 

2.9.1 RAM back-up mode .....................................................................................................

2-59

 

2.9.2 Related register ............................................................................................................

2-60

 

2.9.3 Notes on use ................................................................................................................

2-62

2.10 Oscillation circuit ..............................................................................................................

2-63

 

2.10.1 Oscillation circuit ........................................................................................................

2-63

 

2.10.2 Oscillation operation ..................................................................................................

2-64

 

2.10.3 Notes on use ..............................................................................................................

2-64

ii

4513/4514 Group User’s Manual

 

 

Table of contents

 

 

 

CHAPTER 3 APPENDIX

 

 

 

 

 

 

3.1

Electrical characteristics .....................................................................................................

3-2

 

3.1.1 Absolute maximum ratings ............................................................................................

3-2

 

3.1.2 Recommended operating conditions ............................................................................

3-3

 

3.1.3 Electrical characteristics ................................................................................................

3-5

 

3.1.4 A-D converter recommended operating conditions....................................................

3-6

 

3.1.5 Voltage drop detection circuit characteristics.............................................................

3-6

 

3.1.6 Voltage comparator characteristics ..............................................................................

3-7

 

3.1.7 Basic timing diagram .....................................................................................................

3-7

3.2

Typical characteristics .........................................................................................................

3-8

 

3.2.1 VDD–IDD characteristics .................................................................................................

3-8

 

3.2.2 VOL–IOL characteristics ................................................................................................

3-11

 

3.2.3 VOH–IOH characteristics (Port P5) .............................................................................

3-13

 

3.2.4 VDD–RPU characteristics (Ports P0, P1) ...................................................................

3-13

 

3.2.5 A-D converter typical characteristics .........................................................................

3-14

 

3.2.6 Analog input current characteristics pins AIN0–AIN7 ............................................................

3-17

 

3.2.7 VDD–VIH/VIL characteristics .........................................................................................

3-19

 

3.2.8 Detection voltage temperature characteristics of voltage drop detection circuit . 3-20

3.3

List of precautions ..............................................................................................................

3-21

3.4

Notes on noise .....................................................................................................................

3-24

 

3.4.1 Shortest wiring length ..................................................................................................

3-24

 

3.4.2 Connection of bypass capacitor across VSS line and VDD line ............................

3-26

 

3.4.3 Wiring to analog input pins ........................................................................................

3-27

 

3.4.4 Oscillator concerns.......................................................................................................

3-27

 

3.4.5 Setup for I/O ports .......................................................................................................

3-28

 

3.4.6 Providing of watchdog timer function by software ..................................................

3-28

3.5

Mask ROM order confirmation form ...............................................................................

3-30

3.6

Mark specification form .....................................................................................................

3-36

3.7

Package outline ...................................................................................................................

3-39

4513/4514 Group User’s Manual

iii

List of figures

List of figures

CHAPTER 1 HARDWARE

PIN CONFIGURATION (TOP VIEW) 4513 Group .....................................................................

1-4

PIN CONFIGURATION (TOP VIEW) 4514 Group .....................................................................

1-5

BLOCK DIAGRAM (4513 Group) .................................................................................................

1-6

BLOCK DIAGRAM (4514 Group) .................................................................................................

1-7

PORT BLOCK DIAGRAMS .........................................................................................................

1-12

External interrupt circuit structure ..............................................................................................

1-16

Fig. 1 AMC instruction execution example ...............................................................................

1-17

Fig. 2 RAR instruction execution example ...............................................................................

1-17

Fig. 3 Registers A, B and register E ........................................................................................

1-17

Fig. 4 TABP p instruction execution example ..........................................................................

1-17

Fig. 5 Stack registers (SKs) structure .......................................................................................

1-18

Fig. 6 Example of operation at subroutine call .......................................................................

1-18

Fig. 7 Program counter (PC) structure .....................................................................................

1-19

Fig. 8 Data pointer (DP) structure .............................................................................................

1-19

Fig. 9 SD instruction execution example ..................................................................................

1-19

Fig. 10 ROM map of M34514M8/E8 .........................................................................................

1-20

Fig. 11 Page 1 (addresses 008016 to 00FF16) structure .......................................................

1-20

Fig. 12 RAM map .........................................................................................................................

1-21

Fig. 13 Program example of interrupt processing ...................................................................

1-23

Fig. 14 Internal state when interrupt occurs ............................................................................

1-23

Fig. 15 Interrupt system diagram ...............................................................................................

1-23

Fig. 16 Interrupt sequence..........................................................................................................

1-25

Fig. 17 External interrupt circuit structure ................................................................................

1-26

Fig. 18 Auto-reload function .......................................................................................................

1-29

Fig. 19 Timers structure ..............................................................................................................

1-31

Fig. 20 Watchdog timer function ................................................................................................

1-35

Fig. 21 Program example to enter the RAM back-up mode when using the watchdog timer ....

1-35

Fig. 22 Serial I/O structure .........................................................................................................

1-36

Fig. 23 Serial I/O register state when transferring..................................................................

1-37

Fig. 24 Serial I/O connection example......................................................................................

1-38

Fig. 25 Timing of serial I/O data transfer .................................................................................

1-39

Fig. 26 A-D conversion circuit structure ...................................................................................

1-41

Fig. 27 A-D conversion timing chart..........................................................................................

1-44

Fig. 28 Setting registers ..............................................................................................................

1-44

Fig. 29 Comparator operation timing chart...............................................................................

1-45

Fig. 30 Definition of A-D conversion accuracy ........................................................................

1-46

Fig. 31 Voltage comparator structure ........................................................................................

1-47

Fig. 32 Reset release timing ......................................................................................................

1-49

Fig. 33

 

pin input waveform and reset operation

1-49

RESET

Fig. 34 Power-on reset circuit example ....................................................................................

1-50

Fig. 35 Internal state at reset ....................................................................................................

1-51

Fig. 36 Voltage drop detection reset circuit .............................................................................

1-52

Fig. 37 Voltage drop detection circuit operation waveform....................................................

1-52

Fig. 38 State transition ................................................................................................................

1-55

Fig. 39 Set source and clear source of the P flag .................................................................

1-55

Fig. 40 Start condition identified example using the SNZP instruction ................................

1-55

Fig. 41 Clock control circuit structure .......................................................................................

1-57

iv

4513/4514 Group User’s Manual

 

List of figures

 

 

 

Fig. 42 Ceramic resonator external circuit ...............................................................................

1-58

Fig. 43 External clock input circuit ............................................................................................

1-58

Fig. 44 External 0 interrupt program example .........................................................................

1-59

Fig. 45 External 1 interrupt program example .........................................................................

1-59

Fig. 46 A-D converter operating mode program example ......................................................

1-60

Fig. 47 Analog input external circuit example-1 ......................................................................

1-60

Fig. 48 Analog input external circuit example-2 ......................................................................

1-60

Fig. 49 Pin configuration of built-in PROM version of 4513 Group......................................

1-88

Fig. 50 Pin configuration of built-in PROM version of 4514 Group......................................

1-88

Fig. 51 PROM memory map .......................................................................................................

1-89

Fig. 52 Flow of writing and test of the product shipped in blank.........................................

1-89

CHAPTER 2 APPLICATION

 

 

 

 

Fig. 2.1.1 Key input by key scan.................................................................................................

2-7

Fig. 2.1.2 Key scan input timing ..................................................................................................

2-8

Fig. 2.2.1 INT0 interrupt operation example ............................................................................

2-17

Fig. 2.2.2 INT0 interrupt setting example .................................................................................

2-18

Fig. 2.2.3 INT1 interrupt operation example ............................................................................

2-19

Fig. 2.2.4 INT1 interrupt setting example .................................................................................

2-20

Fig. 2.2.5 Timer 1 constant period interrupt setting example................................................

2-21

Fig. 2.2.6 Timer 2 constant period interrupt setting example................................................

2-22

Fig. 2.2.7 Timer 3 constant period interrupt setting example................................................

2-23

Fig. 2.2.8 Timer 4 constant period interrupt setting example................................................

2-24

Fig. 2.3.1 Peripheral circuit example .........................................................................................

2-30

Fig. 2.3.2 Watchdog timer function............................................................................................

2-31

Fig. 2.3.3 Constant period measurement setting example .....................................................

2-32

Fig. 2.3.4 CNTR0 output setting example ................................................................................

2-33

Fig. 2.3.5 CNTR1 input setting example ..................................................................................

2-34

Fig. 2.3.6 CNTR0 output control setting example ...................................................................

2-35

Fig. 2.3.7 Timer start by external input setting example (1) .................................................

2-36

Fig. 2.3.8 Timer start by external input setting example (2) .................................................

2-37

Fig. 2.3.9 Watchdog timer setting example ..............................................................................

2-38

Fig. 2.4.1 Serial I/O block diagram ...........................................................................................

2-40

Fig. 2.4.2 Serial I/O connection example .................................................................................

2-42

Fig. 2.4.3 Serial I/O register state when transmitting/receiving ............................................

2-42

Fig. 2.4.4 Serial I/O transfer timing ...........................................................................................

2-43

Fig. 2.4.5 Master serial I/O setting example ............................................................................

2-46

Fig. 2.4.6 Slave serial I/O example ...........................................................................................

2-47

Fig. 2.4.7 Input waveform of external clock .............................................................................

2-48

Fig. 2.5.1 A-D converter structure .............................................................................................

2-49

Fig. 2.5.2 A-D conversion mode setting example ...................................................................

2-51

Fig. 2.5.3 Analog input external circuit example-1 ..................................................................

2-52

Fig. 2.5.4 Analog input external circuit example-2 ..................................................................

2-52

Fig. 2.5.5 A-D converter operating mode program example..................................................

2-52

Fig. 2.7.1 Power-on reset circuit example ................................................................................

2-56

Fig. 2.7.2 Oscillation stabilizing time after system is released from reset ..........................

2-56

Fig. 2.7.3 Internal state at reset ................................................................................................

2-57

Fig. 2.8.1 Voltage drop detection reset circuit .........................................................................

2-58

Fig. 2.8.2 Voltage drop detection circuit operation waveform ...............................................

2-58

Fig. 2.9.1 Start condition identified example ............................................................................

2-60

Fig. 2.10.1 Oscillation circuit example connecting ceramic resonator externally................

2-63

Fig. 2.10.2 Structure of clock control circuit ............................................................................

2-64

 

 

 

4513/4514 Group User’s Manual

v

List of figures

CHAPTER 3 APPENDIX

Fig. 3.2.1 A-D conversion characteristics data ........................................................................

3-14

Fig. 44 External 0 interrupt program example .........................................................................

3-21

Fig. 45

External 1 interrupt program example .........................................................................

3-21

Fig. 46

A-D converter operating mode program example ......................................................

3-22

Fig. 47

Analog input external circuit example-1 ......................................................................

3-22

Fig. 48

Analog input external circuit example-2 ......................................................................

3-22

Fig. 3.4.1 Selection of packages ...............................................................................................

3-24

Fig. 3.4.2 Wiring for the

 

input pin

3-24

RESET

Fig. 3.4.3 Wiring for clock I/O pins ...........................................................................................

3-25

Fig. 3.4.4 Wiring for CNVSS pin .................................................................................................

3-25

Fig. 3.4.5 Wiring for the VPP pin of the One Time PROM version ......................................

3-26

Fig. 3.4.6 Bypass capacitor across the VSS line and the VDD line ......................................

3-26

Fig. 3.4.7 Analog signal line and a resistor and a capacitor ................................................

3-27

Fig. 3.4.8 Wiring for a large current signal line ......................................................................

3-27

Fig. 3.4.9 Wiring to a signal line where potential levels change frequently .......................

3-28

Fig. 3.4.10 VSS pattern on the underside of an oscillator .....................................................

3-28

Fig. 3.4.11 Watchdog timer by software ...................................................................................

3-29

vi

4513/4514 Group User’s Manual

List of tables

List of tables

CHAPTER 1 HARDWARE

Table Selection of system clock ................................................................................................

1-11

Table 1 ROM size and pages ....................................................................................................

1-20

Table 2 RAM size ........................................................................................................................

1-21

Table 3 Interrupt sources ............................................................................................................

1-22

Table 4 Interrupt request flag, interrupt enable bit and skip instruction..............................

1-22

Table 5 Interrupt enable bit function .........................................................................................

1-22

Table 6 Interrupt control registers .............................................................................................

1-24

Table 7 External interrupt activated conditions........................................................................

1-26

Table 8 External interrupt control registers ..............................................................................

1-28

Table 9 Function related timers .................................................................................................

1-30

Table 10 Timer control registers ................................................................................................

1-32

Table 11 Serial I/O pins ..............................................................................................................

1-36

Table 12 Serial I/O mode register .............................................................................................

1-36

Table 13 Processing sequence of data transfer from master to slave ................................

1-40

Table 14 A-D converter characteristics .....................................................................................

1-41

Table 15 A-D control registers ...................................................................................................

1-42

Table 16 Change of successive comparison register AD during A-D conversion ..............

1-43

Table 17 Voltage comparator characteristics ...........................................................................

1-47

Table 18 Voltage comparator control register Q3 ...................................................................

1-48

Table 19 Port state at reset .......................................................................................................

1-50

Table 20 Functions and states retained at RAM back-up .....................................................

1-53

Table 21 Return source and return condition ..........................................................................

1-54

Table 22 Key-on wakeup control register, pull-up control register, and interrupt control . 1-56

Table 23 Clock control register MR ..........................................................................................

1-57

Table 24 Maximum value of external clock oscillation frequency .........................................

1-58

Table 25 Product of built-in PROM version .............................................................................

1-88

Table 26 Programming adapters ................................................................................................

1-89

CHAPTER 2 APPLICATION

 

 

 

 

 

 

Table 2.1.1 Pull-up control register PU0 ....................................................................................

2-4

Table 2.1.2 Key-on wakeup control register K0 ........................................................................

2-5

Table 2.1.3 A-D control register Q2 ............................................................................................

2-5

Table 2.1.4 Direction register FR0 ..............................................................................................

2-6

Table 2.1.5 Timer control register W6 ........................................................................................

2-6

Table 2.1.6 connections of unused pins ...................................................................................

2-10

Table 2.2.1 Interrupt control register V1...................................................................................

2-14

Table 2.2.2 Interrupt control register V2...................................................................................

2-14

Table 2.2.3 Interrupt control register I1 ....................................................................................

2-15

Table 2.2.4 Interrupt control register I2 ....................................................................................

2-15

Table 2.3.1 Interrupt control register V1...................................................................................

2-27

Table 2.3.2 Interrupt control register V2...................................................................................

2-27

Table 2.3.3 Timer control register W1 ......................................................................................

2-28

Table 2.3.4 Timer control register W2 ......................................................................................

2-28

Table 2.3.5 Timer control register W3 ......................................................................................

2-29

Table 2.3.6 Timer control register W4 ......................................................................................

2-29

Table 2.4.1 Serial I/O mode register J1 ...................................................................................

2-41

Table 2.4.2 Recommended operating conditions (serial I/O) .................................................

2-48

 

 

 

4513/4514 Group User’s Manual

vii

List of tables

Table 2.5.1 A-D control register Q1 ..........................................................................................

2-50

Table 2.5.2 A-D control register Q2 ..........................................................................................

2-50

Table 2.5.3 Recommended operating conditions (when using A-D converter) ...................

2-53

Table 2.6.1 Voltage comparator control register Q3 ...............................................................

2-54

Table 2.9.1 Functions and states retained at RAM back-up mode ......................................

2-59

Table 2.9.2 Return source and return condition ......................................................................

2-60

Table 2.9.3 Start condition identification...................................................................................

2-60

Table 2.9.4 Key-on wakeup control register K0 ......................................................................

2-60

Table 2.9.5 Pull-up control register PU0 ..................................................................................

2-61

Table 2.9.6 Interrupt control register I1 ....................................................................................

2-61

Table 2.9.7 Interrupt control register I2 ....................................................................................

2-62

Table 2.10.1 Maximum value of oscillation frequency and supply voltage .........................

2-63

CHAPTER 3 APPENDIX

 

 

 

 

 

 

Table 3.1.1 Absolute maximum ratings .......................................................................................

3-2

Table 3.1.2 Recommended operating conditions 1 ...................................................................

3-3

Table 3.1.3 Recommended operating conditions 2 ...................................................................

3-4

Table 3.1.4 Electrical characteristics ...........................................................................................

3-5

Table 3.1.5 A-D converter recommended operating conditions...............................................

3-6

Table 3.1.6 A-D converter characteristics ..................................................................................

3-6

Table 3.1.7 Voltage drop detection circuit characteristics........................................................

3-6

Table 3.1.8 Voltage comparator recommended operating conditions .....................................

3-7

Table 3.1.9 Voltage comparator characteristics .........................................................................

3-7

viii

4513/4514 Group User’s Manual

C H A P T E R 1

HARDWARE

DESCRIPTION FEATURES APPLICATION

PIN CONFIGURATION BLOCK DIAGRAM PERFORMANCE OVERVIEW PIN DESCRIPTION

FUNCTION BLOCK OPERATIONS ROM ORDERING METHOD

LIST OF PRECAUTIONS SYMBOL

LIST OF INSTRUCTION FUNCTION INSTRUCTION CODE TABLE MACHINE INSTRUCTIONS CONTROL REGISTERS

BUILT-IN PROM VERSION

HARDWARE

1-2

4513/4514 Group User’s Manual

HARDWARE

DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION

DESCRIPTION

The 4513/4514 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with serial I/O, four 8-bit timers (each timer has a reload register), and 10-bit A-D converter.

The various microcomputers in the 4513/4514 Group include variations of the built-in memory type and package as shown in the table below.

FEATURES

Minimum instruction execution time ................................ 0.75 μs (at 4.0 MHz oscillation frequency, in high-speed mode, VDD = 4.0 V to 5.5 V)

Supply voltage

• Middle-speed mode

...... 2.5 V to 5.5 V (at 4.2 MHz oscillation frequency, for Mask ROM version and One Time PROM version)

...... 2.0 V to 5.5 V (at 3.0 MHz oscillation frequency, for Mask ROM version)

(Operation voltage of A-D conversion: 2.7 V to 5.5 V)

• High-speed mode

...... 4.0 V to 5.5 V (at 4.2 MHz oscillation frequency, for Mask ROM version and One Time PROM version)

...... 2.5 V to 5.5 V (at 2.0 MHz oscillation frequency, for Mask ROM version and One Time PROM version)

...... 2.0 V to 5.5 V (at 1.5 MHz oscillation frequency, for Mask ROM version)

(Operation voltage of A-D conversion: 2.7 V to 5.5 V)

●Timers

 

Timer 1 ......................................

8-bit timer with a reload register

Timer 2 ......................................

8-bit timer with a reload register

Timer 3 ......................................

8-bit timer with a reload register

Timer 4 ......................................

8-bit timer with a reload register

●Interrupt ........................................................................

8 sources

●Serial I/O .......................................................................

8 bit-wide

●A-D converter ..................

10-bit successive comparison method

●Voltage comparator ........................................................

2 circuits

●Watchdog timer .................................................................

16 bits

Voltage drop detection circuit

Clock generating circuit (ceramic resonator)

LED drive directly enabled (port D)

APPLICATION

Electrical household appliance, consumer electronic products, office automation equipment, etc.

Product

ROM (PROM) size

RAM size

Package

ROM type

( 10 bits)

( 4 bits)

 

 

 

M34513M2-XXXSP/FP

2048 words

128 words

SP: 32P4B FP: 32P6B-A

Mask ROM

M34513M4-XXXSP/FP

4096 words

256 words

SP: 32P4B FP: 32P6B-A

Mask ROM

M34513E4SP/FP (Note)

4096 words

256 words

SP: 32P4B FP: 32P6B-A

One Time PROM

M34513M6-XXXFP

6144 words

384 words

32P6B-A

Mask ROM

M34513M8-XXXFP

8192 words

384 words

32P6B-A

Mask ROM

M34513E8FP (Note)

8192 words

384 words

32P6B-A

One Time PROM

M34514M6-XXXFP

6144 words

384 words

42P2R-A

Mask ROM

M34514M8-XXXFP

8192 words

384 words

42P2R-A

Mask ROM

M34514E8FP (Note)

8192 words

384 words

42P2R-A

One Time PROM

 

 

 

 

 

Note: shipped in blank

4513/4514 Group User’s Manual

1-3

HARDWARE

PIN CONFIGURATION

PIN CONFIGURATION (TOP VIEW) 4513 Group

D0 1

D1 2

D2 3

D3 4

D4 5

D5 6

D6/CNTR0 7

D7/CNTR1 8

P20/SCK 9

P21/SOUT 10

P22/SIN 11

RESET 12

CNVSS 13

XOUT 14

XIN 15

VSS 16

M34513E4SP

XXXSP-M34513Mx

32

P13

 

P12

31

 

P11

 

30

 

P10

 

29

 

P03

 

28

 

P02

 

27

 

P01

 

26

 

P00

 

25

 

AIN3/CMP1+

 

24

 

AIN2/CMP1-

 

23

 

AIN1/CMP0+

 

22

 

AIN0/CMP0-

 

21

 

P31/INT1

 

20

 

P30/INT0

 

19

 

VDCE

 

18

 

 

 

 

17

VDD

Outline 32P4B

D2

D1

D0

P13

P12

32

31

30

29

28

P11 27

P10 26

P03 25

D3 1

D4 2

D5 3

D6/CNTR0 4

D7/CNTR1 5

P20/SCK 6

P21/SOUT 7

P22/SIN 8

M34513Mx-XXXFP

M34513ExFP

24 P02

23 P01

22 P00

21 AIN3/CMP1+

20 AIN2/CMP1-

19 AIN1/CMP0+

18 AIN0/CMP0-

17 P31/INT1

9 RESET

10 CNVSS

11

12

13

14

15

16

XOUT

XIN

VSS

VDD

VDCE

P3/INT00

Outline 32P6B-A

1-4

4513/4514 Group User’s Manual

HARDWARE

PIN CONFIGURATION

PIN CONFIGURATION (TOP VIEW) 4514 Group

P13

1

D0

2

D1

3

D2

4

D3

5

D4

6

D5

7

D6/CNTR0

8

D7/CNTR1

9

P50

10

P51

11

P52

12

P53

13

P20/SCK

14

P21/SOUT

15

P22/SIN

16

RESET

17

CNVSS

18

XOUT

19

XIN

20

VSS

21

M34514E8FP

XXXFP-M34514Mx

Outline 42P2R-A

42

P12

41

P11

40

P10

39

P03

38

P02

37

P01

36

P00

35

P43/AIN7

34

P42/AIN6

33

P41/AIN5

32

P40/AIN4

31

AIN3/CMP1+

30

AIN2/CMP1-

29

AIN1/CMP0+

28

AIN0/CMP0-

27

P33

26

P32

25

P31/INT1

24

P30/INT0

23

VDCE

22

VDD

4513/4514 Group User’s Manual

1-5

6-1

Manual User’s Group 4513/4514

 

4

4

 

3

2

 

8

I/O port

 

 

 

 

 

 

 

 

 

Port P0

 

| [ Portg P1

 

Port P2

 

Port P3

 

Port D

Internal peripheral functions

Timer

Timer 1 (8 bits)

Timer 2 (8 bits)

Timer 3 (8 bits)

Timer 4 (8 bits)

Watchdog timer (16 bits)

A-D converter (10 bits 4 ch)

Serial I/O (8 bits 1)

Voltage comparator

 

System clock generating circuit

(2 circuits)

 

 

 

 

 

XIN–XOUT

 

 

 

Voltage drop detection circuit

4500 Series CPU core

ALU (4 bits)

Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits)

Stack register SK (8 levels) Interrupt stack register SDP (1 level)

Memory

ROM

2048, 4096,6144, 8192 words × 10 bits

RAM

128, 256, 384 words × 4 bits

(4513 DIAGRAM BLOCK

 

DIAGRAM BLOCK

HARDWARE

Group)

 

 

 

 

 

 

 

Manual User’s Group 4513/4514

7-1

 

4

4

3

4

4

I/O port

Port P0

Port P1

Port P2

Port P3

Port P4

Internal peripheral functions

 

 

 

Timer

 

Voltage comparator

 

 

 

 

(2 circuits)

 

 

 

 

 

 

 

Timer 1 (8 bits)

 

 

 

 

 

Timer 2 (8 bits)

 

 

 

 

 

Timer 3 (8 bits)

 

 

 

 

 

Timer 4 (8 bits)

 

 

 

 

 

Watchdog timer

 

 

 

 

 

(16 bits)

 

 

 

 

 

A-D converter

 

4500 Series

 

(10 bits 8 ch)

 

CPU core

 

 

 

 

 

 

ALU (4 bits)

Serial I/O

(8 bits 1)

Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits)

Stack register SK (8 levels) Interrupt stack register SDP (1 level)

4

8

Port P5

Port D

System clock generating circuit

XIN—XOUT

Voltage drop detection circuit

Memory

ROM

6144, 8192 words × 10 bits

RAM

384 words × 4 bits

Group) (4514 DIAGRAM BLOCK

DIAGRAM BLOCK

HARDWARE

HARDWARE

PERFORMANCE OVERVIEW

PERFORMANCE OVERVIEW

 

Parameter

 

Function

 

 

 

 

Number of

 

4513 Group

123

basic instructions

4514 Group

128

Minimum instruction execution time

0.75 μs (at 4.0 MHz oscillation frequency, in high-speed mode)

 

 

 

 

Memory sizes

ROM

M34513M2

2048 words 10 bits

 

 

M34513M4/E4

4096 words 10 bits

 

 

M34513M6

6144 words 10 bits

 

 

M34513M8/E8

8192 words 10 bits

 

 

M34514M6

6144 words 10 bits

 

 

M34514M8/E8

8192 words 10 bits

 

RAM

M34513M2

128 words 4 bits

 

 

M34513M4/E4

256 words 4 bits

 

 

M34513M6

384 words 4 bits

 

 

M34513M8/E8

384 words 4 bits

 

 

M34514M6

384 words 4 bits

 

 

M34514M8/E8

384 words 4 bits

Input/Output

D0–D7

I/O (Input is

Eight independent I/O ports;

ports

 

examined by

ports D6 and D7 are also used as CNTR0 and CNTR1, respectively.

 

skip decision)

 

 

 

 

 

 

 

 

 

P00–P03

I/O

4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both

 

 

 

functions can be switched by software.

 

 

 

 

 

P10–P13

I/O

4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both

 

 

 

functions can be switched by software.

 

P20–P22

Input

3-bit input port; ports P20, P21 and P22 are also used as SCK, SOUT and SIN, respectively.

 

 

 

 

 

P30–P33

I/O

4-bit I/O port (2-bit I/O port for the 4513 Group); ports P30 and P31 are also used as INT0 and

 

 

 

INT1, respectively. The 4513 Group does not have ports P32, P33.

 

P40–P43

I/O

4-bit I/O port; The 4513 Group does not have this port.

 

P50–P53

I/O

4-bit I/O port with a direction register; The 4513 Group does not have this port.

 

CNTR0

I/O

1-bit I/O; CNTR0 pin is also used as port D6.

 

CNTR1

I/O

1-bit I/O; CNTR1 pin is also used as port D7.

 

INT0

Input

1-bit input; INT0 pin is also used as port P30 and equipped with a key-on wakeup function.

 

INT1

Input

1-bit input; INT1 pin is also used as port P31 and equipped with a key-on wakeup function.

Timers

Timer 1

 

8-bit programmable timer with a reload register.

 

Timer 2

 

8-bit programmable timer with a reload register is also used as an event counter.

 

Timer 3

 

8-bit programmable timer with a reload register.

 

Timer 4

 

8-bit programmable timer with a reload register is also used as an event counter.

A-D converter

 

 

10-bit wide, This is equipped with an 8-bit comparator function.

Voltage comparator

 

2 circuits (CMP0, CMP1)

Serial I/O

 

 

8-bit 1

Interrupt

Sources

 

8 (two for external, four for timer, one for A-D, and one for serial I/O)

 

Nesting

 

1 level

Subroutine nesting

 

8 levels

Device structure

 

CMOS silicon gate

Package

4513 Group

32-pin plastic molded SDIP (32P4B)/LQFP(32P6B-A)

 

 

 

 

4514 Group

42-pin plastic molded SSOP (42P2R-A)

 

 

 

Operating temperature range

–20 °C to 85 °C

Supply voltage

 

 

2.0 V to 5.5 V for Mask ROM version, 2.5 V to 5.5 V for One Time PROM version (Refer to the

 

 

 

electrical characteristics because the supply voltage depends on the oscillation frequency.)

Power

Active mode

1.8 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in middlespeed mode, output transis-

dissipation

 

 

tors in the cut-off state)

 

 

3.0 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors

(typical value)

 

 

 

 

in the cut-off state)

 

 

 

 

RAM back-up mode

0.1 μA (at room temperature, VDD = 5 V, output transistors in the cut-off state)

1-8

4513/4514 Group User’s Manual

HARDWARE

PIN DESCRIPTION

PIN DESCRIPTION

 

Pin

Name

Input/Output

 

 

Function

 

 

 

 

 

 

 

 

 

VDD

Power supply

Connected to a plus power supply.

 

 

 

 

 

 

 

 

 

VSS

Ground

Connected to a 0 V power supply.

 

 

 

 

 

 

 

 

 

VDCE

Voltage drop detec-

Input

VDCE pin is used to control the operation/stop of the voltage drop detection circuit.

 

 

 

tion circuit enable

 

When “H” level is input to this pin, the circuit is operating. When “L” level is inpu to

 

 

 

 

 

this pin, the circuit is stopped.

 

 

 

 

 

 

 

 

 

CNVSS

CNVSS

Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.

 

 

 

 

 

 

 

 

 

 

Reset input

 

An N-channel open-drain I/O pin for a system reset. When the watchdog timer

 

RESET

 

I/O

 

 

 

 

causes the system to be reset or system reset is performed by the voltage drop de-

 

 

 

 

 

 

 

 

 

 

tection circuit, the

RESET

pin outputs “L” level.

 

XIN

System clock input

Input

I/O pins of the system clock generating circuit. XIN and XOUT can be connected to

 

 

 

 

 

ceramic resonator. A feedback resistor is built-in between them.

 

XOUT

System clock output

Output

 

 

 

 

 

D0–D7

I/O port D

I/O

Each pin of port D has an independent 1-bit wide I/O function. Each pin has an out-

 

 

 

(Input is examined

 

put latch. For input use, set the latch of the specified bit to “1.” The output structure

 

 

 

by skip decision.)

 

is N-channel open-drain.

 

 

 

 

 

Ports D6 and D7 are also used as CNTR0 and CNTR1, respectively.

 

 

 

 

 

 

 

 

 

P00–P03

I/O port P0

I/O

Each of ports P0 and P1 serves as a 4-bit I/O port, and it can be used as inputs

 

 

 

 

 

when the output latch is set to “1.” The output structure is N-channel open-drain.

 

P10–P13

I/O port P1

I/O

Every pin of the ports has a key-on wakeup function and a pull-up function. Both

 

 

functions can be switched by software.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P20–P22

Input port P2

Input

3-bit input port. Ports P20, P21 and P22 are also used as SCK, SOUT and SIN, re-

 

 

 

 

 

spectively.

 

 

 

 

 

 

 

 

 

P30–P33

I/O port P3

I/O

4-bit I/O port (2-bit I/O port for the 4513 Group). For input use, set the latch of the

 

 

 

 

 

specified bit to “1.” The output structure is N-channel open-drain. Ports P30 and

 

 

 

 

 

P31 are also used as INT0 and INT1, respectively.

 

 

 

 

 

The 4513 Group does not have ports P32, P33.

 

 

 

 

 

 

P40–P43

I/O port P4

I/O

4-bit I/O port. For input use, set the latch of the specified bit to “1.” The output

 

 

 

 

 

structure is N-channel open-drain. Ports P40–P43 are also used as analog input

 

 

 

 

 

pins AIN4–AIN7, respectively.

 

 

 

 

 

The 4513 Group does not have port P4.

 

 

 

 

 

 

P50–P53

I/O port P5

I/O

4-bit I/O port. Each pin has a direction register and an independent 1-bit wide I/O

 

 

 

 

 

function. For input use, set the direction register to “0.” For output use, set the di-

 

 

 

 

 

rection regiser to “1.” The output structure is CMOS.

 

 

 

 

 

The 4513 Group does not have port P5.

 

 

 

 

 

 

AIN0–AIN7

Analog input

Input

Analog input pins for A-D converter. AIN0–AIN3 are also used as voltage compara-

 

 

 

 

 

tor input pins and AIN4–AIN7 are also used as port P4.

 

 

 

 

 

The 4513 Group does not have AIN4–AIN7.

 

 

 

 

 

 

CNTR0

Timer input/output

I/O

CNTR0 pin has the function to input the clock for the timer 2 event counter, and to

 

 

 

 

 

output the timer 1 underflow signal divided by 2.

 

 

 

 

 

CNTR0 pin is also used as port D6.

 

 

 

 

 

 

CNTR1

Timer input/output

I/O

CNTR1 pin has the function to input the clock for the timer 4 event counter, and to

 

 

 

 

 

output the timer 3 underflow signal divided by 2.

 

 

 

 

 

CNTR1 pin is also used as port D7.

 

 

 

 

 

 

INT0, INT1

Interrupt input

Input

INT0, INT1 pins accept external interrupts. They also accept the input signal to re-

 

 

 

 

 

turn the system from the RAM back-up state.

 

 

 

 

 

INT0, INT1 pins are also used as ports P30 and P31, respectively.

 

 

 

 

 

 

SIN

Serial data input

Input

SIN pin is used to input serial data signals by software.

 

 

 

 

 

SIN pin is also used as port P22.

 

 

 

 

 

 

SOUT

Serial data output

Output

SOUT pin is used to output serial data signals by software.

 

 

 

 

 

SOUT pin is also used as port P21.

 

 

 

 

 

 

SCK

Serial I/O clock

I/O

SCK pin is used to input and output synchronous clock signals for serial data trans-

 

 

 

input/output

 

fer by software.

 

 

 

 

 

SCK pin is also used as port P20.

 

 

 

 

 

 

CMP0-

Voltage comparator

Input

CMP0-, CMP0+ pins are used as the voltage comparator input pin when the volt-

 

CMP0+

input

 

age comparator function is selected by software.

 

 

 

 

 

CMP0-, CMP0+ pins are also used as AIN0 and AIN1.

 

 

 

 

 

 

CMP1-

Voltage comparator

Input

CMP1-, CMP1+ pins are used as the voltage comparator input pin when the volt-

 

CMP1+

input

 

age comparator function is selected by software.

 

 

 

 

 

CMP1-, CMP1+ pins are also used as AIN2 and AIN3.

4513/4514 Group User’s Manual

1-9

HARDWARE

PIN DESCRIPTION

MULTIFUNCTION

Pin

Multifunction

 

Pin

Multifunction

 

Pin

Multifunction

 

Pin

Multifunction

D6

CNTR0

 

CNTR0

D6

 

AIN0

CMP0-

 

CMP0-

AIN0

D7

CNTR1

 

CNTR1

D7

 

AIN1

CMP0+

 

CMP0+

AIN1

P20

SCK

 

SCK

P20

 

AIN2

CMP1-

 

CMP1-

AIN2

P21

SOUT

 

SOUT

P21

 

AIN3

CMP1+

 

CMP1+

AIN3

 

 

 

 

 

 

 

 

 

 

 

P22

SIN

 

SIN

P22

 

P40

AIN4

 

AIN4

P40

P30

INT0

 

INT0

P30

 

P41

AIN5

 

AIN5

P41

P31

INT1

 

INT1

P31

 

P42

AIN6

 

AIN6

P42

 

 

 

 

 

 

P43

AIN7

 

AIN7

P43

 

 

 

 

 

 

 

 

 

 

 

Notes 1: Pins except above have just single function.

2:The input of D6, D7, P20–P22, CMP0-, CMP0+, CMP1-, CMP1+ and the input/output of P30, P31, P40–P43 can be used even when CNTR0, CNTR1, SCK, SOUT, SIN, INT0, INT1, and AIN0–AIN7 are selected.

3:The 4513 Group does not have P40/AIN4–P43/AIN7.

CONNECTIONS OF UNUSED PINS

Pin

Connection

XOUT

Open (when using an external clock).

VDCE

Connect to VSS.

D0–D5

Connect to VSS, or set the output latch to

D6/CNTR0

“0” and open.

D7/CNTR1

 

P20/SCK

Connect to VSS.

P21/SOUT

 

P22/SIN

 

P30/INT0

Connect to VSS, or set the output latch to

P31/INT1

“0” and open.

P32, P33

 

P40/AIN4–P43/AIN7

Connect to VSS, or set the output latch to

 

“0” and open.

P50–P53 (Note 1)

When the input mode is selected by soft-

 

ware, pull-up to VDD through a resistor or

 

pull-down to VDD.

 

When selecting the output mode, open.

 

 

AIN0/CMP0-

Connect to VSS.

AIN1/CMP0+

 

AIN2/CMP1-

 

AIN3/CMP1+

 

 

 

P00–P03

Open or connect to VSS (Note 2)

P10–P13

Open or connect to VSS (Note 2)

Notes 1: After system is released from reset, port P5 is in an input mode (direction register FR0 = 00002)

2: When the P00–P03 and P10–P13 are connected to VSS, turn off their pull-up transistors (register PU0i=“0”) and also invalidate the key-on wakeup functions (register K0i=“0”) by software. When these pins are connected to VSS while the key-on wakeup functions are left valid, the system fails to return from RAM back-up state. When these pins are open, turn on their pull-up transistors (register PU0i=“1”) by software, or set the output latch to “0.”

Be sure to select the key-on wakeup functions and the pull-up functions with every two pins. If only one of the two pins for the key-on wakeup function is used, turn on their pull-up transistors by software and also disconnect the other pin. (i = 0, 1, 2, or 3.)

(Note when the output latch is set to “0” and pins are open)

After system is released from reset, port is in a high-impedance state until it is set the output latch to “0” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur while the port is in a high-impedance state.

To set the output latch periodically by software is recommended because value of output latch may change by noise or a program run away (caused by noise).

(Note when connecting to VSS and VDD)

Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise.

1-10

4513/4514 Group User’s Manual

HARDWARE

PIN DESCRIPTION

PORT FUNCTION

Port

 

Pin

Input

Output structure

I/O

Control

Control

Remark

 

Output

unit

instructions

registers

 

 

 

 

 

 

 

 

 

 

 

 

 

Port D

D0–D5

I/O

N-channel open-drain

1

SD, RD

 

 

 

D6/CNTR0

(8)

 

 

SZD

W6

 

 

D7/CNTR1

 

 

 

CLD

 

 

Port P0

P00

–P03

I/O

N-channel open-drain

4

OP0A

PU0, K0

Built-in programmable pull-up

 

 

 

(4)

 

 

IAP0

 

functions

 

 

 

 

 

 

 

 

Key-on wakeup functions

 

 

 

 

 

 

 

 

(programmable)

 

 

 

 

 

 

 

 

 

Port P1

P10

–P13

I/O

N-channel open-drain

4

OP1A

PU0, K0

Built-in programmable pull-up

 

 

 

(4)

 

 

IAP1

 

functions

 

 

 

 

 

 

 

 

Key-on wakeup functions

 

 

 

 

 

 

 

 

(programmable)

 

 

 

 

 

 

 

 

 

Port P2

P20

/SCK

Input

 

3

IAP2

J1

 

 

P21

/SOUT

(3)

 

 

 

 

 

 

P22

/SIN

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Port P3

P30

/INT0

I/O

N-channel open-drain

4

OP3A

I1, I2

Built-in key-on wakeup

(Note 1)

P31

/INT1

(4)

 

 

IAP3

 

function

 

P32

, P33

 

 

 

 

 

(P30/INT0, P31/INT1)

 

 

 

 

 

 

 

 

 

Port P4

P40

/AIN4

I/O

N-channel open-drain

4

OP4A

Q2

 

(Note 2)

–P43/AIN7

(4)

 

 

IAP4

 

 

Port P5

P50

–P53

I/O

CMOS

4

OP5A

FR0

 

(Note 2)

 

 

(4)

 

 

IAP5

 

 

Notes 1: The 4513 Group does not have P32 and P33. 2: The 4513 Group does not have these ports.

DEFINITION OF CLOCK AND CYCLE

System clock

The system clock is the basic clock for controlling this product. The system clock is selected by the bit 3 of the clock control register MR.

Table Selection of system clock

Register MR

System clock

MR3

 

 

 

0

f(XIN)

 

 

1

f(XIN)/2

Note: f(XIN)/2 is selected after system is released from reset.

Instruction clock

The instruction clock is a signal derived by dividing the system clock by 3. The one instruction clock cycle generates the one machine cycle.

Machine cycle

The machine cycle is the standard cycle required to execute the instruction.

4513/4514 Group User’s Manual

1-11

HARDWARE

PIN DESCRIPTION

PORT BLOCK DIAGRAMS

K00

Key-on wakeup input

IAP0 instruction

Register A

Ai D

OP0A instructionT Q

K01

Key-on wakeup input

IAP0 instruction

Register A

Ai D

OP0A instructionT Q

K02

Key-on wakeup input

IAP1 instruction

Register A

Ai D

OP1A instructionT Q

K03

Key-on wakeup input

IAP1 instruction

Register A

Ai D

OP1A instructionT Q

Pull-up transistor

PU00

P00,P01

Pull-up transistor

PU01

P02,P03

Pull-up transistor

PU02

P10,P11

Pull-up transistor

PU03

P12,P13

This symbol represents a parasitic diode on the port.

i represents 0, 1, 2, or 3.

1-12

4513/4514 Group User’s Manual

HARDWARE

PIN DESCRIPTION

PORT BLOCK DIAGRAMS (continued)

IAP2 instruction

Register A

Synchronous clock input for serial transfer

J11

P20/SCK

0

Synchronous clock output for serial transfer

 

 

1

 

J10

 

 

 

 

 

 

 

IAP2 instruction

Register A

J11

P21/SOUT

0

 

Serial data output1

Serial data input

IAP2 instruction

Register A P22/SIN

Key-on wakeup input

External interrupt circuit

IAP3 instruction

Register A P30/INT0,P31/INT1

Ai D

OP3A instructionT Q

IAP3 instruction

Register A P32,P33

Ai

D

 

 

 

OP3A instruction

T Q

This symbol represents a parasitic diode on the port.

Applied potential to ports P20—P2 2 must be VDD.

i represents 0, 1, 2, or 3.

The 4513 Group does not have ports P32, P33.

4513/4514 Group User’s Manual

1-13

HARDWARE

PIN DESCRIPTION

PORT BLOCK DIAGRAMS (continued)

Q1

Decoder

Analog input AIN0/CMP0-

Q30

 

-

 

+

 

CMP0

Q32

Q1

 

 

 

Decoder

Analog input AIN1/CMP0+

Q1

Decoder

Analog input AIN2/CMP1-

 

 

 

-

 

Q31

+

 

CMP1

Q33

Q1

Decoder

Analog input AIN3/CMP1+

IAP4 instruction

Register A P40/AIN4–P43/AIN7

 

Ai

 

D

 

 

Q1

OP4A instruction

T Q

 

 

Decoder

 

 

 

 

 

 

Analog input

This symbol represents a parasitic diode on the port.

• i represents 0, 1, 2, or 3.

• The 4513 Group does not have port P4.

1-14

4513/4514 Group User’s Manual

HARDWARE

PIN DESCRIPTION

PORT BLOCK DIAGRAMS (continued)

Direction register FR0i

Ai

D Q

 

P50–P53

OP5A instruction

T

 

 

Register A

 

 

 

 

IAP5 instruction

 

Register Y

Decoder

Skip decision

 

(SZD instruction)

 

 

CLD instruction

D0–D5

 

 

S

SD instruction

 

 

 

R

Q

RD instruction

 

 

 

 

 

 

 

 

 

 

Skip decision (SZD instruction)

 

 

 

 

 

 

 

 

 

Clock input for timer 2 event count

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register Y

 

 

Decoder

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLD instruction

 

 

 

 

 

 

SD instruction

 

 

 

 

 

 

 

S

 

W60

 

D6/CNTR0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RD instruction

 

 

 

 

 

 

 

R

Q

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Timer 1 underflow signal divided by 2 or

 

 

1

 

 

 

signal of AND operation between

 

 

 

 

 

 

timer 1 underflow signal divided by 2 and

 

 

 

 

 

 

timer 2 underflow signal divided by 2

 

 

 

 

 

 

 

 

 

 

 

Skip decision (SZD instruction)

 

 

 

 

 

 

 

 

Clock input for timer 4 event count

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register Y

 

 

 

Decoder

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLD instruction

 

 

 

 

 

 

SD instruction

 

 

 

 

 

 

 

S

 

W62

 

D7/CNTR1

 

 

 

 

 

 

 

R

 

 

 

 

 

 

 

 

 

 

 

RD instruction

 

 

 

 

 

 

 

Q

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Timer 3 underflow signal divided by 2 or

 

 

1

 

 

 

signal of AND operation between

 

 

 

 

 

 

timer 3 underflow signal divided by 2 and

 

 

 

 

 

 

timer 4 underflow signal divided by 2

 

 

 

 

 

This symbol represents a parasitic diode on the port.

 

Applied potential to ports D0–D7 must be 12 V.

i represents 0, 1, 2, or 3.

The 4513 Group does not have port P5.

4513/4514 Group User’s Manual

1-15

HARDWARE

PIN DESCRIPTION

I12

Falling

One-sided edge

I11

 

0

detection circuit

0

 

 

External 0

P30/INT0

 

EXF0

 

interrupt

1

 

1

 

 

 

 

 

Rising

Both edges

detection circuit

 

Wakeup

Skip

SNZI0

I22

Falling

One-sided edge

I21

 

0

detection circuit

0

 

 

External 1

P31/INT1

 

EXF1

 

interrupt

1

 

1

 

 

 

 

 

Rising

Both edges

detection circuit

 

Wakeup

Skip

SNZI1

This symbol represents a parasitic diode on the port.

External interrupt circuit structure

1-16

4513/4514 Group User’s Manual

HARDWARE

FUNCTION BLOCK OPERATIONS

FUNCTION BLOCK OPERATIONS

CPU

(1) Arithmetic logic unit (ALU)

The arithmetic logic unit ALU performs 4-bit arithmetic such as 4- bit data addition, comparison, AND operation, OR operation, and bit manipulation.

(2) Register A and carry flag

Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation.

Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1).

It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2).

Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction.

(3) Registers B and E

Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A.

Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3).

(4) Register D

Register D is a 3-bit register.

It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4).

<Carry> (CY)

(M(DP))

Addition ALU

(A)

<Result>

Fig. 1 AMC instruction execution example

<Set>

<Clear>

SC instruction

RC instruction

CY A3 A2 A1 A0

<Rotation> RAR instruction

A0

 

CY A3 A2 A1

 

 

 

Fig. 2 RAR instruction execution example

 

Register B

TAB instruction

 

 

Register A

 

B3

B2

B1

B0

 

 

 

 

A3

A2

A1

A0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TEAB instruction

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register E

E7

E6

E5

E4

E3

E2

E1

E0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TABE instruction

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B3

B2

B1

B0

 

 

 

A3

A2

A1

A0

 

 

 

 

 

 

Register B

TBA instruction

 

 

Register A

Fig. 3 Registers A, B and register E

TABP p instruction

 

ROM

 

 

 

 

Specifying address

8

4

0

 

 

 

 

PCH

 

PCL

 

Low-order 4bits

 

 

 

Register A (4)

p6 p5 p4 p3 p2 p1 p0

DR2 DR1DR0 A3 A2 A1 A0

 

 

 

 

 

 

 

 

Middle-order 4 bits

Immediate field

The contents of

The contents of

 

 

Register B (4)

 

 

 

value p

register D

register A

 

 

 

Fig. 4 TABP p instruction execution example

4513/4514 Group User’s Manual

1-17

HARDWARE

FUNCTION BLOCK OPERATIONS

(5) Stack registers (SKS) and stack pointer (SP)

Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when;

branching to an interrupt service routine (referred to as an interrupt service routine),

performing a subroutine call, or

executing the table reference instruction (TABP p).

Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded.

The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction.

Figure 5 shows the stack registers (SKs) structure.

Figure 6 shows the example of operation at subroutine call.

(6) Interrupt stack register (SDP)

Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine.

Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction.

(7) Skip flag

Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained.

Program counter (PC)

 

 

 

 

 

 

Executing BM

 

 

Executing RT

 

instruction

 

 

instruction

 

 

 

 

 

 

 

 

SK0

 

(SP) = 0

 

 

 

 

 

(SP) = 1

 

 

SK1

 

 

 

 

 

 

(SP) = 2

 

 

SK2

 

 

 

 

 

 

(SP) = 3

 

 

SK3

 

 

 

SK4

 

(SP) = 4

 

 

SK5

 

(SP) = 5

 

 

SK6

 

(SP) = 6

 

 

 

 

 

(SP) = 7

 

 

SK7

 

 

 

 

 

 

 

Stack pointer (SP) points “7” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed.

Fig. 5 Stack registers (SKs) structure

 

 

(SP) 0

 

 

(SK0) 000116

 

 

(PC) SUB1

Main program

 

 

Subroutine

 

 

 

 

Address

 

 

SUB1 :

000016

NOP

 

 

NOP

000116

BM SUB1

 

 

·

 

 

·

000216

NOP

 

 

·

 

 

RT

 

 

 

 

 

(PC) (SK0) (SP) 7

Note : Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction.

Fig. 6 Example of operation at subroutine call

1-18

4513/4514 Group User’s Manual

HARDWARE

FUNCTION BLOCK OPERATIONS

(8) Program counter (PC)

Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed.

Program counter consists of PCH (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7).

Make sure that the PCH does not specify after the last page of the built-in ROM.

(9) Data pointer (DP)

Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 8).

Register Y is also used to specify the port D bit position.

When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9).

Program counter

p6 p5 p4 p3 p2 p1 p0a6 a5 a4 a3 a2 a1 a0

PCH

PCL

Specifying page

Specifying address

Fig. 7 Program counter (PC) structure

Data pointer (DP)

Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0

Register Y (4) Specifying

RAM digit

Register X (4) Specifying RAM file

Register Z (2) Specifying RAM file group

Fig. 8 Data pointer (DP) structure

Specifying bit position

 

 

 

 

 

 

 

 

 

Set

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D7 D6 D5 D4 D0

0

1

0

1

 

 

 

 

 

1

 

 

 

 

 

Register Y (4)

Port D output latch

Fig. 9 SD instruction execution example

4513/4514 Group User’s Manual

1-19

HARDWARE

FUNCTION BLOCK OPERATIONS

PROGRAM MEMOY (ROM)

The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34514M8/E8.

Table 1 ROM size and pages

Product

ROM size

Pages

( 10 bits)

 

 

 

 

 

M34513M2

2048 words

16 (0 to 15)

M34513M4/E4

4096 words

32 (0 to 31)

M34513M6

6144 words

48 (0 to 47)

M34513M8/E8

8192 words

64 (0 to 63)

M34514M6

6144 words

48 (0 to 47)

M34514M8/E8

8192 words

64 (0 to 63)

A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address.

Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2.

ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction.

9

8

7

6

5

4

3

2

1

0

000016

 

 

 

 

 

 

 

 

 

 

Page 0

007F16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

008016

 

 

Interrupt address page

 

 

Page 1

00FF16

 

 

 

 

 

 

 

 

 

 

 

 

 

010016

 

Subroutine special page

 

Page 2

017F16

 

 

 

 

 

 

 

 

 

 

 

018016

 

 

 

 

 

 

 

 

 

 

Page 3

 

 

 

 

 

 

 

 

 

 

 

0FFF16

Page 31

1FFF16

Page 63

Fig. 10 ROM map of M34514M8/E8

9 8 7 6 5 4 3 2 1 0

008016 External 0 interrupt address

008216

External 1 interrupt address

008416

Timer 1 interrupt address

008616

Timer 2 interrupt address

008816

Timer 3 interrupt address

008A16

Timer 4 interrupt address

008C16

A-D interrupt address

008E16

Serial I/O interrupt address

00FF16

Fig. 11 Page 1 (addresses 008016 to 00FF16) structure

1-20

4513/4514 Group User’s Manual

HARDWARE

FUNCTION BLOCK OPERATIONS

DATA MEMORY (RAM)

1 word of RAM is composed of 4 bits, but 1-bit manipulation (with

the SB j, RB j, and SZB j instructions) is enabled for the entire

memory area. A RAM address is specified by a data pointer. The

data pointer consists of registers Z, X, and Y. Set a value to the

data pointer certainly when executing an instruction to access

RAM.

Table 2 shows the RAM size. Figure 12 shows the RAM map.

Table 2 RAM size

Product

RAM size

M34513M2

128 words 4 bits (512 bits)

 

 

M34513M4/E4

256 words 4 bits (1024 bits)

 

 

M34513M6

384 words 4 bits (1536 bits)

M34513M8/E8

384 words 4 bits (1536 bits)

 

 

M34514M6

384 words 4 bits (1536 bits)

 

 

M34514M8/E8

384 words 4 bits (1536 bits)

 

 

RAM 384 words 4 bits (1536 bits)

 

 

Register Z

 

 

 

 

0

 

 

 

 

 

1

 

 

 

 

 

Register X

0 1

2

3

4

5

6

7

15 0 1

2

3

4

5

6

7

 

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Y

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M34513M6

 

14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M34513M8/E8

 

15

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M34514M6

Z=0, X=0 to 15

 

 

 

 

 

 

 

 

 

 

 

 

 

384 words

M34514M8/E8

 

 

 

 

 

 

 

 

 

 

 

 

 

Z=1, X=0 to 7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

M34513M4/E4

Z=0, X=0 to 15

 

 

 

256 words

 

 

 

 

 

 

 

128 words

M34513M2

Z=0, X=0 to 7

 

 

 

Fig. 12 RAM map

4513/4514 Group User’s Manual

1-21

HARDWARE

FUNCTION BLOCK OPERATIONS

INTERRUPT FUNCTION

The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied.

An interrupt activated condition is satisfied (request flag = “1”)

Interrupt enable bit is enabled (“1”)

Interrupt enable flag is enabled (INTE = “1”)

Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.)

(1) Interrupt enable flag (INTE)

The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed.

Table 3 Interrupt sources

Priority

Interrupt name

Activated condition

Interrupt

level

address

 

 

 

 

 

 

1

External 0 interrupt

Level change of

Address 0

 

 

INT0 pin

in page 1

 

 

 

 

2

External 1 interrupt

Level change of

Address 2

 

 

INT1 pin

in page 1

 

 

 

 

3

Timer 1 interrupt

Timer 1 underflow

Address 4

 

 

 

in page 1

 

 

 

 

4

Timer 2 interrupt

Timer 2 underflow

Address 6

 

 

 

in page 1

5

Timer 3 interrupt

Timer 3 underflow

Address 8

 

 

 

in page 1

 

 

 

 

6

Timer 4 interrupt

Timer 4 underflow

Address A

 

 

 

in page 1

 

 

 

 

7

A-D interrupt

Completion of

Address C

 

 

A-D conversion

in page 1

 

 

 

 

8

Serial I/O interrupt

Completion of

Address E

 

 

serial I/O transfer

in page 1

 

 

 

 

(2) Interrupt enable bit

Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction.

Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction.

Table 5 shows the interrupt enable bit function.

(3) Interrupt request flag

When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to “1.” Each interrupt request flag is cleared to “0” when either;

an interrupt occurs, or

the next instruction is skipped with a skip instruction.

Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied.

Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set.

If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3.

Table 4 Interrupt request flag, interrupt enable bit and skip in-

struction

Interrupt name

Request flag

Skip instruction

Enable bit

External 0 interrupt

EXF0

SNZ0

V10

 

 

 

 

External 1 interrupt

EXF1

SNZ1

V11

 

 

 

 

Timer 1 interrupt

T1F

SNZT1

V12

 

 

 

 

Timer 2 interrupt

T2F

SNZT2

V13

 

 

 

 

Timer 3 interrupt

T3F

SNZT3

V20

Timer 4 interrupt

T4F

SNZT4

V21

 

 

 

 

A-D interrupt

ADF

SNZAD

V22

 

 

 

 

Serial I/O interrupt

SIOF

SNZSI

V23

 

 

 

 

Table 5 Interrupt enable bit function

Interrupt enable bit

Occurrence of interrupt

Skip instruction

1

Enabled

Invalid

 

 

 

0

Disabled

Valid

 

 

 

1-22

4513/4514 Group User’s Manual

HARDWARE

FUNCTION BLOCK OPERATIONS

(4) Internal state during an interrupt

The internal state of the microcomputer during an interrupt is as follows (Figure 14).

• Program counter (PC)

An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK).

• Interrupt enable flag (INTE)

INTE flag is cleared to “0” so that interrupts are disabled.

• Interrupt request flag

Only the request flag for the current interrupt source is cleared to “0.”

• Data pointer, carry flag, skip flag, registers A and B

The contents of these registers and flags are stored automatically in the interrupt stack register (SDP).

(5) Interrupt processing

When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address.

Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13)

Main routine

Interrupt service routine

Interrupt

occurs

EI

RTI

Interrupt is enabled

: Interrupt enabled state

: Interrupt disabled state

• Program counter (PC)

 

 

 

..............................................................

 

 

Each interrupt address

• Stack register (SK)

 

 

 

 

The address of main routine to be

....................................................................................................

 

executed when returning

 

• Interrupt enable flag (INTE)

 

 

 

..................................................................

 

 

0 (Interrupt disabled)

• Interrupt request flag (only the flag for the current interrupt

source) ...................................................................................

 

 

 

0

• Data pointer, carry flag, registers A and B, skip flag

 

........ Stored in the interrupt stack register (SDP) automatically

Fig. 14 Internal state when interrupt occurs

 

INT0 pin

 

 

 

Address 0

 

 

 

 

(LH or

EXF0

V10

 

in page 1

HL input)

 

 

INT1 pin

 

 

 

Address 2

 

 

 

 

(LH or

EXF1

V11

 

in page 1

 

 

H L input)

 

 

 

 

Timer 1

 

 

 

Address 4

underflow

T1F

V12

 

in page 1

 

 

 

Timer 2

 

 

 

Address 6

underflow

T2F

V13

 

in page 1

 

 

 

Timer 3

 

 

 

Address 8

underflow

T3F

V20

 

in page 1

 

 

 

Timer 4

 

 

 

Address A

underflow

T4F

V21

 

in page 1

 

 

 

Completion of

 

 

 

Address C

A-D conversion

ADF

V22

 

in page 1

 

 

 

Completion of

 

 

 

Address E

serial I/O transfer

SIOF

V23

INTE

in page 1

 

 

Activated

Request flag

Enable

Enable

 

condition

(state retained)

bit

flag

 

Fig. 15 Interrupt system diagram

Fig. 13 Program example of interrupt processing

4513/4514 Group User’s Manual

1-23

HARDWARE

FUNCTION BLOCK OPERATIONS

(6) Interrupt control registers

Interrupt control register V1

Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A.

Table 6 Interrupt control registers

Interrupt control register V2

Interrupt enable bits of timer 3, timer 4, A-D and serial I/O are assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A.

 

Interrupt control register V1

 

at reset : 00002

at RAM back-up : 00002

R/W

 

 

 

 

 

 

 

V13

Timer 2 interrupt enable bit

0

 

Interrupt disabled (SNZT2 instruction is valid)

 

1

 

Interrupt enabled (SNZT2 instruction is invalid)

 

 

 

 

 

V12

Timer 1 interrupt enable bit

0

 

Interrupt disabled (SNZT1 instruction is valid)

 

1

 

Interrupt enabled (SNZT1 instruction is invalid)

 

 

 

 

 

V11

External 1 interrupt enable bit

0

 

Interrupt disabled (SNZ1 instruction is valid)

 

1

 

Interrupt enabled (SNZ1 instruction is invalid)

 

 

 

 

 

V10

External 0 interrupt enable bit

0

 

Interrupt disabled (SNZ0 instruction is valid)

 

1

 

Interrupt enabled (SNZ0 instruction is invalid)

 

 

 

 

 

 

Interrupt control register V2

 

at reset : 00002

at RAM back-up : 00002

R/W

 

 

 

 

 

 

 

V23

Serial I/O interrupt enable bit

0

 

Interrupt disabled (SNZSI instruction is valid)

 

1

 

Interrupt enabled (SNZSI instruction is invalid)

 

 

 

 

 

V22

A-D interrupt enable bit

0

 

Interrupt disabled (SNZAD instruction is valid)

 

1

 

Interrupt enabled (SNZAD instruction is invalid)

 

 

 

 

 

V21

Timer 4 interrupt enable bit

0

 

Interrupt disabled (SNZT4 instruction is valid)

 

1

 

Interrupt enabled (SNZT4 instruction is invalid)

 

 

 

 

 

V20

Timer 3 interrupt enable bit

0

 

Interrupt disabled (SNZT3 instruction is valid)

 

1

 

Interrupt enabled (SNZT3 instruction is invalid)

 

 

 

 

 

Note: “R” represents read enabled, and “W” represents write enabled.

1-24

4513/4514 Group User’s Manual

HARDWARE

FUNCTION BLOCK OPERATIONS

(7) Interrupt sequence

Interrupts only occur when the respective INTE flag, interrupt enable bits (V10–V13 and V20–V23), and interrupt request flag are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt oc-

curs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16).

When an interrupt request flag is set after its interrupt is enabled (Note 1)

f (XIN) (middle-speed mode)

f (XIN) (high-speed mode)

 

 

 

 

 

1 machine cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3

 

 

 

 

T1 T2 T3

 

 

System clock

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt enable

 

 

 

EI instruction

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt disabled state

 

 

 

 

 

 

execution cycle

 

 

 

 

 

flag (INTE)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt enabled state

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INT0, INT1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Retaining

level of system

 

External

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

clock for

4 periods or more

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

is necessary.

 

interrupt

EXF0, EXF1

 

Interrupt activated

 

 

Timer 1,

condition is satisfied.

 

 

 

 

 

Timer 2,

T1F, T2F, T3F,

 

 

Timer 3,

 

 

T4F, ADF,SIOF

 

 

Timer 4,

 

 

 

 

 

A-D, and

 

 

 

Serial I/O

Flag cleared

 

The program starts from

interrupts

 

 

 

the interrupt address.

 

 

 

 

2 to 3 machine cycles

 

 

 

(Notes 2, 3)

 

 

Notes 1: The 4513/4514 Group operates in the middle-speed mode after system is released from reset. 2: The address is stacked to the last cycle.

3: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.

Fig. 16 Interrupt sequence

4513/4514 Group User’s Manual

1-25

HARDWARE

FUNCTION BLOCK OPERATIONS

EXTERNAL INTERRUPTS

The 4513/4514 Group has two external interrupts (external 0 and external 1). An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection).

The external interrupts can be controlled with the interrupt control registers I1 and I2.

Table 7 External interrupt activated conditions

Name

Input pin

Activated condition

Valid waveform

selection bit

 

 

 

 

 

 

 

External 0 interrupt

P30/INT0

When the next waveform is input to P30/INT0 pin

I11

 

 

• Falling waveform (“H”“L”)

I12

 

 

• Rising waveform (“L”“H”)

 

 

 

• Both rising and falling waveforms

 

 

 

 

 

External 1 interrupt

P31/INT1

When the next waveform is input to P31/INT1 pin

I21

 

 

I22

 

 

• Falling waveform (“H” “L”)

 

 

 

• Rising waveform (“L”“H”)

 

 

 

• Both rising and falling waveforms

 

 

 

 

 

I12

Falling

One-sided edge

I11

 

0

detection circuit

0

 

 

External 0

P30/INT0

 

EXF0

 

interrupt

1

 

1

 

 

 

 

 

Rising

Both edges

detection circuit

 

Wakeup

Skip

SNZI0

I22

Falling

One-sided edge

I21

 

0

detection circuit

0

 

 

External 1

P31/INT1

 

EXF1

 

interrupt

1

 

1

 

 

 

 

 

Rising

Both edges

detection circuit

 

Wakeup

Skip

SNZI1

This symbol represents a parasitic diode on the port.

Fig. 17 External interrupt circuit structure

1-26

4513/4514 Group User’s Manual

HARDWARE

FUNCTION BLOCK OPERATIONS

(1) External 0 interrupt request flag (EXF0)

External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to P30/INT0 pin.

The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16).

The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction.

The P30/INT0 pin need not be selected the external interrupt input INT0 function or the normal I/O port P30 function. However, the EXF0 flag is set to “1” when a valid waveform is input even if it is used as an I/O port P30.

• External 0 interrupt activated condition

External 0 interrupt activated condition is satisfied when a valid waveform is input to P30/INT0 pin.

The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows.

Select the valid waveform with the bits 1 and 2 of register I1.

Clear the EXF0 flag to “0” with the SNZ0 instruction.

Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction.

Set both the external 0 interrupt enable bit (V10) and the INTE flag to “1.”

The external 0 interrupt is now enabled. Now when a valid waveform is input to the P30/INT0 pin, the EXF0 flag is set to “1” and the external 0 interrupt occurs.

(2) External 1 interrupt request flag (EXF1)

External 1 interrupt request flag (EXF1) is set to “1” when a valid waveform is input to P31/INT1 pin.

The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16).

The state of EXF1 flag can be examined with the skip instruction (SNZ1). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF1 flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with the skip instruction.

The P31/INT1 pin need not be selected the external interrupt input INT1 function or the normal I/O port P31 function. However, the EXF1 flag is set to “1” when a valid waveform is input even if it is used as an I/O port P31.

• External 1 interrupt activated condition

External 1 interrupt activated condition is satisfied when a valid waveform is input to P31/INT1 pin.

The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 1 interrupt is as follows.

Select the valid waveform with the bits 1 and 2 of register I2.

Clear the EXF1 flag to “0” with the SNZ1 instruction.

Set the NOP instruction for the case when a skip is performed with the SNZ1 instruction.

Set both the external 1 interrupt enable bit (V11) and the INTE flag to “1.”

The external 1 interrupt is now enabled. Now when a valid waveform is input to the P31/INT1 pin, the EXF1 flag is set to “1” and the external 1 interrupt occurs.

4513/4514 Group User’s Manual

1-27

HARDWARE

FUNCTION BLOCK OPERATIONS

(3) External interrupt control registers

• Interrupt control register I1

Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A.

Table 8 External interrupt control registers

• Interrupt control register I2

Register I2 controls the valid waveform for the external 1 interrupt. Set the contents of this register through register A with the TI2A instruction. The TAI2 instruction can be used to transfer the contents of register I2 to register A.

 

Interrupt control register I1

 

at reset : 00002

 

at RAM back-up : state retained

R/W

 

 

 

 

 

 

 

 

I13

Not used

0

 

This bit has no function, but read/write is enabled.

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

Falling waveform (“L” level of INT0 pin is recognized with the SNZI0

 

Interrupt valid waveform for INT0 pin/

 

instruction)/“L” level

 

 

I12

 

 

 

 

return level selection bit (Note 2)

 

 

 

 

 

 

1

 

Rising waveform (“H” level of INT0 pin is recognized with the SNZI0

 

 

 

 

 

instruction)/“H” level

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I11

INT0 pin edge detection circuit control bit

0

 

One-sided edge detected

 

 

 

 

 

 

 

1

 

Both edges detected

 

 

 

 

 

I10

INT0 pin

0

 

Disabled

 

 

timer 1 control enable bit

1

 

Enabled

 

 

 

 

 

 

 

Interrupt control register I2

 

at reset : 00002

 

at RAM back-up : state retained

R/W

 

 

 

 

 

 

 

 

I23

Not used

0

 

This bit has no function, but read/write is enabled.

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

0

 

Falling waveform (“L” level of INT1 pin is recognized with the SNZI1

 

Interrupt valid waveform for INT1 pin/

 

instruction)/“L” level

 

 

I22

 

 

 

 

return level selection bit (Note 3)

1

 

Rising waveform (“H” level of INT1 pin is recognized with the SNZI1

 

 

 

 

 

instruction)/“H” level

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I21

INT1 pin edge detection circuit control bit

0

 

One-sided edge detected

 

 

 

 

 

 

 

1

 

Both edges detected

 

 

 

 

 

 

 

 

 

 

 

 

I20

INT1 pin

0

 

Disabled

 

 

 

 

 

 

 

 

 

timer 3 control enable bit

1

 

Enabled

 

 

 

 

 

 

Notes 1: “R” represents read enabled, and “W” represents write enabled.

2:When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.

3:When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.

1-28

4513/4514 Group User’s Manual

HARDWARE

FUNCTION BLOCK OPERATIONS

TIMERS

The 4513/4514 Group has the programmable timers.

Programmable timer

The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function).

Fixed dividing frequency timer

The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to “1” after every n count of a count pulse.

 

FF16

 

 

 

 

n : Counter initial value

 

 

 

 

Count starts

Reload

Reload

 

 

n

 

 

 

The contents of counter

1st underflow

 

2nd underflow

 

 

 

 

 

0016

 

 

 

 

 

 

Time

 

 

n+1 count

 

n+1 count

Timer

interrupt

“1”

 

 

request flag

“0”

 

 

An interrupt occurs or

a skip instruction is executed.

Fig. 18 Auto-reload function

4513/4514 Group User’s Manual

1-29

HARDWARE

FUNCTION BLOCK OPERATIONS

The 4513/4514 Group timer consists of the following circuits.

Prescaler : frequency divider

Timer 1 : 8-bit programmable timer

Timer 2 : 8-bit programmable timer

Timer 3 : 8-bit programmable timer

Timer 4 : 8-bit programmable timer

(Timers 1 to 4 have the interrupt function, respectively)

16-bit timer

Prescaler and timers 1 to 4 can be controlled with the timer control registers W1 to W6. The 16-bit timer is a free counter which is not controlled with the control register.

Each function is described below.

Table 9 Function related timers

Circuit

Structure

Count source

Frequency

Use of output signal

Control

dividing ratio

register

 

 

 

 

Prescaler

Frequency divider

• Instruction clock

4, 16

• Timer 1, 2, 3 and 4 count sources

W1

Timer 1

8-bit programmable

• Prescaler output (ORCLK)

1 to 256

• Timer 2 count source

W1

 

binary down counter

 

 

• CNTR0 output

W6

 

(link to P30/INT0 input)

 

 

• Timer 1 interrupt

 

 

 

 

 

 

 

Timer 2

8-bit programmable

• Timer 1 underflow

1 to 256

• Timer 3 count source

W2

 

binary down counter

• Prescaler output (ORCLK)

 

• Timer 2 interrupt

W6

 

 

• CNTR0 input

 

• CNTR0 output

 

 

 

• 16-bit timer underflow

 

 

 

 

 

 

 

 

 

Timer 3

8-bit programmable

• Timer 2 underflow

1 to 256

• Timer 4 count source

W3

 

binary down counter

• Prescaler output (ORCLK)

 

• Timer 3 interrupt

W6

 

(link to P31/INT1 input)

 

 

• CNTR1 output

 

 

 

 

 

 

 

Timer 4

8-bit programmable

• Timer 3 underflow

1 to 256

• Timer 4 interrupt

W4

 

binary down counter

• Prescaler output (ORCLK)

 

• CNTR1 output

W6

 

 

• CNTR1 input

 

 

 

 

 

 

 

 

 

16-bit timer

16-bit fixed dividing

• Instruction clock

65536

• Watchdog timer

 

 

frequency

 

 

(The 15th bit is counted twice)

 

 

 

 

 

• Timer 2 count source

 

 

 

 

 

(16-bit timer underflow)

 

1-30

4513/4514 Group User’s Manual

Renesas 4514, 4513 User Manual
(TAB4)
Instruction clock

HARDWARE

FUNCTION BLOCK OPERATIONS

 

 

 

Instruction clock

 

Prescaler

 

 

 

 

W13

 

 

 

 

 

W12

 

 

 

 

 

 

Divistion circuit

MR3

 

 

0

1/4

0

(divided by 2)

 

 

 

1

Internal clock

 

 

 

 

 

 

 

 

generating circuit

 

 

 

XIN

 

1

1/16

1

0 (divided by 3)

 

 

 

 

 

I12

 

I11

ORCLK

 

 

Falling

One-sided edge

 

 

 

 

0

(Note 1)

 

 

 

0

detection circuit

W10

P30/INT0

 

 

S Q

1

Both edges

 

1

 

 

1

 

0

 

 

 

 

 

 

Rising

detection circuit

 

 

 

I10

R

 

 

 

 

 

 

 

 

W11 (Note 3)

 

 

 

 

 

 

0

 

Timer 1 (8)

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

Reload register R1 (8)

 

 

 

 

T1AB

(TR1AB)

T1AB

 

 

 

(TAB1)

Register B Register A

 

 

 

Timer 1 underflow signal

 

 

W21,W20

 

 

 

 

 

00

W23(Note 3)

 

 

 

 

 

 

 

 

 

 

01

0

 

Timer 2 (8)

 

 

 

1

 

 

 

 

 

 

 

 

 

 

10 Not available

 

 

 

 

 

11

 

Reload register R2 (8)

 

 

 

 

 

(T2AB)

 

 

 

 

(TAB2)

Register B Register A

 

 

I22

 

I21

Timer 2 underflow signal

 

 

Falling

One-sided edge

 

 

0

(Note 2)

 

 

 

0

detection circuit

W32

P31/INT1

 

 

S Q

1

Both edges

 

1

 

 

1

 

0

 

 

Rising

detection circuit

 

 

 

I20

R

 

 

 

W31,W30

 

 

 

 

 

 

 

 

00

W33(Note 3)

 

 

 

 

 

01

0

 

Timer 3 (8)

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

10Not available

 

 

 

 

 

11Not available

Reload register R3 (8)

 

 

 

 

 

 

 

 

T3AB

(TR3AB)

T3AB

 

 

 

(TAB3)

Register B Register A

 

 

W41,W40

Timer 3 underflow signal

 

 

 

 

 

 

 

00

W43(Note 3)

 

 

01 0

Timer 4 (8)

1

10Not available

11Not available

Reload register R4 (8)

(T4AB)

Register B Register A

Timer 1

T1F

interrupt

T2F Timer 2

interrupt

T3F Timer 3

interrupt

T4F Timer 4

interrupt

Data is set automatically from each reload register when timer 1, 2, 3, or 4 underflows (auto-reload function)

Notes 1: Timer 1 count start synchronous circuit is set by the valid edge of P30/INT0 pin selected by bits 1 (I11) and 2 (I12) of register I1.

2:Timer 3 count start synchronous circuit is set by the valid edge of P31/INT1 pin selected by bits 1 (I21) and 2 (I22) of register I2.

3:Count source is stopped by clearing to “0.”

16-bit timer (WDT)

1 - - - - - - - - - - - 15 16

System reset

WRST instruction

S

WDF1 WDF2

Reset signal

WEF Q

 

R

 

Fig. 19 Timers structure

4513/4514 Group User’s Manual

1-31

HARDWARE

FUNCTION BLOCK OPERATIONS

Table 10 Timer control registers

 

Timer control register W1

 

 

at reset : 00002

 

at RAM back-up : 00002

R/W

 

 

 

 

 

 

 

 

W13

Prescaler control bit

0

 

Stop (state initialized)

 

1

 

Operating

 

 

 

 

 

 

 

W12

Prescaler dividing ratio selection bit

0

 

Instruction clock divided by 4

 

1

 

Instruction clock divided by 16

 

 

 

 

 

W11

Timer 1 control bit

0

 

Stop (state retained)

 

 

1

 

Operating

 

 

 

 

 

 

 

W10

Timer 1 count start synchronous circuit

0

 

Count start synchronous circuit not selected

 

control bit

1

 

Count start synchronous circuit selected

 

 

 

 

 

Timer control register W2

 

 

at reset : 00002

 

at RAM back-up : state retained

R/W

 

 

 

 

 

 

 

 

W23

Timer 2 control bit

0

 

Stop (state retained)

 

 

 

 

 

 

 

 

1

 

Operating

 

 

 

 

 

 

 

W22

Not used

0

 

This bit has no function, but read/write is enabled.

 

1

 

 

 

 

 

 

 

 

 

W21

 

W21

W20

 

 

Count source

 

 

0

 

0

Timer 1 underflow signal

 

 

 

 

 

 

Timer 2 count source selection bits

0

 

1

Prescaler output

 

 

 

 

 

W20

 

1

 

0

CNTR0 input

 

 

 

 

1

 

1

16 bit timer (WDT) underflow signal

 

 

Timer control register W3

 

 

at reset : 00002

 

at RAM back-up : state retained

R/W

 

 

 

 

 

 

 

W33

Timer 3 control bit

0

 

Stop (state retained)

 

 

 

 

 

 

 

 

1

 

Operating

 

 

 

 

 

 

 

W32

Timer 3 count start synchronous circuit

0

 

Count start synchronous circuit not selected

 

control bit

1

 

Count start synchronous circuit selected

 

 

 

 

W31

 

W31

W30

 

 

Count source

 

 

0

 

0

Timer 2 underflow signal

 

 

 

 

 

 

Timer 3 count source selection bits

0

 

1

Prescaler output

 

 

 

 

 

 

W30

 

1

 

0

Not available

 

 

 

 

 

 

 

 

 

 

 

 

1

 

1

Not available

 

 

 

Timer control register W4

 

 

at reset : 00002

 

at RAM back-up : state retained

R/W

 

 

 

 

 

 

 

 

W43

Timer 4 control bit

0

 

Stop (state retained)

 

 

 

 

 

 

 

 

1

 

Operating

 

 

 

 

 

 

 

W42

Not used

0

 

This bit has no function, but read/write is enabled.

 

1

 

 

 

 

 

 

 

 

 

W41

 

W41

W40

 

 

Count source

 

 

0

 

0

Timer 3 underflow signal

 

 

 

 

 

 

Timer 4 count source selection bits

0

 

1

Prescaler output

 

 

 

 

 

 

W40

 

1

 

0

CNTR1 input

 

 

 

 

1

 

1

Not available

 

 

 

 

 

 

 

 

 

 

 

 

Timer control register W6

 

 

at reset : 00002

 

at RAM back-up : state retained

R/W

 

 

 

 

 

 

 

W63

CNTR1 output control bit

0

 

Timer 3 underflow signal output divided by 2

 

 

 

 

 

 

 

 

1

 

CNTR1 output control by timer 4 underflow signal divided by 2

 

 

 

 

 

 

 

 

 

 

W62

D7/CNTR1 function selection bit

0

 

D7(I/O)/CNTR1 input

 

 

 

 

 

 

 

 

1

 

CNTR1 (I/O)/D7(input)

 

 

 

 

 

 

 

 

 

 

 

 

W61

CNTR0 output control bit

0

 

Timer 1 underflow signal output divided by 2

 

1

 

CNTR0 output control by timer 2 underflow signal divided by 2

 

 

 

 

 

 

 

 

 

W60

D6/CNTR0 output control bit

0

 

D6(I/O)/CNTR0 input

 

 

 

 

 

 

 

 

1

 

CNTR0 (I/O)/D6(input)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note: “R” represents read enabled, and “W” represents write enabled.

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HARDWARE

FUNCTION BLOCK OPERATIONS

(1) Timer control registers

Timer control register W1

Register W1 controls the count operation of timer 1, the selection of count start synchronous circuit, and the frequency dividing ratio and count operation of prescaler. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A.

Timer control register W2

Register W2 controls the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A.

Timer control register W3

Register W3 controls the count operation and count source of timer 3 and the selection of count start synchronous circuit. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A.

Timer control register W4

Register W4 controls the count operation and count source of timer 4. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A.

Timer control register W6

Register W6 controls the D6/CNTR0 pin and D7/CNTR1 functions, the selection and operation of the CNTR0 and CNTR1 output. Set the contents of this register through register A with the TW6A instruction. The TAW6 instruction can be used to transfer the contents of register W6 to register A.

(2) Precautions

Note the following for the use of timers.

Prescaler

Stop the prescaler operation to change its frequency dividing ratio.

Count source

Stop timer 1, 2, 3, or 4 counting to change its count source.

Reading the count value

Stop timer 1, 2, 3, or 4 counting and then execute the TAB1,

TAB2, TAB3, or TAB4 instruction to read its data.

Writing to reload registers R1 and R3

When writing data to reload registers R1 or R3 while timer 1 or timer 3 is operating, avoid a timing when timer 1 or timer 3 underflows.

(4) Timer 1 (interrupt function)

Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Data can be written to reload register (R1) with the TR1AB instruction.

When writing data to reload register R1 with the TR1AB instruction, the downcount after the underflow is started from the setting value of reload register R1.

Timer 1 starts counting after the following process;

set data in timer 1, and

set the bit 1 of register W1 to “1.”

However, P30/INT0 pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register W1 to “1.” When a value set in timer 1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255).

Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function).

Data can be read from timer 1 with the TAB1 instruction. When reading the data, stop the counter and then execute the TAB1 instruction. Timer 1 underflow signal divided by 2 can be output from D6/CNTR0 pin.

(5) Timer 2 (interrupt function)

Timer 2 is an 8-bit binary down counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload register (R2) with the T2AB instruction.

Timer 2 starts counting after the following process;

set data in timer 2,

select the count source with the bits 0 and 1 of register W2, and

set the bit 3 of register W2 to “1.”

When a value set in timer 2 is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255).

Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload register R2, and count continues (auto-reload function).

Data can be read from timer 2 with the TAB2 instruction. When reading the data, stop the counter and then execute the TAB2 instruction. The output from D6/CNTR0 pin by timer 2 underflow signal divided by 2 can be controlled.

(3) Prescaler

Prescaler is a frequency divider. Its frequency dividing ratio can be selected. The count source of prescaler is the instruction clock. Use the bit 2 of register W1 to select the prescaler dividing ratio and the bit 3 to start and stop its operation. Prescaler is initialized, and the output signal (ORCLK) stops when the bit 3 of register W1 is cleared to “0.”

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HARDWARE

FUNCTION BLOCK OPERATIONS

(6) Timer 3 (interrupt function)

Timer 3 is an 8-bit binary down counter with the timer 3 reload register (R3). Data can be set simultaneously in timer 3 and the reload register (R3) with the T3AB instruction. Data can be written to reload register (R3) with the TR3AB instruction.

When writing data to reload register R3 with the TR3AB instruction, the downcount after the underflow is started from the setting value of reload register R3.

Timer 3 starts counting after the following process;

set data in timer 3,

select the count source with the bits 0 and 1 of register W3, and

set the bit 3 of register W3 to “1.”

However, P31/INT1 pin input can be used as the start trigger for timer 3 count operation by setting the bit 2 of register W3 to “1.” When a value set in timer 3 is n, timer 3 divides the count source signal by n + 1 (n = 0 to 255).

Once count is started, when timer 3 underflows (the next count pulse is input after the contents of timer 3 becomes “0”), the timer 3 interrupt request flag (T3F) is set to “1,” new data is loaded from reload register R3, and count continues (auto-reload function).

Data can be read from timer 3 with the TAB3 instruction. When reading the data, stop the counter and then execute the TAB3 instruction. Timer 3 underflow signal divided by 2 can be output from D7/CNTR1 pin.

(7) Timer 4 (interrupt function)

Timer 4 is an 8-bit binary down counter with the timer 4 reload register (R4). Data can be set simultaneously in timer 4 and the reload register (R4) with the T4AB instruction.

Timer 4 starts counting after the following process;

set data in timer 4,

select the count source with the bits 0 and 1 of register W4, and

set the bit 3 of register W4 to “1.”

When a value set in timer 4 is n, timer 4 divides the count source signal by n + 1 (n = 0 to 255).

Once count is started, when timer 4 underflows (the next count pulse is input after the contents of timer 4 becomes “0”), the timer 4 interrupt request flag (T4F) is set to “1,” new data is loaded from reload register R4, and count continues (auto-reload function).

Data can be read from timer 4 with the TAB4 instruction. When reading the data, stop the counter and then execute the TAB4 instruction. The output from D7/CNTR1 pin by timer 4 underflow signal divided by 2 can be controlled.

(8) Timer interrupt request flags (T1F, T2F, T3F, and T4F)

Each timer interrupt request flag is set to “1” when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3, and SNZT4).

Use the interrupt control registers V1, V2 to select an interrupt or a skip instruction.

An interrupt request flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction.

(9) Timer I/O pin (D6/CNTR0, D7/CNTR1)

D6/CNTR0 pin has functions to input the timer 2 count source, and to output the timer 1 and timer 2 underflow signals divided by 2. D7/ CNTR1 pin has functions to input the timer 4 count source, and to output the timer 3 and timer 4 underflow signals divided by 2.

The selection of D6/CNTR0 pin function can be controlled with the bit 0 of register W6. The selection of D7/CNTR1 pin function can be controlled with the bit 2 of register W6.

The following signals can be selected for the CNTR0 output signal with the bit 1 of register W6.

timer 1 underflow signal divided by 2

the signal of AND operation between timer 1 underflow signal divided by 2 and timer 2 underflow signal divide by 2

The following signals can be selected for the CNTR1 output signal with the bit 3 of register W6.

timer 3 underflow signal divided by 2

the signal of AND operation between timer 3 underflow signal divided by 2 and timer 4 underflow signal divide by 2

Timer 2 counts the rising waveform of CNTR0 input when the CNTR0 input is selected as the count source.

Timer 4 counts the rising waveform of CNTR1 input when the CNTR1 input is selected as the count source.

(10) Count start synchronous circuit (timer 1 and 3)

Each of timer 1 and timer 3 has the count start synchronous circuit which synchronizes P30/INT0 pin and P31/INT1 pin, respectively, and can start the timer count operation.

Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register W1 to “1.” The control by P30/INT0 pin input can be performed by setting the bit 0 of register I1 to “1.”

The count start synchronous circuit is set by level change (“H”“L” or “L”“H”) of P30/INT0 pin input. This valid waveform is selected by bits 1 (I11) and 2 (I12) of register I1 as follows;

I11 = “0”: Synchronized with one-sided edge (falling or rising)

I11 = “1”: Synchronized with both edges (both falling and rising) When register I11=“0” (synchronized with the one-sided edge), the rising or falling waveform can be selected by bit 2 of register I1;

I12 = “0”: Falling waveform

I12 = “1”: Rising waveform

Timer 3 count start synchronous circuit function is selected by setting the bit 2 of register W3 to “1.” The control by P31/INT1 pin input can be performed by setting the bit 0 of register I2 to “1.”

The count start synchronous circuit is set by level change (“H”“L” or “L”“H”) of P31/INT1 pin input. This valid waveform is selected by bits 1 (I21) and 2 (I22) of register I2 as follows;

I21 = “0”: Synchronized with one-sided edge (falling or rising)

I21 = “1”: Synchronized with both edges (both falling and rising) When register I21=“0” (synchronized with the one-sided edge), the rising or falling waveform can be selected by bit 2 of register I2;

I22 = “0”: Falling waveform

I22 = “1”: Rising waveform

When timer 1 and timer 3 count start synchronous circuits are used, the count start synchronous circuits are set, the count source is input to each timer by inputting valid waveform to P30/INT0 pin and P31/INT1 pin. Once set, the count start synchronous circuit is cleared by clearing the bit I10 or I20 to “0” or reset.

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HARDWARE

FUNCTION BLOCK OPERATIONS

WATCHDOG TIMER

Watchdog timer provides a method to reset the system when a program runs wild. Watchdog timer consists of a 16-bit timer (WDT), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2).

The timer WDT downcounts the instruction clocks as the count source. The underflow signal is generated when the count value reaches “000016.” This underflow signal can be used as the timer 2 count source.

When the WRST instruction is executed after system is released from reset, the WEF flag is set to “1”. At this time, the watchdog timer starts operating.

When the count value of timer WDT reaches “BFFF16” or “3FFF16,” the WDF1 flag is set to “1.” If the WRST instruction is never executed while timer WDT counts 32767, WDF2 flag is set to “1,” and

the RESET pin outputs “L” level to reset the microcomputer. Execute the WRST instruction at each period of 32766 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally.

To prevent the WDT stopping in the event of misoperation, WEF flag is designed not to initialize once the WRST instruction has been executed. Note also that, if the WRST instruction is never executed, the watchdog timer does not start.

FFFF16

BFFF16

The value of timer (WDT)

3FFF16

0000 16

WEF flag

WDF1 flag

WDF2 flag

RESET pin output

WRST

WRST

 

 

instruction

instruction System reset

executed

executed

Fig. 20 Watchdog timer function

The contents of WEF, WDF1 and WDF2 flags and timer WDT are initialized at the RAM back-up mode.

If WDF2 flag is set to “1” at the same time that the microcomputer enters the RAM back-up state, system reset may be performed. When using the watchdog timer and the RAM back-up mode, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back-up state (refer to Figure 21)

WRST

; WDF1 flag reset

EPOF

; POF instruction enabled

POF

 

Oscillation

(RAM back-up state)

stop

 

Fig. 21 Program example to enter the RAM back-up mode

when using the watchdog timer

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HARDWARE

FUNCTION BLOCK OPERATIONS

SERIAL I/O

The 4513/4514 Group has a built-in clock synchronous serial I/O which can serially transmit or receive 8-bit data.

Serial I/O consists of;

serial I/O register SI

serial I/O mode register J1

serial I/O transmission/reception completion flag (SIOF)

serial I/O counter

Registers A and B are used to perform data transfer with internal CPU, and the serial I/O pins are used for external data transfer. The pin functions of the serial I/O pins can be set with the register J1.

Table 11 Serial I/O pins

 

Pin

Pin function when selecting serial I/O

P20

/SCK

Clock I/O (SCK)

 

 

P21/SOUT

Serial data output (SOUT)

 

 

 

P22

/SIN

Serial data input (SIN)

 

 

 

Note: Input ports P20–P22 can be used regardless of register J1.

Division circuit

MR3

(divided by 2)

1

 

XIN 0

Internal clock

generation circuit Instruction clock (divided by 3)

 

J12

 

 

Serial I/O mode register J1

 

 

 

 

 

 

 

 

1/4

1

 

 

J13

J12

J11

J10

 

 

1/8

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SCK

 

 

Synchronous

Serial I/O counter (3)

SIOF Serial I/O interrupt

P20/SCK

 

 

circuit

 

 

 

 

 

 

 

 

 

P21/SOUT

SOUT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P22/SIN

SIN

 

MSB

Serial I/O register SI (8)

LSB

 

 

 

 

 

 

 

 

 

 

TSIAB

 

TABSI

 

 

 

 

J11 J10

Register B (4)

Register A (4)

 

 

 

Note: The output structure of SCK and SOUT pins is N-channel open-drain.

Fig. 22 Serial I/O structure

Table 12 Serial I/O mode register

 

Serial I/O mode register J1

 

at reset : 00002

at RAM back-up : state retained

R/W

 

 

 

 

 

 

 

J13

Not used

0

 

This bit has no function, but read/write is enabled.

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

J12

Serial I/O internal clock dividing ratio

0

 

Instruction clock signal divided by 8

 

selection bit

1

 

Instruction clock signal divided by 4

 

 

 

 

J11

Serial I/O port selection bit

0

 

Input ports P20, P21, P22 selected

 

1

 

Serial I/O ports SCK, SOUT, SIN/input ports P20, P21, P22 selected

 

 

 

J10

Serial I/O synchronous clock selection bit

0

 

External clock

 

 

1

 

Internal clock (instruction clock divided by 4 or 8)

 

 

 

 

 

Note: “R” represents read enabled, and “W” represents write enabled.

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FUNCTION BLOCK OPERATIONS

When transmitting (D7–D0 : transfer data)

 

SIN pin

Serial I/O register (SI)

SOUT pin

D7 D6 D5 D4 D3 D2 D1 D0

 

When receiving

SOUT pin

 

 

 

SIN pin

Serial I/O register (SI)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D7 D6

D5

D4

D3

D2

D1

D0

Transfer data to be set

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D7

D6

D5

D4

D3

D2

D1

Transfer started

D0

 

 

 

 

 

 

 

 

 

 

D7

D6

D5

D4

D3

D2

 

D1

D0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Transfer completed

D7

D6

D5

D4 D3 D2 D1

D0

 

Fig. 23 Serial I/O register state when transferring

(1) Serial I/O register SI

Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and B with the TSIAB instruction. The contents of register A is transmitted to the low-order 4 bits of register SI, and the contents of register B is transmitted to the high-order 4 bits of register SI.

During transmission, each bit data is transmitted LSB first from the lowermost bit (bit 0) of register SI, and during reception, each bit data is received LSB first to register SI starting from the topmost bit (bit 7).

When register SI is used as a work register without using serial I/O, pull up the SCK pin or set the pin function to an input port P20.

(3) Serial I/O start instruction (SST)

When the SST instruction is executed, the SIOF flag is cleared to “0” and then serial I/O transmission/reception is started.

(4) Serial I/O mode register J1

Register J1 controls the synchronous clock, P20/SCK, P21/SOUT and P22/SIN pin function. Set the contents of this register through register A with the TJ1A instruction. The TAJ1 instruction can be used to transfer the contents of register J1 to register A.

(2) Serial I/O transmission/reception completion flag (SIOF)

Serial I/O transmission/reception completion flag (SIOF) is set to “1” when serial data transmission or reception completes. The state of SIOF flag can be examined with the skip instruction (SNZSI). Use the interrupt control register V2 to select the interrupt or the skip instruction.

The SIOF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction.

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