Renesas g1a, rl78 User Manual

Loading...

Manual User’s

16 RL78/G1A User’s Manual: Hardware

16-Bit Single-Chip Microcontrollers

All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com).

 

 

Rev.2.00 Jul 2013

www.renesas.com

Notice

1.Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

2.Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

3.Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

4.You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of Renesas Electronics product.

5.Renesas Electronics products are classified according to the following two quality grades: “Standard” and “High Quality”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below.

“Standard”:

Computers; office equipment; communications equipment; test and measurement equipment; audio and visual

 

equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc.

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; and safety equipment etc.

Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.

6.You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges.

7.Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you.

8.Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations.

9.Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use Renesas Electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas Electronics products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations.

10.It is the responsibility of the buyer or distributor of Renesas Electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of Renesas Electronics products.

11.This document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of Renesas Electronics.

12.Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries.

(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

(2012.4)

NOTES FOR CMOS DEVICES

(1)VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).

(2)HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device.

(3)PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices.

(4)STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions.

(5)POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device.

(6)INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.

How to Use This Manual

Readers

This manual is intended for user engineers who wish to understand the functions of the

 

RL78/G1A and design and develop application systems and programs for these devices.

 

The target products are as follows.

 

 

 

 

25-pin:

R5F10E8x (x = A, C, D, E)

 

 

 

 

32-pin:

R5F10EBx (x = A, C, D, E)

 

 

 

 

48-pin:

R5F10EGx (x = A, C, D, E)

 

 

 

 

64-pin:

R5F10ELx (x = C, D, E)

 

 

 

Purpose

This manual is intended to give users an understanding of the functions described in the

 

Organization below.

 

 

 

Organization

The RL78/G1A manual is separated into two parts: this manual and the instructions edition

 

(common to the RL78 Microcontroller).

 

 

 

 

 

 

 

 

 

 

 

 

 

RL78/G1A

 

RL78 Microcontroller

 

 

 

 

User’s Manual

 

User’s Manual

 

 

 

 

(This Manual)

 

Instructions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin functions

Internal block functions

Interrupts

Other on-chip peripheral functions

Electrical specifications

CPU functions

Instruction set

Explanation of each instruction

How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers.

To gain a general understanding of functions:

Read this manual in the order of the CONTENTS. The mark “<R>” shows major revised points. The revised points can be easily searched by copying an “<R>” in the PDF file and specifying it in the “Find what:” field.

How to interpret the register format:

For a bit number enclosed in angle brackets, the bit name is defined as a reserved word in the assembler, and is defined as an sfr variable using the #pragma sfr directive in the compiler.

To know details of the RL78G1A Microcontroller instructions:

Refer to the separate document RL78 Microcontroller Instructions User’s Manual (R01US0015E).

Conventions

Data significance:

Higher digits on the left and lower digits on the right

 

Active low representations:

××× (overscore over pin and signal name)

 

Note:

Footnote for item marked with Note in the text

 

Caution:

Information requiring particular attention

 

Remark:

Supplementary information

 

Numerical representations:

Binary

...×××× or ××××B

 

 

Decimal

...××××

 

 

Hexadecimal

...××××H

Related Documents

The related documents indicated in this

publication may include preliminary versions.

 

However, preliminary versions are not marked as such.

Documents Related to Devices

Document Name

Document No.

 

 

RL78/G1A User’s Manual Hardware

This manual

 

 

RL78 family User’s Manual: Software

R01US0015E

 

 

Documents Related to Flash Memory Programming

Document Name

Document No.

 

 

PG-FP5 Flash Memory Programmer User’s Manual

R20UT0008E

 

 

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document when designing.

Other Documents

Document Name

Document No.

 

 

Renesas MPUs & MCUs RL78 Family

R01CP0003E

 

 

Semiconductor Package Mount Manual

Note

 

 

Quality Grades on NEC Semiconductor Devices

C11531E

 

 

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

C11892E

 

 

Semiconductor Reliability Handbook

R51ZZ0001E

 

 

Note See the “Semiconductor Package Mount Manual” website (http://www.renesas.com/products/package/manual/index.jsp).

Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing.

All trademarks and registered trademarks are the property of their respective owners. EEPROM is a trademark of Renesas Electronics Corporation.

SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan.

Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.

 

 

CONTENTS

 

CHAPTER 1

OUTLINE...............................................................................................................................

1

1.1

Features .......................................................................................................................................

1

1.2

List of Part Numbers...................................................................................................................

4

1.3

Pin Configuration (Top View).....................................................................................................

6

 

1.3.1

25-pin products ...............................................................................................................................

6

 

1.3.2

32-pin products ...............................................................................................................................

7

 

1.3.3

48-pin products ...............................................................................................................................

8

 

1.3.4

64-pin products .............................................................................................................................

10

1.4

Pin Identification .......................................................................................................................

12

1.5

Block Diagram ...........................................................................................................................

13

 

1.5.1

25-pin products .............................................................................................................................

13

 

1.5.2

32-pin products .............................................................................................................................

14

 

1.5.3

48-pin products .............................................................................................................................

15

 

1.5.4

64-pin products .............................................................................................................................

16

1.6

Outline of Functions .................................................................................................................

17

CHAPTER 2

PIN FUNCTIONS ...............................................................................................................

19

2.1

Port Function .............................................................................................................................

19

 

2.1.1

25-pin products .............................................................................................................................

20

 

2.1.2

32-pin products .............................................................................................................................

22

 

2.1.3

48-pin products .............................................................................................................................

24

 

2.1.4

64-pin products .............................................................................................................................

26

2.2

Functions Other than Port Pins ...............................................................................................

29

 

2.2.1 With functions for each product ....................................................................................................

29

 

2.2.2

Explanation of function..................................................................................................................

33

2.3

Pin I/O Circuits and Recommended Connection of Unused Pins........................................

35

2.4

Block Diagrams of Pins ............................................................................................................

36

CHAPTER 3

CPU ARCHITECTURE ......................................................................................................

47

3.1

Memory Space ...........................................................................................................................

47

 

3.1.1 Internal program memory space ...................................................................................................

54

 

3.1.2

Mirror area ....................................................................................................................................

57

 

3.1.3 Internal data memory space .........................................................................................................

59

 

3.1.4 Special function register (SFR) area.............................................................................................

60

 

3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area.....................

60

 

3.1.6

Data memory addressing..............................................................................................................

61

3.2

Processor Registers .................................................................................................................

62

 

3.2.1

Control registers ...........................................................................................................................

62

 

3.2.2

General-purpose registers ............................................................................................................

64

 

3.2.3 ES and CS registers .....................................................................................................................

65

 

3.2.4 Special function registers (SFRs) .................................................................................................

66

 

3.2.5 Extended special function registers (2nd SFRs) ...........................................................................

72

Index-1

3.3

Instruction Address Addressing .............................................................................................

79

 

3.3.1

Relative addressing ......................................................................................................................

79

 

3.3.2

Immediate addressing...................................................................................................................

79

 

3.3.3

Table indirect addressing..............................................................................................................

80

 

3.3.4

Register direct addressing ............................................................................................................

81

3.4 Addressing for Processing Data Addresses..........................................................................

82

 

3.4.1

Implied addressing........................................................................................................................

82

 

3.4.2

Register addressing......................................................................................................................

82

 

3.4.3

Direct addressing..........................................................................................................................

83

 

3.4.4

Short direct addressing.................................................................................................................

84

 

3.4.5

SFR addressing ............................................................................................................................

85

 

3.4.6

Register indirect addressing .........................................................................................................

86

 

3.4.7

Based addressing .........................................................................................................................

87

 

3.4.8

Based indexed addressing............................................................................................................

91

 

3.4.9

Stack addressing ..........................................................................................................................

92

CHAPTER 4 PORT FUNCTIONS ...........................................................................................................

96

4.1

Port Functions ...........................................................................................................................

96

4.2

Port Configuration.....................................................................................................................

97

 

4.2.1

Port 0 ............................................................................................................................................

98

 

4.2.2

Port 1 ............................................................................................................................................

98

 

4.2.3

Port 2 ............................................................................................................................................

99

 

4.2.4

Port 3 ............................................................................................................................................

99

 

4.2.5

Port 4 ..........................................................................................................................................

100

 

4.2.6

Port 5 ..........................................................................................................................................

100

 

4.2.7

Port 6 ..........................................................................................................................................

100

 

4.2.8

Port 7 ..........................................................................................................................................

101

 

4.2.9

Port 12 ........................................................................................................................................

101

 

4.2.10

Port 13 ........................................................................................................................................

101

 

4.2.11

Port 14 ........................................................................................................................................

102

 

4.2.12

Port 15 ........................................................................................................................................

102

4.3 Registers Controlling Port Function .....................................................................................

103

 

4.3.1

Port mode registers (PMxx) ........................................................................................................

105

 

4.3.2

Port registers (Pxx) .....................................................................................................................

106

 

4.3.3

Pull-up resistor option registers (PUxx).......................................................................................

107

 

4.3.4

Port input mode registers (PIMxx) ..............................................................................................

108

 

4.3.5

Port output mode registers (POMxx) ..........................................................................................

109

 

4.3.6

Port mode control registers (PMCxx)..........................................................................................

110

 

4.3.7

A/D port configuration register (ADPC).......................................................................................

111

 

4.3.8

Peripheral I/O redirection register (PIOR)...................................................................................

112

 

4.3.9

Global digital input disable register (GDIDIS) .............................................................................

113

 

4.3.10

Global analog input disable register (GAIDIS) ............................................................................

114

4.4

Port Function Operations.......................................................................................................

115

 

4.4.1

Writing to I/O port........................................................................................................................

115

 

4.4.2

Reading from I/O port .................................................................................................................

115

 

4.4.3

Operations on I/O port ................................................................................................................

115

Index-2

 

4.4.4 Handling different potential (1.8 V or 2.5 V) by using EVDD ≤ VDD...............................................

116

 

4.4.5 Handling different potential (1.8 V or 2.5 V) by using I/O buffers ................................................

116

4.5

Register Settings When Using Alternate Function..............................................................

118

 

4.5.1 Basic concept when using alternate function ..............................................................................

118

 

4.5.2 Register settings for alternate function whose output function is not used .................................

119

 

4.5.3 Register setting examples for used port and alternate functions ................................................

120

4.6

Cautions When Using Port Function.....................................................................................

137

 

4.6.1 Cautions on 1-bit manipulation instruction for port register n (Pn) ..............................................

137

 

4.6.2 Notes on specifying the pin settings ...........................................................................................

138

CHAPTER 5

CLOCK GENERATOR ....................................................................................................

139

5.1

Functions of Clock Generator................................................................................................

139

5.2

Configuration of Clock Generator .........................................................................................

141

5.3

Registers Controlling Clock Generator.................................................................................

143

 

5.3.1 Clock operation mode control register (CMC).............................................................................

143

 

5.3.2 System clock control register (CKC) ...........................................................................................

146

 

5.3.3 Clock operation status control register (CSC).............................................................................

147

 

5.3.4 Oscillation stabilization time counter status register (OSTC) ......................................................

148

 

5.3.5 Oscillation stabilization time select register (OSTS) ...................................................................

150

 

5.3.6 Peripheral enable register 0 (PER0) ...........................................................................................

152

 

5.3.7 Subsystem clock supply mode control register (OSMC).............................................................

155

 

5.3.8 High-speed on-chip oscillator frequency select register (HOCODIV)..........................................

156

 

5.3.9 High-speed on-chip oscillator trimming register (HIOTRM).........................................................

157

5.4

System Clock Oscillator .........................................................................................................

158

 

5.4.1

X1 oscillator ................................................................................................................................

158

 

5.4.2

XT1 oscillator ..............................................................................................................................

158

 

5.4.3

High-speed on-chip oscillator......................................................................................................

162

 

5.4.4

Low-speed on-chip oscillator ......................................................................................................

162

5.5

Clock Generator Operation ....................................................................................................

163

5.6

Controlling Clock ....................................................................................................................

165

 

5.6.1 Example of setting high-speed on-chip oscillator........................................................................

165

 

5.6.2 Example of setting X1 oscillation clock .......................................................................................

166

 

5.6.3 Example of setting XT1 oscillation clock.....................................................................................

167

 

5.6.4 CPU clock status transition diagram ...........................................................................................

168

 

5.6.5 Condition before changing CPU clock and processing after changing CPU clock......................

174

 

5.6.6 Time required for switchover of CPU clock and system clock.....................................................

176

 

5.6.7 Conditions before clock oscillation is stopped.............................................................................

177

5.7

Resonator and Oscillator Constants.....................................................................................

178

CHAPTER 6

TIMER ARRAY UNIT......................................................................................................

182

6.1

Functions of Timer Array Unit ...............................................................................................

184

 

6.1.1 Independent channel operation function.....................................................................................

184

 

6.1.2 Simultaneous channel operation function ...................................................................................

185

 

6.1.3 8-bit timer operation function (channels 1 and 3 only) ................................................................

186

 

6.1.4 LIN-bus supporting function (channel 7 of unit 0 only)................................................................

187

6.2

Configuration of Timer Array Unit .........................................................................................

188

Index-3

6.2.1

Timer count register mn (TCRmn) ..............................................................................................

193

6.2.2

Timer data register mn (TDRmn) ................................................................................................

195

6.3 Registers Controlling Timer Array Unit ................................................................................

196

6.3.1

Peripheral enable register 0 (PER0) ...........................................................................................

197

6.3.2

Timer clock select register m (TPSm).........................................................................................

198

6.3.3

Timer mode register mn (TMRmn)..............................................................................................

201

6.3.4

Timer status register mn (TSRmn)..............................................................................................

206

6.3.5

Timer channel enable status register m (TEm) ...........................................................................

207

6.3.6

Timer channel start register m (TSm) .........................................................................................

208

6.3.7

Timer channel stop register m (TTm)..........................................................................................

209

6.3.8

Timer input select register 0 (TIS0).............................................................................................

210

6.3.9

Timer output enable register m (TOEm) .....................................................................................

211

6.3.10

Timer output register m (TOm) ...................................................................................................

212

6.3.11

Timer output level register m (TOLm) .........................................................................................

213

6.3.12

Timer output mode register m (TOMm).......................................................................................

214

6.3.13

Input switch control register (ISC)...............................................................................................

215

6.3.14

Noise filter enable register 1 (NFEN1) ........................................................................................

216

6.3.15

Registers controlling port functions of pins to be used for timer I/O............................................

218

6.4 Basic Rules of Timer Array Unit ............................................................................................

219

6.4.1

Basic rules of simultaneous channel operation function .............................................................

219

6.4.2

Basic rules of 8-bit timer operation function (channels 1 and 3 only)..........................................

221

6.5 Operation of Counter ..............................................................................................................

222

6.5.1

Count clock (fTCLK).......................................................................................................................

222

6.5.2

Start timing of counter.................................................................................................................

224

6.5.3

Operation of counter ...................................................................................................................

225

6.6 Channel Output (TOmn Pin) Control.....................................................................................

230

6.6.1

TOmn pin output circuit configuration .........................................................................................

230

6.6.2

TOmn pin output setting..............................................................................................................

231

6.6.3

Cautions on channel output operation ........................................................................................

232

6.6.4

Collective manipulation of TOmn bit ...........................................................................................

237

6.6.5

Timer Interrupt and TOmn pin output at operation start..............................................................

238

6.7 Timer Input (TImn) Control.....................................................................................................

239

6.7.1

TImn pin input circuit configuration .............................................................................................

239

6.7.2

Noise filter...................................................................................................................................

239

6.7.3

Cautions on channel input ..........................................................................................................

240

6.8 Independent Channel Operation Function of Timer Array Unit .........................................

241

6.8.1

Operation as interval timer/square wave output..........................................................................

241

6.8.2

Operation as external event counter...........................................................................................

247

6.8.3

Operation as frequency divider (channel 0 of unit 0 only)...........................................................

252

6.8.4

Operation as input pulse interval measurement..........................................................................

256

6.8.5

Operation as input signal high-/low-level width measurement ....................................................

260

6.8.6

Operation as delay counter.........................................................................................................

264

6.9 Simultaneous Channel Operation Function of Timer Array Unit .......................................

269

6.9.1

Operation as one-shot pulse output function ..............................................................................

269

6.9.2

Operation as PWM function ........................................................................................................

276

6.9.3

Operation as multiple PWM output function................................................................................

283

6.10 Cautions When Using Timer Array Unit................................................................................

291

 

 

Index-4

 

6.10.1

Cautions when using timer output...............................................................................................

291

CHAPTER 7 REAL-TIME CLOCK........................................................................................................

292

7.1

Functions of Real-time Clock.................................................................................................

292

7.2

Configuration of Real-time Clock ..........................................................................................

293

7.3

Registers Controlling Real-time Clock..................................................................................

295

 

7.3.1

Peripheral enable register 0 (PER0) ...........................................................................................

296

 

7.3.2

Subsystem clock supply mode control register (OSMC).............................................................

297

 

7.3.3

Real-time clock control register 0 (RTCC0) ................................................................................

298

 

7.3.4

Real-time clock control register 1 (RTCC1) ................................................................................

299

 

7.3.5

Second count register (SEC) ......................................................................................................

301

 

7.3.6

Minute count register (MIN) ........................................................................................................

301

 

7.3.7

Hour count register (HOUR) .......................................................................................................

302

 

7.3.8

Day count register (DAY)............................................................................................................

304

 

7.3.9

Week count register (WEEK) ......................................................................................................

305

 

7.3.10

Month count register (MONTH)...................................................................................................

306

 

7.3.11

Year count register (YEAR) ........................................................................................................

306

 

7.3.12

Watch error correction register (SUBCUD) .................................................................................

307

 

7.3.13

Alarm minute register (ALARMWM)............................................................................................

308

 

7.3.14

Alarm hour register (ALARMWH)................................................................................................

308

 

7.3.15

Alarm week register (ALARMWW)..............................................................................................

308

 

7.3.16

Port mode register 3 (PM3).........................................................................................................

309

 

7.3.17

Port register 3 (P3) .....................................................................................................................

309

7.4

Real-time Clock Operation .....................................................................................................

310

 

7.4.1

Starting operation of real-time clock ...........................................................................................

310

 

7.4.2

Shifting to HALT/STOP mode after starting operation ................................................................

311

 

7.4.3

Reading/writing real-time clock ...................................................................................................

312

 

7.4.4

Setting alarm of real-time clock...................................................................................................

314

 

7.4.5

1 Hz output of real-time clock .....................................................................................................

315

 

7.4.6

Example of watch error correction of real-time clock ..................................................................

316

CHAPTER 8 12-BIT INTERVAL TIMER..............................................................................................

321

8.1

Functions of 12-bit Interval Timer .........................................................................................

321

8.2

Configuration of 12-bit Interval Timer...................................................................................

321

8.3

Registers Controlling 12-bit Interval Timer ..........................................................................

322

 

8.3.1

Peripheral enable register 0 (PER0) ...........................................................................................

322

 

8.3.2

Subsystem clock supply mode control register (OSMC).............................................................

323

 

8.3.3

Interval timer control register (ITMC) ..........................................................................................

324

8.4

12-bit Interval Timer Operation..............................................................................................

325

 

8.4.1

12-bit interval timer operation timing...........................................................................................

325

8.4.2Starting counter operation after returning from HALT or STOP mode and then shifting to

HALT or STOP mode again ........................................................................................................

326

CHAPTER 9 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER.................................................

327

9.1 Functions of Clock Output/Buzzer Output Controller .........................................................

327

 

Index-5

9.2 Configuration of Clock Output/Buzzer Output Controller...................................................

329

9.3 Registers Controlling Clock Output/Buzzer Output Controller..........................................

329

 

9.3.1

Clock output select registers n (CKSn) .......................................................................................

329

 

9.3.2

Registers controlling port functions of pins to be used for clock or buzzer output.......................

331

9.4 Operations of Clock Output/Buzzer Output Controller .......................................................

332

 

9.4.1

Operation as output pin...............................................................................................................

332

9.5 Cautions of Clock Output/Buzzer Output Controller...........................................................

332

CHAPTER 10

WATCHDOG TIMER .....................................................................................................

333

10.1

Functions of Watchdog Timer ...............................................................................................

333

10.2

Configuration of Watchdog Timer .........................................................................................

334

10.3

Register Controlling Watchdog Timer ..................................................................................

335

 

10.3.1

Watchdog timer enable register (WDTE) ....................................................................................

335

10.4

Operation of Watchdog Timer................................................................................................

336

 

10.4.1

Controlling operation of watchdog timer......................................................................................

336

 

10.4.2

Setting overflow time of watchdog timer .....................................................................................

337

 

10.4.3

Setting window open period of watchdog timer...........................................................................

338

 

10.4.4

Setting watchdog timer interval interrupt.....................................................................................

339

CHAPTER 11

A/D CONVERTER .........................................................................................................

340

11.1

Function of A/D Converter .....................................................................................................

340

11.2

Configuration of A/D Converter .............................................................................................

343

11.3

Registers Used in A/D Converter...........................................................................................

345

 

11.3.1

Peripheral enable register 0 (PER0) ...........................................................................................

346

 

11.3.2

A/D converter mode register 0 (ADM0).......................................................................................

347

 

11.3.3

A/D converter mode register 1 (ADM1).......................................................................................

359

 

11.3.4

A/D converter mode register 2 (ADM2).......................................................................................

360

 

11.3.5

12-bit A/D conversion result register (ADCR) .............................................................................

362

 

11.3.6

8-bit A/D conversion result register (ADCRH).............................................................................

363

 

11.3.7

Analog input channel specification register (ADS) ......................................................................

364

 

11.3.8

Conversion result comparison upper limit setting register (ADUL)..............................................

366

 

11.3.9

Conversion result comparison lower limit setting register (ADLL)...............................................

366

 

11.3.10 A/D test register (ADTES)...........................................................................................................

367

 

11.3.11 Registers controlling port function of analog input pins...............................................................

368

11.4

A/D Converter Conversion Operations .................................................................................

369

11.5

Input Voltage and Conversion Results .................................................................................

371

11.6

A/D Converter Operation Modes............................................................................................

372

 

11.6.1

Software trigger mode (select mode, sequential conversion mode) ...........................................

372

 

11.6.2

Software trigger mode (select mode, one-shot conversion mode)..............................................

373

 

11.6.3

Software trigger mode (scan mode, sequential conversion mode) .............................................

374

 

11.6.4

Software trigger mode (scan mode, one-shot conversion mode)................................................

375

 

11.6.5

Hardware trigger no-wait mode (select mode, sequential conversion mode)..............................

376

 

11.6.6

Hardware trigger no-wait mode (select mode, one-shot conversion mode) ................................

377

 

11.6.7

Hardware trigger no-wait mode (scan mode, sequential conversion mode) ...............................

378

 

11.6.8

Hardware trigger no-wait mode (scan mode, one-shot conversion mode)..................................

379

 

11.6.9

Hardware trigger wait mode (select mode, sequential conversion mode)...................................

380

Index-6

11.6.10

Hardware trigger wait mode (select mode, one-shot conversion mode) .....................................

381

11.6.11

Hardware trigger wait mode (scan mode, sequential conversion mode).....................................

382

11.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode).......................................

383

11.7 A/D Converter Setup Flowchart .............................................................................................

384

11.7.1

Setting up software trigger mode ................................................................................................

385

11.7.2

Setting up hardware trigger no-wait mode ..................................................................................

386

11.7.3

Setting up hardware trigger wait mode .......................................................................................

387

11.7.4Setup when temperature sensor output voltage/internal reference voltage is selected

 

 

(example for software trigger mode and one-shot conversion mode) .........................................

388

 

11.7.5

Setting up test mode...................................................................................................................

389

11.8

SNOOZE Mode Function ........................................................................................................

390

11.9 How to Read A/D Converter Characteristics Table..............................................................

394

11.10 Cautions for A/D Converter....................................................................................................

396

CHAPTER 12 SERIAL ARRAY UNIT..................................................................................................

400

12.1 Functions of Serial Array Unit ...............................................................................................

401

 

12.1.1

3-wire serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21)..................................................

401

 

12.1.2

UART (UART0 to UART2) ..........................................................................................................

402

 

12.1.3

Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) ..............................................................

403

12.2 Configuration of Serial Array Unit .........................................................................................

404

 

12.2.1

Shift register................................................................................................................................

407

 

12.2.2

Lower 8/9 bits of the serial data register mn (SDRmn) ...............................................................

407

12.3 Registers Controlling Serial Array Unit ................................................................................

409

 

12.3.1

Peripheral enable register 0 (PER0) ...........................................................................................

410

 

12.3.2

Serial clock select register m (SPSm).........................................................................................

411

 

12.3.3

Serial mode register mn (SMRmn) .............................................................................................

412

 

12.3.4

Serial communication operation setting register mn (SCRmn) ...................................................

413

 

12.3.5

Higher 7 bits of the serial data register mn (SDRmn) .................................................................

416

 

12.3.6

Serial flag clear trigger register mn (SIRmn)...............................................................................

418

 

12.3.7

Serial status register mn (SSRmn) .............................................................................................

419

 

12.3.8

Serial channel start register m (SSm) .........................................................................................

421

 

12.3.9

Serial channel stop register m (STm) .........................................................................................

422

 

12.3.10

Serial channel enable status register m (SEm)...........................................................................

423

 

12.3.11

Serial output enable register m (SOEm) .....................................................................................

424

 

12.3.12

Serial output register m (SOm) ...................................................................................................

425

 

12.3.13

Serial output level register m (SOLm).........................................................................................

426

 

12.3.14

Serial standby control register 0 (SSC0).....................................................................................

428

 

12.3.15

Input switch control register (ISC)...............................................................................................

429

 

12.3.16

Noise filter enable register 0 (NFEN0) ........................................................................................

430

 

12.3.17

Registers controlling port functions of serial input/output pins ....................................................

431

12.4

Operation Stop Mode..............................................................................................................

432

 

12.4.1

Stopping the operation by units ..................................................................................................

432

 

12.4.2

Stopping the operation by channels............................................................................................

433

12.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI10, CSI11, CSI20, CSI21)

 

 

Communication .......................................................................................................................

434

 

12.5.1

Master transmission....................................................................................................................

437

Index-7

12.5.2

Master reception .........................................................................................................................

447

12.5.3

Master transmission/reception ....................................................................................................

457

12.5.4

Slave transmission......................................................................................................................

467

12.5.5

Slave reception ...........................................................................................................................

477

12.5.6

Slave transmission/reception ......................................................................................................

485

12.5.7

SNOOZE mode function .............................................................................................................

495

12.5.8 Calculating transfer clock frequency ...........................................................................................

499

12.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI10,

 

 

CSI11, CSI20, CSI21) communication........................................................................................

501

12.6 Operation of UART (UART0 to UART2) Communication.....................................................

502

12.6.1

UART transmission.....................................................................................................................

505

12.6.2

UART reception ..........................................................................................................................

515

12.6.3

SNOOZE mode function .............................................................................................................

522

12.6.4

Calculating baud rate..................................................................................................................

530

12.6.5Procedure for processing errors that occurred during UART (UART0 to UART2)

 

communication............................................................................................................................

534

12.7 LIN Communication Operation ..............................................................................................

535

12.7.1

LIN transmission .........................................................................................................................

535

12.7.2

LIN reception ..............................................................................................................................

538

12.8 Operation of Simplified I2C (IIC00, IIC01, IIC10, IIC11, IIC20, IIC21) Communication .......

544

12.8.1

Address field transmission ..........................................................................................................

547

12.8.2

Data transmission .......................................................................................................................

553

12.8.3

Data reception ............................................................................................................................

557

12.8.4

Stop condition generation ...........................................................................................................

562

12.8.5

Calculating transfer rate..............................................................................................................

563

12.8.6Procedure for processing errors that occurred during simplified I2C (IIC00, IIC01, IIC10, IIC11,

 

 

IIC20, IIC21) communication ......................................................................................................

565

CHAPTER 13

SERIAL INTERFACE IICA ...........................................................................................

566

13.1

Functions of Serial Interface IICA..........................................................................................

566

13.2

Configuration of Serial Interface IICA ...................................................................................

569

13.3

Registers Controlling Serial Interface IICA ..........................................................................

572

 

13.3.1 Peripheral enable register 0 (PER0) ...........................................................................................

572

 

13.3.2 IICA control register 00 (IICCTL00) ............................................................................................

573

 

13.3.3 IICA status register 0 (IICS0) ......................................................................................................

578

 

13.3.4 IICA flag register 0 (IICF0)..........................................................................................................

581

 

13.3.5 IICA control register 01 (IICCTL01) ............................................................................................

583

 

13.3.6 IICA low-level width setting register 0 (IICWL0)..........................................................................

585

 

13.3.7 IICA high-level width setting register 0 (IICWH0)........................................................................

585

 

13.3.8 Port mode register 6 (PM6).........................................................................................................

586

13.4

I2C Bus Mode Functions .........................................................................................................

587

 

13.4.1

Pin configuration .........................................................................................................................

587

 

13.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers ....................................................

588

13.5

I2C Bus Definitions and Control Methods .............................................................................

590

 

13.5.1

Start conditions ...........................................................................................................................

590

 

13.5.2

Addresses...................................................................................................................................

591

Index-8

 

13.5.3

Transfer direction specification ...................................................................................................

591

 

13.5.4

Acknowledge

 

 

592

 

(ACK)

 

13.5.5

Stop condition .............................................................................................................................

593

 

13.5.6

Wait ............................................................................................................................................

594

 

13.5.7

Canceling wait ............................................................................................................................

596

 

13.5.8

Interrupt request (INTIICA0) generation timing and wait control .................................................

597

 

13.5.9

Address match detection method ...............................................................................................

598

 

13.5.10

Error detection ............................................................................................................................

598

 

13.5.11

Extension code ...........................................................................................................................

598

 

13.5.12

Arbitration ...................................................................................................................................

599

 

13.5.13

Wakeup function .........................................................................................................................

601

 

13.5.14

Communication reservation ........................................................................................................

604

 

13.5.15

Cautions......................................................................................................................................

608

 

13.5.16

Communication operations .........................................................................................................

609

 

13.5.17 Timing of I2C interrupt request (INTIICA0) occurrence................................................................

616

13.6

Timing Charts ..........................................................................................................................

637

CHAPTER 14 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR .......................................

652

14.1

Functions of Multiplier and Divider/Multiply-Accumulator.................................................

652

14.2

Configuration of Multiplier and Divider/Multiply-Accumulator ..........................................

652

 

14.2.1

Multiplication/division data register A (MDAH, MDAL) ................................................................

654

 

14.2.2

Multiplication/division data register B (MDBL, MDBH) ................................................................

655

 

14.2.3

Multiplication/division data register C (MDCL, MDCH) ...............................................................

656

14.3

Register Controlling Multiplier and Divider/Multiply-Accumulator....................................

658

 

14.3.1

Multiplication/division control register (MDUC) ...........................................................................

658

14.4

Operations of Multiplier and Divider/Multiply-Accumulator ...............................................

660

 

14.4.1

Multiplication (unsigned) operation .............................................................................................

660

 

14.4.2

Multiplication (signed) operation .................................................................................................

661

 

14.4.3

Multiply-accumulation (unsigned) operation................................................................................

662

 

14.4.4

Multiply-accumulation (signed) operation....................................................................................

664

 

14.4.5

Division operation .......................................................................................................................

666

CHAPTER 15 DMA CONTROLLER .....................................................................................................

668

15.1

Functions of DMA Controller .................................................................................................

668

15.2

Configuration of DMA Controller...........................................................................................

669

 

15.2.1

DMA SFR address register n (DSAn) .........................................................................................

669

 

15.2.2

DMA RAM address register n (DRAn) ........................................................................................

670

 

15.2.3

DMA byte count register n (DBCn) .............................................................................................

671

15.3

Registers Controlling DMA Controller ..................................................................................

672

 

15.3.1

DMA mode control register n (DMCn).........................................................................................

672

 

15.3.2

DMA operation control register n (DRCn) ...................................................................................

674

15.4

Operation of DMA Controller .................................................................................................

675

 

15.4.1

Operation procedure...................................................................................................................

675

 

15.4.2

Transfer mode ............................................................................................................................

676

 

15.4.3

Termination of DMA transfer.......................................................................................................

676

15.5

Example of Setting of DMA Controller..................................................................................

677

Index-9

 

15.5.1

CSI consecutive transmission.....................................................................................................

677

 

15.5.2 Consecutive capturing of A/D conversion results........................................................................

679

 

15.5.3 UART consecutive reception + ACK transmission ......................................................................

681

 

15.5.4 Holding DMA transfer pending by DWAITn bit............................................................................

682

 

15.5.5 Forced termination by software...................................................................................................

683

15.6

Cautions on Using DMA Controller.......................................................................................

685

CHAPTER 16

INTERRUPT FUNCTIONS.............................................................................................

688

16.1

Interrupt Function Types........................................................................................................

688

16.2

Interrupt Sources and Configuration ....................................................................................

688

16.3

Registers Controlling Interrupt Functions............................................................................

694

 

16.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) ..........................................

698

 

16.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H) ................................

699

16.3.3Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L,

PR10H, PR11L, PR11H, PR12L, PR12H) ..................................................................................

701

16.3.4External interrupt rising edge enable registers (EGP0, EGP1), external interrupt falling edge

 

 

enable registers (EGN0, EGN1) .................................................................................................

703

 

16.3.5 Program status word (PSW) .......................................................................................................

705

16.4

Interrupt Servicing Operations ..............................................................................................

706

 

16.4.1 Maskable interrupt request acknowledgment..............................................................................

706

 

16.4.2 Software interrupt request acknowledgment...............................................................................

709

 

16.4.3

Multiple interrupt servicing ..........................................................................................................

709

 

16.4.4

Interrupt request hold..................................................................................................................

713

CHAPTER 17

KEY INTERRUPT FUNCTION .....................................................................................

714

17.1

Functions of Key Interrupt .....................................................................................................

714

17.2

Configuration of Key Interrupt...............................................................................................

715

17.3

Register Controlling Key Interrupt ........................................................................................

717

 

17.3.1 Key return control register (KRCTL) ...........................................................................................

717

 

17.3.2 Key return mode registers 0, 1 (KRM0, KRM1) ..........................................................................

718

 

17.3.3 Key return flag register (KRF) .....................................................................................................

719

 

17.3.4 Port mode registers 0 to 2, 7, 12, 15 (PM0 to PM2, PM7, PM12, PM15)....................................

720

 

17.3.5 Peripheral I/O redirection register (PIOR)...................................................................................

721

17.4

Key Interrupt Operation..........................................................................................................

722

 

17.4.1 When not using the key interrupt flag (KRMD = 0)......................................................................

722

 

17.4.2 When using the key interrupt flag (KRMD = 1) ...........................................................................

723

CHAPTER 18

STANDBY FUNCTION ..................................................................................................

726

18.1

Standby Function....................................................................................................................

726

18.2

Registers Controlling Standby Function ..............................................................................

727

18.3

Standby Function Operation..................................................................................................

727

 

18.3.1

HALT mode.................................................................................................................................

727

 

18.3.2

STOP mode ................................................................................................................................

732

 

18.3.3

SNOOZE mode...........................................................................................................................

737

Index-10

CHAPTER 19

RESET FUNCTION........................................................................................................

740

19.1

Timing of Reset Operation .....................................................................................................

742

19.2

States of Operation During Reset Periods ...........................................................................

744

19.3

Register for Confirming Reset Source..................................................................................

746

 

19.3.1 Reset control flag register (RESF) ..............................................................................................

746

CHAPTER 20

POWER-ON-RESET CIRCUIT ......................................................................................

749

20.1

Functions of Power-on-reset Circuit.....................................................................................

749

20.2

Configuration of Power-on-reset Circuit...............................................................................

750

20.3

Operation of Power-on-reset Circuit .....................................................................................

750

CHAPTER 21

VOLTAGE DETECTOR.................................................................................................

754

21.1

Functions of Voltage Detector ...............................................................................................

754

21.2

Configuration of Voltage Detector.........................................................................................

755

21.3

Registers Controlling Voltage Detector................................................................................

755

 

21.3.1 Voltage detection register (LVIM) ...............................................................................................

756

 

21.3.2 Voltage detection level register (LVIS)........................................................................................

757

21.4

Operation of Voltage Detector ...............................................................................................

760

 

21.4.1 When used as reset mode ..........................................................................................................

760

 

21.4.2 When used as interrupt mode.....................................................................................................

762

 

21.4.3 When used as interrupt & reset mode ........................................................................................

764

21.5

Cautions for Voltage Detector ...............................................................................................

770

CHAPTER 22

SAFETY FUNCTIONS...................................................................................................

772

22.1

Overview of Safety Functions................................................................................................

772

22.2

Registers Used by Safety Functions.....................................................................................

773

22.3

Operation of Safety Functions...............................................................................................

773

 

22.3.1 Flash memory CRC operation function (high-speed CRC) .........................................................

773

 

22.3.2 CRC operation function (general-purpose CRC) ........................................................................

776

 

22.3.3 RAM parity error detection function ............................................................................................

778

 

22.3.4

RAM guard function ....................................................................................................................

780

 

22.3.5

SFR guard function.....................................................................................................................

781

 

22.3.6 Invalid memory access detection function ..................................................................................

782

 

22.3.7

Frequency detection function......................................................................................................

784

 

22.3.8

A/D test function .........................................................................................................................

786

CHAPTER 23

REGULATOR .................................................................................................................

791

23.1

Regulator Overview.................................................................................................................

791

CHAPTER 24

OPTION BYTE...............................................................................................................

792

24.1

Functions of Option Bytes .....................................................................................................

792

 

24.1.1 User option byte (000C0H to 000C2H/010C0H to 010C2H) .......................................................

792

 

24.1.2 On-chip debug option byte (000C3H/ 010C3H) ..........................................................................

793

24.2

Format of User Option Byte ...................................................................................................

794

Index-11

24.3

Format of On-chip Debug Option Byte .................................................................................

798

24.4

Setting of Option Byte ............................................................................................................

799

CHAPTER 25

FLASH MEMORY ..........................................................................................................

800

25.1

Serial Programming Using Flash Memory Programmer .....................................................

802

 

25.1.1

 

Programming environment..........................................................................................................

804

 

25.1.2

 

Communication mode.................................................................................................................

804

25.2

Serial Programming Using External Device (that Incorporates UART).............................

805

 

25.2.1

 

Programming environment..........................................................................................................

805

 

25.2.2

 

Communication mode.................................................................................................................

806

25.3

Connection of Pins on Board.................................................................................................

807

 

25.3.1

 

P40/TOOL0 pin...........................................................................................................................

807

 

25.3.2

 

 

807

 

 

RESET

..................................................................................................................................pin

 

25.3.3

 

Port pins......................................................................................................................................

808

 

25.3.4

 

REGC pin....................................................................................................................................

808

 

25.3.5 X1 and X2 pins ...........................................................................................................................

808

 

25.3.6

 

Power supply ..............................................................................................................................

808

25.4

Serial Programming Method ..................................................................................................

809

 

25.4.1

 

Serial programming procedure ...................................................................................................

809

 

25.4.2 Flash memory programming mode .............................................................................................

810

 

25.4.3

 

Selecting communication mode ..................................................................................................

812

 

25.4.4

 

Communication commands ........................................................................................................

812

25.5

Processing Time for Each Command When PG-FP5 Is in Use (Reference Value)...........

814

25.6

Self-Programming ...................................................................................................................

815

 

25.6.1

 

Self-programming procedure ......................................................................................................

816

 

25.6.2

 

Boot swap function .....................................................................................................................

817

 

25.6.3 Flash shield window function ......................................................................................................

819

25.7

Security Settings.....................................................................................................................

820

25.8

Data Flash ................................................................................................................................

822

 

25.8.1

 

Data flash overview ....................................................................................................................

822

 

25.8.2 Register controlling data flash memory.......................................................................................

822

 

25.8.3 Procedure for accessing data flash memory...............................................................................

823

CHAPTER 26

ON-CHIP DEBUG FUNCTION .....................................................................................

824

26.1

Connecting E1 On-Chip Debugging Emulator .....................................................................

824

26.2

On-Chip Debug Security ID ....................................................................................................

825

26.3

Securing of User Resources ..................................................................................................

825

CHAPTER 27

BCD CORRECTION CIRCUIT .....................................................................................

827

27.1

BCD Correction Circuit Function...........................................................................................

827

27.2

Registers Used by BCD Correction Circuit ..........................................................................

827

 

27.2.1 BCD correction result register (BCDADJ) ...................................................................................

827

27.3

BCD Correction Circuit Operation.........................................................................................

828

CHAPTER 28

INSTRUCTION SET.......................................................................................................

830

 

 

 

 

 

Index-12

28.1

Conventions Used in Operation List.....................................................................................

830

 

28.1.1 Operand identifiers and specification methods ...........................................................................

830

 

28.1.2 Description of operation column .................................................................................................

831

 

28.1.3 Description of flag operation column...........................................................................................

832

 

28.1.4

PREFIX instruction .....................................................................................................................

832

28.2

Operation List ..........................................................................................................................

833

CHAPTER 29

ELECTRICAL SPECIFICATIONS (TA = 40 to +85°C)...........................................

850

29.1

Absolute Maximum Ratings ...................................................................................................

851

29.2

Oscillator Characteristics.......................................................................................................

853

 

29.2.1 X1, XT1 oscillator characteristics................................................................................................

853

 

29.2.2

On-chip oscillator characteristics ................................................................................................

853

29.3

DC Characteristics ..................................................................................................................

854

 

29.3.1

Pin characteristics.......................................................................................................................

854

 

29.3.2

Supply current characteristics.....................................................................................................

859

29.4

AC Characteristics ..................................................................................................................

865

29.5

Peripheral Functions Characteristics ...................................................................................

870

 

29.5.1

Serial array unit...........................................................................................................................

870

 

29.5.2

Serial interface IICA....................................................................................................................

893

29.6

Analog Characteristics ...........................................................................................................

896

 

29.6.1

A/D converter characteristics ......................................................................................................

896

 

29.6.2 Temperature sensor, internal reference voltage output characteristics ......................................

901

 

29.6.3

POR circuit characteristics..........................................................................................................

901

 

29.6.4

LVD circuit characteristics...........................................................................................................

902

 

29.6.5 Supply voltage rise slope characteristics ....................................................................................

903

29.7

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics .............

904

29.8

Flash Memory Programming Characteristics ......................................................................

904

29.9

Dedicated Flash Memory Programmer Communication (UART) .......................................

904

29.10 Timing Specs for Switching Flash Memory Programming Modes.....................................

905

CHAPTER 30

ELECTRICAL SPECIFICATIONS

 

 

 

(G: INDUSTRIAL APPLICATIONS TA = 40 to +105°C).......................................

906

30.1

Absolute Maximum Ratings ...................................................................................................

907

30.2

Oscillator Characteristics.......................................................................................................

909

 

30.2.1 X1, XT1 oscillator characteristics................................................................................................

909

 

30.2.2

On-chip oscillator characteristics ................................................................................................

909

30.3

DC Characteristics ..................................................................................................................

910

 

30.3.1

Pin characteristics.......................................................................................................................

910

 

30.3.2

Supply current characteristics.....................................................................................................

915

30.4

AC Characteristics ..................................................................................................................

921

30.5

Peripheral Functions Characteristics ...................................................................................

925

 

30.5.1

Serial array unit...........................................................................................................................

925

 

30.5.2

Serial interface IICA....................................................................................................................

943

30.6

Analog Characteristics ...........................................................................................................

944

 

30.6.1

A/D converter characteristics ......................................................................................................

944

Index-13

 

30.6.2 Temperature sensor, internal reference voltage output characteristics ......................................

948

 

30.6.3

POR circuit characteristics..........................................................................................................

948

 

30.6.4

LVD circuit characteristics...........................................................................................................

949

 

30.6.5 Supply voltage rise slope characteristics ....................................................................................

949

30.7

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics .............

950

30.8

Flash Memory Programming Characteristics ......................................................................

950

30.9

Dedicated Flash Memory Programmer Communication (UART) .......................................

950

30.10

Timing Specs for Switching Flash Memory Programming Modes.....................................

951

CHAPTER 31

PACKAGE DRAWINGS ................................................................................................

952

31.1

25-pin Products .......................................................................................................................

952

31.2

32-pin Products .......................................................................................................................

953

31.3

48-pin Products .......................................................................................................................

954

31.4

64-pin Products .......................................................................................................................

956

APPENDIX A

REVISION HISTORY .....................................................................................................

958

A.1

Major Revisions in This Edition.............................................................................................

958

A.2 Revision History of Preceding Editions................................................................................

969

Index-14

RL78/G1A RENESAS MCU

R01UH0305EJ0200

Rev.2.00

Jul 04, 2013

CHAPTER 1 OUTLINE

<R> 1.1 Features

Ultra-low power consumption technology

VDD = single power supply voltage of 1.6 to 3.6 V which can operate a 1.8 V device at a low voltage

HALT mode

STOP mode

SNOOZE mode

RL78 CPU core

CISC architecture with 3-stage pipeline

Minimum instruction execution time: Can be changed from high speed (0.03125 μs: @ 32 MHz operation with highspeed on-chip oscillator) to ultra-low speed (30.5 μs: @ 32.768 kHz operation with subsystem clock)

Address space: 1 MB

General-purpose registers: (8-bit register × 8) × 4 banks

On-chip RAM: 2 to 4 KB

Code flash memory

Code flash memory: 16 to 64 KB

Block size: 1 KB

Prohibition of block erase and rewriting (security function)

On-chip debug function

Self-programming (with boot swap function/flash shield window function)

Data flash memory

Data flash memory: 4 KB

Back ground operation (BGO): Instructions can be executed from the program memory while rewriting the data flash memory.

Number of rewrites: 1,000,000 times (TYP.)

Voltage of rewrites: VDD = 1.8 to 3.6 V

High-speed on-chip oscillator

Select from 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz

High accuracy ±1.0 % (VDD = 1.8 to 3.6 V, TA = -20 to +85°C)

Operating ambient temperature

TA = -40 to +85°C (A: Consumer applications)

TA = -40 to +105°C (G: Industrial applications)

Power management and reset function

On-chip power-on-reset (POR) circuit

On-chip voltage detector (LVD) (Select interrupt and reset from 12 levels)

R01UH0305EJ0200 Rev.2.00

 

1

Jul 04, 2013

 

 

RL78/G1A

CHAPTER 1 OUTLINE

DMA (Direct Memory Access) controller

2 channels

Number of clocks during transfer between 8/16-bit SFR and internal RAM: 2 clocks

Multiplier and divider/multiply-accumulator

16 bits × 16 bits = 32 bits (Unsigned or signed)

32 bits ÷ 32 bits = 32 bits (Unsigned)

16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)

Serial interface

CSI: 2 to 6 channels

UART/UART (LIN-bus supported): 2 or 3 channels

I2C/Simplified I2C communication: 2 to 7 channels

Timer

16-bit timer: 8 channels

12-bit interval timer: 1 channel

Real-time clock:

1 channel (calendar for 99 years, alarm function, and clock correction function)

Watchdog timer:

1 channel (operable with the dedicated low-speed on-chip oscillator)

A/D converter

8/12-bit resolution A/D converter (VDD = 1.6 to 3.6 V)

Analog input: 13 to 28 channels

Internal reference voltage (1.45 V) and temperature sensorNote 1

I/O port

• I/O port: 19 to 56 (N-ch open drain I/O [withstand voltage of 6 V]: 2 to 4,

N-ch open drain I/O [VDD withstand voltageNote 2/EVDD withstand voltageNote 3]: 6 to 12)

Can be set to N-ch open drain, TTL input buffer, and on-chip pull-up resistor

Different potential interface: Can connect to a 1.8/2.5 V device

On-chip key interrupt function

On-chip clock output/buzzer output controller

Others

• On-chip BCD (binary-coded decimal) correction circuit

Notes 1. Can be selected only in HS (high-speed main) mode

2.Products with 25 to 48 pins

3.Products with 64 pins

Remark The functions mounted depend on the product. See 1.6 Outline of Functions.

R01UH0305EJ0200 Rev.2.00

 

2

Jul 04, 2013

 

 

RL78/G1A

 

 

 

 

 

CHAPTER 1 OUTLINE

{ ROM, RAM capacities

 

 

 

 

 

 

Flash ROM

Data flash

RAM

 

RL78/G1A

 

 

 

 

 

 

 

 

 

 

 

 

 

25 pins

32 pins

48 pins

64 pins

 

 

 

 

 

 

 

 

 

64 KB

4 KB

4 KB Note

R5F10E8E

R5F10EBE

R5F10EGE

R5F10ELE

 

48 KB

4 KB

3 KB

R5F10E8D

R5F10EBD

R5F10EGD

R5F10ELD

 

 

 

 

 

 

 

 

 

32 KB

4 KB

2 KB

R5F10E8C

R5F10EBC

R5F10EGC

R5F10ELC

 

 

 

 

 

 

 

 

 

16 KB

4 KB

2 KB

R5F10E8A

R5F10EBA

R5F10EGA

 

 

 

 

 

 

 

 

 

Note This is about 3 KB when the self-programming function and data flash function are used. (For details, see

CHAPTER 3)

R01UH0305EJ0200 Rev.2.00

 

3

Jul 04, 2013

 

 

RL78/G1A

CHAPTER 1 OUTLINE

1.2 List of Part Numbers

Figure 1-1. Part Number, Memory Size, and Package of RL78/G1A

Part No. R 5 F 1 0 E L C A x x x F B # V 0

Packing

#U0 : Tray (HWQFN, VFBGA, WFLGA) #V0 : Tray (LFQFP)

#W0 : Embossed Tape (HWQFN, VFBGA, WFLGA) #X0 : Embossed Tape (LFQFP)

Package type:

BG : VFBGA, 0.40 mm pitch

FB : LFQFP, 0.50 mm pitch

LA : WFLGA, 0.50 mm pitch

NA : HWQFN, 0.50 mm pitch

ROM number (Omitted with blank products)

Classification:

A : Consumer applications : TA = −40˚C to 85˚C

G : Industrial applications : TA = −40˚C to 105˚C

ROM capacity:

A : 16 KB

C : 32 KB

D : 48 KB

E : 64 KB

Pin count:

8 : 25-pin B : 32-pin G : 48-pin L : 64-pin

RL78/G1A group

Memory type:

F : Flash memory

Renesas MCU

Renesas semiconductor product

Caution The part number above is valid as of when this manual was issued. For the latest part number, see the web page of the target product on the Renesas Electronics website.

R01UH0305EJ0200 Rev.2.00

 

4

Jul 04, 2013

 

 

RL78/G1A

CHAPTER 1 OUTLINE

<R>

<R>

<R>

<R>

<R>

<R>

Table 1-1. List of Ordering Part Numbers

Pin count

Package

Fields of ApplicationNote 1

Ordering Part Number

 

 

 

 

25 pins

25-pin plastic WFLGA

A

R5F10E8AALA#U0, R5F10E8CALA#U0,

 

(3 × 3 mm, 0.5 mm pitch)

 

R5F10E8DALA#U0, R5F10E8EALA#U0,

 

 

 

R5F10E8AALA#W0, R5F10E8CALA#W0,

 

 

 

R5F10E8DALA#W0, R5F10E8EALA#W0

 

 

 

 

 

 

GNote 2

R5F10E8AGLA#U0, R5F10E8CGLA#U0,

 

 

 

R5F10E8DGLA#U0, R5F10E8EGLA#U0,

 

 

 

R5F10E8AGLA#W0, R5F10E8CGLA#W0,

 

 

 

R5F10E8DGLA#W0, R5F10E8EGLA#W0

 

 

 

 

32 pins

32-pin plastic HWQFN

A

R5F10EBAANA#U0, R5F10EBCANA#U0,

 

(5 × 5 mm, 0.5 mm pitch)

 

R5F10EBDANA#U0, R5F10EBEANA#U0,

 

 

 

R5F10EBAANA#W0, R5F10EBCANA#W0,

 

 

 

R5F10EBDANA#W0, R5F10EBEANA#W0

 

 

 

 

 

 

G

R5F10EBAGNA#U0, R5F10EBCGNA#U0,

 

 

 

R5F10EBDGNA#U0, R5F10EBEGNA#U0,

 

 

 

R5F10EBAGNA#W0, R5F10EBCGNA#W0,

 

 

 

R5F10EBDGNA#W0, R5F10EBEGNA#W0

 

 

 

 

48 pins

48-pin plastic LFQFP

A

R5F10EGAAFB#V0, R5F10EGCAFB#V0,

 

(7 × 7 mm, 0.5 mm pitch)

 

R5F10EGDAFB#V0, R5F10EGEAFB#V0,

 

 

 

R5F10EGAAFB#X0, R5F10EGCAFB#X0,

 

 

 

R5F10EGDAFB#X0, R5F10EGEAFB#X0

 

 

 

 

 

 

G

R5F10EBAGNA#V0, R5F10EBCGNA#V0,

 

 

 

R5F10EBDGNA#V0, R5F10EBEGNA#V0,

 

 

 

R5F10EBAGNA#X0, R5F10EBCGNA#X0,

 

 

 

R5F10EBDGNA#X0, R5F10EBEGNA#X0

 

 

 

 

 

48-pin plastic HWQFN

A

R5F10EGAANA#U0, R5F10EGCANA#U0,

 

(7 × 7 mm, 0.5 mm pitch)

 

R5F10EGDANA#U0, R5F10EGEANA#U0,

 

 

 

R5F10EGAANA#W0, R5F10EGCANA#W0,

 

 

 

R5F10EGDANA#W0, R5F10EGEANA#W0

 

 

 

 

 

 

G

R5F10EGAGNA#U0, R5F10EGCGNA#U0,

 

 

 

R5F10EGDGNA#U0, R5F10EGEGNA#U0,

 

 

 

R5F10EGAGNA#W0, R5F10EGCGNA#W0,

 

 

 

R5F10EGDGNA#W0, R5F10EGEGNA#W0

 

 

 

 

64 pins

64-pin plastic LFQFP

A

R5F10ELCAFB#V0, R5F10ELDAFB#V0, R5F10ELEAFB#V0,

 

(10 × 10 mm, 0.5 mm

 

R5F10ELCAFB#X0, R5F10ELDAFB#X0, R5F10ELEAFB#X0

 

pitch)

 

 

 

G

R5F10ELCGFB#V0, R5F10ELDGFB#V0, R5F10ELEGFB#V0,

 

 

 

 

 

R5F10ELCGFB#X0, R5F10ELDGFB#X0, R5F10ELEGFB#X0

 

 

 

 

 

64-pin plastic VFBGA

A

R5F10ELCABG#U0, R5F10ELDABG#U0, R5F10ELEABG#U0,

 

(4 × 4 mm, 0.4 mm pitch)

 

R5F10ELCABG#W0, R5F10ELDABG#W0, R5F10ELEABG#W0

 

 

 

 

 

 

GNote 2

R5F10ELCGBG#U0, R5F10ELDGBG#U0, R5F10ELEGBG#U0,

 

 

 

R5F10ELCGBG#W0, R5F10ELDGBG#W0, R5F10ELEGBG#W0

 

 

 

 

Notes 1. For the fields of application, see Figure 1-1 Part Number, Memory Size, and Package of RL78/G1A.

2.In planning

Caution The part number above is valid as of when this manual was issued. For the latest part number, see the web page of the target product on the Renesas Electronics website.

R01UH0305EJ0200 Rev.2.00

 

5

Jul 04, 2013

 

 

RL78/G1A

CHAPTER 1 OUTLINE

1.3 Pin Configuration (Top View)

1.3.1 25-pin products

• 25-pin plastic WFLGA (3 × 3 mm, 0.50 mm pitch)

Top View

Bottom View

 

5

 

4

 

3

 

2

 

1

A B C D E

E D C B A

INDEX MARK

INDEX MARK

 

A

 

 

B

C

D

E

 

 

P40/TOOL0

RESET

P03/ANI16/

P23/ANI3/

AVSS

 

5

 

 

 

 

RxD1/TO00/

(KR3)

 

5

 

 

 

 

(KR1)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P122/X2/

P137/INTP0

P02/ANI17/

P22/ANI2/

AVDD

 

4

EXCLK

 

 

 

TxD1/TI00/

(KR2)

 

4

 

 

 

 

(KR0)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P121/X1

VDD

P21/ANI1/

P11/ANI20/

P10/ANI18/

 

3

 

 

 

 

AVREFM

SI00/SDA00/

SCK00/SCL00

3

 

 

 

 

 

RxD0/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TOOLRxD

 

 

 

REGC

VSS

P30/ANI27/

P51/ANI25/

P50/ANI26/

 

2

 

 

 

 

SCK11/SCL11/

SO11/INTP2

SI11/SDA11

2

 

 

 

 

INTP3

 

INTP1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P60/SCLA0

P61/SDAA0

P31/ANI29/TI03/

P12/ANI21/

P20/ANI0/

 

1

 

 

 

 

TO03/PCLBUZ0

SO00/TxD0/

AVREFP

1

 

 

 

 

/INTP4

TOOLTxD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

 

B

C

D

E

 

Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2.Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00

 

6

Jul 04, 2013

 

 

RL78/G1A

CHAPTER 1 OUTLINE

1.3.2 32-pin products

• 32-pin plastic HWQFN (5 × 5 mm, 0.5 mm pitch)

P24/ANI4/(KR5)

P23/ANI3/(KR4)

P22/ANI2/(KR3)

P21/ANI1/AVREFM

P20/ANI0/AVREFP

P03/ANI16/RxD1/TO00/(KR2)

P02/ANI17/TxD1/TI00/(KR1)

P120/ANI19/(KR0)

INDEX MARK

AVSS

AVDD

P10/ANI18/SCK00/SCL00/(KR0)

P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1)

P12/ANI21/SO00/TxD0/TOOLTxD/(KR2)

P13/ANI22/SO20/TxD2/(KR3)

P14/ANI23/SI20/SDA20/RxD2/(KR4)

P15/ANI24/SCK20/SCL20/PCLBUZ1/(KR5)

 

 

 

 

 

 

 

 

 

exposed die pad

24 23 22 21 20 19 18 17

 

25

 

 

 

 

 

 

16

P51/SO11/INTP2

26

 

 

 

 

 

 

15

P50/ANI26/SI11/SDA11/INTP1

27

 

 

 

 

 

 

14

P30/ANI27/SCK11/SCL11/INTP3

28

 

 

 

 

 

 

13

P70/ANI28/KR0

29

 

 

 

 

 

 

12

P31/ANI29/TI03/TO03/PCLBUZ0/INTP4

30

 

 

 

 

 

 

11

P62

31

 

 

 

 

 

 

10

P61/SDAA0

32 1

2

3

4

5

6

7

8 9

P60/SCLA0

P40/TOOL0

RESET

P137/INTP0

P122/X2/EXCLK

P121/X1

REGC

VSS

VDD

 

Caution

Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).

Remarks 1.

For pin identification, see 1.4 Pin Identification.

 

2.

Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

 

 

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

<R>

3.

It is recommended to connect an exposed die pad to Vss.

R01UH0305EJ0200 Rev.2.00

 

7

Jul 04, 2013

 

 

RL78/G1A

 

 

 

 

 

 

 

 

 

 

CHAPTER 1 OUTLINE

1.3.3 48-pin products

 

 

 

 

 

 

 

 

 

 

 

• 48-pin plastic LFQFP (7 × 7 mm, 0.5 mm pitch)

 

 

 

 

 

 

 

P140/PCLBUZ0/INTP6

P02/ANI17/TxD1/TI00/(KR0)

P03/ANI16/RxD1/TO00/(KR1) P130

P20/ANI0/AVREFP

P21/ANI1/AVREFM P22/ANI2/(KR2)

P23/ANI3/(KR3)

P24/ANI4/(KR4)

P25/ANI5/(KR5)

P26/ANI6

P27/ANI7

 

 

36 35 34 33 32 31 30 29 28 27 26 25

 

P120/ANI19

37

 

 

 

 

 

 

 

 

24

AVSS

P41/ANI30/TI07/TO07

38

 

 

 

 

 

 

 

 

23

AVDD

P40/TOOL0

39

 

 

 

 

 

 

 

 

22

P150/ANI8

RESET

40

 

 

 

 

 

 

 

 

21

P10/ANI18/SCK00/SCL00/(KR0)

P124/XT2/EXCLKS

41

 

 

 

 

 

 

 

 

20

P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1)

P123/XT1

42

 

 

 

 

 

 

 

 

19

P12/ANI21/SO00/TxD0/TOOLTxD/(KR2)

P137/INTP0

43

 

 

 

 

 

 

 

 

18

P13/ANI22/SO20/TxD2/(KR3)

P122/X2/EXCLK

44

 

 

 

 

 

 

 

 

17

P14/ANI23/SI20/SDA20/RxD2/(KR4)

P121/X1

45

 

 

 

 

 

 

 

 

16

P15/ANI24/SCK20/SCL20/PCLBUZ1/(KR5)

REGC

46

 

 

 

 

 

 

 

 

15

P16/TI01/TO01/INTP5

VSS

47

 

 

 

 

 

 

 

 

14

P51/ANI25/SO11/INTP2

 

 

 

 

 

 

 

 

13

VDD

48

 

 

 

 

 

 

 

 

P50/ANI26/SI11/SDA11/INTP1

 

3 4

5

6 7 8

9 10 11 12

 

1 2

 

 

P60/SCLA0

P61/SDAA0

P62 P63

P31/ANI29/TI03/TO03/INTP4

P75/SCK01/SCL01/INTP9/KR5 P74/SI01/SDA01/INTP8/KR4

P73/SO01/KR3

P72/SO21/KR2

P71/SI21/SDA21/KR1

P70/ANI28/SCK21/SCL21/KR0

P30/ANI27/SCK11/SCL11/INTP3/RTC1HZ

 

Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2.Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00

 

8

Jul 04, 2013

 

 

RL78/G1A

 

 

 

 

 

 

 

 

 

CHAPTER 1 OUTLINE

• 48-pin plastic HWQFN (7 × 7 mm, 0.5 mm pitch)

 

 

 

 

 

 

P140/PCLBUZ0/INTP6

P02/ANI17/TxD1/TI00/(KR0)

P03/ANI16/RxD1/TO00/(KR1) P130

P20/ANI0/AVREFP

P21/ANI1/AVREFM P22/ANI2/(KR2) P23/ANI3/(KR3)

P24/ANI4/(KR4)

P25/ANI5/(KR5)

P26/ANI6

P27/ANI7

 

 

36 35 34 33 32 31 30 29 28 27 26 25

 

P120/ANI19

37

 

 

 

 

 

 

 

24

AVSS

P41/ANI30/TI07/TO07

38

 

 

 

 

 

 

 

23

AVDD

P40/TOOL0

39

 

 

 

 

 

 

 

22

P150/ANI8

RESET

40

 

 

 

 

 

 

 

21

P10/ANI18/SCK00/SCL00/(KR0)

P124/XT2/EXCLKS

41

 

 

 

 

 

 

 

20

P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1)

P123/XT1

42

 

 

 

 

 

 

 

19

P12/ANI21/SO00/TxD0/TOOLTxD/(KR2)

P137/INTP0

43

 

 

 

 

 

 

 

18

P13/ANI22/SO20/TxD2/(KR3)

P122/X2/EXCLK

44

 

 

 

 

 

 

 

17

P14/ANI23/SI20/SDA20/RxD2/(KR4)

P121/X1

45

 

 

 

 

 

 

 

16

P15/ANI24/SCK20/SCL20/PCLBUZ1/(KR5)

REGC

46

 

 

 

 

 

 

 

15

P16/TI01/TO01/INTP5

VSS

47

 

 

 

 

 

 

 

14

P51/ANI25/SO11/INTP2

 

 

 

 

 

 

 

13

VDD

48

 

 

 

 

 

 

 

P50/ANI26/SI11/SDA11/INTP1

 

3 4

5

6 7 8

9 10 11 12

 

1 2

 

 

P60/SCLA0

P61/SDAA0

P62 P63

P31/ANI29/TI03/TO03/INTP4

P75/SCK01/SCL01/INTP9/KR5 P74/SI01/SDA01/INTP8/KR4 P73/SO01/KR3

P72/SO21/KR2

P71/SI21/SDA21/KR1

P70/ANI28/SCK21/SCL21/KR0

P30/ANI27/SCK11/SCL11/INTP3/RTC1HZ

 

Caution Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2.Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00

 

9

Jul 04, 2013

 

 

RL78/G1A

CHAPTER 1 OUTLINE

1.3.4 64-pin products

• 64-pin plastic LFQFP (10 × 10 mm, 0.5 mm pitch)

 

AVSS

AVDD

P150/ANI8

P151/ANI9/(KR6)

P152/ANI10/(KR7)

P153/ANI11/(KR8)

P154/ANI12/(KR9)

P10/ANI18/SCK00/SCL00/(KR0)

P11/ANI20/SI00/SDA00/RxD0/TOOLRxD/(KR1) P12/ANI21/SO00/TxD0/TOOLTxD/(KR2) P13/ANI22/SO20/TxD2/(KR3) P14/ANI23/SI20/SDA20/RxD2/(KR4) P15/ANI24/SCK20/SCL20/(KR5) P16/TI01/TO01/INTP5

P51/ANI25/SO11/INTP2

P50/ANI26/SI11/SDA11/INTP1

 

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

P27/ANI7

49

 

 

 

 

 

 

 

 

 

32

P26/ANI6/(KR9)

50

 

 

 

 

 

 

 

 

 

31

P25/ANI5/(KR8)

51

 

 

 

 

 

 

 

 

 

30

P24/ANI4/(KR7)

52

 

 

 

 

 

 

 

 

 

29

P23/ANI3/(KR6)

53

 

 

 

 

 

 

 

 

 

28

P22/ANI2/(KR5)

54

 

 

 

 

 

 

 

 

 

27

P21/ANI1/AVREFM

55

 

 

 

 

 

 

 

 

 

26

P20/ANI0/AVREFP

56

 

 

 

 

 

 

 

 

 

25

P130

57

 

 

 

 

 

 

 

 

 

24

P04/SCK10/SCL10/(KR4)

58

 

 

 

 

 

 

 

 

 

23

P03/ANI16/SI10/SDA10/RxD1/(KR3)

59

 

 

 

 

 

 

 

 

 

22

P02/ANI17/SO10/TxD1/(KR2)

60

 

 

 

 

 

 

 

 

 

21

P01/TO00/(KR1)

61

 

 

 

 

 

 

 

 

 

20

P00/TI00/(KR0)

62

 

 

 

 

 

 

 

 

 

19

P141/PCLBUZ1/INTP7

63

 

 

 

 

 

 

 

 

 

18

P140/PCLBUZ0/INTP6

64

 

 

 

 

 

 

 

 

 

17

 

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16

 

P120/ANI19

P43

P42/TI04/TO04

P41/ANI30/TI07/TO07

P40/TOOL0

RESET

P124/XT2/EXCLKS

P123/XT1

P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS EVSS0

VDD

EVDD0

P30/ANI27/SCK11/SCL11/INTP3/RTC1HZ

P05/TI05/TO05/KR8

P06/TI06/TO06/KR9

P70/ANI28/SCK21/SCL21/KR0

P71/SI21/SDA21/KR1

P72/SO21/KR2

P73/SO01/KR3

P74/SI01/SDA01/INTP8/KR4

P75/SCK01/SCL01/INTP9/KR5

P76/INTP10/KR6

P77/INTP11/KR7

P31/ANI29/TI03/TO03/INTP4

P63

P62

P61/SDAA0 P60/SCLA0

Cautions1. Make EVSS0 pin the same potential as VSS pin.

2.Make VDD pin the potential that is higher than EVDD0 pin.

3.Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF).

Remarks 1. For pin identification, see 1.4 Pin Identification.

2.When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0pins to separate ground lines.

3.Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00

 

10

Jul 04, 2013

 

 

Renesas g1a, rl78 User Manual

RL78/G1A

CHAPTER 1 OUTLINE

• 64-pin plastic VFBGA (4 × 4 mm, 0.4 mm pitch)

 

 

Top View

 

Bottom View

 

 

 

 

 

 

8

 

 

 

 

 

 

 

7

 

 

 

 

 

 

 

6

 

 

 

 

 

 

 

5

 

 

 

 

 

 

 

4

 

 

 

 

 

 

 

3

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

1

 

 

 

 

 

A B C D E F G H

 

H G F E D C B A

 

 

 

Index mark

 

 

 

 

Pin No.

Name

Pin No.

Name

Pin No.

Name

Pin No.

Name

A1

P05/TI05/TO05/KR8

C1

P51/ANI25/SO11

E1

P153/ANI11/(KR8)

G1

AVDD

 

 

 

/INTP2

 

 

 

 

A2

P30/ANI27/SCK11

C2

P71/SI21/SDA21/KR1

E2

P154/ANI12/(KR9)

G2

P25/ANI5/(KR8)

 

/SCL11/INTP3

 

 

 

 

 

 

 

/RTC1HZ

 

 

 

 

 

 

A3

P70/ANI28/SCK21

C3

P74/SI01/SDA01

E3

P10/ANI18/SCK00

G3

P24/ANI4/(KR7)

 

/SCL21/KR0

 

/INTP8/KR4

 

/SCL00/(KR0)

 

 

A4

P75/SCK01/SCL01

C4

P16/TI01/TO01/INTP5

E4

P11/ANI20/SI00

G4

P22/ANI2/(KR5)

 

/INTP9/KR5

 

 

 

/SDA00/RxD0

 

 

 

 

 

 

 

/TOOLRxD/(KR1)

 

 

A5

P77/INTP11/KR7

C5

P15/ANI24/SCK20

E5

P03/ANI16/SI10

G5

P130

 

 

 

/SCL20/(KR5)

 

/SDA10/RxD1/(KR3)

 

 

A6

P61/SDAA0

C6

P63

E6

P41/ANI30/TI07/TO07

G6

P02/ANI17/SO10/TxD1

 

 

 

 

 

 

 

/(KR2)

A7

P60/SCLA0

C7

VSS

E7

RESET

G7

P00/TI00/(KR0)

A8

EVDD0

C8

P121/X1

E8

P137/INTP0

G8

P124/XT2/EXCLKS

B1

P50/ANI26 /SI11

D1

P13/ANI22/SO20

F1

P150/ANI8

H1

AVSS

 

/SDA11/INTP1

 

/TxD2/(KR3)

 

 

 

 

B2

P72/SO21/KR2

D2

P06/TI06/TO06/KR9

F2

P151/ANI9/(KR6)

H2

P27/ANI7

B3

P73/SO01/KR3

D3

P12/ANI21/SO00

F3

P152/ANI10/(KR7)

H3

P26/ANI6/(KR9)

 

 

 

/TxD0/TOOLTxD/(KR2)

 

 

 

 

B4

P76/INTP10/KR6

D4

P14/ANI23/SI20/

F4

P21/ANI1/AVREFM

H4

P23/ANI3/(KR6)

 

 

 

SDA20/RxD2/(KR4)

 

 

 

 

B5

P31/ANI29/TI03/TO03

D5

P42/TI04/TO04

F5

P04/SCK10/SCL10

H5

P20/ANI0/AVREFP

 

/INTP4

 

 

 

/(KR4)

 

 

B6

P62

D6

P40/TOOL0

F6

P43

H6

P141/PCLBUZ1/INTP7

B7

VDD

D7

REGC

F7

P01/TO00/(KR1)

H7

P140/PCLBUZ0/INTP6

B8

EVSS0

D8

P122/X2/EXCLK

F8

P123/XT1

H8

P120/ANI19

Cautions 1. Make EVSS0 pin the same potential as VSS pin.

2.Make VDD pin the potential that is higher than EVDD0 pin.

3.Connect the REGC pin to Vss via a capacitor (0.47 to 1 μF). Remarks 1. For pin identification, see 1.4 Pin Identification.

2.When using the microcontroller for an application where the noise generated inside the microcontroller must be reduced, it is recommended to supply separate powers to the VDD and EVDD0 pins and connect the VSS and EVSS0 pins to separate ground lines.

3.Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00

 

11

Jul 04, 2013

 

 

RL78/G1A

 

 

 

CHAPTER 1 OUTLINE

1.4 Pin Identification

 

 

 

ANI0 to ANI12,

 

PCLBUZ0, PCLBUZ1:

Programmable clock output/buzzer

ANI16 to ANI30:

Analog input

 

 

output

AVDD:

Analog power supply

REGC:

Regulator capacitance

AVSS:

Analog ground

 

Reset

RESET:

 

AVREFM:

A/D converter reference

RTC1HZ:

Real-time clock correction clock

 

potential (− side) input

 

 

(1 Hz) output

AVREFP:

A/D converter reference

RxD0 to RxD2:

Receive data

 

potential (+ side) input

SCK00, SCK01, SCK10,

 

EVDD0:

Power supply for port

SCK11, SCK20, SCK21: Serial clock input/output

EVSS0:

Ground for port

SCLA0, SCL00, SCL01,

 

EXCLK:

External clock input (main

SCL10, SCL11, SCL20,

 

 

system clock)

SCL21:

Serial clock output

EXCLKS:

External clock input

SDAA0, SDA00, SDA01,

 

 

(subsystem clock)

SDA10, SDA11, SDA20,

 

INTP0 to INTP11:

Interrupt Request from

SDA21:

Serial data input/output

 

External

SI00, SI01, SI10, SI11,

 

KR0 to KR9:

Key return

SI20, SI21:

Serial data input

P00 to P06:

Port 0

SO00, SO01, SO10,

 

P10 to P16:

Port 1

SO11, SO20, SO21:

Serial data output

P20 to P27:

Port 2

TI00, TI01, TI03 to TI07:

Timer input

P30, P31:

Port 3

TO00, TO01,

 

P40 to P43:

Port 4

TO03 to TO07:

Timer output

P50, P51:

Port 5

TOOL0:

Data input/output for tool

P60 to P63:

Port 6

TOOLRxD, TOOLTxD:

Data input/output for external device

P70 to P77:

Port 7

TxD0 to TxD2:

Transmit data

P120 to P124:

Port 12

VDD:

Power supply

P130, P137:

Port 13

VSS:

Ground

P140, P141:

Port 14

X1, X2:

Crystal oscillator (main system clock)

P150 to P154:

Port 15

XT1, XT2:

Crystal oscillator (subsystem clock)

R01UH0305EJ0200 Rev.2.00

 

12

Jul 04, 2013

 

 

RL78/G1A

CHAPTER 1 OUTLINE

1.5 Block Diagram

1.5.1 25-pin products

 

 

 

 

TIMER ARRAY

 

 

 

 

UNIT (8ch)

TI00/P02

 

 

 

 

 

ch0

 

 

TO00/P03

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ch1

 

 

 

 

 

ch2

TI03/TO03/P31 ch3

 

ch4

 

 

 

 

ch5

 

 

 

 

ch6

 

 

 

 

ch7

 

 

 

 

WINDOW

 

 

 

 

WATCHDOG

 

 

 

 

TIMER

 

 

 

 

 

RL78

CODE FLASH MEMORY

 

 

 

 

LOW-SPEED

INTERVAL

CPU

 

 

ON-CHIP

CORE

 

DATA FLASH MEMORY

TIMER

 

OSCILLATOR

 

 

 

 

 

 

 

REAL-TIME

 

 

 

 

CLOCK

 

 

 

 

SERIAL ARRAY

 

 

 

 

UNIT0 (4ch)

RAM

 

 

 

 

 

 

RxD0/P11

UART0

 

 

 

TxD0/P12

 

 

 

 

 

 

 

RxD1/P03

UART1

 

 

 

TxD1/P02

 

 

 

 

 

 

 

SCK00/P10

 

VDD

VSS

TOOLRxD/P11,

 

AVDD

AVSS

TOOLTxD/P12

SI00/P11

CSI00

 

 

 

SO00/P12

 

 

 

 

SCK11/P30

 

 

 

 

SI11/P50

CSI11

SERIAL

 

SDAA0/P61

SO11/P51

 

 

 

 

SCLA0/P60

 

INTERFACE IICA0

 

 

 

 

SCL00/P10

IIC00

 

 

 

SDA00/P11

 

 

 

 

 

 

 

SCL11/P30

 

BUZZER OUTPUT

 

 

IIC11

 

 

PCLBUZ0/P31

SDA11/P50

 

 

 

CLOCK OUTPUT

 

 

 

 

 

 

 

 

CONTROL

 

 

 

DIRECT MEMORY

 

 

 

 

ACCESS CONTROL

MULTIPLIER&

 

CRC

 

 

DIVIDER,

 

 

 

 

 

 

BCD

MULITIPLY-

 

 

 

ACCUMULATOR

 

 

 

ADJUSTMENT

 

 

 

 

 

 

PORT 0

2

P02, P03

PORT 1

3

P10 to P12

PORT 2

4

P20 to P23

PORT 3

2

P30, P31

PORT 4

 

P40

PORT 5

2

P50, P51

PORT 6

2

P60, P61

PORT 12

2

P121, P122

PORT 13

 

P137

(KEY RETURN)

(4)

(KR0/P02, KR1/P03,

KR2/P22, KR3/P23)

 

 

 

4

ANI0/P20 to

 

ANI3/P23

 

 

 

9

ANI16/P03, ANI17/P02,

 

ANI18/P10, ANI20/P11,

A/D CONVERTER

 

 

ANI21/P12, ANI25/P51,

 

 

ANI26/P50, ANI27/P30,

 

 

ANI29/P31

 

 

AVREFP/P20

 

 

AVREFM/P21

POWER ON RESET/

 

POR/LVD

VOLTAGE

 

 

CONTROL

DETECTOR

 

 

 

RESET CONTROL

 

 

ON-CHIP DEBUG

 

TOOL0/P40

SYSTEM

CONTROL RESET

HIGH-SPEED X1/P121

ON-CHIP

X2/EXCLK/P122

OSCILLATOR

VOLTAGE

REGC

REGULATOR

 

 

INTP0/P137

 

 

INTERRUPT

 

INTP1/P50

 

 

INTP2/P51

CONTROL

 

 

 

2

INTP3/P30,

 

INTP4/P31

 

 

 

 

 

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00

 

13

Jul 04, 2013

 

 

RL78/G1A

CHAPTER 1 OUTLINE

<R> 1.5.2 32-pin products

 

 

 

 

TIMER ARRAY

 

 

 

 

UNIT (8ch)

TI00/P02

 

 

 

 

 

ch0

 

 

TO00/P03

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ch1

 

 

 

 

 

ch2

TI03/TO03/P31 ch3

 

 

 

ch4

 

 

 

 

 

 

 

 

 

 

 

ch5

 

 

 

 

 

 

 

 

 

 

 

ch6

 

 

 

 

 

 

 

 

RxD2/P14

 

 

ch7

 

 

 

 

 

WINDOW

WATCHDOG

TIMER

LOW-SPEED

INTERVAL

 

 

 

ON-CHIP

 

 

 

TIMER

 

 

 

OSCILLATOR

 

 

 

 

 

 

 

 

 

RL78

CODE FLASH MEMORY

 

 

 

 

 

REAL-TIME

CPU

 

 

 

CORE

 

 

 

CLOCK

DATA FLASH MEMORY

 

 

 

SERIAL ARRAY

 

 

 

 

UNIT0 (4ch)

 

 

 

RxD0/P11

UART0

 

 

 

TxD0/P12

 

 

 

 

 

 

 

RxD1/P03

UART1

RAM

 

 

TxD1/P02

 

 

 

 

 

 

SCK00/P10

 

 

 

 

SI00/P11

CSI00

 

 

 

SO00/P12

 

 

 

 

 

 

VDD,

VSS,

TOOLRxD/P11,

SCK11/P30

 

AVDD

AVSS

TOOLTxD/P12

SI11/P50

CSI11

 

 

 

SO11/P51

 

 

 

 

SCL00/P10

IIC00

SERIAL

 

SDAA0/P61

SDA00/P11

 

 

 

INTERFACE IICA0

 

SCLA0/P60

 

 

 

 

 

 

 

SCL11/P30

IIC11

 

 

 

SDA11/P50

BUZZER OUTPUT

 

 

 

 

PCLBUZ0/P31,

 

 

 

2

 

 

 

PCLBUZ1/P15

 

 

CLOCK OUTPUT

 

 

 

 

 

 

SERIAL ARRAY

CONTROL

 

 

 

 

 

 

 

UNIT1 (2ch)

MULTIPLIER&

 

 

RxD2/P14

 

 

CRC

UART2

DIVIDER,

 

 

 

TxD2/P13

MULITIPLY-

 

 

LINSEL

 

 

 

ACCUMULATOR

 

 

SCK20/P15

CSI20

DIRECT MEMORY

 

 

SI20/P14

ACCESS CONTROL

 

 

SO20/P13

 

 

 

 

SCL20/P15

IIC20

BCD

 

 

SDA20/P14

ADJUSTMENT

 

 

 

 

 

PORT 0

2

P02, P03

 

 

 

 

6

 

PORT 1

P10 to P15

 

 

 

 

 

 

PORT 2

5

P20 to P24

 

 

 

 

 

 

PORT 3

2

P30, P31

 

 

 

 

 

 

PORT 4

 

P40

 

 

 

 

 

 

 

PORT 5

2

P50, P51

 

 

 

 

 

 

PORT 6

3

P60 to P62

 

 

 

 

 

 

PORT 7

 

P70

 

 

 

P120

 

 

PORT 12

2

P121, P122

 

 

 

 

PORT 13

 

P137

 

 

 

 

KR0/P70

(KR0/P10 to KR5/P15)

KEY RETURN 1(6) (KR0/P120, KR1/P02, KR2/P03, KR3/P22 to KR5/P24)

 

5

ANI0/P20 to

 

ANI4/P24

 

 

A/D CONVERTER

13

ANI16/P01, ANI17/P00, ANI18/P10,

ANI19/P120 to ANI24/P15, ANI26/P50,

 

 

ANI27/P30, ANI28/P70, ANI29/P31

 

 

AVREFP/P20

 

 

AVREFM/P21

POWER ON RESET/

 

POR/LVD

VOLTAGE

 

CONTROL

DETECTOR

 

 

RESET CONTROL

 

 

ON-CHIP DEBUG TOOL0/P40

SYSTEM

CONTROL RESET

HIGH-SPEED X1/P121

ON-CHIP X2/EXCLK/P122

OSCILLATOR

VOLTAGE

REGC

REGULATOR

 

 

 

 

RxD2/P14

 

 

 

 

 

 

 

 

INTP0/P137

 

 

 

 

 

2

INTP1/P50,

INTERRUPT

INTP2/P51

 

 

 

CONTROL

 

 

 

INTP3/P30,

 

2

 

INTP4/P31

 

 

 

 

 

 

 

 

 

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00

 

14

Jul 04, 2013

 

 

RL78/G1A

CHAPTER 1 OUTLINE

<R> 1.5.3 48-pin products

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TIMER ARRAY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UNIT (8ch)

 

 

 

 

TI00/P02

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ch0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TO00/P03

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TI01/TO01/P16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ch1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ch2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TI03/TO03/P31

 

 

 

 

 

 

 

 

ch3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ch4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ch5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ch6

 

 

 

 

 

TI07/TO07/P41

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ch7

 

 

 

 

 

RxD2/P14

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WINDOW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

WATCHDOG

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TIMER

 

 

 

 

LOW-

SPEED

 

 

 

 

 

 

INTERVAL

 

 

 

 

ON-

CHIP

 

 

 

 

 

 

 

 

 

 

 

 

TIMER

 

 

 

 

OSCILLATOR

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REAL-TIME

 

 

 

CODE FLASH MEMORY

RTC1HZ/P30

 

 

 

 

 

 

 

 

 

 

 

 

CLOCK

 

RL78

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CPU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SERIAL ARRAY

 

CORE

 

DATA FLASH MEMORY

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UNIT0 (4ch)

 

 

 

 

RxD0/P11

UART0

 

 

 

TxD0/P12

 

 

 

 

 

 

 

RxD1/P03

UART1

 

 

 

TxD1/P02

 

 

 

 

 

 

 

SCK00/P10

 

 

 

 

SI00/P11

CSI00

RAM

 

 

SO00/P12

 

 

 

 

 

 

 

SCK01/P75

 

 

 

 

SI01/P74

CSI01

 

 

 

SO01/P73

 

 

 

 

SCK11/P30

CSI11

 

 

 

SI11/P50

VDD,

VSS, TOOLRxD/P11,

SO11/P51

 

SCL00/P10

 

AVDD

AVSS

TOOLTxD/P12

IIC00

 

 

 

SDA00/P11

 

 

 

 

 

 

 

SCL01/P75

IIC01

 

 

 

SDA01/P74

 

 

 

 

 

 

 

SCL11/P30

IIC11

 

 

SDAA0/P61

SDA11/P50

SERIAL

 

 

 

 

 

 

INTERFACE IICA0

 

SCLA0/P60

 

 

 

 

 

SERIAL ARRAY

BUZZER OUTPUT

 

 

 

UNIT1 (2ch)

 

PCLBUZ0/P140,

 

 

 

RxD2/P14

 

 

2

UART2

CLOCK OUTPUT

PCLBUZ1/P15

TxD2/P13

 

 

 

 

 

 

 

LINSEL

CONTROL

 

 

SCK20/P15

 

MULTIPLIER&

 

CRC

SI20/P14

CSI20

DIVIDER,

 

 

 

SO20/P13

 

MULITIPLY-

 

 

 

ACCUMULATOR

 

 

SCK21/P70

 

 

 

 

 

 

 

SI21/P71

CSI21

DIRECT MEMORY

 

 

SO21/P72

 

 

 

 

ACCESS CONTROL

 

 

SCL20/P15

 

 

 

IIC20

 

 

 

SDA20/P14

 

 

 

 

BCD

 

 

SCL21/P70

 

 

 

IIC21

ADJUSTMENT

 

 

SDA21/P71

 

 

 

 

 

 

PORT 0

2

P02, P03

 

 

 

 

7

 

PORT 1

P10 to P16

 

 

 

 

 

 

PORT 2

8

P20 to P27

 

 

 

 

 

 

PORT 3

2

P30, P31

 

 

 

 

 

 

PORT 4

2

P40, P41

 

 

 

 

 

 

PORT 5

2

P50, P51

 

 

 

 

 

 

PORT 6

4

P60 to P63

 

 

 

 

 

 

PORT 7

6

P70 to P75

 

 

P120

 

 

PORT 12

4

P121 to P124

 

 

 

P130

PORT 13

 

 

P137

 

 

 

 

 

PORT 14

 

P140

 

 

 

P150

 

 

PORT 15

 

 

 

 

 

 

9 ANI0/P20 to ANI7/P2, ANI8/P150

 

ANI16/P03, ANI17/P02, ANI18/P147,

A/D CONVERTER

15 ANI19/P120, ANI20/P11 to ANI24/P15,

ANI25, P51, ANI26/P50, P30/ANI27,

 

 

ANI28/P70, ANI29/P31, ANI30/P41

 

AVREFP/P20

 

AVREFM/P21

KEY RETURN

6(6)

KR0/P70 to KR5/P75

 

 

(KR0/P10 to KR5/P15)

 

 

(KR0/P02, KR1/P03, KR2/P22 to KR5/P25)

POWER ON RESET/

VOLTAGE POR/LVD

DETECTOR CONTROL

RESET CONTROL

ON-CHIP DEBUG TOOL0/P40

SYSTEM RESET

CONTROL X1/P121

HIGH-SPEED X2/EXCLK/P122

ON-CHIP XT1/P123

OSCILLATOR XT2/EXCLKS/P124

VOLTAGE

 

REGC

REGULATOR

 

 

 

RxD2/P14 INTP0/P137

INTP1/P50, 2 INTP2/P51

INTP3/P30, INTERRUPT 2 INTP4/P31

CONTROL

INTP5/P16

INTP6/P140

INTP8/P74, 2 INTP9/P75

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00

 

15

Jul 04, 2013

 

 

RL78/G1A

CHAPTER 1 OUTLINE

1.5.4 64-pin products

 

 

 

 

TIMER ARRAY

 

 

 

 

UNIT (8ch)

TI00/P00

 

 

 

 

 

ch0

 

 

TO00/P01

 

 

 

 

 

 

 

TI01/TO01/P16

 

 

 

 

 

ch1

 

 

 

 

 

 

 

ch2

TI03/TO03/P31 ch3

TI04/TO04/P42 ch4

TI05/TO05/P05 ch5

TI06/TO06/P06 ch6

TI07/TO07/P41

ch7

RxD2/P14

 

 

 

 

 

WINDOW

 

 

 

 

 

WATCHDOG

 

 

 

 

 

TIMER

 

 

 

 

 

LOW-SPEED

INTERVAL

ON-CHIP

 

 

 

 

TIMER

OSCILLATOR

 

 

 

 

 

 

 

 

 

 

 

 

REAL-TIME

 

 

 

 

 

RTC1HZ/P30

 

 

 

CLOCK

 

 

 

 

 

 

 

 

 

 

SERIAL ARRAY

 

 

 

 

UNIT0 (4ch)

 

 

 

RxD0/P11

UART0

 

 

CODE FLASH MEMORY

TxD0/P12

RL78

 

 

 

 

RxD1/P03

 

CPU

 

 

UART1

CORE

 

DATA FLASH MEMORY

TxD1/P02

 

 

 

 

 

 

 

SCK00/P10

 

 

 

 

SI00/P11

CSI00

 

 

 

SO00/P12

 

 

 

 

SCK01/P75

 

 

 

 

SI01/P74

CSI01

 

 

 

SO01/P73

 

 

 

 

SCK10/P04

 

RAM

 

 

SI10/P03

CSI10

 

 

 

 

 

SO10/P02

 

 

 

 

SCK11/P30

 

 

 

 

SI11/P50

CSI11

 

 

 

SO11/P51

 

 

 

 

SCL00/P10

IIC00

 

 

 

SDA00/P11

VDD,

VSS,

TOOLRxD/P11,

 

SCL01/P75

 

EVDD0, EVSS0, TOOLTxD/P12

IIC01

AVDD

AVSS

SDA01/P74

 

 

 

 

 

 

 

SCL10/P04

IIC10

SERIAL

 

SDAA0/P61

SDA10/P03

INTERFACE IICA0

 

SCLA0/P60

 

 

SCL11/P30

IIC11

 

 

 

SDA11/P50

 

 

 

 

BUZZER OUTPUT

 

 

 

 

 

 

 

 

 

2

PCLBUZ0/P140,

 

 

 

PCLBUZ1/P141

 

SERIAL ARRAY

CLOCK OUTPUT

 

 

 

 

 

UNIT1 (2ch)

CONTROL

 

 

RxD2/P14

UART2

 

 

 

TxD2/P13

MULTIPLIER&

 

 

 

 

CRC

LINSEL

DIVIDER,

 

 

 

 

 

 

 

 

MULITIPLY-

 

 

SCK20/P15

 

ACCUMULATOR

 

 

 

 

 

 

SI20/P14

CSI20

DIRECT MEMORY

 

 

SO20/P13

 

 

 

 

ACCESS CONTROL

 

 

SCK21/P70

 

 

 

 

 

 

 

SI21/P71

CSI21

 

 

 

SO21/P72

 

BCD

 

 

 

 

 

 

SCL20/P15

IIC20

ADJUSTMENT

 

 

SDA20/P14

 

 

 

 

 

 

 

SCL21/P70

IIC21

 

 

 

SDA21/P71

 

 

 

 

 

 

 

PORT 0

7

P00 to P06

PORT 1

7

P10 to P16

PORT 2

8

P20 to P27

PORT 3

2

P30, P31

PORT 4

4

P40 to P43

PORT 5

2

P50, P51

PORT 6

4

P60 to P63

PORT 7

8

P70 to P77

PORT 12

 

P120

4

P121 to P124

 

PORT 13

 

P130

 

P137

 

 

PORT 14

2

P140, P141

PORT 15

5

P150 to P154

 

13

ANI0/P20 to ANI7/P27,

 

ANI8/P150 to ANI12/P154

 

 

 

 

ANI16/P03, ANI17/P02, ANI18/P10,

A/D CONVERTER

15

ANI19/P120, ANI20/P11 to ANI24/P15,

ANI25//P51, ANI26/P50, ANI27/P30,

 

 

 

 

ANI28/P70ANI29/P31, ANI30/P41

 

 

AVREFP/P20

 

 

AVREFM/P21

KEY RETURN

 

KR0/P70 to KR7/P77, KR8/P05, KR9/P06

10 (10) (KR0/P00 to KR4/P04, KR5/P22 to KR9/P26)

 

 

(KR0/P10 to KR5/P15, KR6/P151 to KR9/P154)

POWER ON RESET/

VOLTAGE

POR/LVD

DETECTOR

CONTROL

RESET CONTROL

ON-CHIP DEBUG TOOL0/P40

SYSTEM

 

 

RESET

 

CONTROL

 

 

 

 

X1/P121

 

 

 

 

 

 

 

X2/EXCLK/P122

HIGH-SPEED

 

 

 

XT1/P123

ON-CHIP

 

 

 

 

 

 

OSCILLATOR

 

 

XT2/EXCLKS/P124

 

 

 

 

 

VOLTAGE

REGC

REGULATOR

RxD2/P14

INTP0/P137

INTP1/P50, 2 INTP2/P51

INTP3/P30, 2 INTP4/P31

INTERRUPT INTP5/P16 CONTROL

INTP6/P140, 2 INTP7/P141

2

INTP8/P74,

INTP9/P75

2

INTP10/P76,

INTP11/P77

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00

 

16

Jul 04, 2013

 

 

RL78/G1A

CHAPTER 1 OUTLINE

1.6 Outline of Functions

(1/2)

 

Item

25-pin

 

32-pin

 

48-pin

64-pin

 

 

 

 

 

 

 

 

 

 

R5F10E8x

 

R5F10EBx

 

R5F10EGx

R5F10ELx

 

 

 

 

 

 

 

 

Code flash memory (KB)

16 to 64

 

16 to 64

 

16 to 64

32 to 64

 

 

 

 

 

 

 

Data flash memory (KB)

4

 

4

4

4

 

 

 

 

 

 

 

 

RAM (KB)

 

2 to 4Note1

 

2 to 4Note1

 

2 to 4Note1

2 to 4Note1

Address space

1 MB

 

 

 

 

 

 

 

 

Main system

High-speed system

X1 (crystal/ceramic) oscillation, external main system clock input (EXCLK)

 

clock

clock

1 to 20 MHz: VDD = 2.7 to 3.6 V, 1 to 8 MHz: VDD = 1.8 to 2.7 V, 1 to 4 MHz: VDD = 1.6 to 1.8 V

 

 

 

 

 

 

High-speed on-chip

HS (High-speed main) mode

: 1 to 32 MHz (VDD = 2.7 to 3.6 V),

 

 

oscillator

HS (High-speed main) mode

: 1 to 16 MHz (VDD = 2.4 to 3.6 V),

 

 

 

 

 

 

LS (Low-speed main) mode

: 1 to 8 MHz (VDD = 1.8 to 3.6 V),

 

 

 

LV (Low-voltage main) mode

: 1 to 4 MHz (VDD = 1.6 to 3.6 V)

 

 

 

 

 

 

 

Subsystem clock

 

 

XT1 (crystal) oscillation, external subsystem

 

 

 

 

 

 

clock input (EXCLKS) 32.768 kHz (TYP.)

 

 

 

 

 

 

Low-speed on-chip oscillator

15 kHz (TYP.)

 

 

 

 

 

 

 

 

 

 

General-purpose register

(8-bit register × 8) × 4 bank

 

 

 

 

 

 

 

Minimum instruction execution time

0.03125 μs (High-speed on-chip oscillator: fIH = 32 MHz operation)

 

0.05μs (High-speed system clock: fMX = 20 MHz operation)

30.5 μs (Subsystem clock: fSUB = 32.768 kHz operation)

 

Instruction set

 

Data transfer (8/16 bits)

 

 

 

 

 

 

 

Adder and subtractor/logical operation (8/16 bits)

 

 

 

 

 

Multiplication (8 bits × 8 bits)

 

 

 

 

 

 

Rotate, barrel shift, and bit manipulation (Set, reset, test, and Boolean operation), etc.

 

 

 

 

 

 

 

 

 

 

 

I/O port

 

Total

 

19

 

26

42

56

<R>

 

 

 

 

 

 

 

 

 

 

 

CMOS I/O

 

14

 

20

32

46

 

 

 

 

 

(N-ch O.D. I/O [VDD

 

(N-ch O.D. I/O [VDD

(N-ch O.D. I/O [VDD

(N-ch O.D. I/O [VDD

 

 

 

 

 

withstand voltage]: 6)

 

withstand voltage]: 9)

withstand voltage]: 11)

withstand voltage]: 12)

 

 

 

 

 

 

 

 

 

 

 

 

 

CMOS input

 

3

 

3

5

5

 

 

 

 

 

 

 

 

 

 

 

 

 

CMOS output

 

 

1

1

 

 

 

 

 

 

 

 

 

 

 

 

 

N-ch open-drain I/O

 

2

 

3

4

4

 

 

 

(6 V tolerance)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Timer

 

16-bit timer

 

 

 

8 channels

 

 

 

 

 

 

 

 

 

 

 

 

 

Watchdog timer

 

 

 

1 channel

 

 

 

 

 

 

 

 

 

 

 

 

Real-time clock (RTC)

 

1 channelNote 2

1 channel

 

 

 

 

 

 

 

 

 

 

 

 

 

12-bit interval timer (IT)

 

 

 

1 channel

 

 

 

 

 

 

 

 

 

 

 

Timer output

2 channels (PWM outputs: 1Note 3)

4 channels

7 channels

 

 

 

 

 

 

 

 

(PWM outputs: 3 Note 3)

(PWM outputs: 6 Note 3)

 

 

 

 

 

 

 

 

 

 

 

 

RTC output

 

 

1

 

 

 

 

 

 

 

 

 

• 1 Hz (subsystem clock: fSUB = 32.768 kHz)

 

 

 

 

 

 

 

 

Notes 1.

In the case of the 4 KB, this is about 3 KB when the self-programming function and data flash function are

 

 

 

used. (For details, see CHAPTER 3)

 

 

 

<R>

2.

 

Only the constant-period interrupt function when the low-speed on-chip oscillator clock (fIL) is selected.

 

3. The number of PWM outputs varies depending on the setting of channels in use (the number of masters

 

 

 

and slaves). (6.9.3 Operation as multiple PWM output function).

 

R01UH0305EJ0200 Rev.2.00

 

17

Jul 04, 2013

 

 

RL78/G1A

 

 

 

 

 

 

 

 

 

CHAPTER 1 OUTLINE

 

 

 

 

 

 

 

 

 

 

(2/2)

 

Item

 

25-pin

 

 

32-pin

48-pin

 

64-pin

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R5F10E8x

 

 

R5F10EBx

R5F10EGx

 

R5F10ELx

 

 

 

 

 

 

 

 

 

 

 

Clock output/buzzer output

 

1

 

 

2

2

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz,

• 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz,

 

 

 

 

2.5 MHz, 5 MHz, 10 MHz

2.5 MHz, 5 MHz, 10 MHz

 

 

 

 

(Main system clock: fMAIN = 20 MHz operation)

(Main system clock: fMAIN = 20 MHz operation)

 

 

 

 

 

 

 

 

 

• 256 Hz, 512 Hz, 1.024 kHz, 2.048 kHz,

 

 

 

 

 

 

 

 

 

4.096 kHz, 8.192 kHz, 16.384 kHz, 32.768 kHz

 

 

 

 

 

 

 

 

 

(Subsystem clock: fSUB = 32.768 kHz operation)

 

 

 

 

 

 

 

 

 

 

8/12-bit resolution A/D converter

13 channels

 

 

18 channels

24 channels

 

28 channels

 

 

 

 

 

 

 

 

 

 

 

Serial interface

 

 

[25-pin products]

 

 

 

 

 

 

 

 

 

CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel

 

 

 

 

 

CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel

 

 

 

 

 

[32-pin products]

 

 

 

 

 

 

 

 

 

CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel

 

 

 

 

 

CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel

 

 

 

 

 

CSI: 1 channel/simplified I2C: 1 channel/UART (UART supporting LIN-bus): 1 channel

 

 

 

[48-pin products]

 

 

 

 

 

 

 

 

 

CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel

 

 

 

 

 

CSI: 1 channel/simplified I2C: 1 channel/UART: 1 channel

 

 

 

 

 

CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel

 

 

 

[64-pin products]

 

 

 

 

 

 

 

 

 

CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel

 

 

 

 

 

CSI: 2 channels/simplified I2C: 2 channels/UART: 1 channel

 

 

 

 

 

CSI: 2 channels/simplified I2C: 2 channels/UART (UART supporting LIN-bus): 1 channel

 

 

 

 

 

 

 

 

 

 

 

 

 

I2C bus

1 channel

 

 

1 channel

1 channel

 

1 channel

 

 

 

 

 

 

 

 

 

Multiplier and divider/multiply-

• 16 bits × 16 bits = 32 bits (Unsigned or signed)

 

 

 

accumulator

 

 

• 32 bits ÷ 32 bits = 32 bits (Unsigned)

 

 

 

 

 

 

• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)

 

 

 

 

 

 

 

 

 

 

 

 

 

DMA controller

 

 

2 channels

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vectored interrupt

Internal

 

24

 

 

27

27

 

27

sources

 

 

 

 

 

 

 

 

 

 

 

 

External

 

6

 

 

6

10

 

13

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Key interrupt

 

 

 

0 ch (4 ch)Note 1

 

 

1 ch (6 ch)Note 1

6 ch

 

10 ch

 

 

 

 

 

 

 

 

 

 

 

Reset

 

 

Reset by

 

pin

 

 

 

 

 

RESET

 

 

 

 

 

 

Internal reset by watchdog timer

 

 

 

 

 

 

Internal reset by power-on-reset

 

 

 

 

 

 

Internal reset by voltage detector

 

 

 

 

 

 

• Internal reset by illegal instruction executionNote 2

 

 

 

 

 

 

Internal reset by RAM parity error

 

 

 

 

 

 

Internal reset by illegal-memory access

 

 

 

 

 

 

 

 

 

 

Power-on-reset circuit

• Power-on-reset:

 

1.51 V (TYP.)

 

 

 

 

 

 

• Power-down-reset:

1.50 V (TYP.)

 

 

 

 

 

 

 

 

 

 

Voltage detector

Rising edge :

1.67 V to 3.14 V (12 stages)

 

 

 

 

 

 

Falling edge : 1.63 V to 3.06 V (12 stages)

 

 

 

 

 

 

 

 

 

 

 

On-chip debug function

Provided

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Power supply voltage

VDD = 1.6 to 3.6 V

 

 

 

 

 

 

 

 

Operating ambient temperature

TA = −40 to +85°C (A: Consumer application), TA = −40 to +105°C (G: Industrial application)

 

 

 

 

 

 

 

 

 

 

 

 

Notes 1. Can be used by the Peripheral I/O redirection register (PIOR).

2.The illegal instruction is generated when instruction code FFH is executed.

Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator.

R01UH0305EJ0200 Rev.2.00

 

18

Jul 04, 2013

 

 

RL78/G1A

CHAPTER 2 PIN FUNCTIONS

CHAPTER 2 PIN FUNCTIONS

2.1 Port Function

Pin I/O buffer power supplies depend on the product. The relationship between these power supplies and the pins is

shown below.

 

 

 

 

Table 2-1. Pin I/O Buffer Power Supplies

(1) 25-pin products

 

 

 

 

 

 

 

 

 

 

 

 

 

Power Supply

 

 

 

 

Corresponding Pins

 

 

 

 

 

 

 

 

VDD

Port pins other than P20 to P23

 

 

 

 

 

 

 

RESET,

REGC

 

 

 

 

 

 

 

 

AVDD

• P20 to P23

 

 

 

 

 

 

 

(2) 32-pin products

 

 

 

 

 

 

 

 

 

 

 

 

 

Power Supply

 

 

 

 

Corresponding Pins

 

 

 

 

 

 

 

 

VDD

Port pins other than P20 to P24

 

 

 

 

 

 

 

RESET,

REGC

 

 

 

 

 

 

 

 

AVDD

• P20 to P24

 

 

 

 

 

 

 

(3) 48-pin products

 

 

 

 

 

 

 

 

 

 

 

 

 

Power Supply

 

 

 

 

Corresponding Pins

 

 

 

 

 

 

 

 

VDD

Port pins other than P20 to P27, P150

 

 

 

 

 

 

 

RESET,

REGC

 

 

 

 

 

 

 

 

AVDD

• P20 to P27, P150

 

 

 

 

 

 

 

(4) 64-pin products

 

 

 

 

 

 

 

 

 

 

 

 

 

Power Supply

 

 

 

 

Corresponding Pins

 

 

 

 

 

 

 

 

EVDD0

Port pins other than P20 to P27, P121 to P124, P137, and P150 to P154

 

 

 

 

 

 

 

 

VDD

• P121 to P124, P137

 

 

 

 

 

RESET,

REGC

 

 

 

 

 

 

 

 

AVDD

• P20 to P27, and P150 to P154

 

 

 

 

 

 

 

R01UH0305EJ0200 Rev.2.00

 

19

Jul 04, 2013

 

 

RL78/G1A

CHAPTER 2 PIN FUNCTIONS

Set in each port I/O, buffer, pull-up resistor is also valid for alternate functions.

2.1.1 25-pin products

(1/2)

<R>

Function

Pin

I/O

After Reset

Alternate Function

Function

 

Name

Type

 

 

 

 

 

 

 

 

 

 

 

 

P02

7-3-2

I/O

Analog input port

ANI17/TI00/TxD1/

Port 0.

 

 

 

 

 

(KR0)

2-bit I/O port.

 

 

 

 

 

 

Input/output can be specified in 1-bit units.

 

P03

8-3-2

 

 

ANI16/TO00/RxD1/

 

 

 

Use of an on-chip pull-up resistor can be specified by a

 

 

 

 

 

(KR1)

 

 

 

 

 

software setting at input port.

 

 

 

 

 

 

 

 

 

 

 

 

Input of P03 can be set to TTL input buffer.

 

 

 

 

 

 

Output of P02 and P03 can be set to N-ch open-drain

 

 

 

 

 

 

output (VDD tolerance).

 

 

 

 

 

 

Can be set to analog inputNote 1.

 

 

 

 

 

 

 

 

P10

8-3-2

I/O

Analog input port

ANI18/SCK00/SCL00

Port 1.

 

 

 

 

 

 

3-bit I/O port.

 

P11

 

 

 

ANI20/SI00/RxD0/

 

 

 

 

Input/output can be specified in 1-bit units.

 

 

 

 

 

TOOLRxD/SDA00

 

 

 

 

 

Use of an on-chip pull-up resistor can be specified by a

 

 

 

 

 

 

 

P12

7-3-2

 

 

ANI21/SO00/TxD0/

 

 

 

software setting at input port.

 

 

 

 

 

TOOLTxD

 

 

 

 

 

Input of P10 and P11 can be set to TTL input buffer.

 

 

 

 

 

 

 

 

 

 

 

 

Output of P10 to P12 can be set to N-ch open-drain

 

 

 

 

 

 

output (VDD tolerance).

 

 

 

 

 

 

Can be set to analog inputNote 1.

 

 

 

 

 

 

 

 

P20

4-3-1

I/O

Analog input port

ANI0/AVREFP

Port 2.

 

 

 

 

 

 

4-bit I/O port.

 

P21

 

 

 

ANI1/AVREFM

 

 

 

 

Input/output can be specified in 1-bit units.

 

 

 

 

 

 

 

P22

 

 

 

ANI2/(KR2)

 

 

 

 

Can be set to analog inputNote 2.

 

P23

 

 

 

ANI3/(KR3)

 

 

 

 

 

 

 

 

 

P30

7-3-1

I/O

Analog input port

ANI27/INTP3/

Port 3.

 

 

 

 

 

SCK11/SCL11

2-bit I/O port.

 

 

 

 

 

 

Input/output can be specified in 1-bit units.

 

P31

 

 

 

ANI29/TI03/TO03/

 

 

 

 

Use of an on-chip pull-up resistor can be specified by a

 

 

 

 

 

INTP4/PCLBUZ0

 

 

 

 

 

software setting at input port.

 

 

 

 

 

 

 

 

 

 

 

 

Can be set to analog inputNote 1.

 

 

 

 

 

 

 

 

P40

7-1-1

I/O

Input port

TOOL0

Port 4.

 

 

 

 

 

 

1-bit I/O port.

 

 

 

 

 

 

Input/output can be specified.

 

 

 

 

 

 

Use of an on-chip pull-up resistor can be specified by a

 

 

 

 

 

 

software setting at input port.

 

 

 

 

 

 

 

 

P50

7-3-2

I/O

Analog input port

ANI26/INTP1/SI11/

Port 5.

 

 

 

 

 

SDA11

2-bit I/O port.

 

 

 

 

 

 

Input/output can be specified in 1-bit units.

 

 

 

 

 

 

Use of an on-chip pull-up resistor can be specified by a

 

P51

7-3-1

 

 

ANI25/INTP2/SO11

software setting at input port.

 

 

 

 

 

 

Output of P50 can be set to N-ch open-drain output

 

 

 

 

 

 

(VDD tolerance).

 

 

 

 

 

 

Can be set to analog inputNote 1.

 

 

 

 

 

 

 

 

P60

12-1-1

I/O

Input port

SCLA0

Port 6.

 

 

 

 

 

 

2-bit I/O port.

 

P61

 

 

 

SDAA0

 

 

 

 

Input/output can be specified in 1-bit units.

 

 

 

 

 

 

 

 

 

 

 

 

Output of P60 and P61 can be set to N-ch open-drain

 

 

 

 

 

 

output (6 V tolerance).

 

 

 

 

 

 

 

Notes 1. Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1- bit units).

2. Digital or analog for each pin can be selected with the A/D port configuration register (ADPC).

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00

 

20

Jul 04, 2013

 

 

 

RL78/G1A

 

 

 

 

CHAPTER 2 PIN FUNCTIONS

 

 

 

 

 

 

 

 

 

(2/2)

 

 

 

 

 

 

 

 

 

 

 

 

<R>

 

 

Function

Pin

I/O

After Reset

Alternate Function

Function

 

 

 

 

Name

Type

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P121

2-2-1

Input

Input port

X1

Port 12.

 

 

 

 

 

 

 

 

 

 

2-bit input only port.

 

 

 

P122

 

 

 

X2/EXCLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P137

2-1-2

Input

Input port

INTP0

Port 13.

 

 

 

 

 

 

 

 

 

 

1-bit input only port.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2-1-1

Input

Input only pin for external reset

 

 

 

 

RESET

 

 

 

 

 

 

 

 

 

 

 

When external reset is not used, connect this pin to VDD

 

 

 

 

 

 

 

 

 

 

directly or via a resistor.

 

 

 

 

 

 

 

 

 

 

 

 

R01UH0305EJ0200 Rev.2.00

 

21

Jul 04, 2013

 

 

 

RL78/G1A

 

 

 

 

CHAPTER 2 PIN FUNCTIONS

 

2.1.2 32-pin products

 

 

 

 

 

 

 

 

 

 

 

(1/2)

 

<R>

 

Function

Pin

I/O

After Reset

Alternate Function

Function

 

 

 

Name

Type

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P02

7-3-2

I/O

Analog input

ANI17/TI00/TxD1/

Port 0.

 

 

 

 

 

 

port

(KR1)

2-bit I/O port.

 

 

 

P03

8-3-2

 

 

ANI16/TO00/RxD1/

Input/output can be specified in 1-bit units.

 

 

 

 

 

 

 

(KR2)

Use of an on-chip pull-up resistor can be specified by a

 

 

 

 

 

 

 

 

software setting at input port.

 

 

 

 

 

 

 

 

Input of P03 can be set to TTL input buffer.

 

 

 

 

 

 

 

 

Output of P02 and P03 can be set to N-ch open-drain

 

 

 

 

 

 

 

 

output (VDD tolerance).

 

 

 

 

 

 

 

 

Can be set to analog inputNote 1.

 

 

 

 

 

 

 

 

 

 

 

 

P10

8-3-2

I/O

Analog input

ANI18/SCK00/

Port 1.

 

 

 

 

 

 

port

SCL00/(KR0)

6-bit I/O port.

 

 

 

 

 

 

 

 

Input/output can be specified in 1-bit units.

 

 

 

P11

 

 

 

ANI20/SI00/RxD0/

 

 

 

 

 

 

Use of an on-chip pull-up resistor can be specified by a

 

 

 

 

 

 

 

TOOLRxD/SDA00/

 

 

 

 

 

 

 

software setting at input port.

 

 

 

 

 

 

 

(KR1)

 

 

 

 

 

 

 

Input of P10, P11, P14, and P15 can be set to TTL input

 

 

 

 

 

 

 

 

 

 

 

P12

7-3-2

 

 

ANI21/SO00/TxD0/

 

 

 

 

 

buffer.

 

 

 

 

 

 

 

TOOLTxD/(KR2)

 

 

 

 

 

 

 

Output of P10 to P15 can be set to N-ch open-drain

 

 

 

 

 

 

 

 

 

 

 

P13

 

 

 

ANI22/TxD2/SO20/

 

 

 

 

 

 

output (VDD tolerance).

 

 

 

 

 

 

 

(KR3)

Can be set to analog input.

 

 

 

P14

8-3-2

 

 

ANI23/RxD2/SI20/

 

 

 

 

 

 

 

 

SDA20/(KR4)

 

 

 

 

 

 

 

 

 

 

 

 

 

P15

 

 

 

ANI24/PCLBUZ1/

 

 

 

 

 

 

 

 

SCK20/SCL20/(KR5)

 

 

 

 

 

 

 

 

 

 

 

 

 

P20

4-3-1

I/O

Analog input

ANI0/AVREFP

Port 2.

 

 

 

 

 

 

port

 

5-bit I/O port.

 

 

 

P21

 

 

ANI1/AVREFM

 

 

 

 

 

 

 

 

Input/output can be specified in 1-bit units.

 

 

 

P22

 

 

 

ANI2/(KR3)

 

 

 

 

 

 

Can be set to analog inputNote 2.

 

 

 

 

 

 

 

 

 

 

 

P23

 

 

 

ANI3/(KR4)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P24

 

 

 

ANI4/(KR5)

 

 

 

 

 

 

 

 

 

 

 

 

 

P30

7-3-1

I/O

Analog input

ANI27/INTP3/

Port 3.

 

 

 

 

 

 

port

SCK11/SCL11

2-bit I/O port.

 

 

 

 

 

 

 

 

Input/output can be specified in 1-bit units.

 

 

 

P31

 

 

 

ANI29/TI03/TO03/

 

 

 

 

 

 

Use of an on-chip pull-up resistor can be specified by a

 

 

 

 

 

 

 

INTP4/PCLBUZ0

 

 

 

 

 

 

 

 

software setting at input port.

 

 

 

 

 

 

 

 

Can be set to analog inputNote 1.

 

 

 

 

 

 

 

 

 

 

 

 

P40

7-1-1

I/O

Input port

TOOL0

Port 4.

 

 

 

 

 

 

 

 

1-bit I/O port.

 

 

 

 

 

 

 

 

Input/output can be specified in 1-bit units.

 

 

 

 

 

 

 

 

Use of an on-chip pull-up resistor can be specified by a

 

 

 

 

 

 

 

 

software setting at input port.

 

 

 

 

 

 

 

 

 

 

Notes 1. Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1- bit units.

2. Digital or analog for each pin can be selected with the A/D port configuration register (ADPC).

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00

 

22

Jul 04, 2013

 

 

 

RL78/G1A

 

 

 

 

CHAPTER 2 PIN FUNCTIONS

 

 

 

 

 

 

 

 

 

(2/2)

 

 

 

 

 

 

 

 

 

 

 

 

<R>

 

 

Function

Pin Type

I/O

After Reset

Alternate Function

Function

 

 

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P50

7-3-2

I/O

Analog input port

ANI26/INTP1/SI11/

Port 5.

 

 

 

 

 

 

 

 

 

SDA11

2-bit I/O port.

 

 

 

P51

7-1-1

 

Input port

INTP2/SO11

Input/output can be specified in 1-bit units.

 

 

 

 

 

 

 

 

 

 

Use of an on-chip pull-up resistor can be specified by a

 

 

 

 

 

 

 

 

 

 

software setting at input port.

 

 

 

 

 

 

 

 

 

 

Output of P50 can be set to N-ch open-drain output

 

 

 

 

 

 

 

 

 

 

(VDD tolerance).

 

 

 

 

 

 

 

 

 

 

P50 can be set to analog inputNote

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P60

12-1-1

I/O

Input port

SCLA0

Port 6.

 

 

 

P61

 

 

 

SDAA0

3-bit I/O port.

 

 

 

 

 

 

 

 

 

 

Input/output can be specified in 1-bit units.

 

 

 

P62

 

 

 

 

 

 

 

 

 

Output of P60 to P62 can be set to N-ch open-drain

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

output (6 V tolerance).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P70

7-3-1

I/O

Analog input port

ANI28/KR0

Port 7.

 

 

 

 

 

 

 

 

 

 

1-bit I/O port.

 

 

 

 

 

 

 

 

 

 

Input/output can be specified.

 

 

 

 

 

 

 

 

 

 

Use of an on-chip pull-up resistor can be specified by a

 

 

 

 

 

 

 

 

 

 

software setting at input port.

 

 

 

 

 

 

 

 

 

 

Can be set to analog input Note.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P120

7-3-1

I/O

Analog input port

ANI19/(KR0)

Port 12.

 

 

 

 

 

 

 

 

 

 

1-bit I/O port and 2-bit input only port.

 

 

 

P121

2-2-1

Input

Input port

X1

 

 

 

P120 can be set to analog input Note.

 

 

 

 

 

 

 

 

 

 

 

 

 

P122

 

 

 

X2/EXCLK

 

 

 

 

 

 

For only P120, input/output can be specified.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

For only P120, use of an on-chip pull-up resistor can be

 

 

 

 

 

 

 

 

 

 

specified by a software setting at input port.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P137

2-1-2

Input

Input port

INTP0

Port 13

 

 

 

 

 

 

 

 

 

 

1bit input only port.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2-1-1

Input

Input only pin for external reset

 

 

 

RESET

 

 

 

 

 

 

 

 

 

 

When external reset is not used, connect this pin to VDD

 

 

 

 

 

 

 

 

 

 

directly or via a resistor.

 

 

 

 

 

 

 

 

 

 

 

 

Note Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1-bit

units).

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection

register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00

 

23

Jul 04, 2013

 

 

 

RL78/G1A

 

 

 

 

CHAPTER 2 PIN FUNCTIONS

 

2.1.3 48-pin products

 

 

 

 

 

 

 

 

 

 

 

(1/2)

 

<R>

 

Function

Pin

I/O

After Reset

Alternate Function

Function

 

 

 

Name

Type

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P02

7-3-2

I/O

Analog input port

ANI17/TI00/TxD1/

Port 0.

 

 

 

 

 

 

 

(KR0)

2-bit I/O port.

 

 

 

 

 

 

 

 

Input/output can be specified in 1-bit units.

 

 

 

P03

8-3-2

 

 

ANI16TO00/RxD1/

 

 

 

 

 

Use of an on-chip pull-up resistor can be specified by a

 

 

 

 

 

 

 

(KR1)

 

 

 

 

 

 

 

software setting at input port.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input of P03 can be set to TTL input buffer.

 

 

 

 

 

 

 

 

Output of P02 and P03 can be set to N-ch open-drain

 

 

 

 

 

 

 

 

output (VDD tolerance).

 

 

 

 

 

 

 

 

Can be set to analog inputNote 1.

 

 

 

 

 

 

 

 

 

 

 

 

P10

8-3-2

I/O

Analog input port

ANI18/SCK00/

Port 1.

 

 

 

 

 

 

 

SCL00/(KR0)

7-bit I/O port.

 

 

 

 

 

 

 

 

Input/output can be specified in 1-bit units.

 

 

 

P11

 

 

 

ANI20/SI00/RxD0/

 

 

 

 

 

 

Use of an on-chip pull-up resistor can be specified by a

 

 

 

 

 

 

 

TOOLRxD/SDA00/

 

 

 

 

 

 

 

software setting at input port.

 

 

 

 

 

 

 

(KR1)

 

 

 

 

 

 

 

Input of P10, P11, and P14 to P16 can be set to TTL

 

 

 

 

 

 

 

 

 

 

 

P12

7-3-2

 

 

ANI21/SO00/TxD0/

 

 

 

 

 

input buffer.

 

 

 

 

 

 

 

TOOLTxD/(KR2)

 

 

 

 

 

 

 

Output of P10 to P15 can be set to N-ch open-drain

 

 

 

 

 

 

 

 

 

 

 

P13

 

 

 

ANI22/TxD2/SO20/

 

 

 

 

 

 

output (VDD tolerance).

 

 

 

 

 

 

 

(KR3)

P10 to P15 can be set to analog inputNote 1.

 

 

 

P14

8-3-2

 

 

ANI23/RxD2/SI20/

 

 

 

 

 

 

 

 

SDA20/(KR4)

 

 

 

 

 

 

 

 

 

 

 

 

 

P15

 

 

 

ANI24/PCLBUZ1/

 

 

 

 

 

 

 

 

SCK20/SCL20/(KR5)

 

 

 

 

 

 

 

 

 

 

 

 

 

P16

8-1-1

 

Input port

TI01/TO01/INTP5

 

 

 

 

 

 

 

 

 

 

 

 

 

P20

4-3-1

I/O

Analog input port

ANI0/AVREFP

Port 2.

 

 

 

 

 

 

 

 

8-bit I/O port.

 

 

 

P21

 

 

 

ANI1/AVREFM

 

 

 

 

 

 

Input/output can be specified in 1-bit units.

 

 

 

 

 

 

 

 

 

 

 

P22

 

 

 

ANI2/(KR2)

 

 

 

 

 

 

Can be set to analog inputNote 2.

 

 

 

 

 

 

 

 

 

 

P23

 

 

 

ANI3/(KR3)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P24

 

 

 

ANI4/(KR4)

 

 

 

 

 

 

 

 

 

 

 

 

 

P25

 

 

 

ANI5/(KR5)

 

 

 

 

 

 

 

 

 

 

 

 

 

P26

 

 

 

ANI6

 

 

 

 

 

 

 

 

 

 

 

 

 

P27

 

 

 

ANI7

 

 

 

 

 

 

 

 

 

 

 

 

 

P30

7-3-1

I/O

Analog input port

ANI27/INTP3/

Port 3.

 

 

 

 

 

 

 

RTC1HZ/SCK11/

2-bit I/O port.

 

 

 

 

 

 

 

SCL11

Input/output can be specified in 1-bit units.

 

 

 

 

 

 

 

 

Use of an on-chip pull-up resistor can be specified by a

 

 

 

P31

 

 

 

ANI29/TI03/TO03/

 

 

 

 

 

 

software setting at input port.

 

 

 

 

 

 

 

INTP4

 

 

 

 

 

 

 

Can be set to analog inputNote 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes 1. Digital or analog for each pin can be selected with the port mode control register x (PMCx) (can be set in 1- bit units).

2. Digital or analog for each pin can be selected with the A/D port configuration register (ADPC).

Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). See Figure 4-8 Format of Peripheral I/O Redirection Register (PIOR).

R01UH0305EJ0200 Rev.2.00

 

24

Jul 04, 2013

 

 

 

RL78/G1A

 

 

 

 

CHAPTER 2 PIN FUNCTIONS

 

 

 

 

 

 

 

 

 

(2/2)

 

 

 

 

 

 

 

 

 

 

 

 

<R>

 

 

Function

Pin

I/O

After Reset

Alternate Function

Function

 

 

 

 

Name

Type

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P40

7-1-1

I/O

Input port

TOOL0

Port 4.

 

 

 

 

 

 

 

 

 

 

2-bit I/O port.

 

 

 

 

P41

7-3-1

 

Analog input port

ANI30/TI07/TO07

 

 

 

 

 

Input/output can be specified in 1-bit units.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Use of an on-chip pull-up resistor can be specified by a

 

 

 

 

 

 

 

 

 

 

software setting at input port.

 

 

 

 

 

 

 

 

 

 

P41 can be set to analog inputNote 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P50

7-3-2

I/O

Analog input port

ANI26/INTP1/SI11/

Port 5.

 

 

 

 

 

 

 

 

 

SDA11

2-bit I/O port.

 

 

 

 

P51

7-3-1

 

 

ANI25/INTP2/SO11

Input/output can be specified in 1-bit units.

 

 

 

 

 

 

 

 

 

 

Use of an on-chip pull-up resistor can be specified by a

 

 

 

 

 

 

 

 

 

 

software setting at input port.

 

 

 

 

 

 

 

 

 

 

Output of P50 can be set to N-ch open-drain output

 

 

 

 

 

 

 

 

 

 

(VDD tolerance).

 

 

 

 

 

 

 

 

 

 

Can be set to analog inputNote 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P60

12-1-1

I/O

Input port

SCLA0

Port 6.

 

 

 

 

P61

 

 

 

SDAA0

4-bit I/O port.

 

 

 

 

 

 

 

 

 

 

Input/output can be specified in 1-bit units.

 

 

 

 

P62

 

 

 

 

 

 

 

 

 

 

N-ch open-drain output (6 V tolerance).

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P63

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P70

7-3-1

I/O

Analog input port

ANI28/KR0/SCK21/

Port 7.

 

 

 

 

 

 

 

 

 

SCL21

6-bit I/O port.

 

 

 

 

 

 

 

 

 

 

Input/output can be specified in 1-bit units.

 

 

 

 

P71

7-1-2

 

Input port

KR1/SI21/SDA21

 

 

 

 

 

Use of an on-chip pull-up resistor can be specified by a

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P72

7-1-1

 

 

KR2/SO21

 

 

 

 

 

 

software setting at input port.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P73

 

 

 

KR3/SO01

 

 

 

 

 

 

 

Output of P71 and P74 can be set to N-ch open-drain

 

 

 

 

P74

7-1-2

 

 

KR4/INTP8/SI01/

output (VDD tolerance).

 

 

 

 

 

 

 

 

 

SDA01

P70 can be set to analog inputNote 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P75

7-1-1

 

 

KR5/INTP9/SCK01/

 

 

 

 

 

 

 

 

 

 

SCL01

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P120

7-3-1

I/O

Analog input port

ANI19

Port 12.

 

 

 

 

 

 

 

 

 

 

1-bit I/O port and 4-bit input only port.

 

 

 

 

P121

2-2-1

Input

Input port

X1