Philips UDA1380 Technical data
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UDA1380
Stereo audio coder-decoder
for MD, CD and MP3
Product specification 2002 Sep 16
Philips Semiconductors Product specification
Stereo audio coder-decoder
for MD, CD and MP3
CONTENTS
1 FEATURES
1.1 General
1.2 Multiple format data input interface
1.3 Multiple format data output interface
1.4 ADC front-end features
1.5 DAC features
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 QUICK REFERENCE DATA
5 ORDERING INFORMATION
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION
8.1 Clock modes
8.2 ADC analog front-end
8.3 Decimation filter (ADC)
8.4 Interpolation filter (DAC)
8.5 Noise shaper
8.6 FSDAC
8.7 Headphone driver
8.8 Digital and analog mixers (DAC)
8.9 Application modes
8.10 Power-on reset
8.11 Power-down requirements
8.12 Plop prevention
8.13 Digital audio data input and output
9 L3-BUS INTERFACE DESCRIPTION
9.1 Introduction
9.2 Device addressing
9.3 Slave address
9.4 Register addressing
9.5 Data write mode
9.6 Data read mode
10 I2C-BUS INTERFACE DESCRIPTION
10.1 Addressing
10.2 WRITE cycle
10.3 READ cycle
11 REGISTER MAPPING
11.1 Evaluation modes and clock settings
11.2 I2S-bus input and output settings
11.3 Power control settings
11.4 Analog mixer settings
11.5 Reserved
11.6 Master volume control
11.7 Mixer volume control
11.8 Mode, bass boost and treble
UDA1380
11.9 Master mute, channel de-emphasis and mute
11.10 Mixer, silence detector and oversampling
settings
11.11 Decimator volume control
11.12 PGA settings and mute
11.13 ADC settings
11.14 AGC settings
11.15 Restore L3 default values (software reset)
11.16 Headphone driver and interpolation filter
(read-out)
11.17 Decimator read-out
12 LIMITING VALUES
13 HANDLING
14 THERMAL CHARACTERISTICS
15 QUALITY SPECIFICATION
16 DC CHARACTERISTICS
17 AC CHARACTERISTICS
18 TIMING
19 APPLICATION INFORMATION
20 PACKAGE OUTLINES
21 SOLDERING
21.1 Introduction to soldering surface mount
packages
21.2 Reflow soldering
21.3 Wave soldering
21.4 Manual soldering
21.5 Suitability of surface mount IC packages for
wave and reflow soldering methods
22 DATA SHEET STATUS
23 DEFINITIONS
24 DISCLAIMERS
25 PURCHASE OF PHILIPS I2C COMPONENTS
2002 Sep 16 2
Philips Semiconductors Product specification
Stereo audio coder-decoder
for MD, CD and MP3
1 FEATURES
1.1 General
• 2.4 to 3.6 V power supply
• 5 V tolerant digital inputs (at 2.4 to 3.6 V power supply)
• 24-bit data path for Analog-to-Digital Converter (ADC)
and Digital-to-Analog Converter (DAC)
• Selectable control via L3-bus microcontroller interface
or I2C-bus interface; choice of 2 device addresses in
L3-bus and I2C-bus mode
Remark: This device does not have a static mode
• Supports sample frequencies from 8 to 55 kHz for the
ADC part, and 8 to 100 kHz forthe DAC part. The ADC
cannot support DVD audio (96 kHz audio), only
Mini-Disc (MD), Compact-Disc (CD) and Moving Picture
Experts Group Layer-3 Audio (MP3). For playback
8 to 100 kHz is specified. DVD playback is supported
• Power management unit:
– Separate power control for ADC, Automatic Volume
Control (AVC), DAC, Phase Locked Loop (PLL) and
headphone driver
– Analog blocks like ADC and Programmable Gain
Amplifier (PGA) have a block to power-down the bias
circuits
– When ADC and/or DAC are powered-down, also the
clocks to these blocks are stopped to save power
Remark: By default, when the IC is powered-up, the
complete chip will be in the Power-down mode.
• ADC part and DAC part can run at different frequencies,
either system clock or Word Select PLL (WSPLL)
• ADC and PGA plus integrated high-pass filter to cancel
DC offset
• Thedecimationfilter is equipped with a digital Automatic
Gain Control (AGC)
• Mono microphone input with Low Noise Amplifier (LNA)
of 29 dB fixed gain and Variable Gain Control (VGA)
from 0 to 30 dB in steps of 2 dB
• Integrated digital filter plus DAC
• Separate single-ended line output and one stereo
headphone output, capable of driving a 16 Ω load. The
headphone driver has a built-in short-circuit protection
with status bits which can be read out from the
L3-bus or I2C-bus interface
• Digital silence detection in the interpolator (playback)
with read-out status via L3-bus or I2C-bus interface
• Easy application.
UDA1380
1.2 Multiple format data input interface
• Slave BCK and WS signals
• I2S-bus format
• MSB-justified format compatible
• LSB-justified format compatible.
1.3 Multiple format data output interface
• Select option for digital output interface: either the
decimatoroutput(ADC signal)ortheoutputsignalofthe
digital mixer which is in the interpolator DSP
• Selectable master or slave BCK and WS signals for
digital ADC output
Remark:SYSCLKmustbeappliedinWSPLLmodeand
master mode
• I2S-bus format
• MSB-justified format compatible
• LSB-justified format compatible.
1.4 ADC front-end features
• ADC plus decimator can run at either WSPLL,
regenerating the clock from WSI signal, or on SYSCLK
• Stereo line input with PGA: gain range from 0 to 24 dB
in steps of 3 dB
• LNA with 29 dB fixed gain for mono microphone input,
including VGA with gain from 0 to 30 dB in steps of 2 dB
• Digital left and right independent volume control and
mute from +24 to −63.5 dB in steps of 0.5 dB.
2002 Sep 16 3
Philips Semiconductors Product specification
Stereo audio coder-decoder
for MD, CD and MP3
1.5 DAC features
• DAC plus interpolator can run at either WSPLL
(regenerating the clock from WSI) or at SYSCLK
• Separate digital logarithmic volume control for left and
right channels via L3-bus or I2C-bus from 0 to −78 dB in
steps of 0.25 dB
• Digital tone control, bass boost and treble via L3-bus or
I2C-bus interface
• Digital de-emphasis for sample frequencies of:
32, 44.1, 48 and 96 kHz via L3-bus or I2C-bus interface
• Cosine roll-off soft mute function
• Output signal polarity control via L3-bus or I2C-bus
interface
• Digital mixer for mixing ADC output signal and digital
serial input signal, if they run at the same sampling
frequency.
2 APPLICATIONS
This audio coder-decoder is suitable for home and
portable applications like MD, CD and MP3 players.
3 GENERAL DESCRIPTION
The UDA1380 is a stereo audio coder-decoder, available
in TSSOP32 (UDA1380TT) and HVQFN32 (UDA1380HN)
packages. All functions and features are identical for both
package versions. The term ‘UDA1380’ in this document
refers to both UDA1380TT and UDA1380HN, unless
particularly specified.
UDA1380
The DAC part is equipped with a stereo line output and a
headphonedriveroutput.Theheadphonedriveriscapable
of driving a 16 Ω load. The headphone driver is also
capable of driving a headphone without the need for
external DC decoupling capacitors, since the headphone
can be connected to a pin V
In addition, there is a built-in short-circuit protection for the
headphone driver output which, in case of short-circuit,
limits the current through the operational amplifiers and
signals the event via its L3-bus or I2C-bus register.
The UDA1380 also supports an application mode in which
the coder-decoder itself is not running, but an analog
signal, for instance coming from an FM tuner, can be
controlled in gain, and applied to the output via the
headphone driver and line outputs.
The UDA1380 supports the I2S-bus data format with word
lengths of up to 24 bits, the MSB-justified data format with
word lengths of up to 24 bits and the LSB-justified serial
data format with word lengths of 16, 18, 20 or 24 bits
(LSB-justified 24 bits is only supported for the output
interface).
The UDA1380 has sound processing features in playback
mode, de-emphasis, volume, mute, bass boost and treble
which can be controlled by the L3-bus or I2C-bus interface.
REF(HP)
on the chip.
The front-end of the UDA1380 is equipped with a stereo
line input, which has a PGA control, and a mono
microphone input with an LNA and a VGA. The digital
decimation filter is equipped with an AGC which can be
used in case of voice-recording.
2002 Sep 16 4
Philips Semiconductors Product specification
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
4 QUICK REFERENCE DATA
V
DDD=VDDA(AD)=VDDA(DA)=VDDA(HP)
unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
V
DDA(AD)
V
DDA(DA)
V
DDA(HP)
ADC analog supply voltage 2.4 3.0 3.6 V
DAC analog supply voltage 2.4 3.0 3.6 V
headphone analog supply
voltage
V
DDD
I
DDA(AD)
I
DDA(DA)
I
DDA(HP)
digital supply voltage 2.4 3.0 3.6 V
ADC analog supply current one ADC and microphone amplifier
DAC analog supply current operating mode; fs= 48 kHz − 3.4 − mA
headphone analog supply
current
I
DDD
I
DD(tot)
T
amb
digital supply current operating mode; fs= 48 kHz − 10.0 − mA
total supply current playback mode (without headphone);
ambient temperature −40 − +85 °C
= 3.0 V; T
enabled; fs= 48 kHz
two ADCs and PGA enabled;
f
all ADCs and PGAs power-down, but
AVC activated; f
all ADCs, PGAs and LNA
power-down; f
Power-down mode; f
no signal applied (quiescent current) − 0.9 − mA
Power-down mode − 0.1 −µA
playback mode; f
record mode; f
Power-down mode; f
fs=48kHz
playbackmode (with headphone); no
signal; f
record mode (audio); f
record mode (speech); f
record mode (audio and speech);
f
fully operating; f
signal mix-in operating, using
FSDAC, AVC(with headphone); no
signal; f
Power-down mode; f
=25°C; RL=5kΩ; all voltages measured with respect to ground;
amb
2.4 3.0 3.6 V
− 4.5 − mA
− 7.0 − mA
=48kHz
s
− 3.3 − mA
=48kHz
s
− 1.0 −µA
=48kHz
s
= 48 kHz − 0.1 −µA
s
= 48 kHz − 5.0 − mA
s
= 48 kHz − 6.0 − mA
s
= 48 kHz − 1.0 −µA
s
− 9.0 − mA
− 8.8 − mA
=48kHz
s
= 48 kHz − 13.0 − mA
s
=48kHz − 10.0 − mA
s
− 13.0 − mA
=48kHz
s
=48kHz − 23.0 − mA
s
− 12.0 − mA
=48kHz
s
= 48 kHz − 2.0 −µA
s
2002 Sep 16 5
Philips Semiconductors Product specification
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Analog-to-digital converter (supply voltage 3.0 V)
D
o
(THD+N)/S
digital output level at 0 dB setting; V
total harmonic distortion-
48
plus-noise to signal ratio at
at −1 dBFS −−85 − dB
at −60 dBFS; A-weighted −−37 − dB
fs=48kHz
S/N
48
signal-to-noise ratio at
Vi= 0 V; A-weighted − 97 − dB
fs=48kHz
α
cs
channel separation − 100 − dB
LNA input plus analog-to-digital converter (supply voltage 3.0 V)
V
i(rms)
input voltage (RMS value) at 0 dBFS digital output; 2.2 kΩ
source impedance
(THD+N)/S
total harmonic
48
distortion-plus-noise to
at 0 dB −−74 − dB
at −60 dB; A-weighted −−25 − dB
signal ratio at fs= 48 kHz
S/N
48
signal-to-noise ratio at
Vi= 0 V; A-weighted − 85 − dB
fs=48kHz
α
cs
channel separation − 70 − dB
Digital-to-analog converter (supply voltage 3.0 V)
V
o(rms)
(THD+N)/S
output voltage (RMS value) at 0 dBFS digital input; note 1 − 0.9 − V
total harmonic
48
distortion-plus-noise to
at 0 dB −−88 − dB
at −60 dB; A-weighted −−40 − dB
signal ratio at fs= 48 kHz
(THD+N)/S
total harmonic
96
distortion-plus-noise to
at 0 dB −−80 − dB
at −60 dB; A-weighted −−37 − dB
signal ratio at fs= 96 kHz
S/N
48
signal-to-noise ratio at
code = 0; A-weighted − 100 − dB
fs=48kHz
S/N
96
signal-to-noise ratio at
code = 0; A-weighted − 97 − dB
fs=96kHz
α
cs
channel separation − 90 − dB
AVC (line input via ADC input; output on line output and headphone driver; supply voltage 3.0 V)
V
i(rms)
(THD+N)/S
input voltage (RMS value) − 150 − mV
total harmonic
48
distortion-plus-noise to
at 0 dB −−80 − dB
at −60 dB; A-weighted −−28 − dB
signal ratio at fs= 48 kHz
S/N
48
signal-to-noise ratio at
Vi= 0 V; A-weighted − 87 − dB
fs=48kHz
= 1.0 V −−1−dBFS
i(rms)
−−35 mV
2002 Sep 16 6
Philips Semiconductors Product specification
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Headphone driver (supply voltage 3.0 V)
P
o(rms)
(THD+N)/S
S/N
48
α
cs
Power consumption (supply voltage 3.0 V; fs= 48 kHz)
output power (RMS value) at 0 dBFS digital input; RL=16Ω− 35 − mW
total harmonic
48
distortion-plus-noise to
signal ratio at fs= 48 kHz
signal-to-noise ratio at
at 0 dB; RL=16Ω−−60 − dB
at 0 dB; R
=5kΩ−−82 − dB
L
at −60 dB; A-weighted −−24 − dB
code = 0; A-weighted − 90 − dB
fs=48kHz
channel separation RL=16Ω using pin V
REF(HP)
; no DC
− 60 − dB
decoupling capacitors; note 2
R
=16Ω single-ended application
L
− 68 − dB
with DC decoupling capacitors
(100 µF typical)
R
=32Ω single-ended application
L
− 74 − dB
with DC decoupling capacitors
(100 µF typical)
P
tot
total power dissipation playback mode (without headphone) − 27 − mW
playback mode (with headphone) − 27 − mW
record mode (audio) − 39 − mW
record mode (speech) − 31 − mW
record mode (audio and speech) − 40 − mW
full operation − 69 − mW
Power-down mode − 6 −µW
Notes
1. The output voltage of the DAC is proportional to the DAC power supply voltage.
2. Channel separation performance is measured at the IC pin.
5 ORDERING INFORMATION
TYPE
NUMBER
NAME DESCRIPTION VERSION
PACKAGE
UDA1380TT TSSOP32 plastic thin shrink small outline package; 32 leads;
body width 6.1 mm; lead pitch 0.65 mm
UDA1380HN HVQFN32 plastic, heatsink very thin quad flat package; no leads;
32 terminals; body 5 × 5 × 0.85 mm
SOT487-1
SOT617-1
2002 Sep 16 7
Philips Semiconductors Product specification
Stereo audio coder-decoder
for MD, CD and MP3
6 BLOCK DIAGRAM
handbook, full pagewidth
VINL
VINM
RESET
SYSCLK
31 (27)
3 (31)
5 (1)
13 (9)
V
DDA(AD)
32 (28)
+29 dB
V
SSA(AD)
AGC
V
30 (26)
SDCPGA PGA
SDCMIC AMP
ADC
DECIMATION FILTER
DC-CANCELLATION FILTER
ADCP
4 (32)
V
ADCN
2 (30)
ADC
SDC
n.c.
V
REF
29 (25)
V
DDD
6 (2)
UDA1380TT
(UDA1380HN)
V
DDA(DA)
26 (22)
1 (29)
UDA1380
VINR
DATAO
BCKO
WSO
BCKI
WSI
DATAI
VOUTL
Pin numbers for UDA1380HN in parentheses.
9 (5)
7 (3)
8 (4)
10 (6)
11 (7)
12 (8)
WSPLL
27 (23)
DATA OUTPUT
INTERFACE
DATA INPUT
INTERFACE
ANA VC
HEADPHONE
DRIVER
DSP FEATURES
INTERPOLATION FILTER
NOISE SHAPER
FSDAC
V
DDA(HP)
FSDAC
22 (18)24 (20)23 (19) 28 (24)
V
REF(HP)
V
HEADPHONE
DRIVER
20 (16) 21 (17)
VOUTRHPVOUTLHP
SSA(HP)
L3 or I2C-BUS
INTERFACE
ANA VC
V
SSA(DA)
V
17 (13)
16 (12)
18 (14)
19 (15)
15 (11)
25 (21)
14 (10)
SSD
L3CLOCK/SCL
L3MODE
L3DATA/SDA
SEL_L3_IIC
RTCB
VOUTR
MGU526
Fig.1 Block diagram.
2002 Sep 16 8
Philips Semiconductors Product specification
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
7 PINNING
SYMBOL
UDA1380TT UDA1380HN
VINR 1 29 analog pad ADC input right, also connected
V
ADCN
VINM 3 31 analog pad microphone input
V
ADCP
RESET 5 1 5 V tolerant digital input pad;
V
DDD
BCKO 7 3 5 V tolerant digital bidirectional
WSO 8 4 word select output
DATAO 9 5 output pad; push-pull; 5 ns
BCKI 10 6 5 V tolerant digital input pad;
WSI 11 7 word select input
DATAI 12 8 data input
SYSCLK 13 9 system clock 256f
V
SSD
RTCB 15 11 5 V tolerant digital input pad;
L3MODE 16 12 5 V tolerant digital bidirectional
L3CLOCK/SCL 17 13 5 V tolerant digital input pad;
L3DATA/SDA 18 14 I
SEL_L3_IIC 19 15 5 V tolerant digital input pad;
V
SSA(HP)
VOUTRHP 21 17 analog pad headphone output right
V
REF(HP)
VOUTLHP 23 19 analog pad headphone output left
V
DDA(HP)
VOUTR 25 21 analog pad DAC output right
V
DDA(DA)
VOUTL 27 23 analog pad DAC output left
PIN
TYPE DESCRIPTION
to the mixer input of the FSDAC
2 30 analog pad ADC reference voltage
4 32 analog pad ADC reference voltage
pin RESET with pull-down, for
push-pull; TTL with hysteresis;
making Power-On Reset (POR)
pull-down
6 2 digital supply pad digital supply voltage
bit clock output
pad; push-pull input; 3-state
output; 5 ns slew-rate control;
TTL with hysteresis
data output
slew-rate control; CMOS
bit clock input
push-pull; TTL with hysteresis
, 384fs,
s
512fsor 768fs input
14 10 digital ground pad digital ground
test control input, to be connected
push-pull; TTL with hysteresis;
to digital ground in the application
pull-down
L3-bus mode input or pin A1 for
pad; push-pull input; 3-state
I2C-bus slave address setting
output; 5 ns slew-rate control;
TTL with hysteresis
2
L3-bus or I
C-bus clock input
push-pull; TTL with hysteresis
2
C-bus pad; 400 kHz I2C-bus
specification
L3-bus or I2C-bus data input and
output
input channel select
push-pull; TTL with hysteresis
20 16 analog ground pad headphone ground
22 18 analog pad headphone reference voltage
24 20 analog supply pad headphone supply voltage
26 22 analog supply pad DAC analog supply voltage
2002 Sep 16 9
Philips Semiconductors Product specification
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
SYMBOL
UDA1380TT UDA1380HN
V
SSA(DA)
V
REF
V
SSA(AD)
VINL 31 27 analog pad ADC input left, also connected to
V
DDA(AD)
handbook, halfpage
V
V
RESET
DATAO
SYSCLK
L3MODE
VINR
ADCN
VINM
ADCP
V
DDD
BCKO
WSO
BCKI
WSI
DATAI
V
SSD
RTCB
1
2
3
4
5
6
7
8
UDA1380TT
9
10
11
12
13
14
15
16
PIN
TYPE DESCRIPTION
28 24 analog ground pad DAC analog ground
29 25 analog pad ADC and DAC reference voltage
30 26 analog ground pad ADC analog ground
the mixer input of the FSDAC
32 28 analog supply pad ADC analog supply voltage
V
32
DDA(AD)
31
VINL
handbook, halfpage
DATAI
WSI
BCKI
DATAO
WSO
BCKO
V
DDD
RESET
8
7
6
5
4
3
2
1
SSD
SYSCLK
V
9
10
31
32
VINM
ADCP
V
RTCB
L3MODE
L3CLOCK/SCL
11
13
UDA1380HN
282627
29
30
VINR
ADCN
V
DDA(AD)
V
SSA(HP)
L3DATA/SDA
SEL_L3_IIC
V
16
141215
17
18
19
20
21
22
23
24
25
REF
VINL
V
SSA(AD)
V
VOUTRHP
V
REF(HP)
VOUTLHP
V
DDA(HP)
VOUTR
V
DDA(DA)
VOUTL
V
SSA(DA)
MGW778
MGU525
V
30
SSA(AD)
V
29
REF
V
28
SSA(DA)
27
VOUTL
V
26
DDA(DA)
25
VOUTR
V
24
DDA(HP)
23
VOUTLHP
V
22
REF(HP)
21
VOUTRHP
V
20
SSA(HP)
19
SEL_L3_IIC
18
L3DATA/SDA
17
L3CLOCK/SCL
Fig.2 Pin configuration UDA1380TT.
2002 Sep 16 10
Fig.3 Pin configuration UDA1380HN.
Philips Semiconductors Product specification
Stereo audio coder-decoder
for MD, CD and MP3
8 FUNCTIONAL DESCRIPTION
8.1 Clock modes
There are two clock systems:
• A SYSCLK signal, coming from the system or the SSA1
chip
• A WSPLL which generates the internal clocks from the
incoming WSI signal.
The system frequency applied to pin SYSCLK is
selectable. The options are 256fs, 384fs, 512fsand 768fs.
Thesystemclockmustbelockedinfrequencytothedigital
interface signals.
Remark: Since there is neither a fixed reference clock
available in the IC itself, nor a fixed clock available in the
systemtheICis in, there is no auto sample rate conversion
detection circuitry.
The system can run in several modes, using the two clock
systems:
• Both the DAC and the ADC part can run at the applied
SYSCLK input. In this case the WSPLL is
powered-down
• The ADC can run at the SYSCLK input, and at the same
time the DAC part can run (at a different frequency) at
the clock re-generated from the WSI signal
• The ADC and the DAC can both run at the clock
regenerated from the WSI signal.
UDA1380
8.1.1 WSPLL REQUIREMENTS
TheWSPLLismeant to lock onto the WSI input signal, and
regenerates a 256fsand 128fs signal for the FSDAC and
the interpolator core (and for the decimator if needed).
Since the operating range of the WSPLL is from
75 to 150 MHz, the complete range of 8 to 100 kHz
sampling frequency must be divided into smaller parts, as
given in Table 1, using Fig.4 as a reference. This means
that the user must set the input range of the WSI input
signal.
In case the SYSCLK is used for clocking the complete
system(decimatorincludinginterpolator)theWSPLLmust
be powered-down with bit ADC_CLK via the L3-bus
or I2C-bus.
The SEL_LOOP_DIV[1:0] can be controlled by the PLL1
and PLL0 bits in the L3-bus or I2C-bus register.
handbook, halfpage
DIV1
128f
(digital parts)
256f
(ADC and FSDAC)
s
VCOWSI
PRE1
s
MGU527
Fig.4 WSPLL set-up.
Table 1 WSPLL divider settings
WORD SELECT
FREQUENCY (kHz)
SEL_LOOP_DIV[1:0] PRE1 DIV1
6.25 to 12.5 00 8 1536
12.5 to 25 01 4 1536
25 to 50 10 2 1536
50 to 100 11 2 768
2002 Sep 16 11
VCO FREQUENCY
(MHz)
76 to 153
Philips Semiconductors Product specification
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
8.1.2 CLOCK DISTRIBUTION
Figure 5 shows the main clock distribution for the SYSCLK domain and the WSPLL clock domain.
For power saving reasons each clock signal inside the system must be controlled and enabled via a separate bit in the
L3-bus and I2C-bus registers (ADC_CLK).
The DAC part of the UDA1380 can operate from 8 to 100 kHz sampling frequency (fs). This applies to the DAC part only;
the ADC part can run from 8 to 55 kHz.
handbook, full pagewidth
SYSCLK
CLK_DIV
256/384/512/768f
128f
s
s
enable clock
ADC_CLK
128f
s
enable
clock
ADC
DECIMATOR
L3 or I2C-BUS
REGISTER
DECIMATOR
I2S-BUS
OUTPUT BLOCK
2
I
INPUT BLOCK
L3 or I2C-BUS
REGISTER
INTERPOLATOR
INTERPOLATOR
FSDAC
MGU528
WSI
WSPLL
256f
enable
clock
s
128f
s
128f
s
DAC_CLK
enable clock
Fig.5 Clock routing for the main blocks inside the coder-decoder.
S-BUS
2002 Sep 16 12
Philips Semiconductors Product specification
Stereo audio coder-decoder
for MD, CD and MP3
8.2 ADC analog front-end
The analog front-end of the UDA1380 consists of one
stereo ADC with a selector in front of it (see Fig.6). Using
this selector one can either select the microphone input
with the microphone amplifier (LNA) with a fixed 29 dB
gain and VGA (no PGA, since a real microphone amplifier
ismuchbetterwith respect to noise), or the line input which
has a PGA for having 0 or 6 dB gain (for supporting 1 and
2 V (RMS)input).The PGA also provides gain control from
0 to 24 dB in steps of 3 dB.
Remarks:
• TheinputimpedanceofthePGA(lineinput)is12 kΩ,for
the LNA this is 5 kΩ
• TheLNAis standard equipped with a microphone power
supply. Since this normally requires two extra pins, this
feature will not be used inside the UDA1380. Instead,
the microphone supply block is replaced by the VGA
block.
UDA1380
8.2.1 APPLICATIONS AND POWER-DOWN MODES
The following Power-down modes and functional modes
are supported:
• Power-down mode in which the power consumption is
very low (only leakage currents)
In this mode there is no reference voltage at the line
input
• Line input mode, in which the PGA can be used
• Microphone mode, in which the rest of the non-used
PGAs and ADCs are powered-down
• Mixed PGA and LNA mode: one line input and one
microphone input.
More information on the analog frond-end is given in
Section 8.11.1.
handbook, full pagewidth
VINL
1
(29)
31
(27)
3
(31)
PGA ADC
PGA
LNA SDC
SDC
SDC
VINR
VINM
Pin numbers for UDA1380HN in parentheses.
Fig.6 Analog front-end.
8.2.2 LNA WITH VGA
The LNA is equipped with a VGA. The function of the VGA
is to have additional variable analog gain from 0 to 30 dB
in steps of 2 dB. This provides more flexibility in the choice
of the microphone.
SEL_MIC
bitstream
right
ADC
bitstream
left
MGU530
8.2.3 APPLICATIONS WITH 2V(RMS) INPUT
For the line input it is preferable to have 0 dB and 6 dB
gain settings in order to be able to apply both
1 and 2 V (RMS) input signals, using a series resistance.
For this purpose a PGA is used which has0 to 24 dB gain,
in steps of 3 dB.
2002 Sep 16 13
Philips Semiconductors Product specification
Stereo audio coder-decoder
for MD, CD and MP3
In applications in which a 2 V (RMS) input signal is used,
a12kΩresistor must be used in series with the input of the
ADC(see Fig.7). This forms a voltage divider together with
the internal ADC resistor and ensures that the voltage,
applied to the input of the IC, never exceeds 1 V (RMS).
Using this application for a 2 V (RMS) input signal, the
switchmust be set to 0 dB.When a 1 V (RMS) input signal
is applied to the ADC in the same application, the gain
switch must be set to 6 dB.
An overview of the maximum input voltages allowed
againstthepresenceofanexternalresistor and the setting
of the gain switch is given in Table 2; the power supply
voltage is assumed to be 3 V.
handbook, halfpage
input signal
2 V (RMS)
Pin numbers for UDA1380HN in parentheses.
Fig.7 ADC front-end with PGA (line input).
external
resistor
12 kΩ
VINL,
VINR
31,
1
(27,
29)
12 kΩ
V
REF
PGA
V
DDA
= 3 V
MGU529
UDA1380
Table 3 Decimation filter characteristics
ITEM CONDITION VALUE (dB)
Pass-band ripple 0 to 0.45f
Stop band >0.55f
Dynamic range 0 to 0.45f
Digital output
level
8.3.1 O
VERLOAD DETECTION
at 0 dB input
analog
s
s
s
TheUDA1380is equipped with an overload detector which
can be read out from the L3-bus or I2C-bus interface.
In practice the output is used to indicate whenever the
output data, in either the output of the left or right channel,
exceeds −1 dB (the actual figure is −1.16 dB) of the
maximum possible digital swing. When this condition is
detected the output bit OVERFLOW in the L3-bus register
is forced to logic 1 for at least 512fs cycles (11.6 ms at
fs= 44.1 kHz). This time-out is reset for each infringement.
8.3.2 VOLUME CONTROL
The decimator is equipped with a digital volume control.
This volume control is separate for left and right and can
be set with bits ML_DEC [7:0] and bits MR_DEC [7:0] via
the L3-bus or I2C-bus interface. The range is from +24 dB
to −63.5 dB and mutes in steps of 0.5 dB.
0.01
−70
>135
−1.5
Table 2 Application modes using input gain stage
RESISTOR
(12 kΩ)
INPUT GAIN
SWITCH
MAXIMUM
INPUT
VOLTAGE
Present 0 dB 2 V (RMS)
6 dB 1 V (RMS)
Absent 0 dB 1 V (RMS)
6 dB 0.5 V (RMS)
8.3 Decimation filter (ADC)
Thedecimation from 128fsisperformed in two stages. The
first stage realizes a characteristic with a decimation
----------x
xsin
factor of 16. The second stage consists of 3 half-band
filters, each decimating by a factor 2. The filter
characteristics are shown in Table 3.
8.3.3 MUTE
The decimator is equipped with a dB-linear mute which
mutes the signal in 256 steps of 0.5 dB.
8.3.4 AGC FUNCTION
The decimation filter is equipped with an AGC block. This
function is intended, when enabled, to keep the output
signal at a constant level. The AGC can be used for
microphone applications in which the distance to the
microphone is not always the same.
The AGC can be enabled via an L3-bus or I2C-bus bit by
setting the bit to logic 1. In that case it bypasses the digital
volume control.
Via the L3-bus or I2C-bus interface also some other
settings of the AGC, like the attack and decaysettings and
the target level settings, can be made.
Remark: The DC filter before the decimation filter must be
enabled by setting the L3-bus or I2C-bus bit SKIP_DCFIL
to logic 0 when AGC is in operation; otherwise the output
will be disturbed by the DC offset added in the ADC.
2002 Sep 16 14
Philips Semiconductors Product specification
Stereo audio coder-decoder
for MD, CD and MP3
8.4 Interpolation filter (DAC)
The interpolation digital filter interpolates from 1 to 64fsor
to 128fs, by cascading FIR filters, see Table 4. The
interpolator is equipped with several sound features like
volume control, mute, de-emphasis and tone control.
Table 4 Interpolation filter characteristics
ITEM CONDITION VALUE (dB)
Pass-band ripple 0 to 0.45f
Stop band >0.55f
Dynamic range 0 to 0.45f
8.4.1
DIGITAL MUTE
s
s
s
Muting the DAC will result in a cosine roll-off soft mute,
using 4 × 32 = 128 samples in normal mode (or 3 ms at
44.1 kHz sampling frequency). The cosine roll-off curve is
illustrated in Fig.8. These cosine roll-off functions are
implementedfor both the digital mixer and themastermute
inside the DAC data path, see Section 8.8.
handbook, halfpage
1
mute
factor
0.8
0.6
0.4
0.2
0
01051525
±0.025
−60
>135
MGU119
20
t (ms)
UDA1380
8.4.2 S
In addition, there are basic sound features:
• dB-linear volume control using 14-bit coefficients in
steps of 0.25 dB: range 0 to −78 dB maximum
suppression and −∞ dB: applies to both master volume
and mixing volume control
• De-emphasis for 32, 44.1, 48 and 96 kHz for both
channel 1 and 2 (selectable independently)
• Treble, which is selectable gain for high frequencies
(positive gain only), the edge frequency of the treble is
fixed (depends on the sampling frequency). Can be set
for left and right independently:
– Two settings: fc= 1.5 kHz and fc= 3 kHz, assuming
– Both settings have 0 to 6 dB gain range in steps
• Bass boost, which is selectable gain for low frequencies
(positive gain only). The edge frequency of the bass
boost is fixed and depends on the sampling frequency.
Can be set for left and right independently:
– Two settings: fc= 250 Hz and fc= 300 Hz, assuming
– First setting: 0 to 18 dB gain range in steps of 2 dB
– Second setting: 0 to 24 dB gain range in
8.5 Noise shaper
The noise shaper consists of two mono 3rd-order noise
shapers and one time-multiplexed stereo 5th-order noise
shaper.
The order of the noise shaper can be chosen between
3rd-order (which runs at 128fs) and 5th-order (which runs
at 64fs) via bit SEL_NS in the L3-bus or I2C-bus register.
The preferable choice for the noise shaper order is:
• 3rd-order noise shaper is preferred at low sampling
frequencies, for instance between 8 and 32 kHz. This is
for preventing out-of-band noise from the noise shaper
to move into the audio band
• 5th-order noise shaper is normally used at higher
sampling frequencies, normally from 32 to 100 kHz.
OUND FEATURES
sampling frequency is 44.1 kHz
of 2 dB
sampling frequency is 44.1 kHz
steps of 2 dB.
Fig.8 Mute as a function of raised cosine roll-off,
displayed assuming 44.1 kHz.
2002 Sep 16 15
The noise shaper shifts in-band quantization noise to
frequencieswellabovetheaudioband.Thisnoiseshaping
technique enables high signal-to-noise ratios to be
achieved. The noise shaper output is converted into an
analog signal using an FSDAC.
Philips Semiconductors Product specification
Stereo audio coder-decoder
for MD, CD and MP3
8.6 FSDAC
8.6.1 GENERAL INFORMATION
The Filter-Stream Digital-to-Analog Converter (FSDAC) is
a semi-digital reconstruction filter that converts the
1-bit data stream (running at either 64fs for the 5th-order
noiseshaperor128fsforthe3rd-ordernoiseshaper)ofthe
noise shaper into an analog output voltage. The filter
coefficients are implemented as current sources, and are
summed at virtual ground of the output operational
amplifier. In this way very high signal-to-noise
performance and low clock jitter sensitivity are achieved.
A post-filteris not needed due to theinherent filter function
of the DAC. On-board amplifiers convert the FSDAC
output current to an output voltage signal, capable of
driving a line output. The output voltage of the FSDAC
scales proportionally with the power supply voltage.
Remark: When the FSDAC is powered-down, the output
of the FSDAC becomes high impedance.
8.6.2 ANALOG MIXER INPUT
UDA1380
8.7 Headphone driver
The UDA1380 is equipped with a headphone driver which
can deliver 36 mW (at 3.0 V power supply) into a 16 Ω
load.
The headphone driver does not need external
DC decoupling capacitors because it can be DC coupled
with respect to a special headphone output reference
voltage. This saves two external capacitors (which is quite
useful in a portable device).
The headphone driver is equipped with short-circuit
protection on all three operationalamplifiers (left, right and
the virtual ground). Each of the operational amplifiers has
a signalling bit which becomes logic 1 in case the limiter is
activated, for instance in case of a short-circuit. This
means the microcontroller in the system can poll the
L3-bus or I2C-bus register of the headphone driver and as
soon as, and for as long as, the short-circuit detection bits
are activated, the microcontroller can signal the user that
something is wrong or power-down the headphone driver
(for instance, for energy-saving purposes).
The FSDAC has a mixer input, which makes it possible to
mix an analog signal to the output signal of the FSDAC
itself. In schematic form this is given in Fig.9.
This mixer input can be used for instance for mixing-in a
GSM signal or an FM signal directly to the line output.
In the UDA1380, the mixer input is connected from the
ADC line input via an AVC unit.
Remark: Before the AVC unit can be used stand-alone,
meaning without the digital part running, first the DAC part
must be initialised in order to have the DAC output
generating zero current. Otherwise the signal will be
clipped.
handbook, halfpage
bitstream
to analog mixer input
FSDAC
MGU531
Fig.9 Mixing signals to the FSDAC output
(analog domain).
Remark: To improve headphone channel separation
performance,thedistancebetweenV
REF(HP)
andthemicro
speaker port must be minimized.
8.8 Digital and analog mixers (DAC)
8.8.1 DIGITAL MIXER
The ADC output signal and digital input signal can be
mixedwithoutexternalDSP as shown in Fig.10. This mixer
can be controlled via the microcontroller interface, and
must only be enabled when the ADC and the DAC are
running at the same frequency. In addition, the mixer
output signal can also be applied to the I2S-bus output
interface.
2002 Sep 16 16
Philips Semiconductors Product specification
Stereo audio coder-decoder
for MD, CD and MP3
data from
handbook, full pagewidth
decimation
filter
(channel 2)
from
digital
data input
(channel 1)
DE-EMPHASIS
DE-EMPHASIS
VOLUME
AND
MUTE
VOLUME
AND
MUTE
1f
s
mixing before
sound features
BASS-BOOST
AND
TREBLE
SEL_SOURCE
I2S-BUS OUTPUT BLOCK
Fig.10 Digital mixer (DAC).
mixing after
sound features
INTERPOLATION
FILTER
2f
s
UDA1380
master
VOLUME
AND
MUTE
to
interpolation
filter
MGU532
8.8.2 ANALOG MIXER
The analog mixer, which uses the mixer input of the FSDAC, can mix a signal into the FSDAC output signal via an AVC
unit (see Fig.11). The mixer can be used to mix a signal into the FSDAC output signal and play it via the headphone
driver without the complete coder-decoder running. The analog control range is 0 to −64.5 dB and mutes in steps
of 1.5 dB, with a gain of 16.5 dB (so actually the range is from +16.5 dB to −48 dB plus mute).
handbook, full pagewidth
from analog
front-end
AVC[5:0] L3 or I
PON_AVC
RESISTOR
NETWORK
2
C-bus control bits
enable mixer
(EN_AVC)
to FSDAC
mixer input
MGU533
Fig.11 Analog mixer configuration.
2002 Sep 16 17
Philips Semiconductors Product specification
Stereo audio coder-decoder
for MD, CD and MP3
8.9 Application modes
The operation mode can be set with pin SEL_L3_IIC,
either to L3-bus mode (LOW) or to the I2C-bus mode
(HIGH) as given in Table 5.
For all features in microcontroller mode see Chapter 9.
Table 5 Pin function in the selected mode
PIN
L3CLOCK/SCL L3CLOCK SCL
L3MODE L3MODE A1
L3DATA/SDA L3DATA SDA
Remark: In the I
the LSB bit of the address of the UDA1380. In
L3-bus mode this bit is not available, meaning the device
has only one L3-bus device address.
L3-BUS MODE
SEL_L3_IIC = L
2
C-bus mode there is a bit A1 which sets
I2C-BUS MODE
SEL_L3_IIC = H
UDA1380
8.11 Power-down requirements
The following blocks have power-down control via the
L3-bus or I
• Microphone amplifier (LNA) including its Single-Ended
to Differential Converter (SDC) and VGA
• ADC plus SDC and the PGA, for left and right separate
• Bias generation circuit for the front-end and the FSDAC
• Headphone driver
• WSPLL
• FSDAC.
Clocksofthe decimator, interpolator and the analog blocks
have separate enable and disable controls.
2
C-bus interface:
8.10 Power-on reset
The UDA1380 has a dedicated pin RESET, which has a
pull-down resistor. This way a Power-on reset circuit can
be made with a capacitor and a resistor at the pin. The
internal pull-down resistor cannot be used because of the
5 V tolerant nature of the pad. The pull-down resistor is
shielded from the outside world by a transmission gate in
order to support 5 V tolerance.
The reset timing is determined by the external capacitor
and resistor which are connected to the pin RESET, and
the internal pull-down resistor. By the Power-on reset, all
the digital sound processing features and the system
controlling features are set to the default setting of the
L3-bus and I2C-bus control modes.
Remark: The reset time should be at least 1 µs, and
during the reset time the system clock should be running.
Incase the WSPLL is selected as theclock source, a clock
must be connected to the SYSCLK input in order to have
proper reset of the L3-bus or I2C-bus registers. This is
because by default the clock source is set to SYSCLK.
2002 Sep 16 18
Philips Semiconductors Product specification
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
8.11.1 ANALOG FRONT-END
Figure 12 shows the power control inside the analog front-end. The control of all power-on pins of the ADC front-end is
done via separate L3-bus or I2C-bus bits.
handbook, full pagewidth
PGA_GAINCTRLL
VINL
1
(29)
31
(27)
3
(31)
VINR
VINM
PGA_GAINCTRLR
PGA
PGA
LNA SDC
SDC
SDC
ADC
ADC
bitstream
right
bitstream
left
PON_BIAS
PON_PGAR PON_ADCRPON_LNA
PON_PGAL PON_ADCL
Pin numbers for UDA1380HN in parentheses.
Fig.12 Analog front-end power-down.
8.11.2 FSDAC POWER CONTROL
The FSDAC block has power-on pins: one of which shuts
down the DAC itself, but leaves the output still at V
REF
voltage (which is half the power supply). This function is
set by the bit PON_DAC in the L3-bus or I2C-bus register.
A second L3-bus or I2C-bus bit shuts down the complete
bias circuit of the FSDAC, via bit PON_BIAS in the
L3-bus or I2C-bus register. This bit PON_BIAS acts the
same as given in Fig.12 for the analog front-end.
8.12 Plop prevention
Plops are ticks and other strange sounds, that can occur
when a part of a device is powered-up or powered-down,
or when switching between modes is done.
Some ways to prevent plops from occurring are:
• When the FSDAC or headphone driver must be
powered-down, first a digital mute is applied. After that
V
REF
FE
BIAS
MGU534
the FSDAC or headphone driver can be powered-down.
In case the FSDAC or headphone driver must be
powered-up,first the analog part is switched on,thenthe
digital part is demuted
• When the ADC must be powered-down, a digital mute
sequence must be applied. When the digital output
signal is completely muted, the ADC can be
powered-down. In case the ADC must be powered-up,
firsttheanalogpartmustbepowered-up,then the digital
part must be demuted
• When there is a change of for example clock divider
settings or clock source (selecting between SYSCLK
and WSPLL clock), then also digital mute for that block
(either decimator or interpolator) should be used.
Remark: All items mentioned in Section 8.12 are not
‘hard-wired’ implemented, but to be followed by the users
as a guideline for plop prevention.
2002 Sep 16 19
Philips Semiconductors Product specification
Stereo audio coder-decoder
for MD, CD and MP3
8.13 Digital audio data input and output
The supported audio formats for the control modes are:
• I2S-bus
• MSB-justified
• LSB-justified, 16 bits
• LSB-justified, 18 bits
• LSB-justified, 20 bits
• LSB-justified, 24 bits (only for the output interface).
The bit clock BCK can be up to 128fs, or in other words the
BCK frequency is 128 times the WS frequency or less:
f
≤ 128f
BCK
Remark: The WS edge must coincide with the negative
edge of the BCK at all times, for proper operation of the
digital I/O data interface. Figure 13 shows the interface
signals.
8.13.1 DIGITAL AUDIO INPUT INTERFACE
The digital audio input interface is slave only, meaning the
system must provide the WSI and BCKI signals (next to
the DATAI signal).
Either the WSPLL locks onto the WSI signal and provides
the internal clocks for the interpolator and the FSDAC, or
a system clock must be applied which must be in
frequency lock to the digital data input interface signals.
8.13.2 DIGITAL AUDIO OUTPUT INTERFACE
The digital audio output interface can be either master or
slave. The data source for the data output can be selected
from either the decimator (ADC front-end) or the digital
mixer output.
Remark: The digital mixer output is only valid if both the
decimator and the interpolator run at the same clock:
• In slave mode the signals on pins BCKO, WSO and
SYSCLK must be applied from the application (signals
mustbein frequency lock) and the UDA1380 returns the
DATAO signal from the decimator. The applied signal
from pin BCKO can be for instance: 32fs, 48fs, 64fs,
96fsor 128f
• In master mode the SYSCLK signal must be applied
from the system, but the UDA1380 returns with the
BCKO, WSO and the DATAO signals. For the BCKO
clock, there are 2 general rules:
– Whenthe SYSCLK is either 256fsor512fs,the BCKO
– Whenthe SYSCLK is either 384fsor 768fs,the BCKO
WS
s
frequency is supposed to be 64f
signal should be 48fs.
s
UDA1380
The slave and master modes can be selected by the
bit Serial Interface Mode (SIM) in the L3-bus or I2C-bus
interface.
9 L3-BUS INTERFACE DESCRIPTION
The UDA1380 has an L3-bus microcontroller
interface mode. Controllable system and digital sound
processing features are:
• Software reset
• System clock frequency (selection between 256fs,
384fs, 512fsand 768fs clock divider settings)
• Clock mode setting, for instance, which block runs at
which clock, and clock enabling
• Power control for the WSPLL
• Data input and data output format control, for input and
output independently including data source selection for
the digital output interface
• ADC features:
– Digital mute
– AGC enable and settings
– Polarity control
– Input line amplifier control (0 to 24 dB in steps of
3 dB)
– DC filtering control
– Digital gain control (+24 to −63 dB gain in steps of
0.5 dB) for left and right
– Power control
– VGA of the microphone input
– Selection of line or microphone input
• DAC and headphone driver features:
– Power control FSDAC and headphone driver
– Polarity control
– Mixing control (only available when both decimator
and interpolator run at the same speed). This
includes the mixer volumes, mute and mixer position
switch
– De-emphasis control
– Master volume and balance control
– Flat/minimum/maximum settings for the bass boost
and treble
– Tone control: bass boost and treble
– Master mute control
– Headphone driver short-circuit protection status bits.
2002 Sep 16 20
Philips Semiconductors Product specification
Stereo audio coder-decoder
for MD, CD and MP3
RIGHT
UDA1380
MBL121
B15 LSB
15 2 1
16
MSB B2
RIGHT
B17 LSB
16 1518 17 2 1
MSB B2 B3 B4
RIGHT
B19 LSB
1518 1720 19 2 1
16
MSB B2 B3 B4 B5 B6
RIGHT
B23 LSB
1518 1720 1922 212324 21
16
B5 B6 B7 B8 B9 B10
B3 B4
B2
> = 8
dbook, full pagewidth
RIGHT
3
21> = 812 3
LEFT
MSB MSBB2
S-BUS FORMAT
2
I
MSB B2
RIGHT
LEFT
MSB
LSB
B15
LSB-JUSTIFIED FORMAT 16 BITS
321321
15 2 1
B2
16
MSB
LSB
B17
LSB-JUSTIFIED FORMAT 18 BITS
1518 17 2 1
16
LSB
B19
LSB-JUSTIFIED FORMAT 20 BITS
1518 1720 19 2 1
16
LSB
B23
LSB-JUSTIFIED FORMAT 24 BITS
1518 1720 1922 212324 2 1
16
Fig.13 Serial interface input and output formats.
> = 8 > = 8
MSB-JUSTIFIED FORMAT
LEFT
MSB B2 MSBLSB LSB MSB B2B2
LEFT
MSB B2 B3 B4
LEFT
MSB B2 B3 B4 B5 B6
LEFT
B5 B6 B7 B8 B9 B10
B3 B4
B2
MSB
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2002 Sep 16 21
WS
BCK
DATA
WS
BCK
DATA
WS
BCK
DATA
WS
BCK
DATA
WS
BCK
DATA
WS
BCK
DATA
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