UDA1380
INTEGRATED CIRCUITS
DATA SHEET
UDA1380
Stereo audio coder-decoder for MD, CD and MP3
Product specification |
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2002 Sep 16 |
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Philips Semiconductors |
Product specification |
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Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
CONTENTS
1 FEATURES
1.1General
1.2Multiple format data input interface
1.3Multiple format data output interface
1.4ADC front-end features
1.5DAC features
2APPLICATIONS
3GENERAL DESCRIPTION
4QUICK REFERENCE DATA
5ORDERING INFORMATION
6BLOCK DIAGRAM
7PINNING
8FUNCTIONAL DESCRIPTION
8.1Clock modes
8.2ADC analog front-end
8.3Decimation filter (ADC)
8.4Interpolation filter (DAC)
8.5Noise shaper
8.6FSDAC
8.7Headphone driver
8.8Digital and analog mixers (DAC)
8.9Application modes
8.10Power-on reset
8.11Power-down requirements
8.12Plop prevention
8.13Digital audio data input and output
9 |
L3-BUS INTERFACE DESCRIPTION |
9.1Introduction
9.2Device addressing
9.3Slave address
9.4Register addressing
9.5Data write mode
9.6Data read mode
11.9Master mute, channel de-emphasis and mute
11.10Mixer, silence detector and oversampling settings
11.11Decimator volume control
11.12PGA settings and mute
11.13ADC settings
11.14AGC settings
11.15Restore L3 default values (software reset)
11.16Headphone driver and interpolation filter (read-out)
11.17Decimator read-out
12LIMITING VALUES
13HANDLING
14THERMAL CHARACTERISTICS
15QUALITY SPECIFICATION
16DC CHARACTERISTICS
17AC CHARACTERISTICS
18TIMING
19APPLICATION INFORMATION
20PACKAGE OUTLINES
21SOLDERING
21.1Introduction to soldering surface mount packages
21.2Reflow soldering
21.3Wave soldering
21.4Manual soldering
21.5Suitability of surface mount IC packages for wave and reflow soldering methods
22DATA SHEET STATUS
23DEFINITIONS
24DISCLAIMERS
25PURCHASE OF PHILIPS I2C COMPONENTS
10 I2C-BUS INTERFACE DESCRIPTION
10.1Addressing
10.2WRITE cycle
10.3READ cycle
11 REGISTER MAPPING
11.1Evaluation modes and clock settings
11.2I2S-bus input and output settings
11.3Power control settings
11.4Analog mixer settings
11.5Reserved
11.6Master volume control
11.7Mixer volume control
11.8Mode, bass boost and treble
2002 Sep 16 |
2 |
Philips Semiconductors |
Product specification |
|
|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
1 FEATURES
1.1General
∙2.4 to 3.6 V power supply
∙5 V tolerant digital inputs (at 2.4 to 3.6 V power supply)
∙24-bit data path for Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC)
∙Selectable control via L3-bus microcontroller interface or I2C-bus interface; choice of 2 device addresses in L3-bus and I2C-bus mode
Remark: This device does not have a static mode
∙Supports sample frequencies from 8 to 55 kHz for the ADC part, and 8 to 100 kHz for the DAC part. The ADC cannot support DVD audio (96 kHz audio), only Mini-Disc (MD), Compact-Disc (CD) and Moving Picture Experts Group Layer-3 Audio (MP3). For playback
8 to 100 kHz is specified. DVD playback is supported
∙Power management unit:
–Separate power control for ADC, Automatic Volume Control (AVC), DAC, Phase Locked Loop (PLL) and headphone driver
–Analog blocks like ADC and Programmable Gain Amplifier (PGA) have a block to power-down the bias circuits
–When ADC and/or DAC are powered-down, also the clocks to these blocks are stopped to save power
Remark: By default, when the IC is powered-up, the complete chip will be in the Power-down mode.
∙ADC part and DAC part can run at different frequencies, either system clock or Word Select PLL (WSPLL)
∙ADC and PGA plus integrated high-pass filter to cancel DC offset
∙The decimation filter is equipped with a digital Automatic Gain Control (AGC)
∙Mono microphone input with Low Noise Amplifier (LNA) of 29 dB fixed gain and Variable Gain Control (VGA) from 0 to 30 dB in steps of 2 dB
∙Integrated digital filter plus DAC
∙Separate single-ended line output and one stereo headphone output, capable of driving a 16 Ω load. The headphone driver has a built-in short-circuit protection with status bits which can be read out from the
L3-bus or I2C-bus interface
∙Digital silence detection in the interpolator (playback) with read-out status via L3-bus or I2C-bus interface
1.2Multiple format data input interface
∙Slave BCK and WS signals
∙I2S-bus format
∙MSB-justified format compatible
∙LSB-justified format compatible.
1.3Multiple format data output interface
∙Select option for digital output interface: either the decimator output (ADC signal) or the output signal of the digital mixer which is in the interpolator DSP
∙Selectable master or slave BCK and WS signals for digital ADC output
Remark: SYSCLK must be applied in WSPLL mode and master mode
∙I2S-bus format
∙MSB-justified format compatible
∙LSB-justified format compatible.
1.4ADC front-end features
∙ADC plus decimator can run at either WSPLL, regenerating the clock from WSI signal, or on SYSCLK
∙Stereo line input with PGA: gain range from 0 to 24 dB in steps of 3 dB
∙LNA with 29 dB fixed gain for mono microphone input, including VGA with gain from 0 to 30 dB in steps of 2 dB
∙Digital left and right independent volume control and mute from +24 to −63.5 dB in steps of 0.5 dB.
∙ Easy application.
2002 Sep 16 |
3 |
Philips Semiconductors |
Product specification |
|
|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
1.5DAC features
∙DAC plus interpolator can run at either WSPLL (regenerating the clock from WSI) or at SYSCLK
∙Separate digital logarithmic volume control for left and right channels via L3-bus or I2C-bus from 0 to −78 dB in steps of 0.25 dB
∙Digital tone control, bass boost and treble via L3-bus or I2C-bus interface
∙Digital de-emphasis for sample frequencies of:
32, 44.1, 48 and 96 kHz via L3-bus or I2C-bus interface
∙Cosine roll-off soft mute function
∙Output signal polarity control via L3-bus or I2C-bus interface
∙Digital mixer for mixing ADC output signal and digital serial input signal, if they run at the same sampling frequency.
2 APPLICATIONS
This audio coder-decoder is suitable for home and portable applications like MD, CD and MP3 players.
3 GENERAL DESCRIPTION
The UDA1380 is a stereo audio coder-decoder, available in TSSOP32 (UDA1380TT) and HVQFN32 (UDA1380HN) packages. All functions and features are identical for both package versions. The term ‘UDA1380’ in this document refers to both UDA1380TT and UDA1380HN, unless particularly specified.
The front-end of the UDA1380 is equipped with a stereo line input, which has a PGA control, and a mono microphone input with an LNA and a VGA. The digital decimation filter is equipped with an AGC which can be used in case of voice-recording.
The DAC part is equipped with a stereo line output and a headphone driver output. The headphone driver is capable of driving a 16 Ω load. The headphone driver is also capable of driving a headphone without the need for external DC decoupling capacitors, since the headphone can be connected to a pin VREF(HP) on the chip.
In addition, there is a built-in short-circuit protection for the headphone driver output which, in case of short-circuit, limits the current through the operational amplifiers and signals the event via its L3-bus or I2C-bus register.
The UDA1380 also supports an application mode in which the coder-decoder itself is not running, but an analog signal, for instance coming from an FM tuner, can be controlled in gain, and applied to the output via the headphone driver and line outputs.
The UDA1380 supports the I2S-bus data format with word lengths of up to 24 bits, the MSB-justified data format with word lengths of up to 24 bits and the LSB-justified serial data format with word lengths of 16, 18, 20 or 24 bits (LSB-justified 24 bits is only supported for the output interface).
The UDA1380 has sound processing features in playback mode, de-emphasis, volume, mute, bass boost and treble which can be controlled by the L3-bus or I2C-bus interface.
2002 Sep 16 |
4 |
Philips Semiconductors |
Product specification |
|
|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
4 QUICK REFERENCE DATA
VDDD = VDDA(AD) = VDDA(DA) = VDDA(HP) = 3.0 V; Tamb = 25 °C; RL = 5 kΩ; all voltages measured with respect to ground; unless otherwise specified.
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Supplies |
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VDDA(AD) |
ADC analog supply voltage |
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2.4 |
3.0 |
3.6 |
V |
VDDA(DA) |
DAC analog supply voltage |
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2.4 |
3.0 |
3.6 |
V |
VDDA(HP) |
headphone analog supply |
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2.4 |
3.0 |
3.6 |
V |
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voltage |
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VDDD |
digital supply voltage |
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2.4 |
3.0 |
3.6 |
V |
IDDA(AD) |
ADC analog supply current |
one ADC and microphone amplifier |
− |
4.5 |
− |
mA |
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enabled; fs = 48 kHz |
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two ADCs and PGA enabled; |
− |
7.0 |
− |
mA |
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fs = 48 kHz |
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all ADCs and PGAs power-down, but |
− |
3.3 |
− |
mA |
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AVC activated; fs = 48 kHz |
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all ADCs, PGAs and LNA |
− |
1.0 |
− |
μA |
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power-down; fs = 48 kHz |
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IDDA(DA) |
DAC analog supply current |
operating mode; fs = 48 kHz |
− |
3.4 |
− |
mA |
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Power-down mode; fs = 48 kHz |
− |
0.1 |
− |
μA |
IDDA(HP) |
headphone analog supply |
no signal applied (quiescent current) |
− |
0.9 |
− |
mA |
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current |
Power-down mode |
− |
0.1 |
− |
μA |
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IDDD |
digital supply current |
operating mode; fs = 48 kHz |
− |
10.0 |
− |
mA |
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playback mode; fs = 48 kHz |
− |
5.0 |
− |
mA |
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record mode; fs = 48 kHz |
− |
6.0 |
− |
mA |
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Power-down mode; fs = 48 kHz |
− |
1.0 |
− |
μA |
IDD(tot) |
total supply current |
playback mode (without headphone); |
− |
9.0 |
− |
mA |
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fs = 48 kHz |
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playback mode (with headphone); no |
− |
8.8 |
− |
mA |
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signal; fs = 48 kHz |
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record mode (audio); fs = 48 kHz |
− |
13.0 |
− |
mA |
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record mode (speech); fs = 48 kHz |
− |
10.0 |
− |
mA |
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record mode (audio and speech); |
− |
13.0 |
− |
mA |
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fs = 48 kHz |
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fully operating; fs = 48 kHz |
− |
23.0 |
− |
mA |
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signal mix-in operating, using |
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12.0 |
− |
mA |
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FSDAC, AVC (with headphone); no |
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signal; fs = 48 kHz |
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Power-down mode; fs = 48 kHz |
− |
2.0 |
− |
μA |
Tamb |
ambient temperature |
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−40 |
− |
+85 |
°C |
2002 Sep 16 |
5 |
Philips Semiconductors |
Product specification |
|
|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Analog-to-digital converter (supply voltage 3.0 V) |
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Do |
digital output level |
at 0 dB setting; Vi(rms) = 1.0 V |
− |
−1 |
− |
dBFS |
(THD+N)/S48 |
total harmonic distortion- |
at −1 dBFS |
− |
−85 |
− |
dB |
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plus-noise to signal ratio at |
at −60 dBFS; A-weighted |
− |
−37 |
− |
dB |
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fs = 48 kHz |
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S/N48 |
signal-to-noise ratio at |
Vi = 0 V; A-weighted |
− |
97 |
− |
dB |
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fs = 48 kHz |
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αcs |
channel separation |
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− |
100 |
− |
dB |
LNA input plus analog-to-digital converter (supply voltage 3.0 V) |
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Vi(rms) |
input voltage (RMS value) |
at 0 dBFS digital output; 2.2 kΩ |
− |
− |
35 |
mV |
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source impedance |
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(THD+N)/S48 |
total harmonic |
at 0 dB |
− |
−74 |
− |
dB |
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distortion-plus-noise to |
at −60 dB; A-weighted |
− |
−25 |
− |
dB |
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signal ratio at fs = 48 kHz |
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S/N48 |
signal-to-noise ratio at |
Vi = 0 V; A-weighted |
− |
85 |
− |
dB |
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fs = 48 kHz |
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αcs |
channel separation |
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− |
70 |
− |
dB |
Digital-to-analog converter (supply voltage 3.0 V) |
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Vo(rms) |
output voltage (RMS value) |
at 0 dBFS digital input; note 1 |
− |
0.9 |
− |
V |
(THD+N)/S48 |
total harmonic |
at 0 dB |
− |
−88 |
− |
dB |
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distortion-plus-noise to |
at −60 dB; A-weighted |
− |
−40 |
− |
dB |
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signal ratio at fs = 48 kHz |
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(THD+N)/S96 |
total harmonic |
at 0 dB |
− |
−80 |
− |
dB |
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distortion-plus-noise to |
at −60 dB; A-weighted |
− |
−37 |
− |
dB |
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signal ratio at fs = 96 kHz |
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S/N48 |
signal-to-noise ratio at |
code = 0; A-weighted |
− |
100 |
− |
dB |
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fs = 48 kHz |
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S/N96 |
signal-to-noise ratio at |
code = 0; A-weighted |
− |
97 |
− |
dB |
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fs = 96 kHz |
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αcs |
channel separation |
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− |
90 |
− |
dB |
AVC (line input via ADC input; output on line output and headphone driver; supply voltage 3.0 V) |
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Vi(rms) |
input voltage (RMS value) |
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− |
150 |
− |
mV |
(THD+N)/S48 |
total harmonic |
at 0 dB |
− |
−80 |
− |
dB |
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distortion-plus-noise to |
at −60 dB; A-weighted |
− |
−28 |
− |
dB |
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signal ratio at fs = 48 kHz |
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S/N48 |
signal-to-noise ratio at |
Vi = 0 V; A-weighted |
− |
87 |
− |
dB |
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fs = 48 kHz |
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2002 Sep 16 |
6 |
Philips Semiconductors |
Product specification |
|
|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
TYP. |
MAX. |
UNIT |
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Headphone driver (supply voltage 3.0 V) |
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Po(rms) |
output power (RMS value) |
at 0 dBFS digital input; RL = 16 Ω |
− |
35 |
− |
mW |
(THD+N)/S48 |
total harmonic |
at 0 dB; RL = 16 Ω |
− |
−60 |
− |
dB |
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distortion-plus-noise to |
at 0 dB; RL = 5 kΩ |
− |
−82 |
− |
dB |
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signal ratio at fs = 48 kHz |
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at −60 dB; A-weighted |
− |
−24 |
− |
dB |
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S/N48 |
signal-to-noise ratio at |
code = 0; A-weighted |
− |
90 |
− |
dB |
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fs = 48 kHz |
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αcs |
channel separation |
RL = 16 Ω using pin VREF(HP); no DC |
− |
60 |
− |
dB |
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decoupling capacitors; note 2 |
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RL = 16 Ω single-ended application |
− |
68 |
− |
dB |
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with DC decoupling capacitors |
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(100 μF typical) |
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RL = 32 Ω single-ended application |
− |
74 |
− |
dB |
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with DC decoupling capacitors |
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(100 μF typical) |
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Power consumption (supply voltage 3.0 V; fs = 48 kHz) |
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Ptot |
total power dissipation |
playback mode (without headphone) |
− |
27 |
− |
mW |
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playback mode (with headphone) |
− |
27 |
− |
mW |
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record mode (audio) |
− |
39 |
− |
mW |
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record mode (speech) |
− |
31 |
− |
mW |
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record mode (audio and speech) |
− |
40 |
− |
mW |
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full operation |
− |
69 |
− |
mW |
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Power-down mode |
− |
6 |
− |
μW |
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Notes
1.The output voltage of the DAC is proportional to the DAC power supply voltage.
2.Channel separation performance is measured at the IC pin.
5 ORDERING INFORMATION
TYPE |
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PACKAGE |
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NUMBER |
NAME |
DESCRIPTION |
VERSION |
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UDA1380TT |
TSSOP32 |
plastic thin shrink small outline package; 32 leads; |
SOT487-1 |
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body width 6.1 mm; lead pitch 0.65 mm |
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UDA1380HN |
HVQFN32 |
plastic, heatsink very thin quad flat package; no leads; |
SOT617-1 |
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32 terminals; body 5 × 5 × 0.85 mm |
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2002 Sep 16 |
7 |
Philips Semiconductors |
Product specification |
|
|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
6 BLOCK DIAGRAM
handbook, full pagewidth |
VDDA(AD) |
VSSA(AD) |
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VADCP |
VADCN |
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VREF |
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VDDD |
VDDA(DA) |
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32 (28) |
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30 (26) |
4 (32) |
2 (30) |
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29 (25) |
6 (2) |
26 (22) |
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VINL |
31 (27) |
PGA |
SDC |
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SDC |
PGA |
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1 (29) |
VINR |
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+29 dB |
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VINM |
3 (31) |
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MIC AMP |
SDC |
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n.c. |
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ADC |
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ADC |
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UDA1380TT |
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(UDA1380HN) |
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RESET |
5 (1) |
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DECIMATION FILTER |
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AGC |
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13 (9) |
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DC-CANCELLATION FILTER |
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SYSCLK |
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DATAO |
9 (5) |
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17 (13) |
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7 (3) |
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DATA OUTPUT |
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L3CLOCK/SCL |
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BCKO |
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L3 or I2C-BUS |
16 (12) |
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8 (4) |
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INTERFACE |
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WSO |
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L3MODE |
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INTERFACE |
18 (14) |
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10 (6) |
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L3DATA/SDA |
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BCKI |
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11 (7) |
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DATA INPUT |
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WSI |
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19 (15) |
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12 (8) |
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INTERFACE |
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SEL_L3_IIC |
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DATAI |
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DSP FEATURES |
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15 (11) |
RTCB |
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WSPLL |
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INTERPOLATION FILTER |
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NOISE SHAPER |
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ANA VC |
FSDAC |
FSDAC |
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ANA VC |
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VOUTL |
27 (23) |
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25 (21) |
VOUTR |
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HEADPHONE |
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HEADPHONE |
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DRIVER |
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DRIVER |
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23 (19) |
24 (20) |
22 (18) |
20 (16) |
21 (17) |
28 (24) |
14 (10) |
MGU526 |
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VOUTLHP |
VREF(HP) |
VOUTRHP |
VSSD |
||
VDDA(HP) |
VSSA(HP) |
VSSA(DA) |
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||
Pin numbers for UDA1380HN in parentheses.
Fig.1 Block diagram.
2002 Sep 16 |
8 |
Philips Semiconductors |
Product specification |
|
|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
7 PINNING
SYMBOL |
PIN |
TYPE |
DESCRIPTION |
||
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||||
UDA1380TT |
UDA1380HN |
||||
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VINR |
1 |
29 |
analog pad |
ADC input right, also connected |
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to the mixer input of the FSDAC |
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VADCN |
2 |
30 |
analog pad |
ADC reference voltage |
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VINM |
3 |
31 |
analog pad |
microphone input |
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VADCP |
4 |
32 |
analog pad |
ADC reference voltage |
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RESET |
5 |
1 |
5 V tolerant digital input pad; |
pin RESET with pull-down, for |
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push-pull; TTL with hysteresis; |
making Power-On Reset (POR) |
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pull-down |
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VDDD |
6 |
2 |
digital supply pad |
digital supply voltage |
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BCKO |
7 |
3 |
5 V tolerant digital bidirectional |
bit clock output |
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pad; push-pull input; 3-state |
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WSO |
8 |
4 |
word select output |
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output; 5 ns slew-rate control; |
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TTL with hysteresis |
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DATAO |
9 |
5 |
output pad; push-pull; 5 ns |
data output |
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slew-rate control; CMOS |
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BCKI |
10 |
6 |
5 V tolerant digital input pad; |
bit clock input |
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push-pull; TTL with hysteresis |
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WSI |
11 |
7 |
word select input |
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DATAI |
12 |
8 |
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data input |
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SYSCLK |
13 |
9 |
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system clock 256fs, 384fs, |
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512fs or 768fs input |
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VSSD |
14 |
10 |
digital ground pad |
digital ground |
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RTCB |
15 |
11 |
5 V tolerant digital input pad; |
test control input, to be connected |
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push-pull; TTL with hysteresis; |
to digital ground in the application |
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pull-down |
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L3MODE |
16 |
12 |
5 V tolerant digital bidirectional |
L3-bus mode input or pin A1 for |
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pad; push-pull input; 3-state |
I2C-bus slave address setting |
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output; 5 ns slew-rate control; |
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TTL with hysteresis |
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L3CLOCK/SCL |
17 |
13 |
5 V tolerant digital input pad; |
L3-bus or I2C-bus clock input |
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push-pull; TTL with hysteresis |
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L3DATA/SDA |
18 |
14 |
I2C-bus pad; 400 kHz I2C-bus |
L3-bus or I2C-bus data input and |
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specification |
output |
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SEL_L3_IIC |
19 |
15 |
5 V tolerant digital input pad; |
input channel select |
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push-pull; TTL with hysteresis |
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VSSA(HP) |
20 |
16 |
analog ground pad |
headphone ground |
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VOUTRHP |
21 |
17 |
analog pad |
headphone output right |
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VREF(HP) |
22 |
18 |
analog pad |
headphone reference voltage |
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VOUTLHP |
23 |
19 |
analog pad |
headphone output left |
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VDDA(HP) |
24 |
20 |
analog supply pad |
headphone supply voltage |
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VOUTR |
25 |
21 |
analog pad |
DAC output right |
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VDDA(DA) |
26 |
22 |
analog supply pad |
DAC analog supply voltage |
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VOUTL |
27 |
23 |
analog pad |
DAC output left |
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|
2002 Sep 16 |
9 |
Philips Semiconductors |
Product specification |
|
|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
SYMBOL |
PIN |
TYPE |
DESCRIPTION |
||
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||||
UDA1380TT |
UDA1380HN |
||||
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VSSA(DA) |
28 |
24 |
analog ground pad |
DAC analog ground |
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VREF |
29 |
25 |
analog pad |
ADC and DAC reference voltage |
|
VSSA(AD) |
30 |
26 |
analog ground pad |
ADC analog ground |
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VINL |
31 |
27 |
analog pad |
ADC input left, also connected to |
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the mixer input of the FSDAC |
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VDDA(AD) |
32 |
28 |
analog supply pad |
ADC analog supply voltage |
|
handbook, halfpage |
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VDDA(AD) |
VINR |
1 |
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32 |
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VADCN |
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2 |
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31 |
VINL |
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VSSA(AD) |
VINM |
3 |
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30 |
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VADCP |
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VREF |
4 |
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29 |
||
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VSSA(DA) |
RESET |
5 |
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28 |
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VDDD |
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6 |
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27 |
VOUTL |
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VDDA(DA) |
BCKO |
7 |
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26 |
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WSO |
8 |
UDA1380TT |
25 |
VOUTR |
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VDDA(HP) |
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DATAO |
9 |
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24 |
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BCKI |
10 |
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23 |
VOUTLHP |
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VREF(HP) |
WSI |
11 |
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22 |
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DATAI |
12 |
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21 |
VOUTRHP |
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VSSA(HP) |
SYSCLK |
13 |
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20 |
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VSSD |
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14 |
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19 |
SEL_L3_IIC |
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RTCB |
15 |
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18 |
L3DATA/SDA |
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L3MODE |
16 |
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17 |
L3CLOCK/SCL |
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handbook, halfpage |
SYSCLK |
V |
RTCB |
L3MODE |
L3CLOCK/SCL |
L3DATA/SDA |
_SELL3_IIC |
V |
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SSD |
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SSA(HP) |
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9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
DATAI |
8 |
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WSI |
7 |
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BCKI |
6 |
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DATAO 5
UDA1380HN
WSO 4
BCKO 3
VDDD 2
RESET 1
32 |
31 |
30 |
29 |
28 |
27 |
26 |
25 |
ADCP |
VINM |
ADCN |
VINR |
DDA(AD) |
VINL |
SSA(AD) |
REF |
V |
V |
V |
|||||
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V |
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V |
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17VOUTRHP
18VREF(HP)
19VOUTLHP
20VDDA(HP)
21VOUTR
22VDDA(DA)
23VOUTL
24VSSA(DA)
MGW778
MGU525
Fig.2 Pin configuration UDA1380TT. |
Fig.3 Pin configuration UDA1380HN. |
2002 Sep 16 |
10 |
Philips Semiconductors |
Product specification |
|
|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
8 FUNCTIONAL DESCRIPTION
8.1Clock modes
There are two clock systems:
∙A SYSCLK signal, coming from the system or the SSA1 chip
∙A WSPLL which generates the internal clocks from the incoming WSI signal.
The system frequency applied to pin SYSCLK is selectable. The options are 256fs, 384fs, 512fs and 768fs. The system clock must be locked in frequency to the digital interface signals.
Remark: Since there is neither a fixed reference clock available in the IC itself, nor a fixed clock available in the system the IC is in, there is no auto sample rate conversion detection circuitry.
The system can run in several modes, using the two clock systems:
∙Both the DAC and the ADC part can run at the applied SYSCLK input. In this case the WSPLL is powered-down
∙The ADC can run at the SYSCLK input, and at the same time the DAC part can run (at a different frequency) at the clock re-generated from the WSI signal
∙The ADC and the DAC can both run at the clock regenerated from the WSI signal.
8.1.1WSPLL REQUIREMENTS
The WSPLL is meant to lock onto the WSI input signal, and regenerates a 256fs and 128fs signal for the FSDAC and the interpolator core (and for the decimator if needed).
Since the operating range of the WSPLL is from 75 to 150 MHz, the complete range of 8 to 100 kHz
sampling frequency must be divided into smaller parts, as given in Table 1, using Fig.4 as a reference. This means that the user must set the input range of the WSI input signal.
In case the SYSCLK is used for clocking the complete system (decimator including interpolator) the WSPLL must be powered-down with bit ADC_CLK via the L3-bus
or I2C-bus.
The SEL_LOOP_DIV[1:0] can be controlled by the PLL1 and PLL0 bits in the L3-bus or I2C-bus register.
handbook, halfpage
WSI |
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VCO |
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DIV1 |
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PRE1 |
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128fs |
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(digital parts) |
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256fs |
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(ADC and FSDAC) |
MGU527 |
|||||||||||
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Fig.4 WSPLL set-up. |
||
Table 1 WSPLL divider settings |
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WORD SELECT |
SEL_LOOP_DIV[1:0] |
PRE1 |
DIV1 |
VCO FREQUENCY |
||
FREQUENCY (kHz) |
(MHz) |
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6.25 to 12.5 |
00 |
8 |
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1536 |
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12.5 to 25 |
01 |
4 |
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1536 |
76 to 153 |
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25 to 50 |
10 |
2 |
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1536 |
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50 to 100 |
11 |
2 |
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768 |
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2002 Sep 16 |
11 |
Philips Semiconductors |
Product specification |
|
|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
8.1.2CLOCK DISTRIBUTION
Figure 5 shows the main clock distribution for the SYSCLK domain and the WSPLL clock domain.
For power saving reasons each clock signal inside the system must be controlled and enabled via a separate bit in the L3-bus and I2C-bus registers (ADC_CLK).
The DAC part of the UDA1380 can operate from 8 to 100 kHz sampling frequency (fs). This applies to the DAC part only; the ADC part can run from 8 to 55 kHz.
|
|
enable clock |
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256/384/512/768fs |
ADC |
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ADC_CLK |
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SYSCLK |
CLK_DIV |
128fs |
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128fs |
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|||
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DECIMATOR |
||
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enable |
L3 or I2C-BUS |
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clock |
REGISTER |
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DECIMATOR |
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I2S-BUS |
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OUTPUT BLOCK |
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I2S-BUS |
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INPUT BLOCK |
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enable |
L3 or I2C-BUS |
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REGISTER |
||
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clock |
||
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INTERPOLATOR |
||
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256fs |
128fs |
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INTERPOLATOR |
||
WSI |
WSPLL |
128fs |
||
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DAC_CLK |
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FSDAC |
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enable clock |
MGU528 |
Fig.5 Clock routing for the main blocks inside the coder-decoder.
2002 Sep 16 |
12 |
Philips Semiconductors |
Product specification |
|
|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
8.2ADC analog front-end
The analog front-end of the UDA1380 consists of one stereo ADC with a selector in front of it (see Fig.6). Using this selector one can either select the microphone input with the microphone amplifier (LNA) with a fixed 29 dB gain and VGA (no PGA, since a real microphone amplifier is much better with respect to noise), or the line input which has a PGA for having 0 or 6 dB gain (for supporting 1 and 2 V (RMS) input). The PGA also provides gain control from 0 to 24 dB in steps of 3 dB.
Remarks:
∙The input impedance of the PGA (line input) is 12 kΩ, for the LNA this is 5 kΩ
∙The LNA is standard equipped with a microphone power supply. Since this normally requires two extra pins, this feature will not be used inside the UDA1380. Instead, the microphone supply block is replaced by the VGA block.
8.2.1APPLICATIONS AND POWER-DOWN MODES
The following Power-down modes and functional modes are supported:
∙Power-down mode in which the power consumption is very low (only leakage currents)
In this mode there is no reference voltage at the line input
∙Line input mode, in which the PGA can be used
∙Microphone mode, in which the rest of the non-used PGAs and ADCs are powered-down
∙Mixed PGA and LNA mode: one line input and one microphone input.
More information on the analog frond-end is given in Section 8.11.1.
SEL_MIC
1 |
PGA |
SDC |
ADC |
bitstream |
VINR |
right |
|||
(29) |
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31 |
PGA |
SDC |
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VINL |
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(27) |
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ADC |
bitstream |
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left |
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3 |
LNA |
SDC |
|
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VINM |
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||
(31) |
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MGU530 |
|
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|
|
Pin numbers for UDA1380HN in parentheses.
Fig.6 Analog front-end.
8.2.2 LNA WITH VGA |
8.2.3 APPLICATIONS WITH 2 V (RMS) INPUT |
The LNA is equipped with a VGA. The function of the VGA is to have additional variable analog gain from 0 to 30 dB in steps of 2 dB. This provides more flexibility in the choice of the microphone.
For the line input it is preferable to have 0 dB and 6 dB gain settings in order to be able to apply both
1 and 2 V (RMS) input signals, using a series resistance. For this purpose a PGA is used which has 0 to 24 dB gain, in steps of 3 dB.
2002 Sep 16 |
13 |
Philips Semiconductors |
Product specification |
|
|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
In applications in which a 2 V (RMS) input signal is used, a 12 kΩ resistor must be used in series with the input of the ADC (see Fig.7). This forms a voltage divider together with the internal ADC resistor and ensures that the voltage, applied to the input of the IC, never exceeds 1 V (RMS). Using this application for a 2 V (RMS) input signal, the switch must be set to 0 dB. When a 1 V (RMS) input signal is applied to the ADC in the same application, the gain switch must be set to 6 dB.
An overview of the maximum input voltages allowed against the presence of an external resistor and the setting of the gain switch is given in Table 2; the power supply voltage is assumed to be 3 V.
handbook, halfpage |
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||||
external |
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PGA |
||||||
resistor |
VINL, |
31, |
12 kΩ |
|||||||||||||
12 kΩ |
VINR |
1 |
||||||||||||||
input signal |
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2 V (RMS) |
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(27, |
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VREF |
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29) |
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VDDA = 3 V
MGU529
Pin numbers for UDA1380HN in parentheses.
Fig.7 ADC front-end with PGA (line input).
Table 2 Application modes using input gain stage
RESISTOR |
INPUT GAIN |
MAXIMUM |
|
INPUT |
|||
(12 kΩ) |
SWITCH |
||
VOLTAGE |
|||
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||
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Present |
0 dB |
2 V (RMS) |
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6 dB |
1 V (RMS) |
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Absent |
0 dB |
1 V (RMS) |
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6 dB |
0.5 V (RMS) |
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8.3Decimation filter (ADC)
The decimation from 128fs is performed in two stages. The
sinx
first stage realizes a ----------- characteristic with a decimation x
factor of 16. The second stage consists of 3 half-band filters, each decimating by a factor 2. The filter characteristics are shown in Table 3.
Table 3 Decimation filter characteristics
ITEM |
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VALUE (dB) |
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|
|
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0 to 0.45fs |
0.01 |
Stop band |
>0.55fs |
−70 |
Dynamic range |
0 to 0.45fs |
>135 |
Digital output |
at 0 dB input |
−1.5 |
level |
analog |
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|
8.3.1OVERLOAD DETECTION
The UDA1380 is equipped with an overload detector which can be read out from the L3-bus or I2C-bus interface.
In practice the output is used to indicate whenever the output data, in either the output of the left or right channel, exceeds −1 dB (the actual figure is −1.16 dB) of the maximum possible digital swing. When this condition is detected the output bit OVERFLOW in the L3-bus register is forced to logic 1 for at least 512fs cycles (11.6 ms at
fs = 44.1 kHz). This time-out is reset for each infringement.
8.3.2VOLUME CONTROL
The decimator is equipped with a digital volume control. This volume control is separate for left and right and can be set with bits ML_DEC [7:0] and bits MR_DEC [7:0] via the L3-bus or I2C-bus interface. The range is from +24 dB to −63.5 dB and mutes in steps of 0.5 dB.
8.3.3MUTE
The decimator is equipped with a dB-linear mute which mutes the signal in 256 steps of 0.5 dB.
8.3.4AGC FUNCTION
The decimation filter is equipped with an AGC block. This function is intended, when enabled, to keep the output signal at a constant level. The AGC can be used for microphone applications in which the distance to the microphone is not always the same.
The AGC can be enabled via an L3-bus or I2C-bus bit by setting the bit to logic 1. In that case it bypasses the digital volume control.
Via the L3-bus or I2C-bus interface also some other settings of the AGC, like the attack and decay settings and the target level settings, can be made.
Remark: The DC filter before the decimation filter must be enabled by setting the L3-bus or I2C-bus bit SKIP_DCFIL to logic 0 when AGC is in operation; otherwise the output will be disturbed by the DC offset added in the ADC.
2002 Sep 16 |
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Philips Semiconductors |
Product specification |
|
|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
8.4Interpolation filter (DAC)
The interpolation digital filter interpolates from 1 to 64fs or to 128fs, by cascading FIR filters, see Table 4. The interpolator is equipped with several sound features like volume control, mute, de-emphasis and tone control.
Table 4 Interpolation filter characteristics
ITEM |
CONDITION |
VALUE (dB) |
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|
|
Pass-band ripple |
0 to 0.45fs |
±0.025 |
Stop band |
>0.55fs |
−60 |
Dynamic range |
0 to 0.45fs |
>135 |
8.4.1DIGITAL MUTE
8.4.2SOUND FEATURES
In addition, there are basic sound features:
∙dB-linear volume control using 14-bit coefficients in steps of 0.25 dB: range 0 to −78 dB maximum suppression and −∞ dB: applies to both master volume and mixing volume control
∙De-emphasis for 32, 44.1, 48 and 96 kHz for both channel 1 and 2 (selectable independently)
∙Treble, which is selectable gain for high frequencies (positive gain only), the edge frequency of the treble is fixed (depends on the sampling frequency). Can be set for left and right independently:
–Two settings: fc = 1.5 kHz and fc = 3 kHz, assuming sampling frequency is 44.1 kHz
Muting the DAC will result in a cosine roll-off soft mute, using 4 × 32 = 128 samples in normal mode (or 3 ms at 44.1 kHz sampling frequency). The cosine roll-off curve is illustrated in Fig.8. These cosine roll-off functions are implemented for both the digital mixer and the master mute inside the DAC data path, see Section 8.8.
MGU119
1 handbook, halfpage
mute factor
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Fig.8 Mute as a function of raised cosine roll-off, displayed assuming 44.1 kHz.
–Both settings have 0 to 6 dB gain range in steps of 2 dB
∙Bass boost, which is selectable gain for low frequencies (positive gain only). The edge frequency of the bass boost is fixed and depends on the sampling frequency. Can be set for left and right independently:
–Two settings: fc = 250 Hz and fc = 300 Hz, assuming sampling frequency is 44.1 kHz
–First setting: 0 to 18 dB gain range in steps of 2 dB
–Second setting: 0 to 24 dB gain range in steps of 2 dB.
8.5Noise shaper
The noise shaper consists of two mono 3rd-order noise shapers and one time-multiplexed stereo 5th-order noise shaper.
The order of the noise shaper can be chosen between 3rd-order (which runs at 128fs) and 5th-order (which runs at 64fs) via bit SEL_NS in the L3-bus or I2C-bus register. The preferable choice for the noise shaper order is:
∙3rd-order noise shaper is preferred at low sampling frequencies, for instance between 8 and 32 kHz. This is for preventing out-of-band noise from the noise shaper to move into the audio band
∙5th-order noise shaper is normally used at higher sampling frequencies, normally from 32 to 100 kHz.
The noise shaper shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using an FSDAC.
2002 Sep 16 |
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Philips Semiconductors |
Product specification |
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|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
8.6FSDAC
8.6.1GENERAL INFORMATION
The Filter-Stream Digital-to-Analog Converter (FSDAC) is a semi-digital reconstruction filter that converts the
1-bit data stream (running at either 64fs for the 5th-order noise shaper or 128fs for the 3rd-order noise shaper) of the noise shaper into an analog output voltage. The filter coefficients are implemented as current sources, and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity are achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal, capable of driving a line output. The output voltage of the FSDAC scales proportionally with the power supply voltage.
Remark: When the FSDAC is powered-down, the output of the FSDAC becomes high impedance.
8.6.2ANALOG MIXER INPUT
The FSDAC has a mixer input, which makes it possible to mix an analog signal to the output signal of the FSDAC itself. In schematic form this is given in Fig.9.
This mixer input can be used for instance for mixing-in a GSM signal or an FM signal directly to the line output. In the UDA1380, the mixer input is connected from the ADC line input via an AVC unit.
Remark: Before the AVC unit can be used stand-alone, meaning without the digital part running, first the DAC part must be initialised in order to have the DAC output generating zero current. Otherwise the signal will be clipped.
8.7Headphone driver
The UDA1380 is equipped with a headphone driver which can deliver 36 mW (at 3.0 V power supply) into a 16 Ω load.
The headphone driver does not need external
DC decoupling capacitors because it can be DC coupled with respect to a special headphone output reference voltage. This saves two external capacitors (which is quite useful in a portable device).
The headphone driver is equipped with short-circuit protection on all three operational amplifiers (left, right and the virtual ground). Each of the operational amplifiers has a signalling bit which becomes logic 1 in case the limiter is activated, for instance in case of a short-circuit. This means the microcontroller in the system can poll the L3-bus or I2C-bus register of the headphone driver and as soon as, and for as long as, the short-circuit detection bits are activated, the microcontroller can signal the user that something is wrong or power-down the headphone driver (for instance, for energy-saving purposes).
Remark: To improve headphone channel separation
performance, the distance between VREF(HP) and the micro speaker port must be minimized.
8.8Digital and analog mixers (DAC)
8.8.1DIGITAL MIXER
The ADC output signal and digital input signal can be mixed without external DSP as shown in Fig.10. This mixer can be controlled via the microcontroller interface, and must only be enabled when the ADC and the DAC are running at the same frequency. In addition, the mixer output signal can also be applied to the I2S-bus output interface.
handbook, halfpage |
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MGU531
Fig.9 Mixing signals to the FSDAC output (analog domain).
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16 |
Philips Semiconductors |
Product specification |
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Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
data from |
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SEL_SOURCE |
I2S-BUS OUTPUT BLOCK |
Fig.10 Digital mixer (DAC).
8.8.2ANALOG MIXER
The analog mixer, which uses the mixer input of the FSDAC, can mix a signal into the FSDAC output signal via an AVC unit (see Fig.11). The mixer can be used to mix a signal into the FSDAC output signal and play it via the headphone driver without the complete coder-decoder running. The analog control range is 0 to −64.5 dB and mutes in steps
of 1.5 dB, with a gain of 16.5 dB (so actually the range is from +16.5 dB to −48 dB plus mute).
handbook, full pagewidth
from analog front-end
PON_AVC |
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RESISTOR |
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AVC[5:0] L3 or I2C-bus control bits |
enable mixer |
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to FSDAC mixer input
MGU533
Fig.11 Analog mixer configuration.
2002 Sep 16 |
17 |
Philips Semiconductors |
Product specification |
|
|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
8.9Application modes
The operation mode can be set with pin SEL_L3_IIC, either to L3-bus mode (LOW) or to the I2C-bus mode (HIGH) as given in Table 5.
For all features in microcontroller mode see Chapter 9.
Table 5 Pin function in the selected mode
PIN |
L3-BUS MODE |
I2C-BUS MODE |
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SEL_L3_IIC = L |
SEL_L3_IIC = H |
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SCL |
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A1 |
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L3DATA |
SDA |
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Remark: In the I2C-bus mode there is a bit A1 which sets the LSB bit of the address of the UDA1380. In
L3-bus mode this bit is not available, meaning the device has only one L3-bus device address.
8.10Power-on reset
The UDA1380 has a dedicated pin RESET, which has a pull-down resistor. This way a Power-on reset circuit can be made with a capacitor and a resistor at the pin. The internal pull-down resistor cannot be used because of the 5 V tolerant nature of the pad. The pull-down resistor is shielded from the outside world by a transmission gate in order to support 5 V tolerance.
The reset timing is determined by the external capacitor and resistor which are connected to the pin RESET, and the internal pull-down resistor. By the Power-on reset, all the digital sound processing features and the system controlling features are set to the default setting of the L3-bus and I2C-bus control modes.
Remark: The reset time should be at least 1 μs, and during the reset time the system clock should be running. In case the WSPLL is selected as the clock source, a clock must be connected to the SYSCLK input in order to have proper reset of the L3-bus or I2C-bus registers. This is because by default the clock source is set to SYSCLK.
8.11Power-down requirements
The following blocks have power-down control via the L3-bus or I2C-bus interface:
∙Microphone amplifier (LNA) including its Single-Ended to Differential Converter (SDC) and VGA
∙ADC plus SDC and the PGA, for left and right separate
∙Bias generation circuit for the front-end and the FSDAC
∙Headphone driver
∙WSPLL
∙FSDAC.
Clocks of the decimator, interpolator and the analog blocks have separate enable and disable controls.
2002 Sep 16 |
18 |
Philips Semiconductors |
Product specification |
|
|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
8.11.1ANALOG FRONT-END
Figure 12 shows the power control inside the analog front-end. The control of all power-on pins of the ADC front-end is done via separate L3-bus or I2C-bus bits.
PGA_GAINCTRLL
PGA_GAINCTRLR
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MGU534 |
Pin numbers for UDA1380HN in parentheses.
Fig.12 Analog front-end power-down.
8.11.2FSDAC POWER CONTROL
The FSDAC block has power-on pins: one of which shuts down the DAC itself, but leaves the output still at VREF voltage (which is half the power supply). This function is set by the bit PON_DAC in the L3-bus or I2C-bus register.
A second L3-bus or I2C-bus bit shuts down the complete bias circuit of the FSDAC, via bit PON_BIAS in the L3-bus or I2C-bus register. This bit PON_BIAS acts the same as given in Fig.12 for the analog front-end.
8.12Plop prevention
Plops are ticks and other strange sounds, that can occur when a part of a device is powered-up or powered-down, or when switching between modes is done.
Some ways to prevent plops from occurring are:
∙When the FSDAC or headphone driver must be powered-down, first a digital mute is applied. After that
the FSDAC or headphone driver can be powered-down. In case the FSDAC or headphone driver must be powered-up, first the analog part is switched on, then the digital part is demuted
∙When the ADC must be powered-down, a digital mute sequence must be applied. When the digital output signal is completely muted, the ADC can be powered-down. In case the ADC must be powered-up, first the analog part must be powered-up, then the digital part must be demuted
∙When there is a change of for example clock divider settings or clock source (selecting between SYSCLK and WSPLL clock), then also digital mute for that block (either decimator or interpolator) should be used.
Remark: All items mentioned in Section 8.12 are not ‘hard-wired’ implemented, but to be followed by the users as a guideline for plop prevention.
2002 Sep 16 |
19 |
Philips Semiconductors |
Product specification |
|
|
Stereo audio coder-decoder
UDA1380
for MD, CD and MP3
8.13Digital audio data input and output
The supported audio formats for the control modes are:
∙I2S-bus
∙MSB-justified
∙LSB-justified, 16 bits
∙LSB-justified, 18 bits
∙LSB-justified, 20 bits
∙LSB-justified, 24 bits (only for the output interface).
The bit clock BCK can be up to 128fs, or in other words the BCK frequency is 128 times the WS frequency or less: fBCK ≤ 128fWS
Remark: The WS edge must coincide with the negative edge of the BCK at all times, for proper operation of the digital I/O data interface. Figure 13 shows the interface signals.
8.13.1DIGITAL AUDIO INPUT INTERFACE
The digital audio input interface is slave only, meaning the system must provide the WSI and BCKI signals (next to the DATAI signal).
Either the WSPLL locks onto the WSI signal and provides the internal clocks for the interpolator and the FSDAC, or a system clock must be applied which must be in frequency lock to the digital data input interface signals.
8.13.2DIGITAL AUDIO OUTPUT INTERFACE
The digital audio output interface can be either master or slave. The data source for the data output can be selected from either the decimator (ADC front-end) or the digital mixer output.
Remark: The digital mixer output is only valid if both the decimator and the interpolator run at the same clock:
∙In slave mode the signals on pins BCKO, WSO and SYSCLK must be applied from the application (signals must be in frequency lock) and the UDA1380 returns the DATAO signal from the decimator. The applied signal
from pin BCKO can be for instance: 32fs, 48fs, 64fs, 96fs or 128fs
∙In master mode the SYSCLK signal must be applied from the system, but the UDA1380 returns with the BCKO, WSO and the DATAO signals. For the BCKO clock, there are 2 general rules:
–When the SYSCLK is either 256fs or 512fs, the BCKO frequency is supposed to be 64fs
–When the SYSCLK is either 384fs or 768fs, the BCKO signal should be 48fs.
The slave and master modes can be selected by the bit Serial Interface Mode (SIM) in the L3-bus or I2C-bus interface.
9 L3-BUS INTERFACE DESCRIPTION
The UDA1380 has an L3-bus microcontroller interface mode. Controllable system and digital sound processing features are:
∙Software reset
∙System clock frequency (selection between 256fs, 384fs, 512fs and 768fs clock divider settings)
∙Clock mode setting, for instance, which block runs at which clock, and clock enabling
∙Power control for the WSPLL
∙Data input and data output format control, for input and output independently including data source selection for the digital output interface
∙ADC features:
–Digital mute
–AGC enable and settings
–Polarity control
–Input line amplifier control (0 to 24 dB in steps of 3 dB)
–DC filtering control
–Digital gain control (+24 to −63 dB gain in steps of 0.5 dB) for left and right
–Power control
–VGA of the microphone input
–Selection of line or microphone input
∙DAC and headphone driver features:
–Power control FSDAC and headphone driver
–Polarity control
–Mixing control (only available when both decimator and interpolator run at the same speed). This includes the mixer volumes, mute and mixer position switch
–De-emphasis control
–Master volume and balance control
–Flat/minimum/maximum settings for the bass boost and treble
–Tone control: bass boost and treble
–Master mute control
–Headphone driver short-circuit protection status bits.
2002 Sep 16 |
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18 |
17 |
|
16 |
15 |
2 |
1 |
|
|
|
|
20 |
19 |
18 |
17 |
16 |
15 |
2 |
1 |
BCK |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
DATA |
|
|
|
|
|
MSB |
B2 |
B3 |
B4 |
|
B5 |
B6 |
B19 |
LSB |
|
|
|
|
MSB |
B2 |
B3 |
B4 |
B5 |
B6 |
B19 |
LSB |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
LSB-JUSTIFIED FORMAT 20 BITS |
|
|
|
|
|
|
|
|
|
|
|
||
WS |
|
|
|
|
|
LEFT |
|
|
|
|
|
|
|
|
|
|
|
|
RIGHT |
|
|
|
|
|
|
||
|
|
24 |
23 |
22 |
21 |
20 |
19 |
|
18 |
17 |
|
16 |
15 |
2 |
1 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
2 |
1 |
BCK |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DATA |
|
MSB |
B2 |
B3 |
B4 |
B5 |
B6 |
B7 |
B8 |
|
B9 |
B10 |
B23 |
LSB |
MSB |
B2 |
B3 |
B4 |
B5 |
B6 |
B7 |
B8 |
B9 |
B10 |
B23 |
LSB |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
LSB-JUSTIFIED FORMAT 24 BITS |
|
|
|
|
|
|
|
|
|
|
MBL121 |
||
Fig.13 Serial interface input and output formats.
MD, for |
Stereo |
MP3 and CD |
decoder-coder audio |
UDA1380
Semiconductors Philips
specification Product
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