Datasheet UDA1345TS Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

UDA1345TS

Economy audio CODEC

Product specification
Supersedes data of 2000 Apr 18
File under Integrated Circuits, IC01

2000 Dec 19

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

CONTENTS

1 FEATURES

1.1 General

1.2 Multiple format input interface

1.3 DAC digital sound processing

1.4 Advanced audio configuration
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 QUICK REFERENCE DATA
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION

7.1 Analog-to-Digital Converter (ADC)

7.2 Analog front-end

7.3 Decimation filter (ADC)

7.4 Interpolation filter (DAC)

7.5 Double speed

7.6 Noise shaper (DAC)

7.7 The Filter Stream DAC (FSDAC)

7.8 Power control

7.9 L3MODE or static pin control

7.10 L3 microcontroller mode

7.10.1 Pinning definition

7.10.2 System clock

7.10.3 Multiple format input/output interface

7.10.4 ADC input voltage control

7.10.5 Overload detection (ADC)

7.10.6 DC cancellation filter (ADC)

7.11 Static pin mode

7.11.1 Pinning definition

7.11.2 System clock

7.11.3 Mute and de-emphasis

7.11.4 Multiple format input/output interface

7.11.5 ADC input voltage control

7.12 L3 interface

7.12.1 Address mode

7.12.2 Data transfer mode

8 LIMITING VALUES
9 THERMAL CHARACTERISTICS
10 DC CHARACTERISTICS
11 AC CHARACTERISTICS (ANALOG)
12 AC CHARACTERISTICS (DIGITAL)
13 APPLICATION INFORMATION
14 PACKAGE OUTLINE
15 SOLDERING

15.1 Introduction to soldering surface mount
packages

15.2 Reflow soldering

15.3 Wave soldering

15.4 Manual soldering

15.5 Suitability of surface mount IC packages for
wave and reflow soldering methods

16 DATA SHEET STATUS
17 DEFINITIONS
18 DISCLAIMERS

2000 Dec 19 2

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

1 FEATURES

1.1 General

• Low power consumption

• 2.4 to 3.6 V power supply range with 3.0 V typical

• 5 V tolerant TTL compatible digital inputs

• 256, 384 and 512fs system clock

• Supports sampling frequencies from 8 to 100 kHz

• Non-inverting ADC plus integrated high-pass filter to

cancel DC offset

• The ADC supports 2 V (RMS) input signals

• Overload detector for easy record level control

• Separate power control for ADC and DAC

• Integrated digital interpolation filter plus non-inverting

DAC

• Functions controllable either by L3 microcontroller
interface or via static pins

• The UDA1345TSis pinand function compatible withthe
UDA1344TS

• Small package size (SSOP28).

1.2 Multiple format input interface

• I2S-bus, MSB-justified up to 24 bits and LSB-justified
16, 18 and 20 bits format compatible

• Three combined data formatswith MSB data output and
LSB 16, 18 and 20 bits data input

• 1fs input and output format data rate.

1.3 DAC digital sound processing

The sound processing features of the UDA1345TS can
only be used in L3 microcontroller mode:

• Digital dB-linear volume control (low microcontroller
load) via L3 microcontroller with 1 dB steps

• Digital de-emphasis for 32, 44.1 and 48 kHz

• Soft mute via cosine roll-off (in 1024 samples).

1.4 Advanced audio configuration

• Stereo single-ended input configuration

• Stereo line output (under microcontroller volume

control), no post filter required

• High linearity, dynamic range and low distortion.

2 GENERAL DESCRIPTION

The UDA1345TS is a single-chip stereo Analog-to-Digital
Converter (ADC) and Digital-to-Analog Converter (DAC)
with signal processing features employing bitstream
conversion techniques. The low power consumption and
low voltage requirements make the device eminently
suitable for use in low-voltage low-power portable digital
audio equipment which incorporates recording and
playback functions.

The UDA1345TS supports the I2S-bus data format with
word lengths of upto 24 bits, theMSB justified dataformat
with word lengths of up to 20 bits and the LSB justified
serial data format with word lengths of 16, 18 and 20 bits.
The UDA1345TS also supports three combined data
formats with MSB justified data output and LSB 16, 18
and 20 bits data input.

The UDA1345TS can be used either with static pin control
or under L3 microcontroller interface. In L3 mode the
UDA1345TS has basic sound features in playback mode
such as de-emphasis, volume control and soft mute.

Note: in contrast to the UDA1344TS, the UDA1345TS
does not have bass-boost and treble.

3 ORDERING INFORMATION

TYPE NUMBER

NAME DESCRIPTION VERSION

UDA1345TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1

2000 Dec 19 3

PACKAGE

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

4 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA(ADC)

V

DDA(DAC)

V

DDD

I

DDA(ADC)

I

DDA(DAC)

I

DDO(DAC)

I

DDD

T

amb

Analog-to-digital converter

V

i(rms)

(THD + N)/S total harmonic distortion-plus-noise to

S/N signal-to-noise ratio V

α

cs

Digital-to-analog converter

V

o(rms)

(THD + N)/S total harmonic distortion plus

α

cs

S/N signal-to-noise ratio code = 0; A-weighted

ADC analog supply voltage 2.4 3.0 3.6 V
DAC analog supply voltage 2.4 3.0 3.6 V
digital supply voltage 2.4 3.0 3.6 V
ADC analog supply current operating mode − 10 14 mA

ADC power-down − 600 800 mA
ADC power-down all − 300 800 mA

DAC analog supply current operating mode − 4 7.0 mA

DAC power-down − 50 150 µA

DAC operational amplifier supply current operating mode − 2.0 3.0 mA

DAC power-down − 200 400 µA

digital supply current operating mode − 58mA

ADC and DAC power-down − 350 500 µA

ambient temperature −40 − +85 °C

input voltage (RMS value) notes 1 and 2 − 1.0 − V

at 0 dB

signal ratio

= 44.1 kHz −−85 −80 dB

f

s

f

=96kHz −−80 −75 dB

s

at −60 dB; A-weighted

fs= 44.1 kHz −−36 −30 dB

=96kHz −−34 −30 dB

f

s

= 0 V; A-weighted

i

f

= 44.1 kHz 90 96 − dB

s

= 96 kHz 90 94 − dB

f

s

channel separation − 100 − dB

output voltage (RMS value) note 3 − 900 − mV

at 0 dB

noise-to-signal ratio

fs= 44.1 kHz −−85 −80 dB

=96kHz −−80 −71 dB

f

s

at −60 dB; A-weighted

= 44.1 kHz −−37 −30 dB

f

s

=96kHz −−35 −30 dB

f

s

channel separation − 100 − dB

= 44.1 kHz 90 100 − dB

f

s

f

= 96 kHz 90 98 − dB

s

2000 Dec 19 4

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Power performance

P

ADDA

P

DA

P

AD

P

PD

Notes

1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately

1 mA by using a series resistor.

2. The input voltage to the ADC scales proportionally with the power supply voltage.

3. The output voltage of the DAC scales proportionally with the power supply voltage.

powerconsumption in recordand playback

− 64 − mW

mode
power consumption in playback only mode − 36 − mW
power consumption in record only mode − 46 − mW
power consumption in Power-down mode − 2.2 − mW

2000 Dec 19 5

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

5 BLOCK DIAGRAM

handbook, full pagewidth

VINL

V

DDD

V

SSD

DATAO

BCK

WS

DATAI

MP1

V

DDA(ADC)VSSA(ADC)

21

3 5

10

11

18
16
17
19

9

0 dB/6 dB

SWITCH

DC-CANCELLATION FILTER

V

ADCP

ADC

DECIMATION FILTER

DIGITAL INTERFACE

INTERPOLATION FILTER

V

76 4

ADC

ADCN

V

ref(A)

0 dB/6 dB

SWITCH

L3-BUS

INTERFACE

21
20

13

14
15
12

UDA1345TS

NOISE SHAPER

VINR

8

MC1
MC2
MP5

MP2
MP3
MP4
SYSCLK

DAC

VOUTL

26

25 27 23 22

V

DDO

V

SSO

V

DDA(DAC)VSSA(DAC)

Fig.1 Block diagram.

2000 Dec 19 6

DAC

V

ref(D)

24

VOUTR

28

MGS875

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

6 PINNING

SYMBOL PIN TYPE DESCRIPTION

V

SSA(ADC)

V

DDA(ADC)

VINL 3 analog input pad ADC input left
V

ref(A)

VINR 5 analog input pad ADC input right
V

ADCN

V

ADCP

MC1 8 5 V tolerant digital input pad with internal pull-down pad mode control 1 (pull-down)
MP1 9 5V tolerant slew rate controlled digital output pad multi purpose pin 1
V

DDD

V

SSD

SYSCLK 12 5 V tolerant digital Schmitt triggered input pad system clock 256, 384 or 512f
MP2 13 3-level input pad multi purpose pin 2
MP3 14 5 V tolerant digital Schmitt triggered input pad multi purpose pin 3
MP4 15 3-level input pad multi purpose pin 4
BCK 16 5 V tolerant digital Schmitt triggered input pad bit clock input
WS 17 5 V tolerant digital Schmitt triggered input pad word select input
DATAO 18 5 V tolerant slew rate controlled digital output pad data output
DATAI 19 5 V tolerant digital Schmitt triggered input pad data input
MP5 20 5 V tolerant digital Schmitt triggered input pad multi purpose pin 5 (pull down)
MC2 21 5 V tolerant digital input pad with internal pull-down pad mode control 2 (pull-down)
V

SSA(DAC)

V

DDA(DAC)

VOUTR 24 analog output pad DAC output right
V

DDO

VOUTL 26 analog output pad DAC output left
V

SSO

V

ref(D)

1 analog ground pad ADC analog ground
2 analog supply pad ADC analog supply voltage

4 analog pad ADC reference voltage

6 analog pad ADC negative reference voltage
7 analog pad ADC positive reference voltage

10 digital supply pad digital supply voltage
11 digital ground pad digital ground

s

22 analog ground pad DAC analog ground
23 analog supply pad DAC analog supply voltage

25 analog supply pad operational amplifier supply voltage

27 analog ground pad operational amplifier ground
28 analog pad DAC reference voltage

2000 Dec 19 7

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

7.1 Analog-to-Digital Converter (ADC)

handbook, halfpage

V

SSA(ADC)

V

DDA(ADC)

1
2

VINL

3

V

4

ref(A)

VINR

5
V
V

SYSCLK

ADCN
ADCP

MC1
MP1

V

DDD

V

SSD

MP2
MP3

6

7

UDA1345TS

8

9

10
11
12
13

Fig.2 Pin configuration.

MGS876

28
27
26
25
24
23
22
21
20
19
18
17
16
1514

V

ref(D)

V

SSO

VOUTL
V

DDO

VOUTR
V

DDA(DAC)

V

SSA(DAC)

MC2
MP5
DATAI
DATAO
WS
BCK
MP4

The stereo ADC of the UDA1345TS consists of two
5th-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The oversampling ratio is 64.

7.2 Analog front-end

The analog front-end isequipped with aselectable 0 dB or
6 dB gain block (the pin to select this mode is given in
Section 7.10). This block can be used in applications in
which both 1 V (RMS) and 2 V (RMS) input signals can be
input to the UDA1345TS.

In applications in which a 2 V (RMS) input signal is used,
a12kΩresistor must be used inseries with theinput ofthe
ADC.This forms a voltage divider together with the internal
ADC resistor and ensures that only 1 V (RMS) maximum
is input to the IC. Using this application for a 2 V (RMS)
input signal, the switch must be set to 0 dB. When a
1 V (RMS) input signal is input to the ADC in the same
application, the gain switch must be set to 6 dB.

An overview of the maximum input voltages allowed
againstthepresence of an external resistor andthe setting
of the gain switch is given in Table 1; the power supply
voltage is assumed to be 3 V.

7 FUNCTIONAL DESCRIPTION

The UDA1345TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clocks (being the system clock itself
and the digital audio interface signals).

Thesystem clock must be locked in frequency to the audio
digital interface input signals.

The BCK clock can be up to 128fs, or in other words the
BCK frequency is 128 times the Word Select (WS)
frequency or less: f

= < 128 × fWS.

BCK

Important: the WS edge MUST fall on the negative edge
oftheBCK at all times for properoperationof the digital I/O
data interface.

Note: the sampling frequency range is from 8 to 100 kHz,
however for the 512fs clock mode the sampling range is
from 8 to 55 kHz.

Table 1 Application modes using input gain stage

RESISTOR

(12 kΩ)

INPUT GAIN

SWITCH

MAXIMUM

INPUT

VOLTAGE

Present 0 dB 2 V (RMS)
Present 6 dB 1 V (RMS)
Absent 0 dB 1 V (RMS)
Absent 6 dB 0.5 V (RMS)

7.3 Decimation filter (ADC)

Thedecimationfrom 64fsto1fsis performed in two stages.
The first stage realizes a 4th-order characteristic.

sin x

----------- ­x

This filter decreases the sample rate by 8. The second
stage consists of 2 half-band filters and a recursive filter,
each decimating by a factor of 2.

2000 Dec 19 8

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

Table 2 Digital decimation filter characteristics

ITEM CONDITIONS VALUE (dB)

Pass-band ripple 0 − 0.45f
Stop band >0.55f
Dynamic range 0 − 0.45f
Overall gain when

DC −1.16

s

s

s

±0.05

−60

114

a 0 dB signal is
input to ADC to
digital output

Note:thedigitaloutputlevel is inversely proportional to the
ADC analog power supply. This means that with a
constant analog input level and increasing power supply
the digital output level will decrease proportionally.

7.4 Interpolation filter (DAC)

The digital filter interpolates from 1 to 128fsby means of a
cascade of a recursive filter and an FIR filter.

Table 3 Digital interpolation filter characteristics

ITEM CONDITIONS VALUE (dB)

Passband ripple 0 − 0.45f
Stopband >0.55f

s

Dynamic range 0 − 0.45f

s

s

±0.03

−65

116.5

Gain DC −3.5

7.7 The Filter Stream DAC (FSDAC)

The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. A post filter is not needed due
to the inherent filter function of the DAC. On-board
amplifiers convert the FSDAC output current to an output
voltage signal capable of driving a line output.

The output voltage of the FSDAC is scaled proportionally
with the power supply voltage.

7.8 Power control

Intheeventthatthe DAC is powered-up or powered-down,
a cosine roll-off mute will be performed (when powering
down) or a cosine roll-up de-mute (when powering up) will
be performed. This is in order to prevent clicks when
powering up or down. This power-on/off mute takes
32 × 4 = 128 samples.

7.9 L3MODE or static pin control

The UDA1345TS can be used under L3 microcontroller
interface mode or under static pin control. The mode can
be set via the Mode Control (MC) pins MC1 (pin 8) and
MC2 (pin 21). The function of these pins is given in
Table 4.

7.5 Double speed

SInce the device supports a sampling range of
8 to 100 kHz, the device can support double speed (e.g.
for 44.1 kHz and 48 kHz sampling frequency) by just
doubling the system speed. In double speed all features
are available.

7.6 Noise shaper (DAC)

The 3rd-order noise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a filter
stream digital-to-analog converter.

2000 Dec 19 9

Table 4 Mode Control pins MC1 and MC2

MODE MC2 MC1

L3MODE LOW LOW
Test modes LOW HIGH

HIGH LOW

Static pin mode HIGH HIGH

Important: in L3MODE the UDA1345TS is completely pin
and function compatible with the UDA1340M and the
UDA1344TS.

Note: the UDA1345TS does NOT supportbass-boost and
treble.

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

7.10 L3 microcontroller mode

The UDA1345TS is set to the L3 microcontroller mode by
setting both MC1 (pin 8) and MC2 (pin 21) LOW.

The definition of the control registers is given in
Section 7.12.

7.10.1 PINNING DEFINITION
The pinning definition underL3 microcontroller interface is

given in Table 5.

Table 5 Pinning definition under L3 control

SYMBOL PIN DESCRIPTION

MP1 9 OVERFL output
MP2 13 L3MODE input
MP3 14 L3CLOCK input
MP4 15 L3DATA input
MP5 20 ADC 1 V or 2 V (RMS) input control

7.10.2 S

YSTEM CLOCK

Under L3 control the options are 256, 384 and 512fs.

7.10.3 MULTIPLE FORMAT INPUT/OUTPUT INTERFACE
The UDA1345TS supports the following data input/output

formats under L3 control:

• I2S-bus with data word length of up to 24 bits

• MSB-justifiedserialformat with data word length ofup to

20 bits

• LSB-justified serial format with data word lengths of
16, 18 or 20 bits

• Three combined data formatswith MSB data output and
LSB 16, 18 and 20 bits data input.

The formats are illustrated in Fig.3. Left and right data
channel words are time multiplexed.

7.10.4 ADC INPUT VOLTAGE CONTROL

The UDA1345TS supports a 2 V (RMS) input using a
series resistor of 12 kΩ as described in Section 7.2. In
L3 microcontroller mode, the gain can be selected via
pin MP5.

When MP5 is set LOW, 0 dB gain is selected. When MP5
is set HIGH, 6 dB gain is selected.

7.10.5 O

VERLOAD DETECTION (ADC)

In practice the output is used to indicate whenever the
output data, in either the left or right channel, is greater
than −1 dB (the actual figure is −1.16 dB) of the maximum
possible digital swing. When this condition is detected the
OVERFL output is forced HIGH for at least 512fs cycles
(11.6 ms at fs= 44.1 kHz). This time-out is reset for each
infringement.

7.10.6 DC CANCELLATION FILTER (ADC)
An optional IIR high-pass filter is provided to remove

unwanted DC components. The operation is selected by
themicrocontrollerviatheL3-bus. The filter characteristics
are given in Table 6.

Table 6 DC cancellation filter characteristics

ITEM CONDITIONS VALUE (dB)

Pass-band ripple none
Pass-band gain 0
Droop at 0.00045f
Attenuation at DC at 0.00000036f
Dynamic range 0 − 0.45f

s

s

s

0.031
>40

>110

7.11 Static pin mode

TheUDA1345TSissettostaticpincontrolmodebysetting
both MC1 (pin 8) and MC2 (pin 21) HIGH.

7.11.1 P

INNING DEFINITION

The pinning definition under static pin control is given in
Table 7.

Table 7 Pinning definition for static pin control

SYMBOL PIN DESCRIPTION

MP1 9 data input/output setting
MP2 13 3-level pin controlling de-emphasis

and mute

MP3 14 256f

or 384fs system clock

s

MP4 15 3-levelpin to control ADC power mode

and 1 V (RMS) or 2 V (RMS) input

MP5 20 data input/output setting

2000 Dec 19 10

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

7.11.2 SYSTEM CLOCK
Under static pin control the options are 256fs and 384fs.

With pin MP3 (pin 14) the mode can be set as is given in
Table 8.

Table 8 System clock settings under static pin mode

MODE MP3

256f

system clock LOW

s

384f

system clock HIGH

s

7.11.3 MUTE AND DE-EMPHASIS
Under static pin control via MP2 de-emphasis and mute

can be selected forthe playback path.The definition of the
MP2 pin is given in Table 9.

Table 9 Settings for pin MP2

MODE MP2

No de-emphasis and mute LOW
De-emphasis 44.1 kHz 0.5V

DDD

Muted HIGH

7.11.5 ADC

INPUT VOLTAGE CONTROL

The UDA1345TS supports a 2 V (RMS) input using a
series resistor as described in Section 7.2.

In static pin mode the 3-level pin MP4 (pin 15) is used to
select 0 or 6 dB gain mode. When MP4 is set LOW the
ADC is powered-down. When MP4 is set to half the power
supply voltage, then 6 dB gain is selected, and when MP4
is set HIGH then 0 dB gain is selected.

Table 11 MP4 mode settings (static mode)

MODE MP4

ADC Power-down mode LOW
6 dB gain mode MID
0 dB gain mode HIGH

7.11.4 M

ULTIPLE FORMAT INPUT/OUTPUT INTERFACE

The data input/output formats supported under static pin
control are as follows:

• I2S-bus with data word length of up to 24 bits

• MSB-justifiedserialformat with data word length ofup to

24 bits

• Two combined data formats with MSB data output and
LSB 16 and 20 bits data input.

The data formats can be selected using pins MP1 (pin 9)
and MP5 (pin 20) as given in Table 10.

Table 10 Data format settings under static pin control

INPUT FORMAT MP1 MP5

MSB mode LOW LOW

2

I

S-bus LOW HIGH

MSB output LSB 20 input HIGH LOW
MSB output LSB 16 input HIGH HIGH

The formats are illustrated in Fig.3. Left and right data
channel words are time multiplexed.

2000 Dec 19 11

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2000 Dec 19 12

ndbook, full pagewidth

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

LEFT

>=8 >=8

MSB B2 MSBLSB LSB MSBB2

LEFT

1321

>=8 >=8

MSB B2 MSBLSB LSB MSB B2B2

LEFT

1516 1

MSB LSBB2

LEFT

RIGHT

321321

INPUT FORMAT I

RIGHT

32

MSB-JUSTIFIED FORMAT

2

B15

LSB-JUSTIFIED FORMAT 16 BITS

215161718 1

2

S-BUS

RIGHT

21516 1

MSB LSBB2 B15

RIGHT

215161718 1

DATA

WS

BCK

DATA

MSB B2 B3 B4

LEFT

MSB B2 B3 B4 B5 B6

LSB

B17

LSB-JUSTIFIED FORMAT 18 BITS

2151617181920 1

LSB

B19

LSB-JUSTIFIED FORMAT 20 BITS

Fig.3 Serial interface formats.

MSB B2 B3 B4

RIGHT

MSB B2 B3 B4 B5 B6

B17

B19

LSB

2151617181920 1

LSB

MGG841

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

7.12 L3 interface

The UDA1345TS has a microcontroller input mode. In the
microcontroller mode, all of the digital sound processing
features and the system controlling features can be
controlledby the microcontroller. The controllablefeatures
are:

• System clock frequency

• Data input format

• Power control

• DC filtering

• De-emphasis

• Volume

• Mute.

Theexchange of data andcontrol information between the
microcontroller and the UDA1345TS is accomplished
through a serial hardware interface comprising the
following pins:

• L3DATA: microcontroller interface data line

• L3MODE: microcontroller interface mode line

• L3CLOCK: microcontroller interface clock line.

Informationtransfervia the microcontroller bus is LSB first,
and is organized in accordance with the so called ‘L3’
format, in which two different modes of operation can be
distinguished; address mode and data transfer mode
(see Figs 4 and 5).

The address mode is required to select a device
communicating via the L3-bus and to define the
destination register set for the data transfer mode. Data
transfer for the UDA1345TS can only be in one direction:
for the UDA1345TS, data can onlybe written to the device.

Important: since the UDA1345TS does not have a
Power-up reset circuit, after power up the L3 interface
registers MUST be initialized.

7.12.1 ADDRESS MODE

The address mode is used to select a device for
subsequent data transfer and to define the destination
register set (DATA or STATUS). The address mode is
characterized by L3MODE being LOW and a burst of
8 pulses on L3CLOCK, accompanied by 8 data bits.
The fundamental timing is shown in Fig.4. Data
bits 0 and 1 indicate the type of subsequent data transfer
as given in Table 12.

Table 12 Selection of data transfer

BIT 1 BIT 0 TRANSFER

0 0 DATA (volume, de-emphasis, mute,

and power control)
0 1 not used
1 0 STATUS(system clock frequency, data

input format and DC filter)
1 1 not used

Data bits 7 to 2 represent a6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The address of the
UDA1345TS is 000101 (bit 7 to bit 2). In theevent that the
UDA1345TS receives a different address, it will deselect
its microcontroller interface logic.

7.12.2 DATA TRANSFER MODE
The selection preformed in the address mode remains

active during subsequent data transfers, until the
UDA1345TS receives a new address command.
The fundamental timing of data transfers is essentially the
same as in the address mode, shown in Fig.4. The
maximum input clock and data rate is 128fs. All transfers
are byte wise,i.e. they are based on groups of 8 bits. Data
will be stored in the UDA1345TS after the eighth bit of a
byte has been received. A multibyte transfer is illustrated
in Fig.6.

7.12.2.1 Programming the sound processing and other
features

The feature values are stored in independent registers.
Thefirstselectionoftheregistersisachievedbythe choice
of data type that is transferred, being DATA or STATUS.
This is performed in the address mode, bit 1 and bit 0
(see Table 12). The second selection is performed by the
2 MSBs of the data byte (bit 7 and bit 6). The other bits in
the data byte (bit 5 to bit 0) are the values that are placed
in the selected registers.

When the data transfer of type DATA is selected, the
features Volume, De-emphasis, Mute and Power control
can be controlled. Whenthe data transferof type STATUS
is selected, the features system clock frequency, data
input format and DC filter can be controlled.

2000 Dec 19 13

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

t

h(MA)

t

BIT 0

t

LC

t

s(MA)

t

s(DAT)

HC

Fig.4 Timing address mode.

t

h(DAT)

t

s(MA)

t

h(MA)

T

cy

BIT 7

MGL883

t

t

s(MT)

halt

BIT 0

t

HC

t

LC

t

h(DAT)

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

write

Fig.5 Timing for data transfer mode.

2000 Dec 19 14

t

s(DAT)

t

halt

T

cy

t

h(DAT)

BIT 7

t

h(MT)

MGL884

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

t

handbook, full pagewidth

L3MODE

L3CLOCK

L3DATA

halt

address

addressdata byte #1 data byte #2

Fig.6 Multibyte transfer.

Table 13 Data transfer of type status

LAST IN TIME FIRST IN TIME

REGISTER SELECTED

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 0 SC1 SC0 IF2 IF1 IF0 DC System Clock frequency (5 : 4);

data Input Format (3 : 1); DC-filter

Table 14 Data transfer of type data

LAST IN TIME FIRST IN TIME

REGISTER SELECTED

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

0 0 VC5 VC4 VC3 VC2 VC1 VC0 Volume Control (5 : 0)
01000000not used
1 0 0 DE1 DE0 MT 0 0 De-Emphasis (4 : 3); MuTe
110000PC1PC0Power Control (1 : 0)

MGD018

2000 Dec 19 15

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

7.12.2.2 System clock frequency

A 2-bit value (SC1 and SC0) to select the used external
clock frequency (see Table 15).

Table 15 System clock frequency settings

SC1 SC0 FUNCTION

0 0 512f
0 1 384f
1 0 256f

s
s
s

1 1 not used

7.12.2.3 Data input format

A 3-bit value (IF2 to IF0) to select the used data format
(see Table 16).

Table 16 Data input format settings

IF2 IF1 IF0 FUNCTION

2

000I

S-bus
0 0 1 LSB-justified; 16 bits
0 1 0 LSB-justified; 18 bits
0 1 1 LSB-justified; 20 bits
1 0 0 MSB-justified
1 0 1 MSB-justified output/

LSB-justified 16 bits input

1 1 0 MSB-justified output/

LSB-justified 18 bits input

1 1 1 MSB-justified output/

LSB-justified 20 bits input

7.12.2.4 DC filter

A 1-bit value to enable the digital DC filter (see Table 17).

Table 17 DC filtering

DC FUNCTION

0 no DC filtering
1 DC filtering

Table 18 Volume settings

VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)

000000 0
000001 0
000010 −1
000011 −2

:::::: :
110011 −50
110100 −52
110001 −54
110010 −57
110111 −60
111000 −66
111001 −∞

:::::: :
111111 −∞

7.12.2.6 De-emphasis

A 2-bit value to enable the digital de-emphasis filter.

Table 19 De-emphasis settings

DE1 DE0 FUNCTION

0 0 no de-emphasis
0 1 de-emphasis; 32 kHz
1 0 de-emphasis; 44.1 kHz
1 1 de-emphasis; 48 kHz

7.12.2.7 Mute

A 1-bit value to enable the digital DAC mute (playback).

Table 20 DAC mute

MT FUNCTION

0 no muting
1 muting

7.12.2.5 Volume control

A 6-bit value to program the left and right channel volume
attenuation (VC5 to VC0). The range is 0 dB to −∞ dB in
steps of 1 dB (see Table 18).

2000 Dec 19 16

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

7.12.2.8 Power control

A 2-bit value to disable the ADC and/or DAC to reduce power consumption.

Table 21 Power control settings

PC1 PC0

FUNCTION

ADC DAC

0 0 off off
0 1 off on
1 0 on off
1 1 on on

8 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages referenced to ground;
V

DDD=VDDA=VDDO

=3V; T

=25°C; unless otherwise specified.

amb

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDD

T

xtal(max)

T

stg

T

amb

V

es

I

lu(prot)

digital supply voltage note 1 − 5.0 V
maximum crystal temperature − 150 °C
storage temperature −65 +125 °C
ambient temperature −40 +85 °C
electrostatic handling according to JEDEC II specification
latch-up protection current T

amb

= 125 °C;

− 200 mA

VDD= 3.6 V

I

sc(DAC)

short-circuit current of DAC T

=0°C; VDD=3V;

amb

note 2

output short-circuited
to V

SSA(DAC)

output short-circuited
to V

DDA(DAC)

− 450 mA

− 325 mA

Notes

1. All V

and VSS connections must be made to the same power supply.

DD

2. DAC operation after short-circuiting cannot be warranted.

9 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to

in free air 90 K/W

ambient

2000 Dec 19 17

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

10 DC CHARACTERISTICS

V

DDD=VDDA=VDDO

(pins 1, 11, 22 and 27); unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA(ADC)

V

DDA(DAC)

V

DDD

I

DDA(ADC)

I

DDA(DAC)

I

DDO(DAC)

I

DDD

Digital input pins (5V tolerant TTL compatible)

V

IH

V

IL

V

IH(th)

V

IL(th)

V

hys

 input leakage current −−10 µA

I

LI

C

i

3-level input pins (MP2; MP4)

V

IH

V

IM

V

IL

Digital output pins

V

OH

V

OL

Analog-to-digital converter

V

ref(A)

R

o(ref)

R

i

C

i

= 3.0 V; fs = 44.1 kHz; T

=25°C; RL=5kΩ; note 1; all voltages referenced to ground

amb

ADC analog supply voltage 2.4 3.0 3.6 V
DAC analog supply voltage 2.4 3.0 3.6 V
digital supply voltage 2.4 3.0 3.6 V
ADC analog supply current operating mode − 10 14 mA

ADC power-down − 600 800 mA
ADC power-down all − 300 800 mA

DAC analog supply current operating mode − 4 7.0 mA

DAC power-down − 50 150 µA

DAC operational amplifier supply
current

operating mode − 2.0 3.0 mA
DAC power-down − 200 400 µA

digital supply current operating mode − 58 mA

ADC and DAC

− 350 500 µA

power-down

HIGH-level input voltage 2.0 − 5.0 V
LOW-level input voltage −0.5 − +0.8 V
HIGH-level threshold input

1.3 − 1.9 V

voltage
LOW-level threshold input voltage 0.9 − 1.35 V
Schmitt trigger hysteresis voltage 0.4 − 0.7 V

input capacitance −−10 pF

HIGH-level input voltage 0.9V
MIDDLE-level input voltage 0.4V

DDD
DDD

− V

DDD

− 0.6V

+ 0.5 V

DDD

V

LOW-level input voltage −0.5 − +0.5 V

HIGH-level output voltage IOH= −2 mA 0.85V

−− V

DDD

LOW-level output voltage IOL=2mA −−0.4 V

reference voltage with respect to V
V

reference output resistance − 24 − kΩ

ref(A)

SSA

0.45V

DDA

0.5V

DDA

0.55V

DDA

V

input resistance fi= 1 kHz − 12 − kΩ
input capacitance − 20 − pF

2000 Dec 19 18

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital-to-analog converter

V

ref(D)

R

o(ref)

R

o

I

o(max)

R

L

C

L

Notes

1. All power supply pins (VDDand VSS) must be connected to the same external power supply unit.

2. When higher capacitive loads must be driven then a 100 Ω resistor must be connected in series with the DAC output
in order to prevent oscillations in the output operational amplifier.

reference voltage with respect to V
V

reference output resistance − 12.5 − kΩ

ref(D)

SSA

0.45V

DDA

0.5V

DDA

0.55V

DDA

V

DAC output resistance − 0.13 3.0 Ω
maximum output current (THD + N)/S < 0.1%;

− 1.7 − mA

RL= 800 Ω
load resistance 3 −− kΩ
load capacitance note 2 −−200 pF

2000 Dec 19 19

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

11 AC CHARACTERISTICS (ANALOG)

V

DDD=VDDA=VDDO

(pins 1, 11, 22 and 27); unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Analog-to-digital converter

V

i(rms)

∆V

i

(THD + N)/S total harmonic distortion plus

S/N signal-to-noise ratio Vi= 0 V; A-weighted

α

cs

PSRR power supply rejection ratio f

Digital-to-analog converter

V

o(rms)

∆V

o

(THD + N)/S total harmonic distortion plus

S/N signal-to-noise ratio code = 0; A-weighted

α

cs

PSRR power supply rejection ratio f

= 3.0 V; fi= 1 kHz; fs = 44.1 kHz; T

=25°C; RL=5kΩ; all voltages referenced to ground

amb

input voltage (RMS value) notes 1 and 2 − 1.0 − V
unbalance between channels − 0.1 − dB

at 0 dB

noise-to-signal ratio

fs= 44.1 kHz −−85 −80 dB
fs= 96 kHz −−80 −75 dB

at −60 dB; A-weighted

fs= 44.1 kHz −−36 −30 dB

= 96 kHz −−34 −30 dB

f

s

fs= 44.1 kHz 90 96 − dB
fs= 96 kHz 90 94 − dB

channel separation − 100 − dB

ripple

V

ripple(p-p)

= 1 kHz;

=1%

− 30 − dB

output voltage (RMS value) note 3 − 900 − mV
unbalance between channels − 0.1 − dB

at 0 dB

noise-to-signal ratio

fs= 44.1 kHz −−85 −80 dB
fs= 96 kHz −−80 −71 dB

at −60 dB; A-weighted

fs= 44.1 kHz −−37 −30 dB
fs= 96 kHz −−35 −30 dB

fs= 44.1 kHz 90 100 − dB
fs= 96 kHz 90 98 − dB

channel separation − 100 − dB

ripple

V

ripple(p-p)

= 1 kHz;

=1%

− 60 − dB

Notes

1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately
1 mA by using a series resistor.

2. The input voltage to the ADC scales proportionally with the power supply voltage.

3. The output voltage of the DAC scales proportionally with the power supply voltage.

2000 Dec 19 20

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

12 AC CHARACTERISTICS (DIGITAL)

V

DDD=VDDA=VDDO

(pins 1, 11, 22 and 27); unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

System clock timing; see Fig.7

T

sys

t

CWL

t

CWH

t

r

t

f

Serial input/output data timing; see Fig.8
t

BCK

t

BCKH

t

BCKL

t

r

t

f

t

s(DATAI)

t

h(DATAI)

t

d(DATAO−BCK)

t

d(DATAO−WS)

t

h(DATAO)

t

s(WS)

t

h(WS)

Address and data transfer mode timing; see Figs 4 and 5
T

cy

t

HC

t

LC

t

s(MA)

t

h(MA)

t

s(MT)

t

h(MT)

= 2.7 to 3.6 V; T

system clock cycle f

f

LOW-level pulse width f

sys

f

HIGH-level pulse width f

sys

= −20 to +85 °C; RL=5kΩ; all voltages referenced to ground

amb

= 256fs; note 1 39 88 488 ns

sys

f

= 384fs; note 1 26 59 325 ns

sys

f

= 512fs; note 2 36 44 244 ns

sys

< 19.2 MHz 0.30T

sys

f

≥ 19.2 MHz 0.40T

sys

< 19.2 MHz 0.30T

sys

≥ 19.2 MHz 0.40T

f

sys

− 0.70T

sys

− 0.60T

sys

− 0.70T

sys

− 0.60T

sys

sys
sys
sys
sys

ns
ns
ns

ns
rise time −−20 ns
fall time −−20 ns

bit clock period

1

⁄

128fs

−−ns
bit clock HIGH time 34 −−ns
bit clock LOW time 34 −−ns
rise time −−20 ns
fall time −−20 ns
data input set-up time 20 −−ns
data input hold time 0 −−ns
data output delay time (from BCK

−−80 ns

falling edge)
data output delay time (from WS edge) MSB-justified format −−80 ns
data output hold time 0 −−ns
word select set-up time 20 −−ns
word select hold time 10 −−ns

L3CLOCK cycle time 500 −−ns
L3CLOCK HIGH period 250 −−ns
L3CLOCK LOW period 250 −−ns
L3MODE set-up time address mode 190 −−ns
L3MODE hold time address mode 190 −−ns
L3MODE set-up time data transfer mode 190 −−ns
L3MODE hold time data transfer mode 190 −−ns

2000 Dec 19 21

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

t

s(DAT)

t

h(DAT)

t

halt

Notes

1. Sampling range from 5 to 100 kHz is supported, with fs= 44.1 kHz typical.

2. Sampling range from 5 to 55 kHz is supported, with fs= 44.1 kHz typical.

L3DATA set-up time data transfer mode

190 −−ns

and address mode

L3DATA hold time data transfer mode

30 −−ns

and address mode

L3MODE halt time 190 −−ns

handbook, full pagewidth

handbook, full pagewidth

WS

BCK

t

CWH

t

CWL

T

sys

MGR984

Fig.7 System clock timing.

t

BCKH

t

r

t

f

t

BCKL

T

cy

t

h(WS)

t

d(DATAO-WS)

t

s(WS)

t

h(DATAO)

t

d(DATAO-BCK)

DATAO

DATAI

Fig.8 Serial interface timing.

2000 Dec 19 22

t

s(DATAI)

t

h(DATAI)

MGL885

Philips Semiconductors Productspecification

h

Economy audio CODEC UDA1345TS

13 APPLICATION INFORMATION

Theapplication information as givenin Fig.9, is anoptimum application environment. Simplification ispossible at the cost
of some performance degradation. The following notes apply:

• The capacitors at the output of the DAC can be reduced. It should be noted that the cut-off frequency of the DC filter
also changes.

• The capacitors at the input of the ADC can also be reduced. It should be noted that the cut-off frequency of the
capacitor with the 12 kW input resistance of the ADC will also change.

andbook, full pagewidth

3 V

ground

system

clock

overload

flag

left

input

right
input

8LM32A07

8LM32A07

X4

X5

L1

L2

C1

47 µF

(16 V)

C6

47 µF

(16 V)

C12

100 µF

(16 V)

R30

47 Ω

C11

100 µF

(16 V)

V

DDA

V

DDD

SYSCLK

DATAO

BCK

DATAI

MP1

VINL

VINR

MP2
MP3
MP4

WS

12

18
16

17
19

9

3

5

13
14
15

100 µF

(16 V)

100 nF

(63 V)

V

SSA(ADC)

1

V

DDA

R21

C2

C21

1 Ω

R24

26711

10 Ω

C25

100 nF

V

DDA(ADC)VADCNVADCPVSSD

(63 V)

UDA1345TS

V

27

SSO

C26

100 nF

(63 V)

C7

100 µF

(16 V)

V

25

DDO

V

R25
1 Ω

DDO

22

V

SSA(DAC)

C27

100 nF

(63 V)

C10

100 µF

(16 V)

V

23

DDA

V

DDD

10

V

DDA(DAC)

R29
1 Ω

R28
10 Ω

V

DDD

V

ref(A)

4

VOUTL

26

VOUTR

24

V

ref(D)

28

C5

47 µF
(16 V)

C8

47 µF
(16 V)

C22
100 nF
(63 V)

C23
100 nF
(63 V)

R22
10 kΩ

R27
10 kΩ

C3
47 µF
(16 V)

R23

100 Ω

R26

100 Ω

C4
47 µF
(16 V)

X2

X3

MGS877

left

output

right

output

Fig.9 Application diagram.

2000 Dec 19 23

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

14 PACKAGE OUTLINE

SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm

SOT341-1

D

c

y

Z

28 15

A

2

A

pin 1 index

114

w M

b

e

p

1

E

H

E

detail X

Q

L

p

L

(A )

A

X

v M

A

A

3

θ

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

A

max.

0.21

mm

2.0

OUTLINE

VERSION

SOT341-1 MO-150

0.05

1.80

0.25

1.65

IEC JEDEC EIAJ

0.38

0.25

p

0.20

0.09

(1)E(1) (1)

cD

10.4

5.4

10.0

REFERENCES

0.65 1.25

5.2

2000 Dec 19 24

eHELLpQZywv θ

7.9

7.6

1.03

0.63

0.9

0.7

EUROPEAN

PROJECTION

0.13 0.10.2

1.1

0.7

ISSUE DATE

95-02-04
99-12-27

o

8

o

0

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

15 SOLDERING

15.1 Introduction to soldering surface mount

packages

Thistextgivesa very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for
certainsurfacemountICs,but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.

15.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board by screen printing,stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.

15.3 Wave soldering

Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadson four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, thepackage must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

15.4 Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

2000 Dec 19 25

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

15.5 Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

SOLDERING METHOD

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2000 Dec 19 26

Philips Semiconductors Productspecification

Economy audio CODEC UDA1345TS

16 DATA SHEET STATUS

DATA SHEET STATUS

Objective specification Development This data sheet contains the design target or goal specifications for

Preliminary specification Qualification This data sheet contains preliminary data, and supplementarydata will be

Product specification Production This data sheet contains final specifications. Philips Semiconductors

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

17 DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseor at any other conditions above thosegiven inthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuchapplicationswillbe
suitable for the specified use without further testing or
modification.

PRODUCT

STATUS

DEFINITIONS

product development. Specification may change in any manner without
notice.

published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

18 DISCLAIMERS Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected toresult in personal injury. Philips
Semiconductorscustomersusingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseofanyof these products, conveys no licence or title
under any patent, copyright, or mask work right to these
products,and makes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

(1)

2000 Dec 19 27

Philips Semiconductors – a w orldwide compan y

Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: seeSouth America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15thfloor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone], Fax. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]

Hungary: seeAustria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT PhilipsDevelopment Corporation,Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. [phone], Fax [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

70

Printed in The Netherlands 753503/03/pp28 Date of release: 2000 Dec 19 Document order number: 9397 750 07498