Datasheet UDA1334TS Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

UDA1334TS

Low power audio DAC

Preliminary specification
File under Integrated Circuits, IC01

1999 Nov 11

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

CONTENTS

1 FEATURES

1.1 General

1.2 Multiple format data interface

1.3 DAC digital sound processing

1.4 Advanced audio configuration
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 ORDERING INFORMATION
5 QUICK REFERENCE DATA
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION

8.1 System clock

8.2 Interpolation filter

8.3 Noise shaper

8.4 Filter stream DAC

8.5 Feature settings

8.5.1 Digital interface format select

8.5.2 Mute control

8.5.3 De-emphasis control

8.5.4 Power control and sampling frequency select

9 LIMITING VALUES
10 HANDLING
11 THERMAL CHARACTERISTICS
12 QUALITY SPECIFICATION
13 DC CHARACTERISTICS
14 AC CHARACTERISTICS

14.1 2.0 V supply voltage

14.2 3.0 V supply voltage

14.3 Timing
15 APPLICATION INFORMATION
16 PACKAGE OUTLINE
17 SOLDERING

17.1 Introduction to soldering surface mount
packages

17.2 Reflow soldering

17.3 Wave soldering

17.4 Manual soldering

17.5 Suitability of surface mount IC packages for
wave and reflow soldering methods

18 DEFINITIONS
19 LIFE SUPPORT APPLICATIONS

1999 Nov 11 2

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

1 FEATURES

1.1 General

• 1.8 to 3.6 V power supply voltage

• Integrated digital filter plus DAC

• Supports sample frequencies from 8 to 100 kHz

• Automatic system clock versus sample rate detection

• Low power consumption

• No analog post filtering required for DAC

• Slave mode only applications

• Easy application

• SSOP16 package.

2 APPLICATIONS

This audio DAC is excellently suitable for digital audio
portable application, such as portable MD, MP3 and
DVD players.

1.2 Multiple format data interface

• I2S-bus and LSB-justified format compatible

• 1fs input data rate.

1.3 DAC digital sound processing

• Digital de-emphasis for 44.1 kHz sampling rate

• Mute function.

1.4 Advanced audio configuration

• High linearity, wide dynamic range and low distortion

• Standby or Sleep mode in which the DAC is powered

down.

4 ORDERING INFORMATION

TYPE

NUMBER

UDA1334TS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

NAME DESCRIPTION VERSION

3 GENERAL DESCRIPTION

The UDA1334TS supports the I2S-bus data format with
word lengths of up to 24 bits and the LSB-justified serial
data format with word lengths of 16, 20 and 24 bits.

The UDA1334TShas basic features such as de-emphasis
(at 44.1 kHz sampling rate) and mute.

PACKAGE

1999 Nov 11 3

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

5 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA

V

DDD

I

DDA

I

DDD

T

amb

Digital-to-analog convertor (V

V

o(rms)

(THD + N)/S total harmonic

S/N signal-to-noise ratio f

α

cs

Digital-to-analog convertor (V

V

o(rms)

(THD + N)/S total harmonic

S/N signal-to-noise ratio f

α

cs

DAC analog supply voltage 1.8 2.0 3.6 V
digital supply voltage 1.8 2.0 3.6 V
DAC analog supply current normal operation − 2.1 − mA

Sleep mode − 150 −µA

digital supply current normal operation − 1.2 − mA

Sleep mode − 50 −µA

ambient temperature −20 − +85 °C

DDA=VDDD

output voltage (RMS value) at 0 dB (FS) digital input;

= 2.0 V)

− 500 − mV

note 1
f

= 44.1 kHz; at 0 dB −−80 − dB

s

distortion-plus-noise to signal ratio

= 44.1 kHz; at −60 dB;

f

s

−−37 − dB

A-weighted
f

= 96 kHz; at 0 dB −−75 − dB

s

f

= 96 kHz; at −60 dB;

s

−−35 − dB

A-weighted

= 44.1 kHz; code = 0;

s

− 97 − dB

A-weighted
f

= 96 kHz; code = 0;

s

− 95 − dB

A-weighted
MUTE = HIGH;

− 110 − dB

A-weighted

channel separation − 100 − dB

DDA=VDDD

output voltage (RMS value) at 0 dB (FS) digital input;

= 3.0 V)

− 750 − mV

note 1

= 44.1 kHz; at 0 dB −−90 − dB

f

s

distortion-plus-noise to signal ratio

f

= 44.1 kHz; at −60 dB;

s

−−40 − dB

A-weighted
f

= 96 kHz; at 0 dB −−85 − dB

s

= 96 kHz; at −60 dB;

f

s

−−37 − dB

A-weighted

= 44.1 kHz; code = 0;

s

− 100 − dB

A-weighted

= 96 kHz; code = 0;

f

s

− 98 − dB

A-weighted
MUTE = HIGH;

− 110 − dB

A-weighted

channel separation − 100 − dB

1999 Nov 11 4

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Power dissipation (at f

= 44.1 kHz)

s

P power dissipation play-back mode; at 2.0 V

supply voltage
play-back mode; at 3.0 V

supply voltage
Sleep mode − 0.5 − mW

Note

1. The DAC output voltage scales proportional to the power supply voltage.

6 BLOCK DIAGRAM

handbook, full pagewidth

BCK

WS

DATAI

V

DDD

4

1
2
3

DIGITAL INTERFACE

V

SSD

5

− 7.0 − mW

− 17 − mW

DE-EMPHASIS

INTERPOLATION FILTER

NOISE SHAPER

DAC

V

SYSCLK

MUTE

DEEM

PCS

VOUTL

UDA1334TS

6
8
9
10

14

13 12

V

DDA

Fig.1 Block diagram.

1999 Nov 11 5

SSA

7

SFOR1

11

SFOR0

V

ref(DAC)

16

VOUTR

MGL877

DAC

15

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

7 PINNING

SYMBOL PIN PAD TYPE DESCRIPTION

BCK 1 5 V tolerant digital input pad; note 1 bit clock input
WS 2 5 V tolerant digital input pad; note 1 word select input
DATAI 3 5 V tolerant digital input pad; note 1 serial data input
V

DDD

V

SSD

SYSCLK 6 5 V tolerant digital input pad; note 1 system clock input
SFOR1 7 5 V tolerant digital input pad; note 1 serial format select 1
MUTE 8 5 V tolerant digital input pad; note 1 mute control
DEEM 9 5 V tolerant digital input pad; note 1 de-emphasis control
PCS 10 3-level input pad; note 2 power control and sampling frequency select
SFOR0 11 digital input pad; note 2 serial format select 0
V

ref(DAC)

V

DDA

VOUTL 14 analog output pad DAC output left
V

SSA

VOUTR 16 analog output pad DAC output right

4 digital supply pad digital supply voltage
5 digital ground pad digital ground

12 analog pad DAC reference voltage
13 analog supply pad DAC analog supply voltage

15 analog ground pad DAC analog ground

Notes

1. 5 V tolerantis only supportedif the powersupply voltage isbetween 2.7 and 3.6 V. Forlower power supplyvoltages
this is maximum 3.3 V tolerant.

2. Because of test issues these pads are not 5 V tolerant and they should be at power supply voltage level or at a
maximum of 0.5 V above that level.

handbook, halfpage

BCK

WS

DATAI

V

DDD

V

SSD

1
2
3
4

UDA1334TS

5
6
7
8

MGL878

16
15
14
13
12
11
10

9

VOUTR
V

SSA

VOUTL
V

DDA

V

ref(DAC)

SFOR0SYSCLK
PCSSFOR1
DEEMMUTE

Fig.2 Pin configuration.

1999 Nov 11 6

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

8 FUNCTIONAL DESCRIPTION

8.1 System clock

The UDA1334TS operates inslave modeonly; thismeans
that in all applicationsthe systemmust providethe system
clock and the digital audio interface signals
(BCK and WS).

Thesystem clockmustbe lockedin frequency tothe digital
interface signals.

The UDA1334TS automatically detects the ratio between
the SYSCLK and WS frequencies.

The BCK clock can be up to 64fs, or in other words the
BCK frequency is 64 times the Word Select (WS)
frequency or less: f

≤ 64 × fWS.

BCK

Important: the WS edge MUST fall on the negative edge
ofthe BCKat all timesfor properoperation of thedigital I/O
data interface.

The modes which are supported are given in Table 1.

Table 1 Supported sampling ranges

CLOCK MODE SAMPLING RANGE

768f
512f
384f
256f
192f
128f

s
s
s
s
s
s

8to55kHz
8 to 100 kHz
8 to 100 kHz
8 to 100 kHz

8 to 100 kHz

8 to 100 kHz

(1)(2)

(2)

Notes

1. This mode can only be supported for power supply
voltages down to 2.4 V. For lower voltages, in
192fsmode the sampling frequency should be limited
to 55 kHz.

2. Not supported in low-sampling frequency mode.

Table 2 Example using a 12.228 MHz system clock

SAMPLING FREQUENCY CLOCK MODE

96 kHz 128f

(1)

64 kHz

48 kHz 256f
32 kHz 384f
24 kHz 512f
16 kHz 768f

192f

s
s
s
s
s
s

Note

1. This mode can only be supported for power supply
voltages down to 2.4 V. For lower voltages, in 192f
mode the sampling frequency should be limited to
55 kHz.

8.2 Interpolation filter

The interpolation digital filter interpolates from 1fsto 64f
by cascading FIR filters (see Table 3).

Table 3 Interpolation filter characteristics

ITEM CONDITION VALUE (dB)

Pass-band ripple 0 to 0.45f
Stop band >0.55f
Dynamic range 0 to 0.45f

s

s

s

±0.02

−50

>114

8.3 Noise shaper

The 5th-order noise shaper operates at 64f

. It shifts

s

in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using an
Filter Stream DAC (FSDAC).

s

s

An example is given in Table 2 for a 12.228 MHz system
clock input.

1999 Nov 11 7

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

8.4 Filter stream DAC

The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivityis achieved. Nopost-filter is needed due to
the inherent filter functionof theDAC. On-boardamplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.

The output voltageof the FSDAC scales proportionalwith
the power supply voltage.

8.5 Feature settings

The features of the UDA1334TS can be set by control
pins SFOR1, SFOR0, MUTE, DEEM and PCS.

8.5.1 DIGITAL INTERFACE FORMAT SELECT
The digital audio interface formats (see Fig.3) can be

selected via the pins SFOR1 and SFOR0 as shown in
Table 4.

The BCK frequency for the digital audio interface can be
maximum 64 times the WS frequency: f

BCK

≤ 64fWS.

Table 4 Data format selection

SFOR1 SFOR0 INPUT FORMAT

LOW LOW I2S-bus input

LOW HIGH LSB-justified 16 bits input
HIGH LOW LSB-justified 20 bits input
HIGH HIGH LSB-justified 24 bits input

8.5.3 DE-EMPHASIS CONTROL
De-emphasis can be switched on for fs= 44.1 kHz by

setting pin DEEM at HIGH level. The function description
of pin DEEM is given in Table 6.

Table 6 De-emphasis control

DEEM FUNCTION

LOW de-emphasis off

HIGH de-emphasis on

8.5.4 POWER CONTROL AND SAMPLING FREQUENCY

SELECT

Pin PCS isa 3-level pin andis used toset the modeof the
UDA1334TS. The definition is given in Table 7.

Table 7 PCS function definition

PCS FUNCTION

LOW normal operating mode

MID low sampling frequency mode

HIGH Power-down or Sleep mode

The low sampling frequency mode is required to have a
higher oversampling rate in the noise shaper in order to
improve the signal-to-noise ratio. In this mode the
oversamplingratio ofthe noiseshaperwill be128f

instead

s

of 64fs.

8.5.2 MUTE CONTROL
The output signal can be soft muted by setting pin MUTE

to HIGH level as shown in Table 5.

Table 5 Mute control

MUTE FUNCTION

LOW mute off

HIGH mute on

When the output signal is fully muted (pin MUTE at
HIGH level), a silence switch inside the FSDAC is
activated. In this way a very high signal-to-noise ratio can
be achieved in case the output is muted.

1999 Nov 11 8

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1999 Nov 11 9

handbook, full pagewidth

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

DATA

WS

BCK

MSB B2

LEFT

RIGHT

3

21> = 812 3

MSB MSBB2

2

S-BUS FORMAT

I

LEFT

16

MSB

LEFT

16

MSB B2 B3 B4 B5 B6

LEFT

16

15 2 1

B2

1518 1720 19 2 1

1518 1720 1922 212324 2 1

B15

LSB-JUSTIFIED FORMAT 16 BITS

B19

LSB-JUSTIFIED FORMAT 20 BITS

> = 8

LSB

LSB

RIGHT

16

MSB B2

RIGHT

16

MSB B2 B3 B4 B5 B6

RIGHT

16

15 2 1

B15 LSB

1518 1720 19 2 1

B19 LSB

1518 1720 1922 212324 21

DATA

MSB

B23

B2

B3 B4

B5 B6 B7 B8 B9 B10

LSB

LSB-JUSTIFIED FORMAT 24 BITS

MSB

B2

B3 B4

B5 B6 B7 B8 B9 B10

B23 LSB

MGS752

Fig.3 Digital audio formats.

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

9 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DD

T

xtal(max)

T

stg

T

amb

V

es

Note

1. All supply connections must be made to the same power supply.

10 HANDLING

Inputs and outputsare protected against electrostatic dischargein normal handling. However, itis good practice to take
normal precautions appropriate to handling MOS devices.

supply voltage note 1 − 4.0 V
maximum crystal temperature − 150 °C
storage temperature −65 +125 °C
ambient temperature −20 +85 °C
electrostatic handling voltage human body model −2000 +2000 V

machine model −200 +200 V

11 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 145 K/W

12 QUALITY SPECIFICATION

In accordance with

“SNW-FQ-611-E”

.

13 DC CHARACTERISTICS

V

DDD=VDDA

= 2.0 V; T

=25°C; RL=5kΩ. All voltages with respect to ground (pins V

amb

SSA

and V

SSD

); unless

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V
V
I

DDA

DDA
DDD

DAC analog supply voltage note 1 1.8 2.0 3.6 V
digital supply voltage note 1 1.8 2.0 3.6 V
DAC analog supply current normal operating mode; at

− 2.1 − mA

2.0 V supply voltage
normal operating mode; at

− 3.3 − mA

3.0 V supply voltage
Sleep mode − 150 −µA

I

DDD

digital supply current normal operating mode; at

− 1.2 − mA

2.0 V supply voltage
normal operating mode; at

− 2.1 − mA

3.0 V supply voltage
Sleep mode − 50 −µA

1999 Nov 11 10

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital input pins; note 2

V

IH

V

IL

ILI input leakage current −−1µA
C

i

3-level input: pin PCS

V

IH

V

IM

V

IL

DAC

V

ref(DAC)

R

O(ref)

I

o(max)

R

L

C

L

Notes

1. All supply connections must be made to the same external power supply unit.

2. At 3 V supply voltage, the input pads are TTL compatible. However, at 2.0 V supply voltage no TTL levels can be
accepted, but levels from 3.3 V domain can be applied to the pins.

3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.

HIGH-level input voltage at 2.0 V supply voltage 1.3 − 3.3 V

at 3.0 V supply voltage 2.0 − 5.0 V

LOW-level input voltage at 2.0 V supply voltage −0.5 − +0.5 V

at 3.0 V supply voltage −0.5 − +0.8 V

input capacitance −−10 pF

HIGH-level input voltage 0.9V
MID-level input voltage 0.4V

− V

DDD

− 0.6V

DDD

DDD

DDD

V
V

LOW-level input voltage 0 − 0.5 V

reference voltage with respect to V
V

reference output

ref(DAC)

SSA

0.45V

DD

0.5V

DD

0.55V

DD

V

− 12.5 − kΩ

resistance
maximum output current (THD + N)/S < 0.1%;

− tbf − mA

RL= 800 Ω
load resistance 3 −−kΩ
load capacitance note 3 −−50 pF

14 AC CHARACTERISTICS

14.1 2.0 V supply voltage

V

DDD=VDDA

= 2.0 V; fi= 1 kHz; T

=25°C; RL=5kΩ. All voltages with respect to ground (pins V

amb

SSA

and V

SSD

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DAC

V

o(rms)

∆V

o

(THD + N)/S total harmonic

output voltage (RMS value) at 0 dB (FS) digital input − 0.5 − V
unbalance between channels − 0.1 − dB

f

= 44.1 kHz; at 0 dB −−80 − dB

s

distortion-plus-noise to signal
ratio

f

= 44.1 kHz; at −60 dB;

s

−−37 − dB

A-weighted
f

= 96 kHz; at 0 dB −−75 − dB

s

= 96 kHz; at −60 dB; A-weighted −−35 − dB

f

s

1999 Nov 11 11

);

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

S/N signal-to-noise ratio f

α

cs

channel separation − 100 − dB

PSRR power supply rejection ratio f

14.2 3.0 V supply voltage

V

DDD=VDDA

= 3.0 V; fi= 1 kHz; T

=25°C; RL=5kΩ. All voltages with respect to ground (pins V

amb

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DAC

V

o(rms)

∆V

o

output voltage (RMS value) at 0 dB (FS) digital input − 0.75 − V
unbalance between channels − 0.1 − dB

(THD + N)/S total harmonic

distortion-plus-noise to signal
ratio

S/N signal-to-noise ratio f

α

cs

channel separation − 100 − dB

PSRR power supply rejection ratio f

= 44.1 kHz; code = 0;

s

− 97 − dB

A-weighted
f

= 96 kHz; code = 0; A-weighted − 95 − dB

s

MUTE = HIGH; A-weighted − 110 − dB

= 1 kHz; V

ripple

f

= 44.1 kHz; at 0 dB −−90 − dB

s

f

= 44.1 kHz; at −60 dB;

s

= 30 mV (p-p) − 60 − dB

ripple

SSA

−−40 − dB

and V

SSD

A-weighted
f

= 96 kHz; at 0 dB −−85 − dB

s

f

= 96 kHz; at −60 dB; A-weighted −−37 − dB

s

= 44.1 kHz; code = 0;

s

− 100 − dB

A-weighted
f

= 96 kHz; code = 0; A-weighted − 98 − dB

s

MUTE = HIGH; A-weighted − 110 − dB

ripple

= 1 kHz; V

= 30 mV (p-p) − 60 − dB

ripple

);

14.3 Timing

V

DDD=VDDA

frequency). All voltages with respect to ground (pins V

= 1.8 to 3.6 V; T

= −20 to +85 °C; RL=5kΩ. The typical timing is specified at fs= 44.1 kHz (sampling

amb

SSA

and V

); unless otherwise specified.

SSD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

System clock timing (see Fig.4)

T

sys

t

CWH

t

CWL

system clock cycle time f

system clock HIGH time f

system clock LOW time f

= 256f

sys

f

sys

f

sys
sys

f

sys
sys

f

sys

s

= 384f

s

= 512f

s

< 19.2 MHz 0.3T
≥ 19.2 MHz 0.4T
< 19.2 MHz 0.3T
≥ 19.2 MHz 0.4T

35 88 780 ns
23 59 520 ns
17 44 390 ns

− 0.7T

sys

− 0.6T

sys

− 0.7T

sys

− 0.6T

sys

sys
sys
sys
sys

1999 Nov 11 12

ns
ns
ns
ns

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Serial interface timing (see Fig.5)

f

BCK

t

BCKH

t

BCKL

t

r

t

f

t

su(DATAI)

t

h(DATAI)

t

su(WS)

t

h(WS)

bit clock frequency −−64f
bit clock HIGH time 50 −−ns
bit clock LOW time 50 −−ns
rise time −−20 ns
fall time −−20 ns
set-up time data input 20 −−ns
hold time data input 0 −−ns
set-up time word select 20 −−ns
hold time word select 10 −−ns

Hz

s

handbook, full pagewidth

handbook, full pagewidth

WS

BCK

t

CWH

t

CWL

T

sys

MGR984

Fig.4 System clock timing.

t

t

BCKH

t

r

T

cy(BCK)

t

f

t

BCKL

h(WS)

t

su(WS)

t

su(DATAI)

t

h(DATAI)

DATAI

Fig.5 Serial interface timing.

1999 Nov 11 13

MGL880

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

15 APPLICATION INFORMATION

handbook, full pagewidth

system

clock

R5

47 Ω

SYSCLK

BCK

WS

DATAI
SFOR1
SFOR0

MUTE

DEEM

PCS

15 13

6

1
2
3
7
11

8
9

10

analog

supply voltage

C9

47 µF

(16 V)

C10

100 nF

(63 V)

V

SSA

R7
1 Ω

V

DDA

UDA1334TS

digital

supply voltage

C5

47 µF

(16 V)

C6

100 nF

(63 V)

V

SSD

45

R6
1 Ω

V

DDD

14

16

12

VOUTL

VOUTR

V

ref(DAC)

C3

47 µF
(16 V)

C4

47 µF
(16 V)

C8
100 nF
(63 V)

100 Ω

R1
220 kΩ

100 Ω

R2
220 kΩ

R3

R4

C7
47 µF
(16 V)

C1

C2

10 nF
(63 V)

10 nF
(63 V)

MGL879

left
output

right
output

Fig.6 Typical application diagram.

1999 Nov 11 14

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

16 PACKAGE OUTLINE

SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm

SOT369-1

D

c

y

Z

16

pin 1 index

9

18

w M

b

e

p

E

H

E

A

2

A

1

L

detail X

A

X

v M

A

Q

(A )

L

p

A

3

θ

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

OUTLINE
VERSION

SOT369-1

A

max.

1.5

0.15

0.00

p

1.4

1.2

IEC JEDEC EIAJ

0.25

0.32

0.20

0.25

0.13

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

(1)E(1)

cD

5.30

5.10

REFERENCES

4.5

4.3

0.65

1999 Nov 11 15

eHELLpQZywv θ

1.0

0.75

0.45

0.65

0.45

PROJECTION

0.130.2 0.1

EUROPEAN

6.6

6.2

(1)

0.48

0.18

ISSUE DATE

94-04-20
95-02-04

o

10

o

0

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

17 SOLDERING

17.1 Introduction to soldering surface mount
packages

Thistext givesavery briefinsight to acomplex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not alwayssuitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

17.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuitboard byscreenprinting, stencillingor
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, solderingand cooling)vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

If wave soldering isused the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wavewith high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackages withleadson foursides,the footprintmust
be placedat a 45° angleto the transport directionof the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and beforesoldering, thepackage must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

17.3 Wave soldering

Conventional single wave soldering is not recommended
forsurface mountdevices(SMDs) orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

1999 Nov 11 16

17.4 Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

17.5 Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

SOLDERING METHOD

HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages arenot suitable for wave soldering as a solder joint between theprinted-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is onlysuitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or largerthan 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave solderingis only suitable for SSOPand TSSOP packageswith a pitch(e) equal to or largerthan 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

18 DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

19 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in suchapplications do so at theirown risk and agree tofully indemnify Philips for anydamages resulting from such
improper use or sale.

1999 Nov 11 17

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

NOTES

1999 Nov 11 18

Philips Semiconductors Preliminary specification

Low power audio DAC UDA1334TS

NOTES

1999 Nov 11 19

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1999

Internet: http://www.semiconductors.philips.com

68

Printed in The Netherlands 545002/25/01/pp20 Date of release: 1999 Nov11 Document order number: 9397 75006399