Datasheet UDA1309H Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

UDA1309H

Low-power stereo bitstream
ADC/DAC

Product specification
Supersedes data of 1996 Jul 18
File under Integrated Circuits, IC01

1998 Jan 06

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

FEATURES

• Low power

• Integrated high-pass filter to cancel DC offset (ADC)

• Analog loop-through function

• Multiple digital input/output formats possible

• 256fs system clock frequency

• Several power-down modes

• Digital de-emphasis (DAC)

• Overload detector to enable automatic recording level

adjustment (ADC)

• High dynamic range

• DAC requires only one capacitor for post-filtering

• Small 44-pin quad flat pack with 0.8 mm pitch

• 256fs system clock frequency in Analog-to-Digital (AD)

and Digital-to-Analog (DA) mode

• Choice of three system clock frequencies
(192fs, 256fs or 384fs) in DA mode.

APPLICATION

• Portable digital audio equipment.

GENERAL DESCRIPTION

The UDA1309H is a single chip stereo analog-to-digital
and digital-to-analog converter employing bitstream
conversion techniques. The device is eminently suitable
for use in low-power portable digital audio equipment
which incorporates recording and playback functions.

ORDERING INFORMATION

TYPE

NUMBER

UDA1309H QFP44 plastic quad flat package; 44 leads (lead length 1.3mm); body 10× 10 × 1.75 mm SOT307-2

NAME DESCRIPTION VERSION

PACKAGE

1998 Jan 06 2

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

QUICK REFERENCE DATA

V

DDD=VDDA=VDDO=VDDD(F)

mode 1; fi= 1 kHz; 16-bit input data; conversion rate = 44.1 kHz; measurement bandwidth = 10 Hz to 20 kHz; unless
otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DDA(AD)

V

DDA(DA)

V

DDO

ADC analog supply voltage (pin 8) 4.5 5.0 5.5 V
DAC analog supply voltage (pin 25) 4.5 5.0 5.5 V
operational amplifiers supply voltage

(pin 19)

V

DDD

ADC and DAC digital supply voltage
(pin 28)

V

DDD(F)

I

DDA(AD)

I

DDA(DA)

I

DDO

digital filters supply voltage (pin 34) 4.5 5.0 5.5 V
ADC analog supply current (pin 8) − 9 13.5 mA
DAC analog supply current (pin 25) − 4.5 6.8 mA
operational amplifiers supply current

(pin 19)

I

DDD

ADC and DAC digital supply current
(pin 28)

I

DDD(F)

T

amb

digital filters supply current (pin 34) − 24 36 mA
operating ambient temperature −20 − +75 °C

Analog-to-digital converter

V

I(rms)

input voltage (RMS value) note 1 0.9 1.0 1.1 V

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

S/N idle channel signal-to-noise ratio V

α

cs

channel separation − 90 − dB

Digital-to-analog converter

V

O(rms)

output voltage (RMS value) note 2 0.9 1.0 1.1 V

(THD + N)/S total harmonic distortion plus

noise-to-signal ratio

S/N idle channel signal-to-noise ratio code 0000H; A-weighted − 104 − dB

α

cs

channel separation 90 100 − dB

=5V; V

SSD=VSSA=VSSO=VSSD(F)

at 0 dB −−85 tbf dB
at −60 dB; A-weighted −−35 −30 dB

= 0 V; A-weighted tbf 95 − dB

I

at 0 dB −−90 −82 dB
at −60 dB; A-weighted −−38 −34 dB
at −60 dB; A-weighted; note 3 −−44 − dB

=0V; T

=25°C; full scale sine wave input;

amb

4.5 5.0 5.5 V

4.5 5.0 5.5 V

− 14 21 mA

− 0.2 0.5 mA

Notes

1. VI for full scale digital output is a function of V

[1.0 V (RMS) at V

DDA(AD)

digital domain].

2. At full scale digital input; no de-emphasis; V

is a function of V

O(rms)

3. 18-bit input data.

1998 Jan 06 3

DDA(AD)

DDA(DA)

= 5.0 V is equivalent to −1.0 dB in the

.

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

BLOCK DIAGRAM

10

µF

µF

ok, full pagewidth

OL

V

analog output

SSA(DA)

V

DDA(DA)

V

SSD(F)

V

DADEM

MODE2

CLKEDGE

TEST0

1 nF

SSO

V

DDO

V

DDD(F)

V

MODE0

MODE1

TEST1

SYSCLK

OLDACL

21

V

22

20

19
26
25
33
34

30

3
42
43
44373840

ref(neg)

V

9

0.22

ref

DA

1.6 kΩ

OR

V

24

DACR

23

SSD

V

27

DDD

V

28

SS(I/O)

V

39

35 29
31
32
36
6
41

1

42
5

1 nF

DAPON

DASDA

ADWS

ADENB

18

1.6 kΩ

DAC

MODE SELECT

Vm

FILTER

DIGITAL

DIGITAL

INTERFACE

DIGITAL

INTERFACE

DAC

UDA1309H

OR

V

analog output

DABCK

DAWS

ANLPTR

ADPON

ADSDA

ADBCK

OVLOAD

MBH527

Fig.1 Block diagram.

DDA(AD)

V

47 µF

IL

V

analog input

4.7 kΩ

0.22 µF

330 pF

7

SSA(AD)

V

ADC

8

DDA(AD)

V

ref(pos)

1112

V

BAOL

4.7 kΩ
BAIL

13

ref

V

10

0.22 µF

DIGITAL

DAC

I

CURRENT

REFERENCE

17
ref

I

47

FILTER

kΩ

1998 Jan 06 4

ADC

Vm

BAOR

15

4.7 kΩ

330 pF

14

BAIR

16

ref

AD

0.22 µF

47 µF

4.7 kΩ

IR

V

analog input

Supply decoupling on pins 19, 25, 28 and 34; 0.22 µF (ceramic), 47 µF (electrolytic).

Capacitance at pin 11 should be close to pins 11 and 9.

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

PINNING

SYMBOL PIN DESCRIPTION

ADBCK 1 ADC input bit clock; 32f
ADWS 2 ADC word select input at f
MODE0 3 ADC/DAC mode select input
ADENB 4 ADC serial data enable input (active HIGH)
OVLOAD 5 ADC output overload flag (active LOW)
ADPON 6 ADC power-on-mode input (active HIGH)
V

SSA(AD)

V

DDA(AD)

V

ref(neg)

V

ref

V

ref(pos)

7 ADC analog ground supply voltage
8 ADC analog supply voltage

9 ADC negative reference voltage input (ground)
10 ADC decoupling capacitor
11 ADC positive reference voltage decoupling capacitor

BAOL 12 ADC input amplifier output left
BAIL 13 ADC input amplifier virtual ground left
BAIR 14 ADC input amplifier virtual ground right
BAOR 15 ADC input amplifier output right
AD
I

ref

DA
V
V
V

ref

ref
DDO
SSO
OL

16 ADC decoupling capacitor
17 ADC/DAC reference current resistor input
18 DAC decoupling capacitor
19 ADC/DAC operational amplifier supply voltage
20 ADC/DAC operational amplifier ground supply voltage

21 DAC output voltage left
DACL 22 DAC output current left
DACR 23 DAC output current right
V

OR

V

DDA(DA)

V

SSA(DA)

V

SSD

V

DDD

24 DAC output voltage right

25 DAC analog supply voltage

26 DAC analog ground supply voltage

27 ADC/DAC digital ground supply voltage

28 ADC/DAC digital supply voltage
DAPON 29 DAC power-on-mode input (active HIGH)
DADEM 30 DAC digital de-emphasis input (active HIGH)
DABCK 31 DAC input bit clock; 32f
DAWS 32 DAC word select input at f
V

SSD(F)

V

DDD(F)

33 ADC/DAC digital filters ground supply voltage

34 ADC/DAC digital filters supply voltage
DASDA 35 DAC serial data input
ANLPTR 36 ADC/DAC analog loop-through input (active HIGH)
TEST0 37 ADC/DAC enable test mode 0 input (LOW is normal mode)
TEST1 38 ADC/DAC enable test mode 1 input (LOW is normal mode)
V

SS(I/O)

39 ADC/DAC digital input/output ground supply voltage
SYSCLK 40 ADC/DAC system clock input (f

or 64f

s

s

s

, 48fs or 64f

s

s

sys

s

= 256fs; DAC also 192fs and 384fs)

1998 Jan 06 5

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

SYMBOL PIN DESCRIPTION

ADSDA 41 ADC serial data output
MODE1 42 ADC/DAC mode 1 select input
MODE2 43 ADC/DAC mode 2 select input
CLKEDGE 44 ADC/DAC input bit clock rising/falling edge

handbook, full pagewidth

ADBCK

ADWS
MODE0
ADENB

OVLOAD

ADPON

V

SSA(AD)

V

DDA(AD)
V

ref(neg)

V

ref(pos)

SSO

DDD(F)

V

DASDA
35

34

21

22

OL

V

DACL

33
32
31
30
29
28
27
26
25
24
23

V
DAWS
DABCK
DADEM
DAPON

V
V
V
V
V
DACR

MBH526

SSD(F)

DDD
SSD
SSA(DA)
DDA(DA)
OR

MODE1

MODE2
43

42

13

14

BAIL

BAIR

ADSDA

41

15

BAOR

CLKEDGE

44

1
2
3
4
5
6
7
8
9

V

10

ref

11

12

BAOL

SS(I/O)

SYSCLK

V

40

39

UDA1309H

16

17

ref

ref

I

AD

TEST1
38

18

ref

DA

TEST0
37

19

DDO

V

ANLPTR
36

20

V

Fig.2 Pin configuration.

1998 Jan 06 6

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

FUNCTIONAL DESCRIPTION

Figure 1 illustrates the various components of the
UDA1309H.
The analog-to-digital converter is a bitstream type
converter, both channels are sampled simultaneously.
The digital-to-analog converter is a BCC (Bitstream
Continuous Calibration) type converter. The digital filter for
the ADC is a bit serial IIR filter that produces a fairly linear
phase response up to 15 kHz. A high-pass filter is
incorporated in the down-sampling path to remove DC
offsets. An overload detection circuit is incorporated to
facilitate automatic recording level adjustment.

The digital up-sample filter for the DAC is partly IIR, with
virtual linear phase response up to 15 kHz, and partly FIR.
A switchable digital de-emphasis circuit is also
incorporated. Due to the BCC principle used, the DAC
needs only single pole post-filtering (one external
capacitor) to meet the out-of-band suppression
requirement.

The ADC and DAC channels have separate power-down
modes, to reduce power if one of them is not in use.
An analog loop-through function enables analog-input
analog-output mode without using the ADC and DAC
converters or filters, thereby switching them off to reduce
power consumption.

The digital interfaces accommodates, 16 and 18-bit,

2

I

S-bus and LSB justified formats. The ADC digital output
can be made 3-state by means of the ADENB signal, this
enables the use of a digital bus.

The UDA1309H interface accommodates slave mode
only, therefore, the system ICs must provide the system
clock, bit clock and word clock signals. For the DAC, the
UDA1309H accepts the data together with these clocks,
for the ADC it delivers the data in response to these clocks.
Within one stereo frame, the first sample always
represents the left channel. When sending data the
unused bit positions are set to zero, when receiving data
these bit positions are don't cares.

To accommodate the various interface formats and
system clock frequencies four control pins are provided,
MODE0 to MODE2 for mode selection and CLKEDGE
which selects the active edge of the BCK signal. Table 1
gives the interface mode selection, Fig.3 illustrates the
ADC/DAC data formats and Fig.5 the operating modes.

The section of the UDA1309H is designed to
accommodate two main modes:

1. The 256fs mode in which analog-to-digital and

digital-to-analog can be used.

2. The 192fs or 384fs mode (digital-to-analog only).

Table 1 Interface mode selection

DEVICE PIN ADC/DAC FORMATS

MODE 2 MODE 1 MODE 0 TYPE BITS BCK SYS; f

0 0 0 LSB justified 16 32f
0 0 1 LSB justified 16 64f
0 1 0 LSB justified 16 48f
0 1 1 LSB justified 18 64f
100I
101I
110I
111I

2

S-bus 16 32f

2

S-bus 16 64f

2

S-bus 16 48f

2

S-bus 18 64f

s
s
s
s
s
s
s
s

Note

1. Only digital-to-analog.

Table 2 Clock edge mode

VALID EDGE OF BCK

CLKEDGE

ADC DAC

0 falling rising
1 rising falling

256f
256f
192f
256f
256f
256f
384f
256f

sys

s
s

(1)

s
s
s
s

(1)

s
s

FIGURE

3(a)
3(b)
4(a)
3(c)
3(d)
3(e)
4(b)

3(f)

1998 Jan 06 7

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

handbook, full pagewidth

BCK

WS

SDA

LSB MSB

BCK

WS

SDA

LSB

BCK

WS

SDA

LSB

MSB

LEFT

LEFT

MSB

LEFT

LSB JUSTIFIED 32fs 16-BIT

LSB MSB

(a)

LSB JUSTIFIED 64fs 16-BIT

LSB

(b)

LSB JUSTIFIED 64fs 18-BIT

LSB

(c)

2

I

S 32fs 16-BIT

RIGHT

RIGHT

MSB LSB

RIGHT

MSB

LSB

LSB

MSB

BCK

WS

SDA

BCK

WS

SDA

BCK

WS

SDA

LEFT

LSB MSB

LEFT

MSB

MSB LSB

LSB

LEFT

Fig.3 DAC and ADC data formats (continued in Fig.4).

RIGHT

LSB MSB

(d)

2

S 64fs 16-BIT

I

RIGHT

MSB LSB MSB

(e)

2

S 64fs 18-BIT

I

RIGHT

MSB

(f)

LSB MSB

LSB

MGE767

1998 Jan 06 8

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

handbook, full pagewidth

BCK

WS

SDA

LSB MSB LSB MSB LSB

BCK

WS

SDA

LEFT

LEFT

LSB JUSTIFIED 48fs 16-BIT

(a)

2

S 48

16-BIT

I

fs

(b)

RIGHT

RIGHT

MSBLSBMSBLSBMSB

MGE768

Fig.4 DAC and ADC data formats (continued from Fig.3).

There are different modes in which the UDA1309H can operate. These modes can be selected as shown in Table 3 and
Fig.5. In mode a, the digital filters clock is switched off. Switching over to one of the ADC active modes (b, c or d) initiates
a reset sequence of the digital filters. This mode should be activated immediately after power-on for at least 2 clock
periods.

Table 3 Operating mode selection

MODE DESCRIPTION

ANLPTR ADPON DAPON

a not used 0 0 0
b record and playback 0 1 1
c record only 0 1 0
d record and analog loop-through 1 1 0
e analog loop-through 1 0 0

f playback only 0 0 1

g and h reserved 1 X

Note

1. X = don’t care.

1998 Jan 06 9

DEVICE PIN LOGIC

(1)

1

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

handbook, full pagewidth

MODE b

MODE c

MODE d

MODE e

MODE f

analog
input

analog
input

analog
input

analog
input

ADC

ANALOG

ADC

ANALOG

ADC

ANALOG

ADC

DIGITAL

FILTER

ADC

DIGITAL

FILTER

ADC

DIGITAL

FILTER

digital
input

digital
output

digital
input

DAC

DIGITAL

FILTER

digital
output

digital
output

DAC

DIGITAL

FILTER

DAC

ANALOG

DAC

ANALOG

analog
output

analog
output

analog
output

analog
output

MGE771

Fig.5 Schematic diagram of operating modes.

1998 Jan 06 10

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDA(AD)

V

DDA(DA)

V

DDO

V

DDD

V

DDD(F)

∆V

DD

∆V

SS

V

I

I

IK

I

OK

T

stg

T

amb

V

es

analog supply voltage (pin 8) − 6.5 V
analog supply voltage (pin 25) − 6.5 V
operational amplifiers supply voltage

− 6.5 V

(pin 19)
digital supply voltage (pin 28) − 6.5 V
digital filters supply voltage (pin 34) − 6.5 V
maximum supply voltage difference − 100 mV
maximum ground supply voltage

− 100 mV

difference
maximum input voltage −0.5 VDD+ 0.5 V
DC clamp input diode current VI< −0.5 V or

−±10 mA

VI>VDD+ 0.5 V

DC output clamp diode current;
(output type 2 mA)

VO< −0.5 V or
VO>VDD+ 0.5 V

−±10 mA

storage temperature −65 +150 °C
operating ambient temperature −20 +75 °C
electrostatic handling note 1 −1500 +1500 V

note 2 −300 +300 V

Notes

1. Human body model: C = 100 pF; R = 1.5 kΩ; 3 zaps positive and 3 zaps negative.

2. Machine model: C = 200 pF; L = 0.5 µH; R = 10 Ω; 3 zaps positive and 3 zaps negative.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 60 K/W

QUALITY SPECIFICATION

In accordance with

Handbook”

. The handbook can be ordered using the code 9397 750 00192.

“SNW-FQ-611E”

. The number of this quality specification can be found in the

“Quality Reference

1998 Jan 06 11

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

CHARACTERISTICS

V

DDD=VDDA=VDDO=VDDD(F)

mode 1; fi= 1 kHz; 16-bit input data; conversion rate = 44.1 kHz; measurement bandwidth = 10 Hz to 20 kHz; unless
otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply

V

DDA(AD)

ADC analog supply
voltage (pin 8)

V

DDA(DA)

DAC analog supply
voltage (pin 25)

V

DDO

operational amplifiers
supply voltage (pin 19)

V

DDD

ADC/DAC digital supply
voltage (pin 28)

V

DDD(F)

digital filters supply voltage
(pin 34)

I

DDA(AD)

ADC analog supply current
(pin 8)

I

DDA(DA)

DAC analog supply current
(pin 25)

I

DDO

operational amplifiers
supply current (pin 19)

I

DDD

ADC/DAC digital supply
current (pin 28)

I

DDD(F)

digital filters supply current
(pin 34)

I

DDD(F)q

digital filters quiescent
current

=5V; V

SSD=VSSA=VSSO=VSSD(F)

=0V; T

=25°C; full scale sine wave input;

amb

4.5 5.0 5.5 V

4.5 5.0 5.5 V

4.5 5.0 5.5 V

4.5 5.0 5.5 V

4.5 5.0 5.5 V

− 9 13.5 mA

ADC power-down − 0.8 1.2 mA

− 4.5 6.8 mA

DAC power-down − 1.1 2.0 mA

− 14 21 mA
DAC power-down − 5.5 8.3 mA
ADC power-down − 7.5 11.3 mA
ADC/DAC power-down − 0 − mA

− 0.2 0.5 mA

− 24 36 mA

DAC power-down − 17 26 mA
ADC power-down − 812 mA

−−100 µA

1998 Jan 06 12

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Analog-to-digital converter

V

I(rms)

I

I

∆V

O

RES resolution 16-bit format − 16 − bits

(THD + N)/S total harmonic distortion

S/N idle channel

α

cs

PSRR power supply rejection ratio note 2 −−30 − dB

input voltage (RMS value) note 1 0.9 1.0 1.1 V
input current

−−10 nA

(pins 13 and 14)
unbalance between

−−tbf dB

channels

18-bit format − 18 − bits
at 0 dB −−85 tbf dB

plus noise-to-signal ratio

at −20 dB −−75 − dB
at −60 dB; A-weighted −−35 −30 dB
V

= 0 V; A-weighted tbf 95 − dB

i

signal-to-noise ratio
channel separation − 90 − dB

Digital-to-analog converter

V

O(rms)

output voltage

note 3 0.9 1.0 1.1 V

(RMS value)

∆V

O

unbalance between

− 0.1 − dB

channels

R

L

C

L

load resistance 5 −− kΩ
load capacitance note 4 −−200 pF

RES resolution 16-bit format − 16 − bits

18-bit format − 18 − bits

(THD + N)/S total harmonic distortion

plus noise-to-signal ratio

at 0 dB −−90 −82 dB
at −20 dB −−75 − dB
at −60 dB; A-weighted −−38 −34 dB
at −60 dB; A-weighted;

−−44 − dB
note 5

S/N idle channel

code 0000H; A-weighted − 104 − dB

signal-to-noise ratio

α

cs

channel separation 90 100 − dB

PSRR power supply rejection ratio note 2 −−30 − dB

Analog loop-through (mode e)

(THD + N)/S total harmonic distortion

at 0 dB −−85 − dB

plus noise-to-signal ratio

S/N idle channel

VI= 0 V; A-weighted − 95 − dB

signal-to-noise ratio

G

ltr

E

os

loop-through gain note 1 −−1.1 − dB
DC offset error − 1.0 − mV

1998 Jan 06 13

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Analog-to-digital decimation filter

f

s(o)

f

s(i)

f

sys

B signal bandwidth f
A

sup

α frequency response f
OL

det

Digital-to-analog interpolation filter

f

s(o)

f

s(i)

f

sys

B signal bandwidth f
α frequency response f
SUP out-of-band suppression 40 50 − dB

output sample frequency 28 44.1 54 kHz
input sample frequency − 128f
system clock frequency 256f

= 44.1 kHz 0.02 − 20 kHz

s(o)

aliasing suppression f

− B<fi<2f

s(o)

s(o)

− B;

60 −− dB

s

− 256f

−

s

s

note 6
f

>2f

i

=20Hzto20kHz −0.2 − +0.2 dB

i

− B; note 6 80 −− dB

s(o)

overload detection level note 7 − 0 − dB

output sample frequency − 64f

s

−

input sample frequency 28 44.1 54 kHz
system clock frequency 256f

= 44.1 kHz 0.02 − 20 kHz

s(i)

=20Hzto20kHz −0.2 − +0.2 dB

i

s

− 256f

s

Digital part; note 8
I

NPUTS (PINS 1 TO 4, 6, 29 TO 32, 35 TO 38, 40 AND 42 TO 44)

V

IL

I

 LOW level input current VI=V

IL

I

 HIGH level input current VI=V

IH

C

I(max)

LOW level input voltage −0.5 − 0.3V

SSD
DDD

maximum input

capacitance
INPUT (PINS 1 TO 4, 6, 29 TO 32, 35 TO 38, 40 AND 42 TO 44)
V

IH

HIGH level input voltage 0.7V
OUTPUTS (PINS 5 AND 41)
V

OL

V

OH

 3-state leakage current VO=V

I

OZ

LOW level output voltage IOL= 2 mA −−0.5 V

HIGH level output voltage IOH= −2 mA V

or V

DDD

SSD

DDD

V

−−10 µA

−−10 µA

−−10 pF

DDD

− 0.5 −− V

DDD

− V

DDD

+ 0.5 V

−−10 µA

1998 Jan 06 14

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Timing

BIT CLOCK (BCK) RELATED SIGNALS (see Fig.6); CLKEDGE = 0
T

cy

t

HC

t

LC

t

r

t

f

t

suWS

t

hWS

t

suDA

t

hDA

t

hAD

t

dAD

SYSTEM CLOCK (SYSCLK) RELATED SIGNALS (see Fig.7)
T

cy

t

HC

t

LC

t

r

t

f

Notes

1. VI for full scale digital output is a function of V
digital domain].

2. V

ripple

3. At full scale digital input; no de-emphasis; V

4. For a load capacitance greater than 33 pF a series resistor of 200 Ω is recommended.

5. 18 bits input data.

6. The aliasing suppression frequency is mirrored around 128fs.

7. V

DDA

8. All digital voltages = 4.5 to 5.5 V; all ground supply voltages = 0 V; T

clock period 300 −− ns
clock HIGH time 100 −− ns
clock LOW time 100 −− ns
rise time −−20 ns
fall time −−20 ns
set-up time WS to rising

20 −− ns

edge of BCK
hold time WS to rising edge

0 −− ns

of BCK
set-up time SDA (DAC) to

20 −− ns

rising edge of BCK
hold time SDA (DAC) to

0 −− ns

rising edge of BCK
hold time SDA (ADC) to

0 −− ns

falling edge of BCK
delay time SDA (ADC) to

−−80 ns

falling edge of BCK

clock period 72 −− ns
clock HIGH time 22 −− ns
clock LOW time 22 −− ns
rise time −−10 ns
fall time −−10 ns

= 1% of the supply voltage and f

ripple

[1.0 V (RMS) at V

DDA(AD)

= 100 Hz.

is a function of V

O(rms)

DDA(AD)

DDA(DA)

= 5.0 V is equivalent to −1.0 dB in the

.

= 5 V; indicated digital level is with respect to −1.0 dB (no overload).

= −20 to +75 °C.

amb

1998 Jan 06 15

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

handbook, full pagewidth

CLKEDGE = 1

CLKEDGE = 0

BCK

WS (LRCK)

SDA (DAC)

SDA (ADC)

T

cy

t

HC

t

r

t

f

t

hAD

t

LC

V

H

V

L

t

dAD

t

suWS

t

suDA

t

hWS

t

hDA

MGE769

Fig.6 Serial timing of BCK related signals.

1998 Jan 06 16

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

handbook, full pagewidth

SYSCLK

T

cy

t

HC

t

r

t

f

t

LC

Fig.7 Serial timing of SYSCLK related signals.

MGE770

1998 Jan 06 17

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

PACKAGE OUTLINE

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm

c

y

X

A

33 23

34

pin 1 index

44

1

22

Z

E

e

H

E

E

w M

b

p

12

11

A

2

A

A

1

detail X

SOT307-2

(A )

3

θ

L

p

L

w M

b

e

DIMENSIONS (mm are the original dimensions)

mm

OUTLINE
VERSION

SOT307-2

A

max.

2.10

0.25

0.05

1.85

1.65

UNIT A1A2A3bpcE

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

p

D

H

D

0.40

0.20

0.25

0.14

0.25

IEC JEDEC EIAJ

Z

D

B

0 2.5 5 mm

scale

(1)

(1) (1)(1)

D

10.1

9.9

REFERENCES

eH

10.1

9.9

12.9

0.8 1.3

12.3

1998 Jan 06 18

v M

H

v M

D

A

B

E

12.9

12.3

LL

p

0.95

0.55

0.15 0.10.15

EUROPEAN

PROJECTION

Z

D

1.2

0.8

Zywv θ

E

1.2

0.8

o

10

o

0

ISSUE DATE

95-02-04
97-08-01

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in

“IC Package Databook”

our

Reflow soldering

Reflow soldering techniques are suitable for all QFP
packages.

The choice of heating method may be influenced by larger
plastic QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our

Reference Handbook”

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.

(order code 9398 652 90011).

“Quality

(order code 9397 750 00192).

If wave soldering cannot be avoided, for QFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

Wave soldering

Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all QFP
packages with a pitch (e) equal or less than 0.5 mm.

1998 Jan 06 19

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1998 Jan 06 20

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

NOTES

1998 Jan 06 21

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

NOTES

1998 Jan 06 22

Philips Semiconductors Product specification

Low-power stereo bitstream ADC/DAC UDA1309H

NOTES

1998 Jan 06 23

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TEL AVIV 61180, Tel. [phone], Fax. [phone]
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20124 MILANO, Tel. [phone], Fax. [phone]
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Tel. [phone], Fax. [phone]
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,

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Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,

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Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
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106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

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Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
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Slovenia: see Italy
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2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
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Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
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Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1998 SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 547027/1200/02/pp24 Date of release: 1998 Jan 06 Document order number: 9397 750 03167