Datasheet UDA1360TS Datasheet (Philips)

INTEGRATED CIRCUITS

DATA SH EET

UDA1360TS

Low-voltage low-power stereo
audio ADC

Preliminary specification
File under Integrated Circuits, IC01

1998 Oct 02

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

FEATURES
General

• Low power consumption

• 2.7 to 3.6 V power supply

• supports 256 and 384f

• Small package size (SSOP16)

• Integrated high-pass filter to cancel DC offset

• Power-down mode

• Supports 2 V (RMS) input signals

• Easy application

• Non-inverting ADC plus decimation filter.

Multiple format output interface

2

• I

S-bus and MSB-justified format compatible

• Up to 20 significant bits serial output.

Advanced audio configuration

system clock

s

GENERAL DESCRIPTION

The UDA1360TS is a single chip stereo Analog-to-Digital
Converter (ADC) employing bitstream conversion
techniques. The low power consumption and low voltage
requirements make the device eminently suitable for use
in low-voltage low-power portable digital audio equipment
which incorporates recording functions.

The UDA1360TS supports the I

2

S-bus data format and the
MSB-justified data format with word lengths of up to
20 bits.

• Stereo single-ended input configuration

• High linearity, dynamic range and low distortion.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V
V
I

DDA

I

DDD

T

DDA
DDD

amb

analog supply voltage 2.7 3.0 3.6 V
digital supply voltage 2.7 3.0 3.6 V
analog supply current − 9 − mA
digital supply current − 3.5 − mA
operating ambient temperature −20 − +85 °C

ADC

V

i(rms)

(THD + N)/S total harmonic distortion plus

S/N signal-to-noise ratio V

α

cs

input voltage (RMS value) see Table 1 − 1.0 − V

at 0 dB −−85 −80 dB

noise-to-signal ratio

at −60 dB; A-weighted −−37 −33 dB

= 0 V; A-weighted − 97 − dB

I

channel separation − 100 − dB

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

UDA1360TS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

1998 Oct 02 2

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

BLOCK DIAGRAM

V

handbook, full pagewidth

V

DDA

V

SSA

16

15 5 4 2

V

ref(n)

ref(p)

UDA1360TS

V

ref

VINL

VINR

DATAO

BCK

WS

1

3

13
11
12

DIGITAL

INTERFACE

SFOR

ADC

(Σ∆)

8

SYSCLK

DECIMATION

FILTER

ADC

(Σ∆)

DC-CANCELLATION

FILTER

6

CLOCK

CONTROL

14

10

MGM967

FSEL

7

PWON

9

V

DDD

V

SSD

Fig.1 Block diagram.

1998 Oct 02 3

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

PINNING

SYMBOL PIN DESCRIPTION

VINL 1 left channel input
V

ref

VINR 3 right channel input
V

ref(n)

V

ref(p)

SFOR 6 data format selection input
PWON 7 power control input
SYSCLK 8 system clock input 256 or 384f
V

DDD

V

SSD

BCK 11 bit clock input
WS 12 word selection input
DATAO 13 data output
FSEL 14 system clock frequency select
V

SSA

V

DDA

2 reference voltage

4 ADC negative reference voltage
5 ADC positive reference voltage

9 digital supply voltage

10 digital ground

15 analog ground
16 analog supply voltage

handbook, halfpage

s

VINL

V

ref

VINR

V

ref(n)

V

ref(p)

SFOR

PWON

SYSCLK

1
2
3
4

UDA1360TS

5
6
7
8

MGM968

16
15
14
13
12
11
10

9

V

DDA

V

SSA

FSEL
DATAO
WS
BCK
V

SSD

V

DDD

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION
System clock

The UDA1360TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system frequency is
selectable via the static FSEL pin, and the system clock
must be locked in frequency to the digital interface input
signals.

The options are 256f

(FSEL = LOW) and 384f

s

s

(FSEL = HIGH).

Analog-to-Digital Converter (ADC)

The stereo ADC of the UDA1360TS consists of two
3rd-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The over-sampling ratio is 128.

Input level

The overall system gain is proportional to V

. The 0 dB

DDA

input level is defined as that which gives a −1 dBFS digital
output (relative to the full-scale swing). In addition, an input
gain switch is incorporated with the above definitions.

The UDA1360TS front-end is equipped with a selectable
0 or 6 dB gain, in order to supports 2 V (RMS) input using
a series resistor of 12 kΩ.

For the definition of the pin settings for 1 or 2 V (RMS)
mode given in Table 1, it is assumed that this resistor is
present as a default component.

If the 2 V (RMS) signal input is not needed, the external
resistor should not be used.

Table 1 Application modes using input gain stage

RESISTOR

(12 kΩ)

INPUT GAIN

SWITCH

MAXIMUM INPUT

VOLTAGE

Present 0 dB 2 V (RMS)
Present 6 dB 1 V (RMS)

Absent 0 dB 1 V (RMS)
Absent 6 dB 0.5 V (RMS)

Multiple format output interface

The UDA1360TS supports the following data output
formats;

2

• I

S-bus with data word length of up to 20 bits

• MSB-justified serial format with data word length of up to

20 bits.

The output format can be set by the static SFOR pin. When
SFOR is LOW, the I2S-bus is selected, when SFOR is set
HIGH the MSB-justified format is selected.

1998 Oct 02 4

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

The data formats are illustrated in Fig.4. Left and right data
channel words are time multiplexed.

Decimation filter

The decimation from 128f

is performed in two stages.

s

The first stage realizes 3rd-order sinx/x characteristic. This
filter decreases the sample rate by 16. The second stage
(an FIR filter) consists of 3 half-band filters, each
decimating by a factor of 2.

Table 2 DC cancellation filter characteristics

ITEM CONDITION

VALUE

(dB)

Pass-band ripple none
Pass-band gain 0
Droop at 0.00045f

s

Attenuation at DC at 0.00000036f
Dynamic range 0 to 0.45f

s

0.031
>40

s

>110

Mute

On recovery from power-down, the serial data output
DATAO is held LOW until valid data is available from the
decimation filter. This time tracks with the sampling
frequency:

t

12288

---------------­f

279 ms==

s

; where fs= 44.1 kHz.

Power-down mode

The PWON pin can control the power saving together with
the optional gain switch for 2 V (RMS) or 1 V (RMS) input.
When the PWON pin is set LOW, the ADC is set to
power-down. When PWON is set to HIGH or to half the
power supply, then either 6 dB gain or 0 dB gain in the
analog front-end is selected.

Application modes

The UDA1360TS can be set to different modes using two
3-level pins and one 2-level pin. The selection of modes is
given in Table 3.

Table 3 Mode selection summary

PIN V

SS

1

⁄2V

DD

V

DD

SFOR I2S-bus test mode MSB
PWON power-down 0 dB gain 6 dB gain
FSEL 256f

s

− 384f

s

handbook, full pagewidth

WS

t

BCK(H)

t

f

t

BCK(L)

T

cy

t

h;WS

t

d;DAT(WS)

BCK

DATAO

t

r

Fig.3 Serial interface timing.

1998 Oct 02 5

t

s;WS

t

h;DAT

t

d;DAT

MGM969

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134). All voltage referenced to ground,
V

DDD=VDDA

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DDD

V

DDA

T

xtal(max)

T

stg

T

amb

V

es

Notes

1. All V

2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.

3. Equivalent to discharging a 200 pF capacitor via a 0.75 µH series inductor.

= 3 V; T

=25°C; unless otherwise specified.

amb

digital supply voltage note 1 − 5.0 V
analog supply voltage note 1 − 5.0 V
maximum crystal temperature − 150 °C
storage temperature −65 +125 °C
operating ambient temperature −20 +85 °C
electrostatic handling note 2 −3000 +3000 V

note 3 −300 +300 V

and VSS connections must be made to the same power supply.

DD

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 140 K/W

1998 Oct 02 6

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

DC CHARACTERISTICS

V

DDD=VDDA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA

V

DDD

I

DDA

I

DDD

Digital inputs

P

INS BCK, FSEL, SYSCLK AND WS

V

IH

V

IL

I

 input leakage current −−10 µA

LI

C

I

PINS PWON AND SFOR
V

IH

V

IM

V

IL

Digital output; Pin DATAO

V

OH

V

OL

Analog

V

ref

R

I

C

I

=3V; T

=25°C; all voltages referenced to ground (pins 10 and 15); unless otherwise specified.

amb

analog supply voltage note 1 2.7 3.0 3.6 V
digital supply voltage note 1 2.7 3.0 3.6 V
analog supply current operation mode − 9 − mA

power-down mode − 3.5 − mA

digital supply current operation mode − 3.5 − mA

power-down mode − 0.5 − mA

HIGH-level input voltage 0.8V

DDD

LOW-level input voltage −0.5 − 0.2V

− V

DDD

DDD

+ 0.5 V

input capacitance −−10 pF

HIGH-level input voltage 0.8V
MIDDLE-level input voltage 0.3V

DDD
DDD

LOW-level input voltage −0.5 − 0.2V

HIGH-level output voltage IOH= −2 mA 0.85V

− V

− 0.7V

−− V

DDD

DDD

DDD
DDD

+ 0.5 V

LOW-level output voltage IOL=2mA −−0.4 V

reference voltage referenced to V

SSA

0.45V

DDA

0.5V

DDA

0.55V

DDA

input resistance − 12 − kΩ
input capacitance − tbf − pF

V

V
V

V

Note

1. All power supply pins (V

and VSS) must be connected to the same external power supply unit.

DD

1998 Oct 02 7

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

AC CHARACTERISTICS (ANALOG)

V

DDD=VDDA

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT

V

i(rms)

∆V

i

(THD + N)/S total harmonic distortion plus

S/N signal-to-noise ratio V

α

cs

PSRR power supply rejection ratio tbf − dB

AC CHARACTERISTICS (DIGITAL)

V

DDD=VDDA

unless otherwise specified.

=3V; fi= 1 kHz; T

=25°C; all voltages referenced to ground (pins 10 and 15);

amb

input voltage (RMS value) see Table 1 1.0 − V
unbalance between channels 0.1 − dB

at 0 dB −85 −80 dB

noise-to-signal ratio

at −60 dB; A-weighted −37 −33 dB

= 0 V; A-weighted 97 − dB

I

channel separation 100 − dB

= 2.7 to 3.6 V; T

= −20 to +85 °C; all voltages referenced to ground (pins 10 and 15);

amb

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Timing

T

t

CWL

t

CWH

sys

clock cycle f

f

LOW-level pulse width 0.4T

sys

f

HIGH-level pulse width 0.4T

sys

f

sys
sys

= 256f
= 384f

s
s

78 88 131 ns
52 59 87 ns

− 0.6T

sys

− 0.6T

sys

sys
sys

Serial data timing (see Fig.3)
T

cy

t

BCK(H)

t

BCK(L)

t

r

t

f

t

d;DAT

bit clock frequency −−64 kHz
bit clock HIGH time 100 −−ns
bit clock LOW time 100 −−ns
rise time −−20 ns
fall time −−20 ns
data output delay time (from BCK

−−80 ns

falling edge)

t

d;DAT(WS)

data output delay time (from WS

MSB-justified format −−80 ns

edge)

t

h;DAT

t

s;WS

data output hold time 0 −−ns
word selection set-up time 20 −−ns

ns
ns

1998 Oct 02 8

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1998 Oct 02 9

full pagewidth

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

WS

BCK

DATA

WS

BCK

DATA

LEFT

123 1≥823

B2

LEFT

123 1≥823

B2

LSB MSB LSB MSBB2MSB

LSB MSB LSB MSBB2 B2MSB

RIGHT

I2S-BUS FORMAT

RIGHT

MSB-JUSTIFIED FORMAT

≥8

≥8

MGM970

Fig.4 Serial interface formats.

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

APPLICATION INFORMATION

handbook, full pagewidth

X5

X6

V

DDA

V

DDD

V

DDD

X2-1
X2-2
X2-3

V

D

R

in

R

in

R1

1Ω

V

SSD

L1 BLM32A07

L2 BLM32A07

C1

100 µF

(16 V)

V

SSA

C11

47 µF (16 V)

C3

47 µF

(16 V)

C12

47 µF (16 V)

47 µF

(16 V)

X4

R4
47 kΩ

R5
47 kΩ

R10

47 Ω

C4

V

SSA

C2
100 µF
(16 V)

V

SSD

V

SSA

V

C7
100 nF
(63 V)

C8
100 nF
(63 V)

SSD

V

DDD

V

DDA

V

V

VINL

116

V

ref

215

VINR FSEL

314

V

ref(n)

413

UDA1360TS

V

ref(p)

512

SFOR BCK

611

PWON

SSD

SYSCLK

SSD

710

89

R11

47 Ω

V

DDA

V

SSA

DATAO

WS

V

SSD

V

DDD

C6
47 µF
(16 V)

C5

47 µF

(16 V)

V

V

SSD

SSA

C10
100 nF
(63 V)

V

SSD

V

SSD

C9
100 nF
(63 V)

MGM971

R3
1Ω

R7
47 kΩ

R6
47 kΩ

R2
1Ω

V

DDA

V

DDD

X3-1
X3-2
X3-3

X1-1
X1-2
X1-3
X1-4
X1-5
X1-6
X1-7
X1-8
X1-9
X1-10

Fig.5 Application diagram.

1998 Oct 02 10

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

PACKAGE OUTLINE

SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm

D

c

y

Z

16

pin 1 index

9

18

w M

b

e

p

A

2

A

1

E

H

E

detail X

SOT369-1

A

X

v M

A

Q

(A )

L

p

L

A

3

θ

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

mm

OUTLINE
VERSION

SOT369-1

A

max.

1.5

0.15

0.00

b

3

p

1.4

1.2

IEC JEDEC EIAJ

0.25

0.32

0.20

0.25

0.13

UNIT A1A2A

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

(1)E(1)

cD

5.30

5.10

REFERENCES

4.5

4.3

0.65

1998 Oct 02 11

eHELLpQZywv θ

1.0

0.75

0.45

0.65

0.45

PROJECTION

0.130.2 0.1

EUROPEAN

6.6

6.2

(1)

0.48

0.18

ISSUE DATE

94-04-20
95-02-04

o

10

o

0

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

SOLDERING
Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(order code 9398 652 90011).

Reflow soldering

Reflow soldering techniques are suitable for all SSOP
packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.

Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.

Wave soldering

Wave soldering is not recommended for SSOP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following
conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The longitudinal axis of the package footprint must

be parallel to the solder flow and must incorporate
solder thieves at the downstream end.

Even with these conditions, only consider wave
soldering SSOP packages that have a body width of

4.4 mm, that is SSOP16 (SOT369-1) or
SSOP20 (SOT266-1).

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1998 Oct 02 12

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

DEFINITIONS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

1998 Oct 02 13

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

NOTES

1998 Oct 02 14

Philips Semiconductors Preliminary specification

Low-voltage low-power stereo audio ADC UDA1360TS

NOTES

1998 Oct 02 15

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Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

© Philips Electronics N.V. 1998 SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

Printed in The Netherlands 545102/750/01/pp16 Date of release: 1998 Oct 02 Document order number: 9397 750 03598