Philips UDA1355H Technical data

UDA1355H

INTEGRATED CIRCUITS

DATA SHEET

UDA1355H

Stereo audio codec with SPDIF interface

Preliminary specification			2003 Apr 10

Philips Semiconductors	Preliminary specification
Stereo audio codec with SPDIF interface	UDA1355H

CONTENTS

1 FEATURES

1.1General

1.2Control

1.3IEC 60958 input

1.4IEC 60958 output

1.5Digital I/O interface

1.6ADC digital sound processing

1.7DAC digital sound processing

2GENERAL DESCRIPTION

3ORDERING INFORMATION

4QUICK REFERENCE DATA

5BLOCK DIAGRAM

6PINNING

7FUNCTIONAL DESCRIPTION

7.1IC control

7.2Microcontroller interface

7.3Clock systems

7.4IEC 60958 decoder

7.5IEC 60958 encoder

7.6Analog input

7.7Analog output

7.8Digital audio input and output

7.9Power-on reset

8	APPLICATION MODES

8.1Static mode pin assignment

8.2Static mode basic applications

8.3Microcontroller mode pin assignment

8.4Microcontroller mode applications

9	SPDIF SIGNAL FORMAT

9.1SPDIF channel encoding

9.2SPDIF hierarchical layers

9.3Timing characteristics

10 L3-BUS DESCRIPTION

10.1Device addressing

10.2Register addressing

10.3Data write mode

10.4Data read mode

11 I2C-BUS DESCRIPTION

11.1Characteristics

11.2Bit transfer

11.3Byte transfer

11.4Data transfer

11.5Register address

11.6Device address

11.7Start and stop conditions

11.8Acknowledgment

11.9Write cycle

11.10Read cycle

12 REGISTER MAPPING

12.1Address mapping

12.2Read/write registers mapping

12.3Read registers mapping

13LIMITING VALUES

14THERMAL CHARACTERISTICS

15CHARACTERISTICS

16TIMING CHARACTERISTICS

17PACKAGE OUTLINE

18SOLDERING

18.1Introduction to soldering surface mount packages

18.2Reflow soldering

18.3Wave soldering

18.4Manual soldering

18.5Suitability of surface mount IC packages for wave and reflow soldering methods

19DATA SHEET STATUS

20DEFINITIONS

21DISCLAIMERS

22PURCHASE OF PHILIPS I2C COMPONENTS

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Philips Semiconductors	Preliminary specification
Stereo audio codec with SPDIF interface	UDA1355H

1 FEATURES

1.1General

∙2.7 to 3.6 V power supply

∙Integrated digital interpolator filter and Digital-to-Analog Converter (DAC)

∙24-bit data path in interpolator

∙No analog post filtering required for DAC

∙Integrated Analog-to-Digital Converter (ADC), Programmable Gain Amplifier (PGA) and digital decimator filter

∙24-bit data path in decimator

∙Master or slave mode for digital audio data I/O interface

∙I2S-bus, MSB-justified, LSB-justified 16, 18, 20,

and 24 bits formats supported on digital I/O interface.

1.2Control

∙Controlled by means of static pins or microcontroller (L3-bus or I2C-bus) interface.

1.3IEC 60958 input

∙On-chip amplifier for converting IEC 60958 input to CMOS levels

∙Supports level I, II and III timing

∙Selectable IEC 60958 input channel, one of four

∙Supports input frequencies from 28 to 96 kHz

∙Lock indication signal available on pin LOCK

∙40 status bits can be read for left and right channel via L3-bus or I2C-bus

∙Channel status bits available via L3-bus or I2C-bus: lock, pre-emphasis, audio sample frequency, two channel Pulse Code Modulation (PCM) indication and clock accuracy

∙Pre-emphasis information of incoming IEC 60958 bitstream available in register

∙Detection of digital data preamble, such as AC3, available on pin in microcontroller mode.

1.4IEC 60958 output

∙CMOS output level converted to IEC 60958 output signal

∙Full-swing digital signal, with level II timing using crystal oscillator clock

∙32, 44.1 and 48 kHz output frequencies supported in static mode

∙32, 44.1 and 48 kHz output frequencies (including double and half of these frequencies) supported in microcontroller mode

∙Via microcontroller, 40 status bits can be set for left and right channel.

1.5Digital I/O interface

∙Supports sampling frequencies from 16 to 100 kHz

∙Supported static mode:

–I2S-bus format

–LSB-justified 16 and 24 bits format

–MSB-justified format.

∙Supported microcontroller mode:

–I2S-bus format

–LSB-justified 16, 18, 20 or 24 bits format

–MSB-justified format.

∙BCK and WS signals can be slave or master, depending on application mode.

1.6ADC digital sound processing

∙Supports sampling frequencies from 16 to 100 kHz

∙Analog front-end includes a 0 to +24 dB PGA in steps of 3 dB, selectable via microcontroller interface

∙Digital independent left and right volume control of +24 to −63.5 dB in steps of 0.5 dB via microcontroller interface

∙Bitstream ADC operating at 64fs

∙Comb filter decreases sample rate from 64fs to 8fs

∙Decimator filter (8fs to fs) made of a cascade of three FIR half-band filters.

1.7DAC digital sound processing

∙Digital de-emphasis for 32, 44.1, 48 and 96 kHz audio sampling frequencies

∙Automatic de-emphasis when using IEC 60958 to DAC

∙Soft mute made of a cosine roll-off circuit selectable via pin MUTE or L3-bus interface

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Philips Semiconductors	Preliminary specification
Stereo audio codec with SPDIF interface	UDA1355H

∙Programmable digital silence detector

∙Interpolating filter (fs to 64fs or fs to 128fs) comprising a recursive and a FIR filter in cascade

∙Selectable fifth-order noise shaper operating at 64fs or third-order noise shaper operating at 128fs (specially for low sampling frequencies, e.g. 16 kHz) generating bitstream for DAC

∙Filter Stream DAC (FSDAC)

∙In microcontroller mode:

–Left and right volume control (for balance control) 0 to −78 dB and −∞

–Left and right bass boost and treble control

–Optional resonant bass boost control

–Mixing possibility of two data streams.

2 GENERAL DESCRIPTION

The UDA1355H is a single-chip IEC 60958 decoder and encoder with integrated stereo digital-to-analog converters and analog-to-digital converters employing bitstream conversion techniques.

The UDA1355H has a selectable one-of-four SPDIF input (accepting level I, II and III timing) and one SPDIF output

3 ORDERING INFORMATION

which can generate level II output signals with CMOS levels. In microcontroller mode the UDA1355H offers a large variety of possibilities for defining signal flows through the IC, offering a flexible analog, digital and SPDIF converter chip with possibilities for off-chip sound processing via the digital input and output interface.

A lock indicator is available on pin LOCK when the IEC 60958 decoder and the clock regeneration

mechanism is in lock. By default the DAC output and the digital data interface output are muted when the decoder is not in lock.

The UDA1355H contains two clock systems which can run at independent frequencies, allowing to lock-on to an incoming SPDIF or digital audio signal, and in the mean time generating a stable signal by means of the crystal oscillator for driving, for example, the ADC or SPDIF output signal.

Using the crystal oscillator (which requires a 12.288 MHz crystal) and the on-chip low jitter PLL, all standard audio sampling frequencies (fs = 32, 44.1 and 48 kHz including half and double these frequencies) can be generated.

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
UDA1355H	QFP44	plastic quad flat package; 44 leads (lead length 1.3 mm); body	SOT307-2
		10 × 10 × 1.75 mm

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Philips Semiconductors				Preliminary specification
Stereo audio codec with SPDIF interface				UDA1355H
4 QUICK REFERENCE DATA
SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supplies
VDDA1	DAC supply voltage		2.7	3.0	3.6	V
VDDA2	ADC supply voltage		2.7	3.0	3.6	V
VDDX	crystal oscillator and PLL		2.7	3.0	3.6	V
	supply voltage
VDDI	digital core supply voltage		2.7	3.0	3.6	V
VDDE	digital pad supply voltage		2.7	3.0	3.6	V
IDDA1	DAC supply current	fs = 48 kHz; power-on	−	4.7	−	mA
		fs = 96 kHz; power-on	−	4.7	−	mA
		fs = 48 kHz; power-down	−	1.7	−	μA
		fs = 96 kHz; power-down	−	1.7	−	μA
IDDA2	ADC supply current	fs = 48 kHz; power-on	−	10.2	−	mA
		fs = 96 kHz; power-on	−	10.4	−	mA
		fs = 48 kHz; power-down	−	0.2	−	μA
		fs = 96 kHz; power-down	−	0.2	−	μA
IDDX	crystal oscillator and PLL	fs = 48 kHz; power-on	−	0.9	−	mA
	supply current	fs = 96 kHz; power-on	−	1.2	−	mA
IDDI	digital core supply current	fs = 48 kHz; all on	−	18.2	−	mA
		fs = 96 kHz; all on	−	34.7	−	mA
IDDE	digital pad supply current	fs = 48 kHz; all on	−	0.5	−	mA
		fs = 96 kHz; all on	−	0.7	−	mA
Tamb	ambient temperature		−40	−	+85	°C
Digital-to-analog converter; fi = 1 kHz; VDDA1 = 3.0 V
Vo(rms)	output voltage (RMS		−	900	−	mV
	value)
Vo	output voltage unbalance		−	0.1	−	dB
(THD+N)/S	total harmonic	IEC 60958 input; fs = 48 kHz
	distortion-plus-noise to	at 0 dB	−	−88	−	dB
	signal ratio	at −20 dB	−	−75	−	dB
		at −60 dB; A-weighted	−	−37	−	dB
		IEC 60958 input; fs = 96 kHz
		at 0 dB	−	−83	−	dB
		at −60 dB; A-weighted	−	−37	−	dB
S/N	signal-to-noise ratio	IEC 60958 input; code = 0;
		A-weighted
		fs = 48 kHz	−	98	−	dB
		fs = 96 kHz	−	96	−	dB
αcs	channel separation		−	100	−	dB

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Philips Semiconductors				Preliminary specification
Stereo audio codec with SPDIF interface				UDA1355H
SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Analog-to-digital converter; fi = 1 kHz; VDDA2 = 3.0 V
Vi(rms)	input voltage (RMS value)	Vo = −1.16 dBFS digital output	−	1.0	−	V
Vi	input voltage unbalance		−	0.1	−	dB
(THD+N)/S	total harmonic	fs = 48 kHz
	distortion-plus-noise to	at 0 dB	−	−85	−	dB
	signal ratio	at −60 dB; A-weighted	−	−35	−	dB
		fs = 96 kHz
		at 0 dB	−	−85	−	dB
		at −60 dB; A-weighted	−	−35	−	dB
S/N	signal-to-noise ratio	code = 0; A-weighted
		fs = 48 kHz	−	97	−	dB
		fs = 96 kHz	−	95	−	dB
αcs	channel separation		−	100	−	dB
External crystal
fxtal	crystal frequency		−	12.288	−	MHz
CL(xtal)	crystal load capacitor		−	10	−	pF
Device reset
trst	reset time		−	250	−	μs
Power consumption
Ptot	total power consumption	IEC 60958 input; fs = 48 kHz
		DAC in playback mode	−	74	−	mW
		DAC in Power-down mode	−	63	−	mW

2003 Apr 10

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_

10 Apr 2003

full andbook,

codecaudio Stereo

Semiconductors Philips

VDDX

VSSX

VADCP VDDA2

CLK_OUT

VDDI

VREF

VDDE

VDDA1

12

15

32

37

11

27

pagewidth

38

6

39

XTALIN

13

CLOCK AND

XTAL

14

XTALOUT

TIMING

VINL

34

ADC

DAC

40

VOUTL

AUDIO

AUDIO

COMB

DECI-

INTER-

NOISE

DIAGRAMBLOCK5

FEATURE

FEATURE

with

36

FILTER

MATOR

POLATOR SHAPER

42

PROCESSOR

VINR

ADC

PROCESSOR

DAC

VOUTR

RESET

16

44

MUTE

SPDIF

RTCB

43

INPUT

AND

WSI

2

9

WSO

OUTPUT

3

8

DATAI

DATA IN

SELECT

DATA OUT

DATAO

interface

1

10

BCKI

BCKO

SPDIF0

23

SLICER

7

SPDIF1

24

IEC 60958

IEC 60958

25

SPDIF2

DECODER

ENCODER

26

SPDIF3

5

SPDIFOUT

SLICER_SEL0

21

SLICER_SEL1

22

LOCK

4

CONTROL

UDA1355H

INTERFACE

33

35

28

29

30

31

20

17

18

19

7

41

specification Preliminary

MGU826

UDA1355H

VADCN

VSSIS

MP0

MP2

MODE0

MODE2

VSSE

VSSA1

VSSA2

MP1

SEL_STATIC

MODE1

Fig.1

Block diagram.

Philips Semiconductors				Preliminary specification
Stereo audio codec with SPDIF interface				UDA1355H
6 PINNING
SYMBOL	PIN	PAD(1)	DESCRIPTION
BCKI	1	bpt4mtht5v	bit clock input (master or slave)
WSI	2	bpt4mtht5v	word select input (master or slave)
DATAI	3	iptht5v	digital data input
LOCK	4	op4mc	PLL lock indicator output
SPDIFOUT	5	op4mc	SPDIF output
VDDE	6	vdde	digital pad supply voltage
VSSE	7	vsse	digital pad ground
DATAO	8	ops5c	digital data output
WSO	9	bpt4mtht5v	word select output (master or slave)
BCKO	10	bpt4mtht5v	bit clock output (master or slave)
CLK_OUT	11	op4mc	clock output; 256fs or 384fs
VDDX	12	vddco	crystal oscillator and PLL supply voltage
XTALIN	13	apio	crystal oscillator input
XTALOUT	14	apio	crystal oscillator output
VSSX	15	vssco	crystal oscillator and PLL ground
RESET	16	ipthdt5v	reset input
MODE0	17	apio	mode selection input 0 for static mode or microcontroller mode (grounded
			for I2C-bus)
MODE1	18	bpts5tht5v	mode selection input 1 for static mode or AO address input and output for
			microcontroller mode
MODE2	19	bpts5tht5v	mode selection input 2 for static mode or U_RDY output for microcontroller
			mode
SEL_STATIC	20	apio	selection input for static mode, I2C-bus mode or L3-bus mode
SLICER_SEL0	21	bpts5tht5v	SPDIF slicer selection input 0 for static mode and USER bit output for
			microcontroller mode
SLICER_SEL1	22	bpts5tht5v	SPDIF slicer selection input 1 for static mode and AC3 preamble detect
			output for microcontroller mode
SPDIF0	23	apio	SPDIF input 0
SPDIF1	24	apio	SPDIF input 1
SPDIF2	25	apio	SPDIF input 2
SPDIF3	26	apio	SPDIF input 3
VDDI	27	vddi	digital core supply voltage
VSSIS	28	vssis	digital core ground
MP0	29	apio	multi-purpose pin 0: frequency select for static mode, not used for
			microcontroller mode
MP1	30	iptht5v	multi-purpose pin 1: SFOR1 for static mode, SCL for I2C-bus mode and
			L3CLOCK for L3-bus mode
MP2	31	iic400kt5v	multi-purpose pin 2: SFOR0 for static mode, SDA for I2C-bus mode and
			L3DATA for L3-bus mode
VADCP	32	vddco	positive ADC reference voltage
VADCN	33	vssco	negative ADC reference voltage

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Philips Semiconductors				Preliminary specification
Stereo audio codec with SPDIF interface				UDA1355H
SYMBOL	PIN	PAD(1)	DESCRIPTION
VINL	34	apio	ADC left channel input
VSSA2	35	vssco	ADC ground
VINR	36	apio	ADC right channel input
VDDA2	37	vddco	ADC supply voltage
VREF	38	apio	reference voltage for ADC and DAC
VDDA1	39	vddco	DAC supply voltage
VOUTL	40	apio	DAC left channel output
VSSA1	41	vssco	DAC ground
VOUTR	42	apio	DAC right channel output
RTCB	43	ipthdt5v	test control input
MUTE	44	iipthdt5v	DAC mute input
Note
1. See Table 1.
Table 1 Pad description
PAD			DESCRIPTION
iptht5v	input pad; push-pull; TTL with hysteresis; 5 V tolerant
ipthdt5v	input pad; push-pull; TTL with hysteresis; pull-down; 5 V tolerant
op4mc	output pad; push-pull; 4 mA output drive; CMOS
ops5c	output pad; push-pull; 5 ns slew rate control; CMOS
bpt4mtht5v	bidirectional pad; push-pull input; 3-state output; 4 mA output drive; TTL with hysteresis;
	5 V tolerant
bpts5tht5v	bidirectional pad; push-pull input; 3-state output; 5 ns slew rate control; TTL with hysteresis;
	5 V tolerant
iic400kt5v	I2C-bus pad; 400 kHz I2C-bus specification with open drain; 5 V tolerant
apio	analog pad; analog input or output
vddco	analog supply pad
vssco	analog ground pad
vdde	digital supply pad
vsse	digital ground pad
vddi	digital core supply pad
vssis	digital core ground pad

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Philips Semiconductors	Preliminary specification
Stereo audio codec with SPDIF interface	UDA1355H

	MUTE	RTCB	VOUTR	V	VOUTL	V	V	V	VINR	V	VINL
				SSA1		DDA1	REF	DDA2		SSA2
	44	43	42	41	40	39	38	37	36	35	34
BCKI	1										33	VADCN
WSI	2										32	VADCP
DATAI	3										31	MP2
LOCK	4										30	MP1
SPDIFOUT	5										29	MP0
VDDE	6				UDA1355H						28	VSSIS
VSSE	7										27	VDDI
DATAO	8										26	SPDIF3
WSO	9										25	SPDIF2
BCKO 10											24	SPDIF1
CLK_OUT	11										23	SPDIF0

12		13		14		15		16		17		18		19		20		21		22
V		XTALIN		XTALOUT		V		RESET		MODE0		MODE1		MODE2		STATICSEL		SLICERSEL0		SLICERSEL1
DDX						SSX

MGU828

Fig.2 Pin configuration.

7 FUNCTIONAL DESCRIPTION

7.1IC control

The UDA1355H can be controlled either via static pins or via the microcontroller serial hardware interface being the I2C-bus with a clock up to 400 kHz or the L3-bus with a clock up to 2 MHz. It is recommended to use the microcontroller interface since this gives full access to all the IC features.

The two microcontroller interfaces only differ in interface format. The register addresses and features that can be controlled are identical for L3-bus mode and I2C-bus mode.

The UDA1355H can operate in three control modes:

∙Static mode with limited features

∙L3-bus mode with full featuring

∙I2C-bus mode with full featuring.

The modes are selected via the 3-level pin SEL_STATIC according to Table 2.

Table 2 Control mode selection via pin SEL_STATIC

LEVEL	MODE
HIGH	static mode
MID	I2C-bus mode
LOW	L3-bus mode

7.2Microcontroller interface

The UDA1355H has a microcontroller interface and all the sound processing features and system settings can be controlled by the microcontroller.

The controllable settings are:

∙Restoring L3-bus defaults

∙Power-on settings for all blocks

∙Digital interface input and output formats

∙Volume settings for the decimator

∙PGA gain settings

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Philips Semiconductors	Preliminary specification
Stereo audio codec with SPDIF interface	UDA1355H

∙Set two times 40 bits of channel status bits of the SPDIF output

∙Select one of four SPDIF input sources

∙Enable digital mixer inside interpolator

∙Control mute and mixer volumes of digital mixer

∙Selection of filter mode and settings of treble and bass boost for the interpolator (DAC) section

∙Volume settings of interpolator

∙Selection of soft mute via cosine roll-off (only effective in L3-bus control mode) and bypass of auto mute

∙Selection of de-emphasis

∙Enable and control of digital mixer inside interpolator.

The readable settings are:

∙Mute status of interpolator

∙PLL lock and adaptive lock

∙Two times 40 bits of channels status bits of the SPDIF input signal.

7.3Clock systems

The UDA1355H has two clock systems.

The first system uses an external crystal of 12.288 MHz to generate the audio related system clocks. Only a crystal with a frequency of 12.288 MHz is allowed.

The second system is a PLL which locks on the SPDIF or incoming digital audio signal (e.g. I2S-bus) and recovers the system clock.

7.3.1CRYSTAL OSCILLATOR CLOCK SYSTEM

The crystal oscillator and the on-chip PLL and divider circuit can be used to generate internal and external clock signals related to standard audio sampling frequencies (such as 32, 44.1 and 48 kHz including half and double of these frequencies).

The audio frequencies supported in either microcontroller mode or static mode are given in Table 3.

	Table 3	Output frequencies
				OUTPUT FREQUENCY
	BASIC AUDIO
				MICRO-
	FREQUENCY
			CONTROLLER		STATIC MODE
				MODE
	32 kHz		256 × 16 kHz
			384	× 16 kHz
			256	× 32 kHz	256 × 32 kHz
			384	× 32 kHz
			256	× 64 kHz
			384	× 64 kHz
	44.1 kHz		256 × 22.05 kHz
			384	× 22.05 kHz
			256	× 44.1 kHz	256 × 44.1 kHz
			384	× 44.1 kHz
			256	× 88.2 kHz
			384	× 88.2 kHz
	48 kHz		256 × 24 kHz
			384	× 24 kHz
			256	× 48 kHz	256 × 48 kHz
			384	× 48 kHz
			256	× 96 kHz
			384	× 96 kHz

Remarks:

∙If an application mode is selected which does not need a crystal oscillator, the crystal oscillator cannot be omitted. The reason is that the interpolator switches to the crystal clock when an SPDIF input signal is removed. This switch prevents the noise shaper noise from moving inside the audio band as the PLL gradually decreases in frequency.

∙If no accurate output frequency is needed, the crystal can be replaced with a resonator.

∙Instead of the crystal, a 12.288 MHz system clock can be applied to pin XTALIN.

The block diagram of the crystal oscillator and the PLL circuit is given in Fig.3.

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Philips Semiconductors	Preliminary specification
Stereo audio codec with SPDIF interface	UDA1355H

12.288 MHz

handbook, halfpage

13

XTALIN

CRYSTAL

PLL

14

OSCILLATOR

MODULE

XTALOUT

11

256fs or 384fs clock

CLK_OUT

PLL clock

L3-bus

or I2C-bus

UDA1355H

register setting

MGU830

Fig.3 Crystal oscillator clock system.

7.3.4CLOCK OUTPUT

The UDA1355H has a clock output pin (pin CLK_OUT), which can be used to drive other audio devices in the system. In microcontroller mode the output clock is

256fs or 384fs. In static mode the output clock is 256 times 32, 44.1 and 48 kHz.

The source of the output clock is either the crystal oscillator or the PLL, depending on the selected application and control mode.

7.4IEC 60958 decoder

The UDA1355H IEC 60958 decoder can select one of four SPDIF input channels. An on-chip amplifier with hysteresis amplifies the SPDIF input signal to CMOS level, making it possible to accept both analog and digital SPDIF signals (see Fig.5).

7.3.2PLL CLOCK SYSTEM

The PLL locks on the incoming digital data of the SPDIF or WS input signal. The PLL recovers the clock from the SPDIF or WSI signal and removes jitter to produce a stable system clock (see Fig.4).

	select SPDIF source		UDA1355H
SPDIF0	23
SPDIF1	24		IEC 60958
	25
SPDIF2			DECODER
SPDIF3	26
	SLICER			256fs
			PLL
	2			or
WSI				384fs
				MGU827
	Fig.4	PLL clock system.

7.3.3WORD SELECTION DETECTION CIRCUIT

This circuit is clocked by the 12.288 MHz crystal oscillator clock and generates a Word Selection (WS) detection signal. If the WS detector does not detect any WS edge, defined as 7 times LOW and 7 times HIGH, then the

WS detection signal is LOW. This information can be used to set the clock for the noise shaper in the interpolator. This will prevent noise shaper noise in the audio band.

handbook, halfpage
	10 nF	SPDIF0	23
		SPDIF1	24
		SPDIF2	25
75 Ω	180 pF	SPDIF3	26
			UDA1355H
			MGU829
	Fig.5	IEC 60958 input circuit.

7.4.1AUDIO DATA

From the incoming SPDIF bitstream 24 bits of data for the left and right channel are extracted.

There is a hard mute (not a cosine roll-off mute) if the IEC 60958 decoder is out of lock or detects bi-mark phase encoding violations. The lock indicator and the key channel status bits are accessible in L3-bus mode.

The UDA1355H supports the following sample frequencies and data rates, including half and double of these frequencies:

∙fs = 32 kHz; resulting in a data rate of 2.048 Mbit/s

∙fs = 44.1 kHz; resulting in a data rate of 2.8224 Mbit/s

∙fs = 48 kHz; resulting in a data rate of 3.072 Mbit/s.

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Philips Semiconductors	Preliminary specification
Stereo audio codec with SPDIF interface	UDA1355H

7.4.2CHANNEL STATUS AND USER BITS

As well as the data bits there are several IEC 60958 key channel status bits:

∙Pre-emphasis and audio sampling frequency bits

∙Two channel PCM indicator bits

∙Clock accuracy bits.

In total 40 status bits per channel are recovered from the incoming IEC 60958 bitstream. These are readable via the microcontroller interface.

User bits, which can contain a large variety of data, such as CD text, are output to pin SLICER_SEL0 (see Table 4). In microcontroller mode this signal contains the raw user bits extracted from the SPDIF bitstream. Signal U_RDY gives a pulse on pin MODE2 each time there is a new user bit available. Both signals can be used by an external microcontroller to grab and decode the user bits.

Table 4 Signal names in microcontroller mode

PIN NAME	SIGNAL NAME
SLICER_SEL0	USER
MODE2	U_RDY
SLICER_SEL1	AC3

7.4.3DIGITAL DATA

Audio and digital data can be transmitted in the SPDIF bitstream. The PCM channel status bit should be set to logic 1 if the SPDIF bitstream is carrying digital data instead of audio data, but in practice it proves that not all equipment handles these channel status bits properly.

In the UDA1355H, digital data is detected via bit PCM, or via the sync bytes as specified by IEC. These sync bytes are two sync words, F872H and 4E1FH (two subframes) preceded by four or more subframes filled with zeros.

Signal AC3 is kept HIGH for 4096 frames when the UDA1355H detects this burst preamble. Signal AC3 is present on pin SLICER_SEL1 in microcontroller mode (see Table 4).

7.5IEC 60958 encoder

When using the crystal oscillator clock, the IEC 60958 encoder output is a full-swing digital signal with level II timing.

When the recovered clock from the PLL is used the

IEC 60958 encoder will function correctly but will not meet level II timing requirements.

7.5.1STATIC MODE

All user and channel status bits are set to logic 0. This is default value specified by IEC.

In static mode 0 and 2, the selected SPDIF input channel can be looped through to pin SPDIFOUT (see Fig.6).

7.5.2MICROCONTROLLER MODE

Two times 40 channel status bits can be set. Default value for each status bit is logic 0. When setting the channel status bits, it is possible to set only the left channel status bits and have the bits copied to the right channel.

The procedure of writing the channel status bits is as follows:

1.Set bit SPDO_VALID = 0 to prevent immediately sending the status bits during writing.

2.Set bit l_r_copy = 1 if the right channel needs the same status bits as the left channel or set

bit l_r_copy = 0 if the right channel needs different status bits to the left channel.

3.Write the left and right channel status bits.

4.Set bit SPDO_VALID = 1 after writing all channel status bits to the register. Starting from the next SPDIF block the IEC 60958 encoder will use the new status bits.

In microcontroller modes 2 and 13, the selected SPDIF input channel can be looped through to pin SPDIFOUT (see Fig.6).

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SPDOUT_SEL1

SPDOUT_SEL0

UDA1355H

SPDOUT_SEL2

23

MODE[3:0]

IEC 60958

SPDIF0

DECODER

24

SPDIF1

25

SPDIF2

5

26

SLICER

SPDIF OUT

SPDIF3

select

SPDIF source

SPDIF

IEC 60958

ENCODER

21, 22

source

17 to 19

20

SLICER_SEL[1:0]

MODE[2:0] SEL_STATIC

MGU833

Fig.6 Selection options for SPDIF output.

7.6Analog input

7.6.1ADC

The analog input is equipped with a Programmable Gain Amplifier (PGA) which can be controlled via the microcontroller interface. The control range is from

0 to 24 dB gain in 3 dB steps independent for the left and right channels.

In applications in with a 2 V (RMS) input signal, a 12 kΩ resistor must be used in series with the input of the ADC. The 12 kΩ resistor forms a voltage divider together with the internal ADC resistor and ensures that the voltage, applied to the input of the IC, never exceeds 1 V (RMS). In the application for a 2 V (RMS) input signal, the PGA must be set to 0 dB. When a 1 V (RMS) input signal is applied to the ADC in the same application, the PGA gain must be set to 6 dB.

An overview of the maximum input voltages allowed with and without an external resistor and the PGA gain setting is given in Table 5.

Table 5 Maximum input voltage; VDD = 3 V

	EXTERNAL	PGA GAIN	MAXIMUM
	RESISTOR		INPUT
		SETTING
	(12 kΩ)		VOLTAGE
	Present	0 dB	2 V (RMS)
		6 dB	1 V (RMS)
	Absent	0 dB	1 V (RMS)
		6 dB	0.5 V (RMS)

7.6.2DECIMATION

The decimation from 64fs is performed in two stages: comb filter and decimation filter. The first stage realizes a

sin x

fourth-order ----------- characteristic with a decimation factor x

of eight. The second stage consists of three half-band filters each decimating by a factor of two. Table 6 shows the characteristics.

Table 6 Decimation filter characteristics

ITEM	CONDITIONS	VALUE (dB)
Pass-band ripple	0 to 0.45fs	±0.02
Stop band	>0.55fs	−60
Dynamic range	0 to 0.45fs	140
Overall gain from ADC	DC; VI = 0 dB;	−1.16
input to digital output	note 1

Note

1.The output is not 0 dB when VI(rms) = 1 V at VDD = 3 V. This is because the analog components can spread

over the process. When there is no external resistor, the −1.16 dB scaling prevents clipping caused by process mismatch.

In the ADC path there are left and right independent digital volume controls with a range from +24 to −63.5 dB

and −∞ dB. This volume control is also used as a digital linear mute that can be used to prevent plops when powering-up or powering down the ADC front path.

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7.6.3DC FILTERING

In the decimator there are two digital DC blocking circuits.

The first blocking circuit is in front of the volume control to remove DC bias from the ADC output. The DC bias is added in the ADC to prevent audio band Idle tones occurring in the noise shaper. With the DC components removed, a signal gain of 24 dB can be achieved.

The second blocking circuit removes the DC components introduced by the decimator stage.

7.6.4OVERLOAD DETECTION

Bit OVERFLOW = 1 when the output data in the left or right channel is larger than −1.16 dB of the maximum possible digital swing. This condition is set for at least 512fs cycles (that is 11.6 ms at fs = 44.1 kHz). This time-out is reset for each infringement.

7.7Analog output

7.7.1AUDIO FEATURE PROCESSOR

∙Support for 1fs and 2fs input data rate and 192 kHz audio via I2S-bus.

The stereo interpolator has the following sound features:

∙Linear volume control using 14-bit coefficients with 0.25 dB steps: range 0 to −78 dB and −∞ dB; hold for master volume and mixing volume control

∙A cosine roll-off soft mute with 32 coefficients; each coefficient is used for four samples, in total 128 samples are needed to fully mute or de-mute (approximately

3 ms at fs = 44.1 kHz)

∙Independent selectable de-emphasis for 32, 44.1, 48 and 96 kHz for both channels

∙Treble is the selectable positive gain for high frequencies. The edge frequency of the treble is fixed and depends on the sampling frequency. Treble can be set independently for left and right channel with two settings:

– fc = 1.5 kHz; fs = 44.1 kHz; 0 to 6 dB gain range with 2 dB steps

The audio feature processor provides automatic de-emphasis for the IEC 60958 bitstream.

In microcontroller mode all features are available and there is a default mute on start up.

7.7.2INTERPOLATING FILTER

The digital filter interpolates from 1fs to 64fs, or from

1fs to 128fs, by cascading a half-band filter and a FIR filter.

The stereo interpolator has the following basic features:

∙24-bit data path

∙Mixing of two channels:

–To prevent clipping inside the core, there is an automatic signal level correction of −6 dB scaling before mixing and +6 dB gain after digital volume control

–Position of mixing can be set before or after bass boost and treble

–Master volume control and mute with independent left and right channel settings for balance control

–Independently left and right channel de-emphasis, volume control and mute (no left or right)

–Output of the mixer is to the I2S-bus or IEC 60958 decoder.

∙Full FIR filter implementation for all the upsampling filters

∙Integrated digital silence detection for left and right channels with selectable silence detection time

–fc = 3 kHz; fs = 44.1 kHz; 0 to 6 dB gain range with 2 dB steps.

∙Normal bass boost is the selectable positive gain for low frequencies. The edge frequency of the bass boost is fixed and depends on the sampling frequency. Normal bass boost can be set independently for the left and right channel with two sets:

–fc = 250 Hz; fs = 44.1 kHz; 0 to 18 dB gain range with 2 dB steps

–fc = 300 Hz; fs = 44.1 kHz; 0 to 24 dB gain range with 2 dB steps.

∙Resonant bass boost optional function is selected if bit BASS_SEL = 1. When selected, the characteristics

are determined by six 14-bit coefficients. Resonant bass boost controls the left and right channel with the same characteristics. When resonant bass boost is selected, the treble control also changes to a single control for both channels following the gain setting of the left channel.

A software program is available for users to generate the required six 14-bit coefficients by entering the desired

centre frequency (fc), positive or negative peak gain, sampling frequency (fs) and shape factor (see

Figs 7 and 8).

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Stereo audio codec with SPDIF interface	UDA1355H

Table 7 Interpolation filter characteristics

ITEM	CONDITIONS	VALUE (dB)
Pass-band ripple	0 to 0.45fs	±0.035
Stop band	>0.55fs	−60
Dynamic range	0 to 0.4535fs	140

7.7.3DIGITAL MIXER

The UDA1355H has a digital mixer inside the interpolator. The digital mixer can be used as a cross over or a selector. A functional block diagram of the mixer mode is shown in Fig.9. This mixer can be used in microcontroller mode only.

The UDA1355H can be set to the mixer mode by setting bit MIX = 1. In the mixer mode, there are three volume and

mute controls available: for source 1, for source 2 and for the master (sum) signal. All three volume ranges can be controlled in 0.25 dB steps.

To prevent clipping inside the mixer, the signals are scaled with −6 dB before mixing, therefore the sum of the two signals is always equal to or lower than 0 dB. After the mixing there is a 6 dB gain in the master volume control. This means that at the analog output the signal can clip, but the clipping can be undone by decreasing the master volume control.

The output of the mixer is available via the I2S-bus output or via the SPDIF output. The output signal of the mixer is scaled to a maximum of 0 dB, so the digital output can never clip.

	10			MGU832			10			MGU831
handbook, halfpage						handbook, halfpage
gain	8					gain	8
(dB)						(dB)
	6						6
	4						4
	2						2
	0						0
	−2						−2
	−4						−4
	−6						−6
	−8						−8
−10			102		103	−10			102		103
	1	10		f (Hz))			1	10		f (Hz))

fc = 70 Hz	Peak gain = 10 dB	fc = 70 Hz	Peak gain = 10 dB
fs = 44.1 kHz	Shape factor = 1.4142	fs = 44.1 kHz	Shape factor = 1.4142
Fig.7 Resonant bass boost example 1.		Fig.8 Resonant bass boost example 2.

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		mixing before	mixing after
channel 2		sound features	sound features
	VOLUME		1fs		UDA1355H
DE-EMPHASIS	AND
	MUTE
			L3/I2C bit
	VOLUME	BASS-BOOST			2fs	MASTER	to
DE-EMPHASIS	AND		AND
				INT.		VOLUME	interpolation
	MUTE		TREBLE	FILTER		AND	filter and
channel 1						MUTE	DAC output
			output of mixer
							MGU834

Fig.9 Digital mixer (DAC) inside the interpolator DSP.

7.7.4DIGITAL SILENCE DETECTOR

The UDA1355H is equipped with a digital silence detector. This detects whether a certain amount of consecutive samples are 0. The number of samples can be set with bits SD_VALUE[1:0] to 3200, 4800, 9600 or 19600 samples.

The digital silence detection status can be read via the microcontroller interface.

7.7.5NOISE SHAPER (DAC)

The noise shaper shifts in-band quantization noise to frequencies above the audio band. The noise shaper output is converted into an analog signal using a Filter Stream Digital-to-Analog Converter (FSDAC). This noise shaping technique enables high signal-to-noise ratios to be achieved.

The UDA1355H is equipped with two noise shapers:

∙A third-order noise shaper operating at 128fs. Which is used at low sampling frequencies (8 to 16 kHz) to prevent noise shaper noise shifting into the audio band for the fifth-order noise shaper

∙A fifth-order noise shaper operating at 64fs. Which is used at high sampling frequencies (from 32 kHz upwards).

When the noise shaper changes, the clock to the FSDAC changes and the filter characteristic of the FSDAC also changes. The effect on the roll of is compensated by selecting the filter matching speed and order of the noise shaper.

7.7.6FILTER STREAM DAC

The FSDAC is a semi digital reconstruction filter that converts the 1-bit data bitstream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the operational amplifier output. In this way, very high signal-to-noise performance and low clock jitter sensitivity are achieved. A post filter is not needed due to the inherent filter function of the FSDAC. On-chip amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC scales proportionally with the supply voltage.

7.7.7DAC MUTE

The DAC and interpolator can be muted by setting

pin MUTE to a HIGH level. The output signal is muted to zero via a cosine roll-off curve and the DAC is powered down. When pin MUTE is at LOW level the signal rise follows the same cosine curve.

To prevent plops in case of changing inputs, clock to the DAC or application modes, a special mute circuit for the DAC is implemented (see Table 8).

In all application modes in which the DAC is active the DAC can be muted by pin MUTE. The microcontroller mute bits and pin MUTE act as an OR function.

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	Philips Semiconductors				Preliminary specification
	Stereo audio codec with SPDIF interface				UDA1355H
	Table 8 Muting to prevent plopping
	OCCASION		BIT		DE-MUTE CONDITION
		MT1	MT2	MTM
	Input selection
	Select channel 1 source	x	−	−	no mute after selection
	Select channel 2 source	−	x	−	no mute after selection
	Select chip mode
	PLL is source for the DAC	−	−	x	wait until PLL is locked again
	Crystal is source for the DAC	−	−	x	no mute after selection
	Select between microcontroller mode and static mode
	PLL is source for the DAC	−	−	x	wait until PLL is locked again
	Crystal is source for the DAC	−	−	x	no mute after selection
	Audio features
	Select noise shaper order	−	−	x	no mute after selection
	Select FSDAC output polarity	−	−	x	no mute after selection
	Select SPDIF input	−	−	x	PLL is locked again
	Select mixer	−	−	−	no mute needed
	Select mixer position	−	−	−	no mute needed
	Select crystal clock source	−	−	x	no mute after selection

7.8Digital audio input and output

The selection of the digital audio input and output formats and master or slave modes differ for static and microcontroller mode.

In master mode, when 256fs output clock is selected and the digital interface is master, the BCK output clock will be 64fs. In case 384fs output clock is selected, the BCK output clock will be 48fs.

In the static mode the digital audio input formats are:

∙I2S-bus

∙LSB-justified; 16 bits

∙LSB-justified; 24 bits

∙MSB-justified.

The digital audio output formats are:

∙I2S-bus

∙MSB-justified.

In the microcontroller mode, the following formats are independently selectable:

∙I2S-bus

∙LSB-justified; 16 bits

∙LSB-justified; 18 bits

∙LSB-justified; 20 bits

∙LSB-justified; 24 bits

∙MSB-justified.

7.9Power-on reset

The UDA1355H has a dedicated reset pin with an internal pull-down resistor. In this way a Power-on reset circuit can be made with a capacitor and a resistor at pin RESET. The external resistor is needed since the pad is 5 V tolerant.

This means that there is a transmission gate in series with the input and the resistor inside the pad cannot be seen from the outside world (see Fig.10).

The reset timing is determined by the external pull-down resistor and the external capacitor which is connected to pin RESET. At Power-on reset, all the digital sound processing features and the system controlling features are set to the default setting of the microcontroller mode. Since the bit controlling the clock of the synchronous registers is set to enable, the synchronous registers are also reset.

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Stereo audio codec with SPDIF interface	UDA1355H

	Transmission gate
	for 5V tolerance
RESET	16
	UDA1355H	VSS
		MGU835

Fig.10 5 V tolerant pull-down input pad.

The clock should be running during the reset time. When no clock can be guaranteed in microcontroller mode, a soft reset should be given when the system is running by writing to register 7FH.

Table 9 Static mode pin assignment

8 APPLICATION MODES

In this chapter the application modes for static mode and microcontroller mode are described.

The UDA1355H can be controlled by static pins, the L3-bus or I2C-bus interface. Due to the limitations imposed by the pin count, only basic functions are available in static mode. For optimum use of the UDA1355H features, the microcontroller mode is strongly recommended.

There are 11 application modes available in the static mode and 14 application modes in microcontroller mode. The application modes are explained in the two sections: Section 8.2 explains the application modes 0 to 10. Section 8.4 explains the more advanced features of modes 0 to 10 and modes 12 to 14 available in the microcontroller mode.

8.1Static mode pin assignment

The default values for all non-pin controlled settings are identical to the start-up defaults from the microcontroller mode. Whether BCK and WS are master or slave depends on the selected application mode.

Table 9 defines the pin functions in static mode.

	PIN	STATIC MODE	LEVEL	DESCRIPTION
		SYMBOL
	4	LOCK	LOW	IEC 60958 decoder out of lock (when SPDIF input) or clock
				regeneration out of lock (I2S-bus input)
			HIGH	IEC 60958 decoder in lock (when SPDIF input) or clock
				regeneration in lock (I2S-bus input)
	16	RESET	LOW	normal operation
			HIGH	reset
	17, 18,	MODE0, MODE1,	−	select application mode; see Table 10
	19	MODE2
	20	SEL_STATIC	HIGH	static pin control
			LOW	microcontroller mode
	22, 21	SLICER_SEL1,	LOW, LOW	IEC 60958 input from pin SPDIF0
		SLICER_SEL0
			LOW, HIGH	IEC 60958 input from pin SPDIF1
			HIGH, LOW	IEC 60958 input from pin SPDIF2
			HIGH, HIGH	IEC 60958 input from pin SPDIF3
	29	FREQ_SEL	LOW	select 44.1 kHz sampling frequency for the crystal oscillator,
				note 1
			MID	select 32 kHz sampling frequency for the crystal oscillator, note 1
			HIGH	select 48 kHz sampling frequency for the crystal oscillator, note 1

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Stereo audio codec with SPDIF interface				UDA1355H
PIN	STATIC MODE	LEVEL		DESCRIPTION
	SYMBOL
30, 31	SFOR1, SFOR0	LOW, LOW	set I2S-bus format for digital data input and output interface
		LOW, HIGH	set LSB-justified 16 bits format for digital data input interface and
			MSB-justified format for digital data output interface
		HIGH, LOW	set LSB-justified 24 bits format for digital data input interface and
			MSB-justified format for digital data output interface
		HIGH, HIGH	set MSB-justified format for digital data input and output interface
44	MUTE	LOW	normal operation
		HIGH	mute active

Note

1. FPLL 256fs is output from pin CLKOUT in PLL locked static mode.

8.2Static mode basic applications

The static application modes are selected with the pins MODE2, MODE1 and MODE0, with pin MODE0 being a 3-level pin. In Table 10, the encoding of the pins MODE[2:0] is given.

Table 10 Static mode basic applications

	MODE SELECTION PINS(1)					CLOCK(2)					PLL
MODE				SPDIF	SPDIF				I2S-BUS	I2S-BUS	LOCKS
	MODE2	MODE1	MODE0			ADC	DAC		INPUT	OUTPUT	ON
				INPUT	OUTPUT
											INPUT
									SLAVE	MASTER
0	L	L	L	PLL	PLL	−	PLL		−	PLL	SPDIF
1	L	L	M	−	PLL	−	PLL		PLL	−	I2S-bus
2	L	L	H	PLL	PLL	−	PLL		PLL	PLL	SPDIF
3	L	H	L	−	xtal	xtal	−		−	xtal	−
4	L	H	M	−	xtal	xtal	xtal		xtal	xtal	−
5	L	H	H	−	xtal	xtal	xtal		xtal	xtal	−
6	H	L	L	−	PLL	xtal	PLL		PLL	xtal	I2S-bus
7	H	L	M	PLL	xtal	xtal	PLL		−	xtal	SPDIF
8	H	L	H	−	xtal	xtal	PLL		PLL	xtal	I2S-bus
9	H	H	L	PLL	xtal	−	xtal		xtal	PLL	SPDIF
10	H	H	M	PLL	xtal	−	PLL		xtal	PLL	SPDIF
11	H	H	H				not used

Notes

1.In column mode selection pins means:

L: pin at 0 V; M: pin at half VDDD; H: pin at VDDD.

2.In column clock means:

xtal: the clock is based on the crystal oscillator; PLL: the clock is based on the PLL.

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The first 11 application modes are given in this section. Schematic diagrams of these application modes are given in Table 11. In this table the basic features are mentioned and also the extra features in case of microcontroller mode are given. It should be noted that the blocks running at the crystal clock (XTAL) are marked unshaded while the blocks running at the PLL clock are shaded.

Table 11 Overview of static mode basic applications

MODE

FEATURES

SCHEMATIC

0Data path:

∙Input SPDIF to outputs DAC, I2S or SPDIFOUT via loop through.

	Features:			PLL	SPDIF LOCK
	∙	System locks onto the SPDIF input					MUTE
		signal				DAC
	∙	BCK and WS are master					SPDIFOUT
	∙
		Microcontroller mode:		SPDIF IN
		– DAC sound features can be used			I2S OUTPUT		I2S master
		– SPDIF input channel status bits				MGU836
		(two times 40 bits) can be read.
1	Data path:
	∙	Input I2S to outputs DAC or SPDIF
		(level II not guaranteed: depends on				I2S LOCK
		I2S-bus clock).			PLL
	Features:						MUTE
	∙	System locks onto the WSI signal				DAC
	∙	BCKI and WSI are slave
	∙	Microcontroller mode:				SPDIF OUT
		– DAC sound features can be used	I2S slave	I2S INPUT

– SPDIF output channel status bits	MGU837
(two times 40 bits) setting.

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Stereo audio codec with SPDIF interface		UDA1355H
MODE	FEATURES	SCHEMATIC

2Data path:

∙Input SPDIF to outputs I2S or SPDIFOUT via loop through

	∙	Input I2S to output DAC.	PLL	SPDIF LOCK
				MUTE
	Features:			DAC
	∙	Possibility to process input SPDIF via
				SPDIFOUT
		I2S-bus using an external DSP and
			SPDIF IN
		then to output DAC

∙	System locks onto the SPDIF input
					I2S INPUT			I2S OUTPUT
	signal
∙	2					I2S slave			I2S master
	I S input and output with BCK and WS
	are master					EXTERNAL DSP
∙	Microcontroller mode: see Section 8.4.				(e.g. equalizing, spatializing)
							(SAA7715)
								MGU838

3	Data path:
	∙	Input ADC to outputs I2S or SPDIF.
	Features:
	∙	Crystal oscillator generates the clocks	XTAL
	∙	Microcontroller mode:	ADC
		– PGA gain setting
		– Volume control in decimator setting		SPDIF OUT
		– SPDIF output channel status bits		I2S OUTPUT	I2S master
		(two times 40 bits) setting.
				MGU839
4	Data path:
	∙	Input ADC to output I2S
	∙	Input I2S to outputs DAC or SPDIF.	XTAL
	Features:		ADC		MUTE
	∙	Possibility to process input ADC via		DAC
		I2S-bus using a external DSP and then
		to outputs DAC or SPDIF		SPDIF OUT
	∙	Crystal oscillator generates the clocks	I2S INPUT	I2S OUTPUT
	∙
		I2S input and output with BCK and WS
		are master	I2S slave	I2S master

∙ Microcontroller mode: see Section 8.4.	EXTERNAL DSP
	(e.g. equalizing, spatializing)
	(SAA7715)

MGU840

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Stereo audio codec with SPDIF interface		UDA1355H
MODE	FEATURES	SCHEMATIC

5Data path:

∙ Input ADC to outputs I2S or SPDIF

	∙	Input I2S to output DAC.	XTAL
	Features:			MUTE
	∙	Possibility to process input ADC via	ADC	DAC
		I2S-bus using an external DSP and
		then to output DAC		SPDIF OUT
	∙	Crystal oscillator generates the clocks	I2S INPUT	I2S OUTPUT
	∙	I2S input and output with BCK and WS
		are master	I2S slave	I2S master
	∙	Microcontroller mode: see Section 8.4.	EXTERNAL DSP
			(e.g. equalizing, spatializing)
			(SAA7715)
				MGU841

6Data path:

∙Input ADC to output I2S

∙Input I2S to outputs DAC or SPDIF

	(level II not guaranteed: depends on	XTAL	PLL	I2S LOCK
				MUTE
	I2S-bus clock).
Features:		ADC		DAC
∙	Possibility to process input ADC via
	I2S-bus using an external DSP and			SPDIF OUT
	then to outputs DAC or SPDIF

∙	Crystal oscillator generates the clocks		I2S INPUT			I2S OUTPUT
	for input ADC and output I2S
				I2S slave			I2S master
∙	WSI is slave				EXTERNAL DSP
∙	WSO is master
					(SAA7715)
∙
	Microcontroller mode: see Section 8.4.					MGU842

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