Philips UDA1334ATS Technical data

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UDA1334ATS

Low power audio DAC with PLL

Product speciﬁcation Supersedes data of 2000 Feb 09 File under Integrated Circuits, IC01

2000 Jul 31

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

CONTENTS

1 FEATURES

1.1 General

1.2 Multiple format data interface

1.3 DAC digital features

1.4 Advanced audio configuration

1.5 PLL system clock generation 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 QUICK REFERENCE DATA 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION

8.1 System clock

8.1.1 Audio mode

8.1.2 Video mode

8.2 Interpolation filter

8.3 Noise shaper

8.4 Filter stream DAC

8.5 Power-on reset

8.6 Feature settings

8.6.1 Digital interface format select

8.6.2 De-emphasis control

8.6.3 Mute control

9 LIMITING VALUES 10 HANDLING 11 THERMAL CHARACTERISTICS 12 QUALITY SPECIFICATION 13 DC CHARACTERISTICS 14 AC CHARACTERISTICS

14.1 Analog

14.2 Timing 15 APPLICATION INFORMATION 16 PACKAGE OUTLINE 17 SOLDERING

17.1 Introduction to soldering surface mount packages

17.2 Reflow soldering

17.3 Wave soldering

17.4 Manual soldering

17.5 Suitability of surface mount IC packages for wave and reflow soldering methods

18 DATA SHEET STATUS 19 DEFINITIONS 20 DISCLAIMERS

2000 Jul 31 2

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

1 FEATURES

1.1 General

• 2.4 to 3.6 V power supply voltage

• On-board PLL to generate the internal system clock:

– OperatesasanasynchronousDAC,regeneratingthe

internal clock from the WS signal (called audio mode)

– Generatesaudio related system clock (output)based

on32, 48 or 96 kHzsamplingfrequency(calledvideo mode).

• Integrated digital filter plus DAC

• Supports sample frequencies from 16 to 100 kHz in

asynchronous DAC mode

• No analog post filtering required for DAC

• Easy application

• SSOP16 package.

1.2 Multiple format data interface

• I2S-bus and LSB-justified format compatible

• 1fs input data rate.

1.3 DAC digital features

• Digital de-emphasis for 44.1 kHz sampling frequency

• Mute function.

2 APPLICATIONS

This audio DAC is excellently suitable for digital audio portable application, specially in applications in which an audio related system clock is not present.

3 GENERAL DESCRIPTION

The UDA1334ATS is a single chip 2 channel digital-to-analog converter employing bitstream conversion techniques, including an on-board PLL. The extremely low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates a playback function.

The UDA1334ATS supports the I2S-bus data format with word lengths of up to 24 bits and the LSB-justified serial data format with word lengths of 16, 20 and 24 bits.

1.4 Advanced audio conﬁguration

• High linearity, wide dynamic range and low distortion.

1.5 PLL system clock generation

• Integrated low jitter PLL for use in applications in which there is digital audio data present but the system cannot provide an audio related system clock. This mode is called audio mode.

• The PLL can generate 256 × 48 kHz and 384 × 48 kHz from a 27 MHz input clock. This mode is called video mode.

4 ORDERING INFORMATION

TYPE

NUMBER

UDA1334ATS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

NAME DESCRIPTION VERSION

The UDA1334ATS has basic features such as de-emphasis (44.1 kHz sampling frequency, only supported in audio mode) and mute.

PACKAGE

2000 Jul 31 3

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

5 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

DDA

DDD

DDA

DDD

amb

Digital-to-analog converter (V

o(rms)

(THD+N)/S total harmonic distortion-plus-noise to

S/N signal-to-noise ratio f

Power dissipation (at fs= 44.1 kHz)

DAC analog supply voltage 2.4 3.0 3.6 V digital supply voltage 2.4 3.0 3.6 V DAC analog supply current audio mode − 3.5 − mA

video mode − 3.5 − mA

digital supply current audio mode − 2.5 − mA

video mode − 4.5 − mA

ambient temperature −40 − +85 °C

DDA=VDDD

output voltage (RMS value) at 0 dB (FS) digital input;

= 3.0 V)

− 900 − mV

note 1 f

= 44.1 kHz; at 0 dB −−90 − dB

signal ratio

= 44.1 kHz; at −60 dB;

−−40 − dB

A-weighted f

= 96 kHz; at 0 dB −−85 − dB

= 96 kHz; at −60 dB;

−−38 − dB

A-weighted

= 44.1 kHz; code = 0;

− 100 − dB

A-weighted f

= 96 kHz; code = 0;

− 98 − dB

A-weighted

channel separation − 100 − dB

P power dissipation audio mode − 18 − mW

video mode − 24 − mW

Note

1. The output voltage of the DAC scales proportionally to the power supply voltage.

2000 Jul 31 4

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

6 BLOCK DIAGRAM

handbook, full pagewidth

SYSCLK/PLL1

DEEM/CLKOUT

BCK

DATAI

MUTE

VOUTL

1 2 3

UDA1334ATS

6 8 9

DDA

DDD

DIGITAL INTERFACE PLL

DE-EMPHASIS

INTERPOLATION FILTER

NOISE SHAPER

DAC

13 12

SSA

DAC

SSD

PLL0

ref(DAC)

Fig.1 Block diagram.

SFOR1

SFOR0

VOUTR

MGL973

2000 Jul 31 5

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

7 PINNING

SYMBOL PIN PAD TYPE DESCRIPTION

BCK 1 5 V tolerant digital input pad bit clock input WS 2 5 V tolerant digital input pad word select input DATAI 3 5 V tolerant digital input pad serial data input V

DDD

SSD

SYSCLK/PLL1 6 5 V tolerant digital input pad system clock input in video mode/PLL

SFOR1 7 5 V tolerant digital input pad serial format select 1 input MUTE 8 5 V tolerant digital input pad mute control input DEEM/CLKOUT 9 5 V tolerant digital input/output pad de-emphasis control input in audio

PLL0 10 3-level input pad; note 1 PLL mode control 0 input SFOR0 11 digital input pad; note 1 serial format select 0 input V

ref(DAC)

DDA

VOUTL 14 analog output pad DAC output left V

SSA

VOUTR 16 analog output pad DAC output right

4 digital supply pad digital supply voltage 5 digital ground pad digital ground

mode control 1 input in audio mode

mode/clock output in video mode

12 analog pad DAC reference voltage 13 analog supply pad DAC analog supply voltage

15 analog ground pad DAC analog ground

Note

1. Because of test issues these pads are not 5 V tolerant and both pads should be at power supply voltage level or at

a maximum of 0.5 V above that level.

handbook, halfpage

BCK

DATAI

DDD

SSD

1 2 3 4

UDA1334ATS

5 6 7 8

MGL972

16 15 14 13 12 11 10

VOUTR V

SSA

VOUTL V

DDA

ref(DAC)

SFOR0SYSCLK/PLL1 PLL0SFOR1 DEEM/CLKOUTMUTE

Fig.2 Pin configuration.

2000 Jul 31 6

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

8 FUNCTIONAL DESCRIPTION

8.1 System clock

The UDA1334ATS incorporates a PLL capable of generating the system clock. The UDA1334ATS can operate in 2 modes:

• It operates as an asynchronous DAC, which means the device regenerates the internal clocks using a PLL from the incoming WS signal. This mode is called audio mode.

• It generates the internal clocks from a 27 MHz clock input, based on 32, 48 and 96 kHz sampling frequencies. This mode is called video mode.

In video mode, the digital audio input is slave, which means that the system must generate the BCK and WS signalsfromthe output clock available at pin CLKOUT of the UDA1334ATS. The digital audio signals should be frequency locked to the CLKOUT signal.

Remarks:

1. The WS edge MUST fall on the negative edge of the

BCK at all times for proper operation of the digital I/O data interface

2. For LSB-justified formats it is important to have a WS

signal with a duty factor of 50%.

8.1.1 AUDIO MODE

Audio mode is enabled by setting pin PLL0 to LOW. De-emphasis can be activated via pin DEEM/CLKOUT according to Table 5.

In audio mode, pin SYSCLK/PLL1 is used to set the sampling frequency range as given in Table 1.

Table 2 Clock output selection in video mode

PLL0 SELECTION

MID 12.228 MHz clock; note 1

HIGH 18.432 MHz clock; note 2

LOW audio mode

Notes

1. The supported sampling frequencies are: 96, 48 and 24 kHz or 64, 32 and 16 kHz.

2. The supported sampling frequencies are: 96, 48 and 24 kHz; 72 and 36 kHz or 32 kHz.

8.2 Interpolation ﬁlter

The interpolation digital filter interpolates from 1f

to 64f

by cascading FIR filters (see Table 3).

Table 3 Interpolation ﬁlter characteristics

ITEM CONDITION VALUE (dB)

Pass-band ripple 0f

to 0.45f

Stop band >0.55f Dynamic range 0f

to 0.45f

±0.02

−50

>114

8.3 Noise shaper

The 5th-order noise shaper operates at 64f

. It shifts

in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream DAC (FSDAC).

Table 1 Sampling frequency range in audio mode

SYSCLK/PLL1 SELECTION

LOW f

HIGH f

=16to50kHz

= 50 to 100 kHz

8.1.2 VIDEO MODE Invideomode, the master clock is a 27 MHzexternalclock

(as is available invideo environment). A clock-out signal is generated at pin DEEM/CLKOUT. The output frequency can be selected using pin PLL0. The output frequency is either 12.228 MHz (256 × 48 kHz) with pin PLL0 being at MID level or 18.432 MHz (384 × 48 kHz) with pin PLL0 being HIGH, as given in Table 2.

2000 Jul 31 7

Philips Semiconductors Product speciﬁcation

Low power audio DAC with PLL UDA1334ATS

8.4 Filter stream DAC

The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. No post filter is needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output.

The output voltage of the FSDAC scales proportionally to the power supply voltage.

handbook, halfpage

3.0 V

ref(DAC)

C1 > 10 µF

DDA

50 kΩ

RESET

CIRCUIT

50 kΩ

UDA1334A TS

MGT015

8.5 Power-on reset

The UDA1334ATS has an internal Power-on reset circuit (see Fig.3) which resets the test control block.

The reset time (see Fig.4) is determined by an external capacitor which is connected between pin V

ref(DAC)

and ground. The reset time should be at least 1 µs for V

ref(DAC)

will be reset again for V

< 1.25 V. When V

ref(DAC)

is switched off, the device

DDA

< 0.75 V.

During the reset time the system clock should be running.

3.0

handbook, halfpage

DDD (V)

1.5

DDA (V)

ref(DAC)

(V)

1.25

0.75

3.0

1.5

3.0

1.5

>1 µs

MGL984

Fig.3 Power-on reset circuit.

2000 Jul 31 8

Fig.4 Power-on reset timing.

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