Datasheet UDA1334ATS Datasheet (Philips)

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UDA1334ATS

Low power audio DAC with PLL

Product specification
Supersedes data of 2000 Feb 09
File under Integrated Circuits, IC01

2000 Jul 31

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

CONTENTS

1 FEATURES

1.1 General

1.2 Multiple format data interface

1.3 DAC digital features

1.4 Advanced audio configuration

1.5 PLL system clock generation
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 ORDERING INFORMATION
5 QUICK REFERENCE DATA
6 BLOCK DIAGRAM
7 PINNING
8 FUNCTIONAL DESCRIPTION

8.1 System clock

8.1.1 Audio mode

8.1.2 Video mode

8.2 Interpolation filter

8.3 Noise shaper

8.4 Filter stream DAC

8.5 Power-on reset

8.6 Feature settings

8.6.1 Digital interface format select

8.6.2 De-emphasis control

8.6.3 Mute control

9 LIMITING VALUES
10 HANDLING
11 THERMAL CHARACTERISTICS
12 QUALITY SPECIFICATION
13 DC CHARACTERISTICS
14 AC CHARACTERISTICS

14.1 Analog

14.2 Timing
15 APPLICATION INFORMATION
16 PACKAGE OUTLINE
17 SOLDERING

17.1 Introduction to soldering surface mount
packages

17.2 Reflow soldering

17.3 Wave soldering

17.4 Manual soldering

17.5 Suitability of surface mount IC packages for
wave and reflow soldering methods

18 DATA SHEET STATUS
19 DEFINITIONS
20 DISCLAIMERS

2000 Jul 31 2

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

1 FEATURES

1.1 General

• 2.4 to 3.6 V power supply voltage

• On-board PLL to generate the internal system clock:

– OperatesasanasynchronousDAC,regeneratingthe

internal clock from the WS signal (called audio mode)

– Generatesaudio related system clock (output)based

on32, 48 or 96 kHzsamplingfrequency(calledvideo
mode).

• Integrated digital filter plus DAC

• Supports sample frequencies from 16 to 100 kHz in

asynchronous DAC mode

• No analog post filtering required for DAC

• Easy application

• SSOP16 package.

1.2 Multiple format data interface

• I2S-bus and LSB-justified format compatible

• 1fs input data rate.

1.3 DAC digital features

• Digital de-emphasis for 44.1 kHz sampling frequency

• Mute function.

2 APPLICATIONS

This audio DAC is excellently suitable for digital audio
portable application, specially in applications in which an
audio related system clock is not present.

3 GENERAL DESCRIPTION

The UDA1334ATS is a single chip 2 channel
digital-to-analog converter employing bitstream
conversion techniques, including an on-board PLL.
The extremely low power consumption and low voltage
requirements make the device eminently suitable for use
in low-voltage low-power portable digital audio equipment
which incorporates a playback function.

The UDA1334ATS supports the I2S-bus data format with
word lengths of up to 24 bits and the LSB-justified serial
data format with word lengths of 16, 20 and 24 bits.

1.4 Advanced audio configuration

• High linearity, wide dynamic range and low distortion.

1.5 PLL system clock generation

• Integrated low jitter PLL for use in applications in which
there is digital audio data present but the system cannot
provide an audio related system clock. This mode is
called audio mode.

• The PLL can generate 256 × 48 kHz and 384 × 48 kHz
from a 27 MHz input clock. This mode is called video
mode.

4 ORDERING INFORMATION

TYPE

NUMBER

UDA1334ATS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

NAME DESCRIPTION VERSION

The UDA1334ATS has basic features such as
de-emphasis (44.1 kHz sampling frequency, only
supported in audio mode) and mute.

PACKAGE

2000 Jul 31 3

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

5 QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DDA

V

DDD

I

DDA

I

DDD

T

amb

Digital-to-analog converter (V

V

o(rms)

(THD+N)/S total harmonic distortion-plus-noise to

S/N signal-to-noise ratio f

α

CS

Power dissipation (at fs= 44.1 kHz)

DAC analog supply voltage 2.4 3.0 3.6 V
digital supply voltage 2.4 3.0 3.6 V
DAC analog supply current audio mode − 3.5 − mA

video mode − 3.5 − mA

digital supply current audio mode − 2.5 − mA

video mode − 4.5 − mA

ambient temperature −40 − +85 °C

DDA=VDDD

output voltage (RMS value) at 0 dB (FS) digital input;

= 3.0 V)

− 900 − mV

note 1
f

= 44.1 kHz; at 0 dB −−90 − dB

s

signal ratio

= 44.1 kHz; at −60 dB;

f

s

−−40 − dB

A-weighted
f

= 96 kHz; at 0 dB −−85 − dB

s

f

= 96 kHz; at −60 dB;

s

−−38 − dB

A-weighted

= 44.1 kHz; code = 0;

s

− 100 − dB

A-weighted
f

= 96 kHz; code = 0;

s

− 98 − dB

A-weighted

channel separation − 100 − dB

P power dissipation audio mode − 18 − mW

video mode − 24 − mW

Note

1. The output voltage of the DAC scales proportionally to the power supply voltage.

2000 Jul 31 4

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

6 BLOCK DIAGRAM

handbook, full pagewidth

SYSCLK/PLL1

DEEM/CLKOUT

BCK

WS

DATAI

MUTE

VOUTL

1
2
3

UDA1334ATS

6
8
9

14

V

DDA

V

DDD

4

DIGITAL INTERFACE PLL

DE-EMPHASIS

INTERPOLATION FILTER

NOISE SHAPER

DAC

13 12

V

15

SSA

V

DAC

SSD

PLL0

5

10

V

ref(DAC)

Fig.1 Block diagram.

7

SFOR1

11

SFOR0

16

VOUTR

MGL973

2000 Jul 31 5

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

7 PINNING

SYMBOL PIN PAD TYPE DESCRIPTION

BCK 1 5 V tolerant digital input pad bit clock input
WS 2 5 V tolerant digital input pad word select input
DATAI 3 5 V tolerant digital input pad serial data input
V

DDD

V

SSD

SYSCLK/PLL1 6 5 V tolerant digital input pad system clock input in video mode/PLL

SFOR1 7 5 V tolerant digital input pad serial format select 1 input
MUTE 8 5 V tolerant digital input pad mute control input
DEEM/CLKOUT 9 5 V tolerant digital input/output pad de-emphasis control input in audio

PLL0 10 3-level input pad; note 1 PLL mode control 0 input
SFOR0 11 digital input pad; note 1 serial format select 0 input
V

ref(DAC)

V

DDA

VOUTL 14 analog output pad DAC output left
V

SSA

VOUTR 16 analog output pad DAC output right

4 digital supply pad digital supply voltage
5 digital ground pad digital ground

mode control 1 input in audio mode

mode/clock output in video mode

12 analog pad DAC reference voltage
13 analog supply pad DAC analog supply voltage

15 analog ground pad DAC analog ground

Note

1. Because of test issues these pads are not 5 V tolerant and both pads should be at power supply voltage level or at

a maximum of 0.5 V above that level.

handbook, halfpage

BCK

WS

DATAI

V

DDD

V

SSD

1
2
3
4

UDA1334ATS

5
6
7
8

MGL972

16
15
14
13
12
11
10

9

VOUTR
V

SSA

VOUTL
V

DDA

V

ref(DAC)

SFOR0SYSCLK/PLL1
PLL0SFOR1
DEEM/CLKOUTMUTE

Fig.2 Pin configuration.

2000 Jul 31 6

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

8 FUNCTIONAL DESCRIPTION

8.1 System clock

The UDA1334ATS incorporates a PLL capable of
generating the system clock. The UDA1334ATS can
operate in 2 modes:

• It operates as an asynchronous DAC, which means the
device regenerates the internal clocks using a PLL from
the incoming WS signal. This mode is called audio
mode.

• It generates the internal clocks from a 27 MHz clock
input, based on 32, 48 and 96 kHz sampling
frequencies. This mode is called video mode.

In video mode, the digital audio input is slave, which
means that the system must generate the BCK and
WS signalsfromthe output clock available at pin CLKOUT
of the UDA1334ATS. The digital audio signals should be
frequency locked to the CLKOUT signal.

Remarks:

1. The WS edge MUST fall on the negative edge of the

BCK at all times for proper operation of the digital I/O
data interface

2. For LSB-justified formats it is important to have a WS

signal with a duty factor of 50%.

8.1.1 AUDIO MODE

Audio mode is enabled by setting pin PLL0 to LOW.
De-emphasis can be activated via pin DEEM/CLKOUT
according to Table 5.

In audio mode, pin SYSCLK/PLL1 is used to set the
sampling frequency range as given in Table 1.

Table 2 Clock output selection in video mode

PLL0 SELECTION

MID 12.228 MHz clock; note 1

HIGH 18.432 MHz clock; note 2

LOW audio mode

Notes

1. The supported sampling frequencies are:
96, 48 and 24 kHz or 64, 32 and 16 kHz.

2. The supported sampling frequencies are:
96, 48 and 24 kHz; 72 and 36 kHz or 32 kHz.

8.2 Interpolation filter

The interpolation digital filter interpolates from 1f

to 64f

s

by cascading FIR filters (see Table 3).

Table 3 Interpolation filter characteristics

ITEM CONDITION VALUE (dB)

Pass-band ripple 0f

to 0.45f

s

Stop band >0.55f
Dynamic range 0f

to 0.45f

s

s

s

s

±0.02

−50

>114

8.3 Noise shaper

The 5th-order noise shaper operates at 64f

. It shifts

s

in-band quantization noise to frequencies well above the
audio band. This noise shaping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a
Filter Stream DAC (FSDAC).

s

Table 1 Sampling frequency range in audio mode

SYSCLK/PLL1 SELECTION

LOW f

HIGH f

=16to50kHz

s

= 50 to 100 kHz

s

8.1.2 VIDEO MODE
Invideomode, the master clock is a 27 MHzexternalclock

(as is available invideo environment). A clock-out signal is
generated at pin DEEM/CLKOUT. The output frequency
can be selected using pin PLL0. The output frequency is
either 12.228 MHz (256 × 48 kHz) with pin PLL0 being at
MID level or 18.432 MHz (384 × 48 kHz) with pin PLL0
being HIGH, as given in Table 2.

2000 Jul 31 7

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

8.4 Filter stream DAC

The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at
virtual ground of the output operational amplifier. In this
way very high signal-to-noise performance and low clock
jitter sensitivity is achieved. No post filter is needed due to
the inherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.

The output voltage of the FSDAC scales proportionally to
the power supply voltage.

handbook, halfpage

3.0 V

V

V

ref(DAC)

C1 >
10 µF

DDA

13

50 kΩ

RESET

12

CIRCUIT

50 kΩ

UDA1334A TS

MGT015

8.5 Power-on reset

The UDA1334ATS has an internal Power-on reset circuit
(see Fig.3) which resets the test control block.

The reset time (see Fig.4) is determined by an external
capacitor which is connected between pin V

ref(DAC)

and
ground. The reset time should be at least 1 µs for
V

ref(DAC)

will be reset again for V

< 1.25 V. When V

ref(DAC)

is switched off, the device

DDA

< 0.75 V.

During the reset time the system clock should be running.

3.0

handbook, halfpage

V

DDD
(V)

1.5

V

DDA
(V)

V

ref(DAC)

(V)

1.25

0.75

0

3.0

1.5

0

3.0

1.5

0

>1 µs

t

t

t

MGL984

Fig.3 Power-on reset circuit.

2000 Jul 31 8

Fig.4 Power-on reset timing.

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

8.6 Feature settings

8.6.1 DIGITAL INTERFACE FORMAT SELECT
The digital audio interface formats (see Fig.5) can be

selected via pins SFOR1 and SFOR0 as shown in
Table 4.

For the digital audio interface holds that the
BCK frequency can be maximum 64 times WS frequency.

The WS signal must change at the negative edge of the
BCK signal for all digital audio formats.

Table 4 Data format selection

SFOR1 SFOR0 INPUT FORMAT

LOW LOW I

LOW HIGH LSB-justified 16 bits input
HIGH LOW LSB-justified 20 bits input
HIGH HIGH LSB-justified 24 bits input

2

S-bus input

8.6.2 DE-EMPHASIS CONTROL
This function is only available in audio mode. In that case,

pin DEEM/CLKOUT can be used to activate the digital
de-emphasis for 44.1 kHz as given in Table 5.

Table 5 De-emphasis control (audio mode)

DEEM/CLKOUT FUNCTION

LOW de-emphasis off

HIGH de-emphasis on

8.6.3 MUTE CONTROL
The output signal can be soft muted by setting pin MUTE

to HIGH as given in Table 6.

Table 6 Mute control

MUTE FUNCTION

LOW mute off

HIGH mute on

2000 Jul 31 9

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

MGS752

B15 LSB

B19 LSB

B23 LSB

ndbook, full pagewidth

RIGHT

> = 8

3

21> = 812 3

RIGHT

1518 1720 19 2 1

16

MSB B2 B3 B4 B5 B6

LSB

B19

LSB-JUSTIFIED FORMAT 20 BITS

1518 1720 19 2 1

16

15 2 1

16

MSB B2

RIGHT

LSB

B15

LSB-JUSTIFIED FORMAT 16 BITS

15 2 1

B2

16

MSB

MSB MSBB2

RIGHT

1518 1720 1922 212324 21

16

1518 1720 1922 212324 2 1

16

B5 B6 B7 B8 B9 B10

B3 B4

B2

MSB

LSB

B23

LSB-JUSTIFIED FORMAT 24 BITS

Fig.5 Digital audio formats.

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2000 Jul 31 10

LEFT

WS

BCK

2

MSB B2

DATA

S-BUS FORMAT
I

LEFT

WS

BCK

DATA

LEFT

WS

BCK

MSB B2 B3 B4 B5 B6

DATA

LEFT

WS

BCK

B5 B6 B7 B8 B9 B10

B3 B4

B2

MSB

DATA

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

9 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

DD

T

xtal(max)

T

stg

T

amb

V

es

I

sc(DAC)

Notes

1. All supply connections must be made to the same power supply.

2. ESD behaviour is tested according to JEDEC II standard.

3. Short-circuit test at T

supply voltage note 1 − 4.0 V
maximum crystal

− 150 °C

temperature
storage temperature −65 +125 °C
ambient temperature −40 +85 °C
electrostatic handling voltage human body model; note 2 −2000 +2000 V

machine model; note 2 −250 +250 V

short-circuit current of DAC note 3

=0°C and V

amb

output short-circuited to V
output short-circuited to V

= 3 V. DAC operation after short-circuiting cannot be warranted.

DDA

SSA
DDA

− 450 mA

− 300 mA

10 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.

11 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R

th(j-a)

thermal resistance from junction to ambient in free air 145 K/W

12 QUALITY SPECIFICATION

In accordance with

“SNW-FQ-611-E”

.

13 DC CHARACTERISTICS

V

DDD=VDDA

= 3.0 V; T

=25°C; RL=5kΩ; all voltages with respect to ground (pins V

amb

SSA

and V

SSD

); unless

otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V
V
I

DDA

DDA
DDD

DAC analog supply voltage note 1 2.4 3.0 3.6 V
digital supply voltage note 1 2.4 3.0 3.6 V
DAC analog supply current audio mode − 3.5 − mA

video mode − 3.5 − mA

I

DDD

digital supply current audio mode − 2.5 − mA

video mode − 4.5 − mA

2000 Jul 31 11

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Digital input pins: TTL compatible

V

IH

V

IL

I

 input leakage current −−1 µA

LI

C

i

3-level input: pin PLL0

V

IH

V

IM

V

IL

Digital output pins

V

OH

V

OL

DAC

V

ref(DAC)

R

o(ref)

I

o(max)

R

L

C

L

Notes

1. All supply connections must be made to the same external power supply unit.

2. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent
oscillations in the output operational amplifier.

HIGH-level input voltage 2.0 − 5.0 V
LOW-level input voltage −0.5 − +0.8 V

input capacitance −−10 pF

HIGH-level input voltage 0.9V
MID-level input voltage 0.4V

DDD
DDD

− V

DDD

− 0.6V

+ 0.5 V

DDD

V

LOW-level input voltage −0.5 − +0.5 V

HIGH-level output voltage IOH= −2 mA 0.85V

−− V

DDD

LOW-level output voltage IOL=2mA −−0.4 V

reference voltage with respect to V

SSA

output resistance on
pin V

ref(DAC)

maximum output current (THD + N)/S < 0.1%;

0.45V

0.5VDD0.55V

DD

DD

V

− 25 − kΩ

− 1.6 − mA

RL=5kΩ
load resistance 3 −− kΩ
load capacitance note 2 −−50 pF

14 AC CHARACTERISTICS

14.1 Analog

V

DDD=VDDA

= 3.0 V; fi= 1 kHz; T

=25°C; RL=5kΩ; all voltages with respect to ground (pins V

amb

SSA

and V

unless otherwise specified.

SYMBOL PARAMETER CONDITIONS TYP. UNIT

DAC

V

o(rms)

∆V

o

(THD + N)/S total harmonic

output voltage (RMS value) at 0 dB (FS) digital input; note 1 900 mV
unbalance between channels 0.1 dB

f

= 44.1 kHz; at 0 dB −90 dB

s

distortion-plus-noise to signal
ratio

f

= 44.1 kHz; at −60 dB; A-weighted −40 dB

s

= 96 kHz; at 0 dB −85 dB

f

s

f

= 96 kHz; at −60 dB; A-weighted −38 dB

s

2000 Jul 31 12

SSD

);

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

SYMBOL PARAMETER CONDITIONS TYP. UNIT

S/N signal-to-noise ratio f

α

CS

channel separation 100 dB

PSRR power supply rejection ratio f

Note

1. The output voltage of the DAC scales proportionally to the analog power supply voltage.

14.2 Timing

V

DDD=VDDA

= 2.4 to 3.6 V; T

= −20 to +85 °C; RL=5kΩ; all voltages with respect to ground (pins V

amb

unless otherwise specified; note 1.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Output clock timing in video mode (see Fig.6)

T

sys

t

CWL

t

CWH

output clock cycle fo= 12.228 MHz − 81.38 − ns

output clock LOW time fo= 12.228 MHz 0.3T

output clock HIGH time fo= 12.228 MHz 0.3T

Serial input data timing (see Fig.7)
f

BCK

t

BCKH

t

BCKL

t

r

t

f

t

su(DATAI)

t

h(DATAI)

t

su(WS)

t

h(WS)

bit clock frequency −−64f
bit clock HIGH time 50 −−ns
bit clock LOW time 50 −−ns
rise time −−20 ns
fall time −−20 ns
set-up time data input 20 −−ns
hold time data input 0 −−ns
set-up time word select 20 −−ns
hold time word select 10 −−ns

= 44.1 kHz; code = 0; A-weighted 100 dB

s

f

= 96 kHz; code = 0; A-weighted 98 dB

s

= 1 kHz; V

ripple

f

= 18.432 MHz − 54.25 − ns

o

f

= 18.432 MHz 0.4T

o

= 18.432 MHz 0.4T

f

o

= 30 mV (p-p) 60 dB

ripple

− 0.7T

sys

− 0.6T

sys

− 0.7T

sys

− 0.6T

sys

SSA

sys
sys
sys
sys

s

and V

ns
ns
ns
ns

Hz

SSD

);

Note

1. The typical value of the timing is specified for a sampling frequency of 44.1 kHz.

2000 Jul 31 13

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

handbook, full pagewidth

handbook, full pagewidth

WS

BCK

t

CWH

t

CWL

T

sys

MGR984

Fig.6 Output clock timing.

t

t

BCKH

t

r

T

cy(BCK)

t

f

t

BCKL

h(WS)

t

su(WS)

t

su(DATAI)

t

h(DATAI)

DATAI

MGL880

Fig.7 Serial interface timing.

2000 Jul 31 14

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

15 APPLICATION INFORMATION

handbook, full pagewidth

SYSCLK/PLL1

BCK

WS

DATAI
SFOR1
SFOR0

MUTE

DEEM/CLKOUT

PLL0

15 13

6

1

2
3
7
11

8
9
10

analog

supply voltage

C9

47 µF

(16 V)

C10

100 nF

(63 V)

V

SSA

UDA1334ATS

V

R7
1 Ω

DDA

digital

supply voltage

C5

47 µF

(16 V)

C6

100 nF

(63 V)

V

SSD

45

R6
1 Ω

V

DDD

14

16

12

VOUTL

VOUTR

V

ref(DAC)

C3

47 µF
(16 V)

C4

47 µF
(16 V)

C8
100 nF
(63 V)

100 Ω

R1
220 kΩ

100 Ω

R2
220 kΩ

R3

R4

C7
47 µF
(16 V)

C1

C2

10 nF
(63 V)

10 nF
(63 V)

MGL971

left
output

right
output

In audio mode, the system does not need to supply a system clock.

Fig.8 Audio mode application diagram.

2000 Jul 31 15

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

27 MHz

clock

MPEG

DECODER

R5

SYSCLK/PLL1

47 Ω

2

I

S-bus

(master)

DEEM/CLKOUT

audio clock

BCK

WS

DATAI
SFOR1
SFOR0

MUTE

PLL0

6

1

2
3
7

11

8
9
10

analog

supply voltage

C9

47 µF

(16 V)

C10

100 nF

(63 V)

V

SSA

15 13

UDA1334ATS

V

R7
1 Ω

DDA

digital

supply voltage

C5

47 µF

(16 V)

C6

100 nF

(63 V)

V

SSD

45

V

R6
1 Ω

DDD

14

16

12

VOUTL

VOUTR

V

ref(DAC)

C3

47 µF
(16 V)

C4

47 µF
(16 V)

C8
100 nF
(63 V)

100 Ω

R1
220 kΩ

100 Ω

R2
220 kΩ

R3

R4

C7
47 µF
(16 V)

C1

C2

10 nF
(63 V)

10 nF
(63 V)

MGL974

left
output

right
output

In video mode, a clock output signal isgeneratedbytheUDA1334ATSwhichismasterforthe audio signals in the system; the digital audio interface is
slave, which means the system must generate the BCK and WS signal from the UDA1334ATS output clock.

Fig.9 Video mode application diagram.

handbook, full pagewidth

2000 Jul 31 16

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

16 PACKAGE OUTLINE

SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm

SOT369-1

D

c

y

Z

16

pin 1 index

9

18

w M

b

e

p

E

H

E

A

2

A

1

L

detail X

A

X

v M

A

Q

(A )

L

p

A

3

θ

0 2.5 5 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A1A2A3b

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

A

max.

0.15

mm

1.5

OUTLINE
VERSION

SOT369-1 MO-152

0.00

1.4

0.25

1.2

IEC JEDEC EIAJ

0.32

0.20

p

0.25

0.13

(1)E(1)

cD

5.30

5.10

REFERENCES

4.5

4.3

0.65

2000 Jul 31 17

eHELLpQZywv θ

1.0

0.75

0.45

0.65

0.45

PROJECTION

0.130.2 0.1

EUROPEAN

6.6

6.2

(1)

0.48

0.18

ISSUE DATE

95-02-04
99-12-27

o

10

o

0

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

17 SOLDERING

17.1 Introduction to soldering surface mount
packages

Thistextgivesavery brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering is not alwayssuitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.

17.2 Reflow soldering

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit board by screen printing, stencillingor
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.

Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.

If wave soldering is used the following conditions must be
observed for optimal results:

• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.

• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the
printed-circuit board.

The footprint must incorporate solder thieves at the
downstream end.

• Forpackageswithleadsonfoursides,thefootprintmust
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

17.3 Wave soldering

Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)orprinted-circuitboards
with a high component density, as solder bridging and
non-wetting can present major problems.

To overcome these problems the double-wave soldering
method was specifically developed.

2000 Jul 31 18

17.4 Manual soldering

Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.

When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

17.5 Suitability of surface mount IC packages for wave and reflow soldering methods

PACKAGE

WAVE REFLOW

(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

SOLDERING METHOD

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable

(3)

PLCC

, SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended
SSOP, TSSOP, VSO not recommended

(2)

(3)(4)
(5)

suitable

suitable
suitable

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

.

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2000 Jul 31 19

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

18 DATA SHEET STATUS

DATA SHEET STATUS

Objective specification Development This data sheet contains the design target or goal specifications for

Preliminary specification Qualification This data sheet contains preliminary data, and supplementarydata will be

Product specification Production This data sheet contains final specifications. Philips Semiconductors

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

19 DEFINITIONS
Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseorat any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.

Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentation or warranty that such applications will be
suitable for the specified use without further testing or
modification.

PRODUCT

STATUS

DEFINITIONS

product development. Specification may change in any manner without
notice.

published at a later date. Philips Semiconductors reserves the right to
make changes at any time without notice in order to improve design and
supply the best possible product.

reserves the right to make changes at any time without notice in order to
improve design and supply the best possible product.

20 DISCLAIMERS
Life support applications  These products are not

designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury.Philips
Semiconductorscustomers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.

Right to make changes  Philips Semiconductors
reserves the right to make changes, without notice, in the
products, including circuits, standard cells, and/or
software, described or contained herein in order to
improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
theuseofanyoftheseproducts,conveysnolicenceortitle
under any patent, copyright, or mask work right to these
products,andmakes no representations or warranties that
these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified.

(1)

2000 Jul 31 20

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

NOTES

2000 Jul 31 21

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

NOTES

2000 Jul 31 22

Philips Semiconductors Product specification

Low power audio DAC with PLL UDA1334ATS

NOTES

2000 Jul 31 23

Philips Semiconductors – a w orldwide compan y

Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,

Tel. [phone], Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
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Ireland: Newstead, Clonskeagh, DUBLIN 14,
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Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
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Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone], Fax [phone]

Middle East: see Italy

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
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Portugal: see Spain
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Tel. [phone], Fax. [phone]
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Slovenia: see Italy
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Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
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Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

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60/14 MOO 11, Bangna Trad Road KM. 3, Bagna, BANGKOK 10260,
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Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone], Fax. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
Marketing Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN,
The Netherlands, Fax. [phone]

© Philips Electronics N.V. SCA
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

2000

Internet: http://www.semiconductors.philips.com

70

Printed in The Netherlands 753503/25/02/pp24 Date of release: 2000 Jul 31 Document order number: 9397 750 07238