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TDA8783
User Manual
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Philips TDA8783 User Manual

INTEGRATED CIRCUITS
DATA SH EET
TDA8783
40 Msps, 10-bit analog-to-digital interface for CCD cameras
Product specification Supersedes data of 1999 Jun 25
2002 Oct 23
Philips Semiconductors Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras

FEATURES

• Correlated Double Sampling (CDS), AGC, 10-bit ADC and reference regulator included,adjustable bandwidth (CDS and AGC)
• Fully programmable via a 3-wire serial interface
• Sampling frequency up to 40 MHz
• AGC gain from 4.5 to 34.5 dB (in 0.1 dB steps)
• CDS programmable bandwidth from 4 to 120 MHz
• AGC programmable bandwidth from 4 to 54 MHz
• Standby mode available for each block for power saving
applications 20 mW (typ.)
• 6 dB fixed gain analog output for analog iris control
• 8-bit and 10-bit DAC included for analog settings
• Low power consumption of only 483 mW (typ.)
• 5 V operation and 2.5 to 5.25 V operation for the digital
outputs
• TTL compatible inputs, TTL and CMOS compatible outputs.
TDA8783

APPLICATIONS

• CCD camera systems.

GENERAL DESCRIPTION

The TDA8783 is a 10-bit analog-to-digital interface for CCD cameras. The device includes a correlated double sampling circuit, AGC and a low-power 10-bit Analog-to-Digital Converter (ADC) together with its reference voltage regulator.
The AGC and CDS have a bandwidth circuit controlled by on-chip DACs via a serial interface.
A 10-bit DAC controls the ADC input clamp level. An additional 8-bit DAC is provided for additional system
controls; its output voltage range is 1.4 V (p-p) which is available at pin OFDOUT.

ORDERING INFORMATION

TYPE
NUMBER
TDA8783HL LQFP48 plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2
NAME DESCRIPTION VERSION
PACKAGE
Philips Semiconductors Product specification
40 Msps, 10-bit analog-to-digital
TDA8783
interface for CCD cameras

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
CCA
V
CCD
V
CCO
I
CCA
I
CCD
I
CCO
ADC
res
V
i(CDS)(p-p)
G
CDS
f
CLK(max)
AGC
dyn
N
tot(rms)
P
tot
analog supply voltage 4.75 5 5.25 V digital supply voltage 4.75 5 5.25 V digital outputs supply voltage 2.5 3 5.25 V analog supply current − 78 95 mA digital supply current − 18 20 mA digital outputs supply current f
= 27 MHz;
CLK
− 1 − mA
CL= 20 pF; ramp input ADC resolution − 10 − bits CDS input voltage (peak-to-peak value) − 400 1200 mV CDS output amplifier gain − 6 − dB maximum clock frequency f
cut(CDS)
f
cut(AGC)
= 120 MHz; = 54 MHz
40 −−MHz
AGC dynamic range − 30 − dB total noise from CDS input to ADC output
(RMS value)
gain = 4.5 dB;
f
cut(CDS)
f
cut(AGC)
= 120 MHz; = 40 MHz
− 0.125 − LSB
total power consumption − 483 − mW
Philips Semiconductors Product specification
40 Msps, 10-bit analog-to-digital interface for CCD cameras

BLOCK DIAGRAM

V
handbook, full pagewidth
CPCDS AGND1
IND INP AGND3 SHD SHP CLPDM CLK
47
TRACK-
AND-HOLD
8 5
4-BIT DAC
CUT-OFF
CCA3
454846
TRACK-
AND-HOLD
TRACK-
AND-HOLD
CLAMP
CLAMP
ref1
CLPOB
1
DGND2
CLOCK
GENERATOR
V
CCD2
OE
TDA8783
V
CCO
3738394041424344
36
35
34
33
32
OGND
D9
D8
D7
D6
AMPOUT
AGND4
AGCOUT
V
CCA1
AGND5
ADCIN
V
ref
CLPADC
31
30
29
28
27
26
25
3
D5
D4
D3
D2
D1
D0
DGND1
OFDOUT
MGM491
4 2
6 dB
10-BIT ADC
OUTPUTS
BUFFER
TDA8783
7
6 9 10
12 11
1
1
4-BIT DAC
CUT-OFF
+
-
10-BIT DAC
14
13 15 16 17 18
AGND2
V
CCA2
DACOUT
AGC
9-BIT DAC
REGULATOR
V
RT
V
RB
DEC1
STDBY
INTERFACE
2319
SENAGND6
SERIAL
21
22
SDATA
SCLK
20
8-BIT DAC
V
CCD1
24
Fig.1 Block diagram.
Philips Semiconductors Product specification
40 Msps, 10-bit analog-to-digital
TDA8783
interface for CCD cameras

PINNING

SYMBOL PIN DESCRIPTION
CLPOB 1 clamp pulse input at optical black AGND4 2 analog ground 4 OFDOUT 3 analog output of the additional 8-bit control DAC (controlled via the serial interface) AMPOUT 4 CDS amplifier output (fixed gain = 6 dB) AGND1 5 analog ground 1 V
CCA1
AGCOUT 7 AGC amplifier signal output CPCDS 8 clamp storage capacitor pin AGND5 9 analog ground 5 ADCIN 10 ADC analog signal input from AGCOUT via a short circuit CLPADC 11 clamp control input for ADC analog input signal clamp (used with a capacitor from V V
ref
DACOUT 13 DAC output for ADC clamp level AGND2 14 analog ground 2 V
CCA2
V
RB
V
RT
DEC1 18 decoupling 1 (decoupled to ground via a capacitor) AGND6 19 analog ground 6 SDATA 20 serial data input for the 4 control DACs (9-bit DAC for AGC gain, 8-bit DAC for frequency cut-off;
SCLK 21 serial clock input for the control DACs and their serial interface; see Fig.3, Fig.4 and Table 1 SEN 22 enableinput for the serial interface shift register (active when SEN = logic 0); see Fig.3, Fig.4 and
STDBY 23 standby control (active HIGH); all the output bits are logic 0 when standby is enabled V
CCD1
DGND1 25 digital ground1 D0 26 ADC digital output 0 (LSB) D1 27 ADC digital output 1 D2 28 ADC digital output 2 D3 29 ADC digital output 3 D4 30 ADC digital output 4 D5 31 ADC digital output 5 D6 32 ADC digital output 6 D7 33 ADC digital output 7 D8 34 ADC digital output 8 D9 35 ADC digital output 9 (MSB) OGND 36 digital output ground
6 analog supply voltage 1
to ground)
ref
12 ADC input clamp reference voltage (normally connected to pin VRB or DACOUT, or connected to
ground via a capacitor)
15 analog supply voltage 2 16 ADC reference voltage (BOTTOM) code 0 17 ADC reference voltage (TOP) code 1023
additional 8-bit DAC for OFD output voltage; 10-bit DAC for ADC clamp level and the standby mode per block and edge pulse control); see Fig.3, Fig.4 and Table 1
Table 1
24 digital supply voltage 1
Philips Semiconductors Product specification
40 Msps, 10-bit analog-to-digital
TDA8783
interface for CCD cameras
SYMBOL PIN DESCRIPTION
V
CCO
OE 38 output enable (active LOW: digital outputs active; active HIGH: digital outputs high impedance) V
CCD2
DGND2 40 digital ground2 CLK 41 ADC clock input CLPDM 42 clamp pulse input at dummy pixel SHP 43 pre-set sample-and-hold pulse input SHD 44 data sample-and-hold pulse input V
CCA3
INP 46 pre-set input signal from CCD IND 47 data input signal from CCD AGND3 48 analog ground 3
37 digital output supply voltage
39 digital supply voltage 2
45 analog supply voltage 3
CLPOB
AGND4 OFDOUT AMPOUT
AGND1
V
CCA1
AGCOUT
CPCDS
AGND5
ADCIN
CLPADC
V
ref
CCA3
INP
IND 47
46
14
15
V
AGND2
CCA2
V 45
16
V
SHD
44
TDA8783HL
17
RT
RB
V
AGND3
48
1 2 3 4 5 6 7 8
9 10 11 12
13
DACOUT
SHP 43
18
DEC1
CLK
CLPDM 42
41
19
20
SDATA
AGND6
CCD2
DGND2
V
40
39
21
22
SEN
SCLK
OE
V
38
23
STDBY
V
CCO
24 37
CCD1
36 35 34 33 32 31 30 29 28 27 26 25
MGM492
OGND D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DGND1
Fig.2 Pin configuration.
Philips Semiconductors Product specification
40 Msps, 10-bit analog-to-digital
TDA8783
interface for CCD cameras

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CCA
V
CCD
V
CCO
∆V
CC
V
i
V
CLK(p-p)
I
o
T
stg
T
amb
T
j
analog supply voltage note 1 −0.3 +7.0 V digital supply voltage note 1 −0.3 +7.0 V output stages supply voltage note 1 −0.3 +7.0 V supply voltage difference
between V between V between V
CCA CCA CCD
and V and V and V
CCD CCO CCO
−1.0 +1.0 V
−1.0 +4.0 V
−1.0 +4.0 V
input voltage referenced to AGND −0.3 +7.0 V AC input voltage for switching
referenced to DGND − V
CCD
V
(peak-to-peak value) output current − 10 mA storage temperature −55 +150 °C ambient temperature −20 +75 °C junction temperature − 150 °C
Note
1. The supply voltages V
CCA
, V
CCD
and V
may have any value between −0.3 and +7.0 V provided that the supply
CCO
voltage difference ∆VCC remains as indicated.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th(j-a)
thermal resistance from junction to ambient in free air 76 K/W
Philips Semiconductors Product specification
40 Msps, 10-bit analog-to-digital
TDA8783
interface for CCD cameras

CHARACTERISTICS

V
CCA=VCCD
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
V
CCA
V
CCD
V
CCO
I
CCA
I
CCD
I
CCO
Digital inputs
LOCK INPUT: CLK (REFERENCED TO DGND)
C V
IL
V
IH
I
IL
I
IH
Z
i
C
i
INPUTS: SHP AND SHD V
IL
V
IH
I
IL
I
IH
INPUTS: SEN, SCLK, SDATA, OE, STDBY, CLPDM, CLPOB AND CLPADC V
IL
V
IH
I
i
Correlated Double Sampling (CDS); note 1 V
i(CDS)(p-p)
I
CPCDS, IINP,
I
IND
t
CDS(min)
t
hd1
=5V; V
CCO
=3V; f
= 27 MHz; T
CLK
=25°C; unless otherwise specified.
amb
analog supply voltage 4.75 5 5.25 V digital supply voltage 4.75 5 5.25 V digital outputs supply voltage 2.5 3 5.25 V analog supply current − 78 95 mA digital supply current − 18 20 mA digital outputs supply current CL= 20 pF on all data
− 1 − mA
outputs; ramp input
LOW-level input voltage 0 − 0.8 V HIGH-level input voltage 2.0 − V LOW-level input current V HIGH-level input current V input impedance f input capacitance f
= 0.8 V −1 − +1 µA
CLK
= 2.0 V −−20 µA
CLK
= 27 MHz − 46 − kΩ
CLK
= 27 MHz − 1 − pF
CLK
CCD
LOW-level input voltage 0 − 0.8 V HIGH-level input voltage 2.0 − V
CCD
LOW-level input current VIL= 0.8 V −−6−µA HIGH-level input current VIH= 2.0 V − 0 −µA
LOW-level input voltage 0 − 0.8 V HIGH-level input voltage 2.0 − V
CCD
input current −2 − +2 µA
CDS input amplitude pin 47
− 400 1200 mV
(peak-to-peak value) input current pins 8, 46 and 47 −2 − +2 µA
CDS control pulses minimum active time
f
i(CDS1,2)=fCLK(pix)
V
i(CDS)(p-p)
= 600 mV
;
8 −−ns
black-to-white transition in 1 pixel (±1 LSB typ.);
hold time INP compared to control
f
cut(CDS)
f
cut(AGC)
see Fig.5 − 1 − ns
= 120 MHz; = 54 MHz
pulse SHP
V
V
V
Philips Semiconductors Product specification
40 Msps, 10-bit analog-to-digital
TDA8783
interface for CCD cameras
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
t
hd2
t
set(CDS)
Amplifier outputs
G
AMPOUT
Z
AMPOUT
V
AMPOUT(p-p)
V
AMPOUT(bl)
V
AGCOUT(p-p)
V
AGCOUT(bl)
Z
AGCOUT
I
AGCOUT
G
AGC(min)
G
AGC(max)
f
cut(AGC)
hold time of IND compared to
see Fig.5 − 1 − ns
control pulse SHD CDS settling time see Fig.12; control DAC
4 bits input code; AGC gain = 0 dB; f
cut(AGC)
V
= 54 MHz;
= 600 mV (p-p)
i(CDS)
black-to-white transition in 1 pixel (±1 LSB typ.)
0000 − 8 − ns 0001 − 21 − ns 0010 − 42 − ns 0011 − 52 − ns 0100 − 82 − ns 0111 − 94 − ns 1000 − 195 − ns 1011 − 219 − ns 1111 − 280 − ns
output amplifier gain − 6 − dB output amplifier impedance − 300 −Ω output amplifier dynamic voltage
− 2.4 − V
(peak-to-peak value) output amplifier black level
− 1.5 − V
voltage AGC output amplifier dynamic
− 2000 − mV
voltage level (peak-to-peak value) AGC output amplifier blacklevel
V
connected to DACOUT − V
ref
ref
− V
voltage AGC output amplifier output
at 10 kHz − 5 −Ω
impedance AGC output static drive current static −−1mA minimum gain of AGC circuit AGC DAC input code = 00
− 4.5 − dB
(9-bit control); see Fig.7
maximum gain of AGC circuit AGC DAC input code ≥ 319
− 34.5 − dB
(9-bit control); see Fig.7
cut-off frequency AGC 4-bit control DAC
input code = 00 − 54 − MHz input code = 15 − 4 − MHz other codes see Fig.13
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