Philips TDA8783 User Manual

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Page 1

INTEGRATED CIRCUITS

DATA SH EET

TDA8783

40 Msps, 10-bit analog-to-digital interface for CCD cameras

Product speciﬁcation Supersedes data of 1999 Jun 25

2002 Oct 23

Page 2

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital interface for CCD cameras

FEATURES

• Correlated Double Sampling (CDS), AGC, 10-bit ADC and reference regulator included,adjustable bandwidth (CDS and AGC)

• Fully programmable via a 3-wire serial interface

• Sampling frequency up to 40 MHz

• AGC gain from 4.5 to 34.5 dB (in 0.1 dB steps)

• CDS programmable bandwidth from 4 to 120 MHz

• AGC programmable bandwidth from 4 to 54 MHz

• Standby mode available for each block for power saving

applications 20 mW (typ.)

• 6 dB fixed gain analog output for analog iris control

• 8-bit and 10-bit DAC included for analog settings

• Low power consumption of only 483 mW (typ.)

• 5 V operation and 2.5 to 5.25 V operation for the digital

outputs

• TTL compatible inputs, TTL and CMOS compatible outputs.

TDA8783

APPLICATIONS

• CCD camera systems.

GENERAL DESCRIPTION

The TDA8783 is a 10-bit analog-to-digital interface for CCD cameras. The device includes a correlated double sampling circuit, AGC and a low-power 10-bit Analog-to-Digital Converter (ADC) together with its reference voltage regulator.

The AGC and CDS have a bandwidth circuit controlled by on-chip DACs via a serial interface.

A 10-bit DAC controls the ADC input clamp level. An additional 8-bit DAC is provided for additional system

controls; its output voltage range is 1.4 V (p-p) which is available at pin OFDOUT.

ORDERING INFORMATION

TYPE

NUMBER

TDA8783HL LQFP48 plastic low proﬁle quad ﬂat package; 48 leads; body 7 × 7 × 1.4 mm SOT313-2

NAME DESCRIPTION VERSION

PACKAGE

2002 Oct 23 2

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Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital

TDA8783

interface for CCD cameras

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

CCA

CCD

CCO

CCA

CCD

CCO

ADC

res

i(CDS)(p-p)

CDS

CLK(max)

AGC

dyn

tot(rms)

tot

analog supply voltage 4.75 5 5.25 V digital supply voltage 4.75 5 5.25 V digital outputs supply voltage 2.5 3 5.25 V analog supply current − 78 95 mA digital supply current − 18 20 mA digital outputs supply current f

= 27 MHz;

CLK

− 1 − mA

CL= 20 pF; ramp input ADC resolution − 10 − bits CDS input voltage (peak-to-peak value) − 400 1200 mV CDS output ampliﬁer gain − 6 − dB maximum clock frequency f

cut(CDS)

cut(AGC)

= 120 MHz; = 54 MHz

40 −−MHz

AGC dynamic range − 30 − dB total noise from CDS input to ADC output

(RMS value)

gain = 4.5 dB;

cut(CDS)

cut(AGC)

= 120 MHz; = 40 MHz

− 0.125 − LSB

total power consumption − 483 − mW

2002 Oct 23 3

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Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital interface for CCD cameras

BLOCK DIAGRAM

handbook, full pagewidth

CPCDS AGND1

IND INP AGND3 SHD SHP CLPDM CLK

TRACK-

AND-HOLD

8 5

4-BIT DAC

CUT-OFF

CCA3

454846

TRACK-

AND-HOLD

TRACK-

AND-HOLD

CLAMP

ref1

CLPOB

DGND2

CLOCK

GENERATOR

CCD2

TDA8783

CCO

3738394041424344

OGND

AMPOUT

AGND4

AGCOUT

CCA1

AGND5

ADCIN

ref

CLPADC

DGND1

OFDOUT

MGM491

4 2

6 dB

10-BIT ADC

OUTPUTS

BUFFER

TDA8783

6 9 10

12 11

4-BIT DAC

CUT-OFF

10-BIT DAC

13 15 16 17 18

AGND2

CCA2

DACOUT

AGC

9-BIT DAC

REGULATOR

DEC1

STDBY

INTERFACE

2319

SENAGND6

SERIAL

SDATA

SCLK

8-BIT DAC

CCD1

Fig.1 Block diagram.

2002 Oct 23 4

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Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital

TDA8783

interface for CCD cameras

PINNING

SYMBOL PIN DESCRIPTION

CLPOB 1 clamp pulse input at optical black AGND4 2 analog ground 4 OFDOUT 3 analog output of the additional 8-bit control DAC (controlled via the serial interface) AMPOUT 4 CDS ampliﬁer output (ﬁxed gain = 6 dB) AGND1 5 analog ground 1 V

CCA1

AGCOUT 7 AGC ampliﬁer signal output CPCDS 8 clamp storage capacitor pin AGND5 9 analog ground 5 ADCIN 10 ADC analog signal input from AGCOUT via a short circuit CLPADC 11 clamp control input for ADC analog input signal clamp (used with a capacitor from V V

ref

DACOUT 13 DAC output for ADC clamp level AGND2 14 analog ground 2 V

CCA2

DEC1 18 decoupling 1 (decoupled to ground via a capacitor) AGND6 19 analog ground 6 SDATA 20 serial data input for the 4 control DACs (9-bit DAC for AGC gain, 8-bit DAC for frequency cut-off;

SCLK 21 serial clock input for the control DACs and their serial interface; see Fig.3, Fig.4 and Table 1 SEN 22 enableinput for the serial interface shift register (active when SEN = logic 0); see Fig.3, Fig.4 and

STDBY 23 standby control (active HIGH); all the output bits are logic 0 when standby is enabled V

CCD1

DGND1 25 digital ground1 D0 26 ADC digital output 0 (LSB) D1 27 ADC digital output 1 D2 28 ADC digital output 2 D3 29 ADC digital output 3 D4 30 ADC digital output 4 D5 31 ADC digital output 5 D6 32 ADC digital output 6 D7 33 ADC digital output 7 D8 34 ADC digital output 8 D9 35 ADC digital output 9 (MSB) OGND 36 digital output ground

6 analog supply voltage 1

to ground)

ref

12 ADC input clamp reference voltage (normally connected to pin VRB or DACOUT, or connected to

ground via a capacitor)

15 analog supply voltage 2 16 ADC reference voltage (BOTTOM) code 0 17 ADC reference voltage (TOP) code 1023

additional 8-bit DAC for OFD output voltage; 10-bit DAC for ADC clamp level and the standby mode per block and edge pulse control); see Fig.3, Fig.4 and Table 1

Table 1

24 digital supply voltage 1

2002 Oct 23 5

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Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital

TDA8783

interface for CCD cameras

SYMBOL PIN DESCRIPTION

CCO

OE 38 output enable (active LOW: digital outputs active; active HIGH: digital outputs high impedance) V

CCD2

DGND2 40 digital ground2 CLK 41 ADC clock input CLPDM 42 clamp pulse input at dummy pixel SHP 43 pre-set sample-and-hold pulse input SHD 44 data sample-and-hold pulse input V

CCA3

INP 46 pre-set input signal from CCD IND 47 data input signal from CCD AGND3 48 analog ground 3

37 digital output supply voltage

39 digital supply voltage 2

45 analog supply voltage 3

CLPOB

AGND4 OFDOUT AMPOUT

AGND1

CCA1

AGCOUT

CPCDS

AGND5

ADCIN

CLPADC

ref

CCA3

INP

IND 47

AGND2

CCA2

V 45

SHD

TDA8783HL

AGND3

1 2 3 4 5 6 7 8

9 10 11 12

DACOUT

SHP 43

DEC1

CLK

CLPDM 42

SDATA

AGND6

CCD2

DGND2

SEN

SCLK

STDBY

CCO

24 37

CCD1

36 35 34 33 32 31 30 29 28 27 26 25

MGM492

OGND D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DGND1

Fig.2 Pin configuration.

2002 Oct 23 6

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Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital

TDA8783

interface for CCD cameras

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

CCA

CCD

CCO

∆V

CLK(p-p)

stg

amb

analog supply voltage note 1 −0.3 +7.0 V digital supply voltage note 1 −0.3 +7.0 V output stages supply voltage note 1 −0.3 +7.0 V supply voltage difference

between V between V between V

CCA CCA CCD

and V and V and V

CCD CCO CCO

−1.0 +1.0 V

−1.0 +4.0 V

input voltage referenced to AGND −0.3 +7.0 V AC input voltage for switching

referenced to DGND − V

CCD

(peak-to-peak value) output current − 10 mA storage temperature −55 +150 °C ambient temperature −20 +75 °C junction temperature − 150 °C

Note

1. The supply voltages V

CCA

, V

CCD

and V

may have any value between −0.3 and +7.0 V provided that the supply

CCO

voltage difference ∆VCC remains as indicated.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

th(j-a)

thermal resistance from junction to ambient in free air 76 K/W

2002 Oct 23 7

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Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital

TDA8783

interface for CCD cameras

CHARACTERISTICS

CCA=VCCD

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

CCA

CCD

CCO

CCA

CCD

CCO

Digital inputs

LOCK INPUT: CLK (REFERENCED TO DGND)

C V

INPUTS: SHP AND SHD V

INPUTS: SEN, SCLK, SDATA, OE, STDBY, CLPDM, CLPOB AND CLPADC V

Correlated Double Sampling (CDS); note 1 V

i(CDS)(p-p)

CPCDS, IINP,

IND

CDS(min)

hd1

=5V; V

CCO

=3V; f

= 27 MHz; T

CLK

=25°C; unless otherwise speciﬁed.

amb

− 1 − mA

outputs; ramp input

LOW-level input voltage 0 − 0.8 V HIGH-level input voltage 2.0 − V LOW-level input current V HIGH-level input current V input impedance f input capacitance f

= 0.8 V −1 − +1 µA

CLK

= 2.0 V −−20 µA

CLK

= 27 MHz − 46 − kΩ

CLK

= 27 MHz − 1 − pF

CLK

CCD

LOW-level input voltage 0 − 0.8 V HIGH-level input voltage 2.0 − V

CCD

LOW-level input current VIL= 0.8 V −−6−µA HIGH-level input current VIH= 2.0 V − 0 −µA

LOW-level input voltage 0 − 0.8 V HIGH-level input voltage 2.0 − V

CCD

input current −2 − +2 µA

CDS input amplitude pin 47

− 400 1200 mV

(peak-to-peak value) input current pins 8, 46 and 47 −2 − +2 µA

CDS control pulses minimum active time

i(CDS1,2)=fCLK(pix)

i(CDS)(p-p)

= 600 mV

;

8 −−ns

black-to-white transition in 1 pixel (±1 LSB typ.);

hold time INP compared to control

cut(CDS)

cut(AGC)

see Fig.5 − 1 − ns

= 120 MHz; = 54 MHz

pulse SHP

2002 Oct 23 8

Page 9

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital

TDA8783

interface for CCD cameras

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

hd2

set(CDS)

Ampliﬁer outputs

AMPOUT

AMPOUT(p-p)

AMPOUT(bl)

AGCOUT(p-p)

AGCOUT(bl)

AGCOUT

AGC(min)

AGC(max)

cut(AGC)

hold time of IND compared to

see Fig.5 − 1 − ns

control pulse SHD CDS settling time see Fig.12; control DAC

4 bits input code; AGC gain = 0 dB; f

cut(AGC)

= 54 MHz;

= 600 mV (p-p)

i(CDS)

black-to-white transition in 1 pixel (±1 LSB typ.)

0000 − 8 − ns 0001 − 21 − ns 0010 − 42 − ns 0011 − 52 − ns 0100 − 82 − ns 0111 − 94 − ns 1000 − 195 − ns 1011 − 219 − ns 1111 − 280 − ns

output ampliﬁer gain − 6 − dB output ampliﬁer impedance − 300 −Ω output ampliﬁer dynamic voltage

− 2.4 − V

(peak-to-peak value) output ampliﬁer black level

− 1.5 − V

voltage AGC output ampliﬁer dynamic

− 2000 − mV

voltage level (peak-to-peak value) AGC output ampliﬁer blacklevel

connected to DACOUT − V

ref

− V

voltage AGC output ampliﬁer output

at 10 kHz − 5 −Ω

impedance AGC output static drive current static −−1mA minimum gain of AGC circuit AGC DAC input code = 00

− 4.5 − dB

(9-bit control); see Fig.7

maximum gain of AGC circuit AGC DAC input code ≥ 319

− 34.5 − dB

(9-bit control); see Fig.7

cut-off frequency AGC 4-bit control DAC

input code = 00 − 54 − MHz input code = 15 − 4 − MHz other codes see Fig.13

2002 Oct 23 9

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Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital

TDA8783

interface for CCD cameras

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Clamps

m(ADC)

m(CDS)

Analog-to-Digital Converter (ADC)

CLK(max)

CPH

CPL

CLK

i(ADC)(p-p)

ADCIN

INL integral non-linearity ramp input −±0.6 ±1.5 LSB DNL differential non-linearity ramp input −±0.2 ±0.75 LSB t

d(s)

Total chain characteristics (CDS + AGC + ADC)

tot(rms)

offset(ﬂ-d)

n(i)(eq)(rms)

Digital-to-Analog Converter (OFDOUT)

OFDOUT(p-p)

OFDOUT(0)

OFDOUT(255)

ADC clamp transconductance at clamp level − 7 − mS CDS clamp transconductance at clamp level − 1.5 − mS

maximum clock frequency 40 −−MHz clock pulse width HIGH 12 −−ns clock pulse width LOW 12 −−ns clock input slew rate (rising and

10% to 90% 0.5 −−V/ns

falling edge) ADC input voltage level

− 2 − V

(peak-to-peak value) ADC reference voltage output

− 1.5 − V

code 0 ADC reference voltage output

− 3.5 − V

code 1023 ADC input current −2 − +120 µA

sampling delay time −−5ns

delay between SHD and CLK 50% at rising edges

− 30 − ns CLK and SHD: transition full scale code 0 to 1023;

total output noise (RMS value) f

maximum offset between CCD

cut(CDS)

cut(AGC)

cut(CDS)

cut(AGC)

= 120 MHz; = 54 MHz;

= 600 mV

i(CDS)

= 120 MHz; = 40 MHz; note 2

= 4.5 dB − 0.125 − LSB

AGC

= 34.5 dB − 1.6 − LSB

AGC

−200 − +200 mV

ﬂoating level and CCD dark pixel level

equivalent input noise voltage (RMS value)

additional 8-bit control DAC

AGC gain = 34.5 dB − 125 −µV AGC gain = 4.5 dB − 150 −µV

− 1.4 − V

(OFD) output voltage (peak-to-peak value)

DC output voltage for code 0 − 2.3 − V DC output voltage for code 255 − 3.7 − V

2002 Oct 23 10

Page 11

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital

TDA8783

interface for CCD cameras

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

OFDOUT

ADC clamp control DAC (see Fig.8) V

DACOUT(p-p)

DACOUT

OFE

LOOP

Digital outputs (f

o(h)

o(d)

Serial interface

SCLK(max)

additional 8-bit control DAC

− 2000 −Ω

(OFD) output impedance OFD output current drive static −−50 µA

ADC clamp 10-bit control DAC

− 1 − V

output voltage (peak-to-peak value)

DC output voltage code 0 − 1.5 − V

code 1023 − 2.5 − V

ADC clamp control DAC output

−−250 Ω

impedance DAC output current drive static −−50 µA maximum offset error of

DAC+ ADC clamp loop

= 40 MHz; CL= 20 pF); note 3

CLK

HIGH-level output voltage IOH= −1mA V

code 0 −±5−LSB code 1023 −±5−LSB

− 0.5 − V

CCO

V LOW-level output voltage IOL=1mA 0 − 0.5 V output current in 3-state mode 0V<Vo<V

CCO

−20 − +20 µA output hold time 8 −−ns output delay time CL= 20 pF; V

= 10 pF; V

= 20 pF; V

= 10 pF; V

= 20 pF; V

= 10 pF; V

maximum frequency of serial

=5V − 17 23 ns

CCO

=5V − 15 21 ns

CCO

=3V − 20 29 ns

CCO

=3V − 17 25 ns

CCO

= 2.5 V − 22 33 ns

CCO

= 2.5 V − 18 28 ns

CCO

5 −−MHz

interface

Notes

1. More information about CDS related signals is available in the following figures: The clamp current for pin CPCDS is given in Fig. 9, clamp current for pins IND and INP in Fig 10 and for clamp current for pin V

in Fig 11. The CDS

ref

output amplitude is shown in Fig. 14

2. Noisemeasurementat ADC outputs: the coupling capacitor at the input isconnectedto ground, so that only the noise contributionofthefront-endisevaluated.Thefront-endoperatesat18 Mpix with a line of 1024 pixels. The first 40 are used to run CLPOB and the last 40 to run CLPDM. Data at the ADC outputs is measured during the other pixels. The differences between the types of codes statistic is then computed; the result is the noise. No quantization noise is taken into account as no signal is input. Figure15 gives noise figure graphs with signal input.

3. Depending on operating pixel frequency, the output voltage and capacitance must be determined according to the output delay timings (t

), see Fig.5.

o(d)

2002 Oct 23 11

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Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital interface for CCD cameras

handbook, full pagewidth

SDATA

SCLK

SEN

8 (D7 to D0)

OFD

LATCHES

8-bit DAC 10-bit DAC

D0 LSB MSB

AGC GAIN

LATCHES

AGC control frequency

SHIFT REGISTER

D1 D2 D3 D4 D510D6

9 (D8 to D0)

8 (D7 to D0)

FREQUENCY

LATCHES

control

CDS and AGC

D7 D8 D9 A0 A1 A2

LATCH

SELECTION

7 (D6 to D0)

PARTIAL

STANDBY

AND EDGE

standby

control

or edge clocks

CLAMP

REFERENCE

LATCHES

10 (D9 to D0)

MGM515

TDA8783

handbook, full pagewidth

SCLK

SEN

Fig.3 Serial interface block diagram.

su2

MSB LSB

A1 A0 D9 D7 D6 D5 D4 D3

A2SDATA

su1

hd4

D2 D1 D0

su3

hd3

MGE373

su1=tsu2=tsu3

= 4 ns (min.); t

hd3=thd4

= 4 ns (min.).

Fig.4 Loading sequence of control DACs input data via the serial interface.

2002 Oct 23 12

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Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital

TDA8783

interface for CCD cameras

Table 1 Serial interface programming

ADDRESS BITS

A2 A1 A0

0 0 0 OFD output control (D7 to D0). 0 0 1 Cut-off frequency of CDS and AGC. Only the 4 LSBs (D3 to D0) are used for

CDS. D4 to D7 are used for AGC. D8 and D9 should be set to logic 0. 0 1 0 AGC gain control (D8 to D0). 0 1 1 Partial standby controls for power consumption optimization. Only the 4 LSBs

(D3 to D0) are used. Edge control for pulses SHP, SHD, CLAMP and

clock ADC:

D0 = 1: CDS + AGC in standby; I D1 = 1: OFD DAC in standby; I D2 = 1: 6 dB amplifier (output on AMPOUT pin) in standby;

CCA+ICCD

D3 = 1: SHP and SHD activated with falling edge (for positive pulse) D4 = 1: CLPDM, CLPOB and CLPADC activated on HIGH level; note 1 D5 = 0: CLKADC activated with falling edge D6 must be set to logic 0.

1 0 0 Clamp reference DAC (D9 to D0).

= 95.5 mA

DATA BITS D9 to D0

CCA+ICCD

=35mA

=95mA

Note

1. When CLPADC is HIGH (D4 = 1: serial interface), the ADC input is clamped to voltage level V V

is connected to ground via a capacitor.

ref

Table 2 Standby selection

STDBY DATA BITS D9 to D0 I

1LOW4mA 0 active 96 mA

CCA+ICCD

ref

(TYP.)

2002 Oct 23 13

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Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital interface for CCD cameras

handbook, full pagewidth

IND

SHP 1.4 V

SHD

CLK

1.4 V

n(IN; SHP)

n(IN; SHD)

CDS

CPH

TDA8783

N + 3N + 2N + 1

1.4 V

ADCIN

DATA

d(s)

N − 3N − 2

o(h)

90%

N − 1

10%

Fig.5 Pixel frequency timing diagram.

o(d)

MGR395

2002 Oct 23 14

Page 15

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital interface for CCD cameras

handbook, full pagewidth

CLPOB (active HIGH)

CLPDM (active HIGH)

1 pixel

OPTICAL BLACK HORIZONTAL FLYBLACK DUMMY VIDEOVIDEOAGCOUT

CLPDM

CLPADC

WINDOW

CLPOB

WINDOW

TDA8783

1 pixel

CLPDM

CLPADC

WINDOW

(1)

CLPADC (active HIGH)

(1) When dummy pixels are not available.

(1)

MGR396

Fig.6 Line frequency timing diagram.

2002 Oct 23 15

Page 16

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital interface for CCD cameras

handbook, halfpage

34.5

AGC

(dB)

4.5 0 319

TDA8783

MGM507

511

AGC control DAC input code

handbook, full pagewidth

ADC CLAMP DAC

voltage

output

(V)

2.5

1.5

Fig.7 AGC gain as a function of DAC input code.

ADC CLAMP control DAC input code

1023

3.7

OFD DAC

voltage

output

(V)

2.3

MGM508

OFD control DAC input code

255

Fig.8 DAC voltage output as a function of DAC input code.

2002 Oct 23 16

Page 17

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital interface for CCD cameras

handbook, halfpage

(µA)

+100

−100

Fig.9 Typical clamp current for pin CPCDS.

2.00

200 mV

TDA8783

V (V)

MGR397

handbook, halfpage

(µA)

+300

−300

2.85

400 mV

Fig.10 Typical clamp current for pins IND and INP.

handbook, halfpage

(µA)

+200

ref

V (V)

MGR398

V (V)

−200

Fig.11 Typical clamp current for pin V

2002 Oct 23 17

400 mV

ref

MGR399

Page 18

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital interface for CCD cameras

160

handbook, full pagewidth

cut

(MHz)

120

(1)

TDA8783

MGR441

300

set

(ns)

250

(2) (3)

(4)

200

150

100

(1) f

cut

(2) t

(10 bits accuracy).

set

(3) t

(9 bits accuracy).

set

(4) t

(8 bits accuracy).

set

Fig.12 CDS settling time and bandwidth.

4-bit control DAC input code

F05A16B27C38D49E

2002 Oct 23 18

Page 19

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital interface for CCD cameras

handbook, full pagewidth

cut

(MHz)

05A16B27C38D49E

TDA8783

MGR401

4-bit control DAC input code

1.6

handbook, full pagewidth

o(CDS)(p-p)

(V)

1.2

0.8

0.4

0 0.4 1.2

Fig.13 AGC bandwidth.

0.80.2 0.6 1.41.0 V

i(CDS)(p-p)

MGR442

(1) (2)

(3)

(4)

(5) (6)

1.6

(V)

(1) t (2) t

set(CDS) set(CDS)

=12ns =10ns

(3) t (4) t

set(CDS) set(CDS)

=8ns =7ns

(5) t (6) t

set(CDS) set(CDS)

=6ns =5ns

Fig.14 CDS output.

2002 Oct 23 19

Page 20

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital interface for CCD cameras

handbook, full pagewidth

tot(rms) (LSB)

00 40 80 C0 100

(1)

(2) (3)

(4)

(5)

(6)

code

AGC

(dB)

TDA8783

MGR443

13F

(34.5)(4.5) (10.5) (16.5) (22.5) (28.5)

(1) f

= 27 MHz; control DAC = 00H; f

pix

(2) f

= 18 MHz; control DAC = 10H; f

pix

(3) f

= 10 MHz; control DAC = 31H; f

pix

(4) f

= 5 MHz; control DAC = 43H; f

pix

(5) f

= 1 MHz; control DAC = F8H; f

pix

(6) f

= 375 kHz; control DAC = FFH; f

pix

cut(CDS) cut(CDS)

cut(CDS) cut(CDS) cut(CDS)

cut(CDS)

= 120 MHz; f = 120 MHz; f

= 80 MHz; f = 35 MHz; f = 6 MHz; f

= 4 MHz; f

cut(AGC)

cut(AGC) cut(AGC)

cut(AGC)

= 54 MHz. = 40 MHz.

= 30 MHz.

= 12 MHz.

= 4 MHz.

Fig.15 Output noise (RMS value).

2002 Oct 23 20

Page 21

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital interface for CCD cameras

APPLICATION INFORMATION

handbook, full pagewidth

5.0 V

1 µF

CLPOB

AGND4

OFDOUT

AMPOUT

(3)

AGND1

AGCOUT

CPSDS AGND5

CLPADC

CCA1

ADCIN

ref

1 2 3 4 5 6 7

9 10 11 12

CCD

AGND3

48 47 46 45 44 43 42 41 40 39 38 37

5.0 V 5.0 V

(3)

220

IND

INP

CCA3

from timing

generator

SHD

SHP

CLK

CLPDM

DGND2

CCD2

2.5 to 5.25 V

(3)

TDA8783

13 14 15 16 17 18 19 20 21 22 23 24

CCO

(3)

36 35 34 33 32 31 30 29 28 27 26 25

TDA8783

OGND D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DGND1

CCA2

AGND2

(2)

(1)

Depending on the application, the following connections must be made: (1) The clamp level of the signal input at ADCIN can be tuned from code 00 to code 511 in 0.5 LSB steps of ADC via the serial interface

(clamp ADC activated). (2) Clamp ADC not activated, direct connection from DACOUT to V (3) All supply pins must be decoupled with 100 nF capacitors as close as possible to the device.

DACOUT

100

5.0 V

(3)

ref

DEC1

AGND6

2.2 nF

SCLK

SDATA

serial

interface

SEN

CCD1

STDBY

5.0 V

(3)

MGM504

Fig.16 Application diagram.

2002 Oct 23 21

Page 22

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital interface for CCD cameras

Power and grounding recommendations

Care must be taken to minimize noise when designing a printed-circuit board forapplications such as PC cameras, surveillance cameras, camcorders and digital still cameras.

For the front-end integrated circuit, the basic rules of printed-circuit board design and implementation of analog components (such as classical operational amplifiers) must be taken into account, particularly with respect to power and ground connections.

The connections between CCD interface and CDS input should be as short as possible and a ground ring protection around these connections can be beneficial.

Decoupling capacitors are necessary on all supply pins as shown in Fig.16.

Separate analog and digital supplies provide the best performance. If it is not possible to do this on the board, then decouple the analog supply pins effectively from the digital supply pins. The decoupling capacitors must be placed as close as possible to the IC package.

TDA8783

In a two-ground system, in order to minimize the noise from package and die parasitics, the following recommendations must be implemented:

• The ground pin associated with the digital outputs must be connected to the digital ground plane and special care should be taken to avoid feedthrough in the analog ground plane. The analog and digital ground planes mustbeconnected with an inductor as close as possible to the IC package,in order to havethe same DC voltage on the ground planes.

• The digital output pins and their associated lines should be shielded by the digital ground plane, which can be used as return path for the digital signals.

2002 Oct 23 22

Page 23

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital interface for CCD cameras

PACKAGE OUTLINE

LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm

TDA8783

SOT313-2

w M

pin 1 index

DIMENSIONS (mm are the original dimensions)

A1A2A3b

max.

0.20

1.60

0.05

1.45

1.35

UNIT

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.25

w M

0.27

0.17

(1) (1)(1)

0.18

7.1

0.12

6.9

v M

0 2.5 5 mm

scale

(1)

7.1

6.9

0.5

9.15

8.85

9.15

8.85

0.75

0.45

detail X

0.12 0.10.21.0

0.95

0.55

(A )

Zywv θ

0.95

0.55

OUTLINE VERSION

SOT313-2 MS-026136E05

IEC JEDEC EIAJ

REFERENCES

2002 Oct 23 23

EUROPEAN

PROJECTION

ISSUE DATE

99-12-27 00-01-19

Page 24

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital interface for CCD cameras

SOLDERING Introduction to soldering surface mount packages

Thistextgivesavery brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011). There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for certainsurfacemount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.

Reﬂow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied totheprinted-circuitboard by screen printing, stencilling or pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages.

Wave soldering

Conventional single wave soldering is not recommended forsurfacemount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.

To overcome these problems the double-wave soldering method was specifically developed.

TDA8783

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• Forpackageswith leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

2002 Oct 23 24

Page 25

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital

TDA8783

interface for CCD cameras

Suitability of surface mount IC packages for wave and reﬂow soldering methods

PACKAGE

BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,

HVSON, SMS

(4)

PLCC LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO not recommended

Notes

1. Formoredetailedinformationonthe BGA packages refer to the

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder

4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not

6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

, SO, SOJ suitable suitable

from your Philips Semiconductors sales office.

temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the

cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface.

The package footprint must incorporate solder thieves downstream and at the side corners.

suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

(1)

not suitable

“(LF)BGAApplicationNote

SOLDERING METHOD

WAVE REFLOW

(3)

suitable

(4)(5)

suitable

(6)

suitable

”(AN01026);orderacopy

(2)

2002 Oct 23 25

Page 26

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital

TDA8783

interface for CCD cameras

DATA SHEET STATUS

LEVEL

I Objective data Development This data sheet contains data from the objective speciﬁcation for product

II Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation.

III Product data Production This data sheet contains data from the product speciﬁcation. Philips

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

DATA SHEET

STATUS

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

(1)

PRODUCT

STATUS

(2)(3)

DEFINITION

development. Philips Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in order to improve the design and supply the best possible product.

Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

DEFINITIONS Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device attheseoratanyotherconditionsabovethosegiveninthe Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make norepresentationor warranty that such applications will be suitable for the specified use without further testing or modification.

DISCLAIMERS Life support applications  These products are not

designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductorscustomersusing or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

2002 Oct 23 26

Page 27

Philips Semiconductors Product speciﬁcation

40 Msps, 10-bit analog-to-digital interface for CCD cameras

TDA8783

NOTES

2002 Oct 23 27

Page 28

Philips Semiconductors – a w orldwide compan y

Contact information

For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales ofﬁces addresses send e-mail to: [email protected].

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands 753504/03/pp28 Date of release: 2002 Oct 23 Document order number: 9397 750 10176

SCA74