Philips TDA8762AM-8-C1, TDA8762AM-6-C1 Datasheet
DATA SH EET
Product specification
Supersedes data of 1995 April 27
File under Integrated Circuits, IC02
1996 Mar 21
INTEGRATED CIRCUITS
TDA8762A
10-bit high-speed low-power
analog-to-digital converter
1996 Mar 21 2
Philips Semiconductors Product specification
10-bit high-speed low-power
analog-to-digital converter
TDA8762A
FEATURES
• 10-bit resolution
• Sampling rate up to 80 MHz
• DC sampling allowed
• One clock cycle conversion only
• High signal-to-noise ratio over a large analog input
frequency range (9.3 effective bits at 4.43 MHz
full-scale input at f
clk
= 80 MHz)
• No missing codes guaranteed
• In range (IR) TTL output
• TTL compatible digital inputs and outputs
• Low-level AC clock input signal allowed
• External reference voltage regulator
• Power dissipation only 380 mW (typical)
• Low analog input capacitance, no buffer amplifier
required
• No sample-and-hold circuit required.
APPLICATIONS
High-speed analog-to-digital conversion for:
• Video data digitizing
• Radar pulse analysis
• Transient signal analysis
• High energy physics research
•Σ∆ modulators
• Medical imaging.
GENERAL DESCRIPTION
The TDA8762A is a 10-bit high-speed analog-to-digital
converter (ADC) for professional video and other
applications. It converts the analog input signal into 10-bit
binary-coded digital words at a maximum sampling rate of
80 MHz. All digital inputs and outputs are TTL compatible,
although a low-level sine wave clock input signal is
allowed.
QUICK REFERENCE DATA
ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
CCA
analog supply voltage 4.75 5.0 5.25 V
V
CCD
digital supply voltage 4.75 5.0 5.25 V
V
CCO
output stages supply voltage 4.4 5.0 5.25 V
I
CCA
analog supply current − 29 36 mA
I
CCD
digital supply current − 24 30 mA
I
CCO
output stages supply current CL= 15 pF; ramp input − 23 30 mA
INL integral non-linearity f
clk
= 80 MHz; ramp input −±0.75 ±1.5 LSB
DNL differential non-linearity f
clk
= 80 MHz; ramp input −±0.3 ±0.7 LSB
f
clk(max)
maximum clock frequency
TDA8762AM/6 60 −−MHz
TDA8762AM/8 80 −−MHz
P
tot
total power dissipation − 380 500 mW
TYPE
NUMBER
PACKAGE
SAMPLING
FREQUENCY (MHz)
NAME DESCRIPTION VERSION
TDA8762AM/6 SSOP28
plastic shrink small outline package; 28 leads;
body width 5.3 mm
SOT341-1 60
TDA8762AM/8 SSOP28 SOT341-1 80
1996 Mar 21 3
Philips Semiconductors Product specification
10-bit high-speed low-power
analog-to-digital converter
TDA8762A
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
12
DGND
5
6
8
7
9
AGND2
V
RB
V
RM
V
RT
V
I
11
V
CCD
3
26
V
CCA
21
22
23
24
20 D4
D5
D6
D7
D8
19
18
25
2
D3
D2
17 D1
16 D0
D9
IN RANGE LATCH
TTL OUTPUTSLATCHES
CLOCK DRIVER
MBE560
TTL OUTPUT
1
CLK
10
OE
TC
TDA8762A
13
V
CCO1
4
AGND1
analog grounds digital ground
27
OGND2
14
OGND1
output grounds
analog
voltage input
data outputs
LSB
MSB
28
V
CCO2
IR
output
R
LAD
ANALOG -TO - DIGITAL
CONVERTER
1996 Mar 21 4
Philips Semiconductors Product specification
10-bit high-speed low-power
analog-to-digital converter
TDA8762A
PINNING
SYMBOL PIN DESCRIPTION
CLK 1 clock input
TC 2 two’s complement input (active LOW)
V
CCA
3 analog supply voltage (5 V)
AGND1 4 analog ground 1
AGND2 5 analog ground 2
V
RB
6 reference voltage BOTTOM input
V
RM
7 reference voltage MIDDLE
V
I
8 analog input voltage
V
RT
9 reference voltage TOP input
OE 10 output enable input
(TTL level input, active LOW)
V
CCD
11 digital supply voltage (5 V)
DGND 12 digital ground
V
CCO1
13 supply voltage for output stages 1
(5 V)
OGND1 14 output ground 1
n.c. 15 not connected
D0 16 data output; bit 0 (LSB)
D1 17 data output; bit 1
D2 18 data output; bit 2
D3 19 data output; bit 3
D4 20 data output; bit 4
D5 21 data output; bit 5
D6 22 data output; bit 6
D7 23 data output; bit 7
D8 24 data output; bit 8
D9 25 data output; bit 9 (MSB)
IR 26 in range data output
OGND2 27 output ground 2
V
CCO2
28 supply voltage for output stages 2
(5 V)
Fig.2 Pin configuration.
handbook, halfpage
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
CLK
TC
CCA
AGND1
AGND2
RB
RM
I
RT
OE
CCD
DGND
CCO1
OGND1
CCO2
OGND2
IR
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
n.c.
V
V
V
V
V
V
V
V
TDA8762A
MBE561
1996 Mar 21 5
Philips Semiconductors Product specification
10-bit high-speed low-power
analog-to-digital converter
TDA8762A
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note
1. The supply voltages V
CCA
, V
CCD
and V
CCO
may have any value between −0.3 and +7.0 V provided that the supply
voltage differences ∆VCC are respected.
HANDLING
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V
CCA
analog supply voltage note 1 −0.3 +7.0 V
V
CCD
digital supply voltage note 1 −0.3 +7.0 V
V
CCO
output stages supply voltage note 1 −0.3 +7.0 V
∆V
CC
supply voltage difference
V
CCA
− V
CCD
−1.0 +1.0 V
V
CCA
− V
CCO
−1.0 +1.0 V
V
CCD
− V
CCO
−1.0 +1.0 V
V
I
input voltage referenced to AGND −0.3 +7.0 V
V
clk(p-p)
AC input voltage for switching
(peak-to-peak value)
referenced to DGND − V
CCD
V
I
O
output current − 10 mA
T
stg
storage temperature −55 +150 °C
T
amb
operating ambient temperature 0 +70 °C
T
j
junction temperature − +150 °C
SYMBOL PARAMETER VALUE UNIT
R
th j-a
thermal resistance from junction to ambient in free air 110 K/W
1996 Mar 21 6
Philips Semiconductors Product specification
10-bit high-speed low-power
analog-to-digital converter
TDA8762A
CHARACTERISTICS
V
CCA=V3
to V4and V5= 4.75 to 5.25 V; V
CCD=V11
to V12= 4.75 to 5.25 V; V
CCO=V13
and V28to V14 and
V27= 4.4 to 5.25 V; AGND and DGND shorted together; T
amb
= 0 to +70 °C; typical values measured at
V
CCA=VCCD=VCCO
=5V; V
I(p-p)
= 2.0 V; CL= 15 pF and T
amb
=25°C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply
V
CCA
analog supply voltage 4.75 5.0 5.25 V
V
CCD
digital supply voltage 4.75 5.0 5.25 V
V
CCO
output stages supply voltage 4.4 5.0 5.25 V
∆V
CC
voltage difference
V
CCA
− V
CCD
−0.25 − +0.25 V
V
CCA
− V
CCO
−0.4 − +0.4 V
V
CCD
− V
CCO
−0.4 − +0.4 V
I
CCA
analog supply current − 29 36 mA
I
CCD
digital supply current − 24 30 mA
I
CCO
output stages supply current CL= 15 pF; ramp input − 23 30 mA
Inputs
C
LOCK INPUT CLK (REFERENCED TO DGND); note 1
V
IL
LOW level input voltage 0 − 0.8 V
V
IH
HIGH level input voltage 2.0 − V
CCD
V
I
IL
LOW level input current V
clk
= 0.4 V −10 +1 µA
I
IH
HIGH level input current V
clk
= 2.7 V −−20 µA
Z
I
input impedance f
clk
= 80 MHz − 2 − kΩ
C
I
input capacitance f
clk
= 80 MHz − 2 − pF
INPUTS OE AND TC (REFERENCED TO DGND); see Table 2
V
IL
LOW level input voltage 0 − 0.8 V
V
IH
HIGH level input voltage 2.0 − V
CCD
V
I
IL
LOW level input current VIL= 0.4 V −400 −− µA
I
IH
HIGH level input current VIH= 2.7 V −−20 µA
VI(ANALOG INPUT VOLTAGE REFERENCED TO AGND)
I
IL
LOW level input current VI= 1.3 V − 0 −µA
I
IH
HIGH level input current VI= 3.8 V − 70 −µA
Z
I
input impedance fi= 4.43 MHz − 5 − kΩ
C
I
input capacitance fi= 4.43 MHz − 8 − pF
1996 Mar 21 7
Philips Semiconductors Product specification
10-bit high-speed low-power
analog-to-digital converter
TDA8762A
Reference voltages for the resistor ladder; see Table 1
V
RB
reference voltage BOTTOM 1.2 1.3 − V
V
RT
reference voltage TOP − 3.8 V
CCA
− 0.8 V V
V
diff
differential reference voltage
VRT− V
RB
1.8 2.5 3.0 V
I
ref
reference current − 28 − mA
R
LAD
resistor ladder − 90 −Ω
TC
RLAD
temperature coefficient of the
resistor ladder
− 1860 − ppm
167 mΩ/K
V
osB
offset voltage BOTTOM note 2 − 220 − mV
V
osT
offset voltage TOP note 2 − 220 − mV
V
I(p-p)
analog input voltage
(peak-to-peak value)
note 3 1.5 2.06 2.5 V
Outputs
D
IGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO OGND)
V
OL
LOW level output voltage IO= 1 mA 0 − 0.4 V
V
OH
HIGH level output voltage IO= 0 mA 2.7 − V
CCO
− 0.5 V
I
O
= −0.4 mA 2.7 − V
CCO
− 1.3 V
I
O
= −1 mA 2.4 − V
CCO
− 1.4 V
I
OZ
output current in 3-state mode 0.4 V < VO<V
CCO
−20 − +20 µA
Switching characteristics
C
LOCK INPUT CLK; see Fig.4; note 1
f
clk(max)
maximum clock frequency
TDA8762A/6 60 −− MHz
TDA8762A/8 80 −− MHz
t
CPH
clock pulse width HIGH 5 −− ns
t
CPL
clock pulse width LOW 5 −− ns
Analog signal processing
L
INEARITY
INL integral non-linearity f
clk
= 80 MHz; ramp input −±0.75 ±1.5 LSB
DNL differential non-linearity f
clk
= 80 MHz; ramp input −±0.3 ±0.7 LSB
OFER offset error middle code; V
RB
= 1.3 V;
VRT= 3.8 V
−±1− LSB
GER gain error (from device to device) V
RB
= 1.3 V; VRT= 3.8 V;
note 4
−±0.1 − %
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
1996 Mar 21 8
Philips Semiconductors Product specification
10-bit high-speed low-power
analog-to-digital converter
TDA8762A
BANDWIDTH (f
clk
= 80 MHz)
B analog bandwidth full-scale sine wave; note 5 − 40 − MHz
75% full-scale sine wave;
note 5
− 55 − MHz
small signal at mid-scale;
V
I
= ±10 LSB at code 512;
note 5
− 700 − MHz
t
STLH
analog input settling time
LOW-to-HIGH
full-scale square wave;
see Fig.6; note 6
− 2.0 3 ns
t
STHL
analog input settling time
HIGH-to-LOW
full-scale square wave;
see Fig.6; note 6
− 2.5 3.5 ns
HARMONICS (f
clk
=80MHZ)
h
1
fundamental harmonics (full scale) fi= 4.43 MHz −−0dB
h
all
harmonics (full scale);
all components
fi= 4.43 MHz
second harmonics −−70 62 dB
third harmonics −−75 67 dB
THD total harmonic distortion f
i
= 4.43 MHz −−68 − dB
SIGNAL-TO-NOISE RATIO; see Fig.8; note 7
S/N signal-to-noise ratio (full scale) without harmonics;
f
clk
= 80 MHz;
fi= 4.43 MHz
56 58 − dB
EFFECTIVE BITS; see Figs 7, 8 and 9; note 7
EB effective bits
TDA8762AM/6 f
clk
= 60 MHz
f
i
= 4.43 MHz − 9.35 − bits
f
i
= 10 MHz − 9.0 − bits
f
i
= 20 MHz − 8.1 − bits
TDA8762AM/8 f
clk
= 80 MHz
f
i
= 4.43 MHz − 9.3 − bits
f
i
= 10 MHz − 8.9 − bits
f
i
= 20 MHz − 8.0 − bits
TWO-TONE; note 8
TTIR two-tone intermodulation rejection f
clk
= 80 MHz −−68 − dB
BIT ERROR RATE
BER bit error rate f
clk
= 80 MHz;
fi= 4.43 MHz;
VI= ±16 LSB at code 512
− 10
−13
− times/
sample
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
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