Philips tda8762 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

TDA8762

10-bit high-speed low-power analog-to-digital converter

Product speciﬁcation Supersedes data of 1995 Feb 15 File under Integrated Circuits, IC02

1996 Mar 28

Philips Semiconductors Product speciﬁcation

10-bit high-speed low-power analog-to-digital converter

FEATURES

• 10-bit resolution

• Sampling rate up to 40 MHz

• DC sampling allowed

• One clock cycle conversion only

• High signal-to-noise ratio over a large analog input

frequency range (9.4 effective bits at 4.43 MHz full-scale input at f

• No missing codes guaranteed

• In range (IR) TTL output

• TTL compatible digital inputs and outputs

• Low-level AC clock input signal allowed

• External reference voltage regulator

• Power dissipation only 380 mW (typical)

• Low analog input capacitance, no buffer amplifier

required

• No sample-and-hold circuit required.

= 40 MHz)

clk

TDA8762

APPLICATIONS

High-speed analog-to-digital conversion for:

• Video data digitizing

• Radar pulse analysis

• Transient signal analysis

• High energy physics research

•Σ∆ modulators

• Medical imaging.

GENERAL DESCRIPTION

The TDA8762 is a 10-bit high-speed analog-to-digital converter (ADC) for professional video and other applications. It converts the analog input signal into 10-bit binary-coded digital words at a maximum sampling rate of 40 MHz. All digital inputs and outputs are TTL compatible, although a low-level sine wave clock input signal is allowed.

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

V

CCA

V

CCD

V

CCO

I

CCA

I

CCD

I

CCO

INL integral non-linearity f

analog supply voltage 4.75 5.0 5.25 V digital supply voltage 4.75 5.0 5.25 V output stages supply voltage 4.4 5.0 5.25 V analog supply current − 29 36 mA digital supply current − 24 30 mA output stages supply current − 23 30 mA

= 40 MHz;

clk

−±0.75 ±1.5 LSB

ramp input

DNL differential non-linearity f

= 40 MHz;

clk

−±0.3 ±0.7 LSB

ramp input

f

clk(max)

P

tot

maximum clock frequency 40 −−MHz total power dissipation − 380 500 mW

ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

TDA8762M/4 SSOP28 plastic shrink small outline package;

PACKAGE

SAMPLING

FREQUENCY (MHz)

SOT341-1 40

28 leads; body width 5.3 mm

1996 Mar 28 2

Philips Semiconductors Product speciﬁcation

10-bit high-speed low-power analog-to-digital converter

BLOCK DIAGRAM

handbook, full pagewidth

analog

voltage input

V

RT

V

RM

V

RB

V

CCA

3

9

R

LAD

I

8

7

6

ANALOG -TO - DIGITAL

CONVERTER

CLK

1

CLOCK DRIVER

IN RANGE LATCH

V

CCD

11

TDA8762

OE 10

TTL OUTPUTSLATCHES

TTL OUTPUT

2

25

D9

D8

24

D7

23

D6

22

D5

21 20 D4

19

D3

18

D2 17 D1 16 D0

V

13

28

V

26

TDA8762

TC

MSB

data outputs

LSB

CCO1

CCO2

IR output

4 AGND1

analog grounds digital ground

5 AGND2

12 DGND

Fig.1 Block diagram.

1996 Mar 28 3

14 OGND1

output grounds

27 OGND2

MGC035

Philips Semiconductors Product speciﬁcation

10-bit high-speed low-power analog-to-digital converter

PINNING

SYMBOL PIN DESCRIPTION

CLK 1 clock input TC 2 two’s complement input (active LOW) V

CCA

AGND1 4 analog ground 1 AGND2 5 analog ground 2 V

RB

V

RM

V

I

V

RT

OE 10 output enable input

V

CCD

DGND 12 digital ground V

CCO1

OGND1 14 output ground 1 n.c. 15 not connected D0 16 data output; bit 0 (LSB) D1 17 data output; bit 1 D2 18 data output; bit 2 D3 19 data output; bit 3 D4 20 data output; bit 4 D5 21 data output; bit 5 D6 22 data output; bit 6 D7 23 data output; bit 7 D8 24 data output; bit 8 D9 25 data output; bit 9 (MSB) IR 26 in range data output OGND2 27 output ground 2 V

CCO2

3 analog supply voltage (+5 V)

6 reference voltage BOTTOM input 7 reference voltage MIDDLE 8 analog input voltage 9 reference voltage TOP input

(TTL level input, active LOW)

11 digital supply voltage (+5 V)

13 supply voltage for output stages 1

(+5 V)

28 supply voltage for output stages 2

(+5 V)

handbook, halfpage

1

CLK

2

TC

V

3

CCA

V

RB

V

RM

V

RT OE

V

CCD

DGND

CCO1

4 5 6 7

I

8

9 10 11 12 13

TDA8762

MGC036

V

AGND1 AGND2

V

OGND1

Fig.2 Pin configuration.

TDA8762

V

28

CCO2

27

OGND2 IR

26 25

D9

24

D8

23

D7

22

D6 D5

21 20

D4 D3

19 18

D2

17

D1

16

D0

1514

n.c.

1996 Mar 28 4

Philips Semiconductors Product speciﬁcation

10-bit high-speed low-power

TDA8762

analog-to-digital converter

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V

CCA

V

CCD

V

CCO

∆V

V

I

V

clk(p-p)

I

O

T

stg

T

amb

T

j

CC

analog supply voltage note 1 −0.3 +7.0 V digital supply voltage note 1 −0.3 +7.0 V output stages supply voltage note 1 −0.3 +7.0 V supply voltage difference

V V V

CCA CCA CCD

− V

CCD CCO CCO

−1.0 +1.0 V

input voltage referenced to AGND −0.3 +7.0 V AC input voltage for switching

referenced to DGND − V

CCD

(peak-to-peak value) output current − 10 mA storage temperature −55 +150 °C operating ambient temperature 0 +70 °C junction temperature − +150 °C

V

Note

1. The supply voltages V

CCA

CCD

and V

may have any value between −0.3 V and +7.0 V provided that the supply

CCO

, V

voltage differences ∆VCC are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER VALUE UNIT

R

th j-a

thermal resistance from junction to ambient in free air 110 K/W

1996 Mar 28 5

Philips Semiconductors Product speciﬁcation

10-bit high-speed low-power

TDA8762

analog-to-digital converter

CHARACTERISTICS

V

CCA=V3

V27= 4.4 to 5.25 V; AGND and DGND shorted together; T V

CCA=VCCD=VCCO

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply

V

CCA

V

CCD

V

CCO

∆V

I

CCA

I

CCD

I

CCO

Inputs

to V4and V5= 4.75 to 5.25 V; V

=5V; V

analog supply voltage 4.75 5.0 5.25 V digital supply voltage 4.75 5.0 5.25 V output stages supply voltage 4.4 5.0 5.25 V

CC

voltage difference

V

− V V V

CCA CCA CCD

− V

CCD CCO CCO

analog supply current − 29 36 mA digital supply current − 24 30 mA output stages supply current CL= 15 pF; ramp input − 23 30 mA

CCD=V11

= 2.0 V; CL= 15 pF and T

I(p-p)

to V12= 4.75 to 5.25 V; V

= 0 to +70 °C; typical values measured at

amb

=25°C; unless otherwise speciﬁed.

amb

CCO=V13

and V28to V14 and

−0.25 − +0.25 V

−0.4 − +0.4 V

LOCK INPUT CLK (REFERENCED TO DGND); note 1

C V

IL

V

IH

I

IL

I

IH

Z

I

C

I

LOW level input voltage 0 − 0.8 V HIGH level input voltage 2.0 − V LOW level input current V HIGH level input current V input impedance f input capacitance f

clk clk

= 40 MHz − 2 − kΩ

clk

= 40 MHz − 2 − pF

clk

INPUTS OE AND TC (REFERENCED TO DGND); see Table 2 V

IL

V

IH

I

IL

I

IH

LOW level input voltage 0 − 0.8 V HIGH level input voltage 2.0 − V LOW level input current VIL= 0.4 V −400 −− µA

HIGH level input current VIH= 2.7 V −−20 µA VI(ANALOG INPUT VOLTAGE REFERENCED TO AGND) I

IL

I

IH

Z

I

C

I

LOW level input current VI= 1.3 V − 0 −µA

HIGH level input current VI= 3.8 V − 70 −µA

input impedance fi= 4.43 MHz − 5 − kΩ

input capacitance fi= 4.43 MHz − 8 − pF

CCD

V = 0.4 V −10 +1 µA = 2.7 V −−20 µA

CCD

V

1996 Mar 28 6

Philips Semiconductors Product speciﬁcation

10-bit high-speed low-power

TDA8762

analog-to-digital converter

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Reference voltages for the resistor ladder; see Table 1

V

RB

V

RT

V

diff

I

ref

R

LAD

TC

RLAD

V

osB

V

osT

V

I(p-p)

Outputs

D

IGITAL OUTPUTS D9 TO D0 AND IR (REFERENCED TO OGND)

V

OL

V

OH

I

OZ

Switching characteristics

reference voltage BOTTOM 1.2 1.3 − V reference voltage TOP − 3.8 V differential reference voltage

VRT− V

RB

1.8 2.5 3.0 V

CCA

− 0.8 V V

reference current − 28 − mA resistor ladder − 90 −Ω temperature coefﬁcient of the resistor

ladder

− 1860 − ppm

− 167 − mΩ/K

offset voltage BOTTOM note 2 − 220 − mV offset voltage TOP note 2 − 220 − mV analog input voltage

note 3 1.5 2.06 2.5 V

(peak-to-peak value)

LOW level output voltage IO= 1 mA 0 − 0.4 V HIGH level output voltage IO= 0 mA 2.7 − V

I

= −0.4 mA 2.7 − V

O

I

= −1 mA 2.4 − V

O

output current in 3-state mode 0.4 V < VO<V

CCO

−20 − +20 µA

CCO CCO CCO

− 0.5 V

− 1.3 V

− 1.4 V

LOCK INPUT CLK; see Fig.4; note 1

C f

clk(max)

t

CPH

t

CPL

maximum clock frequency 40 −− MHz clock pulse width HIGH 8 −− ns clock pulse width LOW 8 −− ns

Analog signal processing

INEARITY

L INL integral non-linearity f

= 40 MHz;

clk

ramp input

DNL differential non-linearity f

= 40 MHz;

clk

ramp input

OFER offset error middle code;

= 1.3 V; VRT= 3.8 V

V

RB

GER gain error (from device to device) V

= 1.3 V;

RB

VRT= 3.8 V; note 4

−±0.75 ±1.5 LSB

−±0.3 ±0.7 LSB

−±1− LSB

−±0.1 − %

1996 Mar 28 7

Philips Semiconductors Product speciﬁcation

10-bit high-speed low-power

TDA8762

analog-to-digital converter

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

BANDWIDTH (f B analog bandwidth full-scale sine wave;

t

STLH

t

STHL

HARMONICS (f h

1

h

all

THD total harmonic distortion f SIGNAL-TO-NOISE RATIO; see Fig.8; note 7 S/N signal-to-noise ratio (full scale) without harmonics;

EFFECTIVE BITS; see Figs 7, 8 and 9; note 7 EB effective bits f

TWO-TONE; note 8 TTIR two-tone intermodulation rejection f BIT ERROR RATE BER bit error rate f

= 40 MHz)

clk

− 40 − MHz

note 5 75% full-scale sine

− 55 − MHz

wave; note 5 small signal at

− 700 − MHz mid-scale; V

= ±10 LSB at

I

code 512; note 5

analog input settling time LOW-to-HIGH

analog input settling time HIGH-to-LOW

=40MHZ)

clk

full-scale square wave; Fig.6; note 6

− 2.0 3 ns

− 2.5 3.5 ns

fundamental harmonics (full scale) fi= 4.43 MHz −−0dB harmonics (full scale); all components fi= 4.43 MHz

second harmonics −−70 −62 dB third harmonics −−75 −67 dB

= 4.43 MHz −−70 − dB

i

57 59 − dB

= 40 MHz;

f

clk

fi= 4.43 MHz

= 40 MHz

clk

= 4.43 MHz − 9.4 − bits

f

i

f

= 7.5 MHz − 9.3 − bits

i

f

= 10 MHz − 9.0 − bits

i

f

= 15 MHz − 8.7 − bits

i

= 40 MHz −−70 − dB

clk

= 40 MHz;

clk

fi= 4.43 MHz;

− 10

−13

− times/

sample VI= ±16 LSB at code 512

1996 Mar 28 8