Philips TDA8761AM-C4, TDA8761AM-C3, TDA8761AM-C1 Datasheet

INTEGRATED CIRCUITS

DATA SHEET

TDA8761A

9-bit analog-to-digital converter for digital video

Product specification

1998 Nov 03

Supersedes data of 1997 Aug 21

File under Integrated Circuits, IC02

Philips Semiconductors	Product specification

9-bit analog-to-digital converter

TDA8761A

for digital video

FEATURES

∙9-bit resolution

∙Sampling rate up to 40 MHz

∙DC sampling allowed

∙One clock cycle conversion only

∙High signal-to-noise ratio over a large analog input frequency range (8.2 effective bits at 10 MHz full-scale input at fclk = 30 MHz)

∙No missing codes guaranteed

∙In Range (IR) CMOS output

∙Levels TTL and CMOS compatible digital inputs

∙3 to 5 V CMOS digital outputs

∙Low-level AC clock input signal allowed

∙External reference voltage regulator

∙Power dissipation only 158 mW (typical)

∙Low analog input capacitance, no buffer amplifier required

∙No sample-and-hold circuit required.

APPLICATIONS

Analog-to-digital conversion for:

∙Video data digitizing

∙Digital Video Broadcasting (DVB)

∙Cable TV.

GENERAL DESCRIPTION

The TDA8761A is a 9-bit Analog-to-Digital Converter (ADC) for professional video and digital video set box applications. It converts the analog input signal into 9-bit binary-coded digital words at a maximum sampling rate of 40 MHz. Its linearity performance ensures the required conversion accuracy in the event of 256-QAM demodulator concept and for all symbol frequencies.

All digital inputs and outputs are TTL and CMOS compatible, although a low-level sine wave clock input signal is allowed.

QUICK REFERENCE DATA

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
VCCA	analog supply voltage		4.75	5.0	5.25	V
VCCD	digital supply voltage		4.75	5.0	5.25	V
VCCO	output stages supply voltage		3.0	3.3	5.25	V
ICCA	analog supply current		−	18	24	mA
ICCD	digital supply current		−	13	18	mA
ICCO	output stages supply current	fclk = 30 MHz; ramp input	−	1	2	mA
INL	integral non-linearity	fclk = 30 MHz; ramp input	−	±0.8	±1.6	LSB
AINL	AC integral non-linearity	full-scale input sine wave; note 1	−	±0.75	0.9	LSB
		50% full-scale input sine wave; note 1	−	±0.5	±0.75	LSB
DNL	differential non-linearity	fclk = 30 MHz; ramp input	−	±0.3	±0.7	LSB
ADNL	AC differential non-linearity	full-scale input sine wave; note 1	−	±0.5	±0.75	LSB
		50% full-scale input sine wave; note 1	−	±0.3	±0.5	LSB
fclk(max)	maximum clock frequency		40	−	−	MHz
Ptot	total power dissipation		−	158	173	mW

Note

1. fi = 10 MHz and fclk = 30 MHz; fi = 8 MHz and fclk = 20 MHz.

1998 Nov 03

2

Philips Semiconductors	Product specification

9-bit analog-to-digital converter

TDA8761A

for digital video

ORDERING INFORMATION

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
TDA8761AM	SSOP28	plastic shrink small outline package; 28 leads; body width 5.3 mm	SOT341-1

BLOCK DIAGRAM

			VCCA		CLK	VCCD2	OE
			3		1	11	10
				CLOCK DRIVER				2		TC
						TDA8761A
	VRT	9
								25	D8	MSB
								24	D7
			RLAD					23	D6
								22	D5
analog	V I	8	ANALOG -TO - DIGITAL		LATCHES		CMOS	21	D4	data outputs
voltage input				CONVERTER			OUTPUTS	20	D3
	VRM	7						19	D2
								18	D1
								17	D0	LSB
	VRB	6						13	VCCO
								28	VCCD1
					IN RANGE LATCH			26		IR
						CMOS OUTPUT				output
			4	12	27	14
			AGND	DGND2	DGND1	OGND		MBG910

analog ground

output ground

digital grounds

Fig.1 Block diagram.

1998 Nov 03

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Philips Semiconductors	Product specification

9-bit analog-to-digital converter

TDA8761A

for digital video

PINNING

		SYMBOL			PIN	DESCRIPTION
	CLK				1	clock input
					2	two’s complement input (active LOW)
	TC
	VCCA				3	analog supply voltage (5 V)
		AGND			4	analog ground
		n.c.			5	not connected
		VRB			6	reference voltage BOTTOM input
		VRM			7	reference voltage MIDDLE
		VI			8	analog input voltage
		VRT			9	reference voltage TOP input
					10	output enable input (CMOS level
		OE
						input, active LOW)
	VCCD2				11	digital supply voltage 2 (5 V)
	DGND2				12	digital ground 2
	VCCO				13	supply voltage for output stages
						(3 to 5 V)
	OGND				14	output ground
	n.c.				15	not connected
	n.c.				16	not connected
	D0				17	data output; bit 0 (LSB)
	D1				18	data output; bit 1
	D2				19	data output; bit 2
	D3				20	data output; bit 3
	D4				21	data output; bit 4
	D5				22	data output; bit 5
	D6				23	data output; bit 6
	D7				24	data output; bit 7
	D8				25	data output; bit 8 (MSB)
	IR				26	in range data output
	DGND1				27	digital ground 1
	VCCD1				28	digital supply voltage 1 (5 V)

handbook, halfpage			1			VCCD1
CLK					28
			2
TC					27	DGND1
VCCA			3			IR
					26
			4
AGND					25	D8
			5
n.c.					24	D7
VRB			6
					23	D6
VRM			7
				TDA8761A	22	D5
	VI		8			D4
					21
VRT			9
					20	D3
						D2
	OE		10		19
VCCD2			11
					18	D1
			12
DGND2					17	D0
VCCO			13
					16	n.c.
OGND			14		15	n.c.
				MBG909

Fig.2 Pin configuration.

1998 Nov 03

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Philips Semiconductors	Product specification

9-bit analog-to-digital converter

TDA8761A

for digital video

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

SYMBOL	PARAMETER	CONDITIONS	MIN.	MAX.	UNIT
VCCA	analog supply voltage	note 1	−0.3	+7.0	V
VCCD	digital supply voltage	note 1	−0.3	+7.0	V
VCCO	output stages supply voltage	note 1	−0.3	+7.0	V
VCC	supply voltage differences
	between
	VCCA and VCCD		−1.0	+1.0	V
	VCCD and VCCO		−1.0	+4.0	V
	VCCA and VCCO		−1.0	+4.0	V
VI	input voltage	referenced to AGND	−0.3	+7.0	V
Vi(p-p)	AC input voltage for switching	referenced to DGND	−	VCCD	V
	(peak-to-peak value)
IO	output current		−	10	mA
Tstg	storage temperature		−55	+150	°C
Tamb	operating ambient temperature		0	+70	°C
Tj	junction temperature		−	+150	°C

Note

1. The supply voltages VCCA, VCCD and VCCO may have any value between −0.3 and +7.0 V provided that the supply voltage differences VCC are respected.

HANDLING

Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits.

THERMAL CHARACTERISTICS

SYMBOL	PARAMETER	CONDITIONS	VALUE	UNIT
Rth(j-a)	thermal resistance from junction to ambient	in free air	110	K/W

1998 Nov 03

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Philips Semiconductors	Product specification

9-bit analog-to-digital converter

TDA8761A

for digital video

CHARACTERISTICS

VCCA = V3 to V4 = 4.75 to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 to 5.25 V; VCCO = V13 to V14 = 3.0 to 5.25 V; AGND and DGND shorted together; Tamb = 0 to 70 °C; typical values measured at VCCA = VCCD = 5 V and

VCCO = 3.3 V; Vi(p-p) = 1.8 V; CL = 15 pF and Tamb = 25 °C; unless otherwise specified.

SYMBOL					PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Supplies
VCCA			analog supply voltage				4.75	5.0	5.25	V
VCCD			digital supply voltage				4.75	5.0	5.25	V
VCCO			output stages supply voltage				3.0	3.3	5.25	V
VCC			supply voltage differences
			between
			VCCA and VCCD				−0.2	−	+0.2	V
			VCCA and VCCO				−0.2	−	+2.25	V
			VCCD and VCCO				−0.2	−	+2.25	V
ICCA			analog supply current				−	18	24	mA
ICCD			digital supply current				−	13	18	mA
ICCO			output stages supply current			fclk = 30 MHz; ramp input	−	1	2	mA
Inputs
CLOCK INPUT CLK (REFERENCED TO DGND); note 1
VIL			LOW-level input voltage				0	−	0.8	V
VIH			HIGH-level input voltage				2	−	VCCD	V
IIL			LOW-level input current			Vclk = 0.8 V	−1	0	+1	μA
IIH			HIGH-level input current			Vclk = 2 V	−	2	10	μA
Zi			input impedance			fclk = 30 MHz	−	2	−	kΩ
Ci			input capacitance				−	2	−	pF
INPUTS			AND		(REFERENCED TO DGND); see Table 2
	OE			TC
VIL			LOW-level input voltage				0	−	0.8	V
VIH			HIGH-level input voltage				2	−	VCCD	V
IIL			LOW-level input current			VIL = 0.8 V	−1	−	−	μA
IIH			HIGH-level input current			VIH = 2.0 V	−	−	1	μA
VI (ANALOG INPUT VOLTAGE REFERENCED TO AGND)
IIL			LOW-level input current			VI = VRB = 1.3 V	−	17	−	μA
IIH			HIGH-level input current			VI = VRT = 3.43 V	−	35	−	μA
Zi			input impedance			fi = 10 MHz	−	8	−	kΩ
Ci			input capacitance				−	5	−	pF

1998 Nov 03

6

Philips Semiconductors	Product specification

9-bit analog-to-digital converter

TDA8761A

for digital video

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
Reference voltages for the resistor ladder; see Table 1
VRB	reference voltage BOTTOM		1.2	1.3	2.45	V
VRT	reference voltage TOP		3.2	3.43	VCCA − 0.8	V
Vdiff	differential reference voltage		2	2.13	3.0	V
	VRT − VRB
Iref	reference current	VRT − VRB = 2.13 V	−	8.7	−	mA
RLAD	resistor ladder		−	245	−	Ω
TCRLAD	temperature coefficient of the		−	1860	−	ppm
	resistor ladder		−	456	−	mΩ/K
VosB	offset voltage BOTTOM	note 2	−	160	−	mV
VosT	offset voltage TOP	note 2	−	160	−	mV
Vi(p-p)	analog input voltage	note 3	1.7	1.81	2.55	V
	(peak-to-peak value)
Outputs
DIGITAL OUTPUTS D8 TO D0 AND IR (REFERENCED TO OGND)
VOL	LOW-level output voltage	IOL = 1 mA	0	−	0.5	V
VOH	HIGH-level output voltage	IOH = −1 mA	VCCO − 0.5	−	VCCO	V
IOZ	output current in 3-state mode	0.5 V < VO < VCCO	−20	−	+20	μA
Switching characteristics
CLOCK INPUT CLK; see Fig.4; note 1
fclk(max)	maximum clock frequency		40	−	−	MHz
tCPH	clock pulse width HIGH		10	−	−	ns
tCPL	clock pulse width LOW		10	−	−	ns
Analog signal processing
LINEARITY
INL	integral non-linearity	fclk = 30 MHz; ramp input	−	±0.4	±1	LSB
AINL	AC integral non-linearity	full-scale input sine	−	±0.75	±0.9	LSB
		wave; note 4
		50% full-scale input sine	−	±0.5	±0.75	LSB
		wave; note 4
DNL	differential non-linearity	fclk = 30 MHz; ramp input	−	±0.3	±0.7	LSB
ADNL	AC differential non-linearity	full-scale input sine	−	±0.5	±0.75	LSB
		wave; note 4
		50% full-scale input sine	−	±0.3	±0.5	LSB
		wave; note 4
OFER	offset error	middle code;	−	±1	−	LSB
		VRB = 1.3 V;
		VRT = 3.43 V
GER	gain error (from	VRB = 1.3 V;	−	±0.1	−	%
	device to device)	VRT = 3.43 V; note 5

1998 Nov 03

7

Philips Semiconductors	Product specification

9-bit analog-to-digital converter

TDA8761A

for digital video

SYMBOL	PARAMETER	CONDITIONS	MIN.	TYP.	MAX.	UNIT
BANDWIDTH (fclk = 30 MHZ)
B	analog bandwidth	full-scale sine wave;	−	15	−	MHz
		note 6
		75% full-scale sine wave;	−	20	−	MHz
		note 6
		small signal at mid-scale;	−	350	−	MHz
		VI = ±10 LSB at
		code 256; note 6
tSTLH	analog input settling time	full-scale square wave;	−	1.5	3.0	ns
	LOW-to-HIGH	Fig.6; note 7
tSTHL	analog input settling time	full-scale square wave;	−	1.5	3.0	ns
	HIGH-to-LOW	Fig.6; note 7
HARMONICS (fclk = 30 MHZ); see Figs 7 and 8
THD	total harmonic distortion	fi = 10 MHz	−	−56	−	dB
SIGNAL-TO-NOISE RATIO; see Figs 7 and 8; note 8
SNR	signal-to-noise ratio (full scale)	without harmonics;	53	55	−	dB
		fclk = 30 MHz;
		fi = 10 MHz
EFFECTIVE BITS; see Figs 7 and 8; note 8
ENOB	effective bits	fclk = 30 MHz
		fi = 4.43 MHz	−	8.8	−	bits
		fi = 10 MHz	−	8.2	−	bits
TWO-TONE; note 9
TTIR	two-tone intermodulation	fclk = 30 MHz	−	−56	−	dB
	rejection
BIT ERROR RATE
BER	bit error rate	f = 30 MHz;	−	10−13	−	times/
		clk
		fi = 10 MHz;				sample
		VI = ±16 LSB at
		code 256
DIFFERENTIAL GAIN; note 10
Gdiff	differential gain	fclk = 30 MHz;	−	0.5	−	%
		PAL modulated ramp
DIFFERENTIAL PHASE; note 10
ϕdiff	differential phase	fclk = 30 MHz;	−	0.3	−	°C
		PAL modulated ramp

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