Philips SAA4998H Technical data

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SAA4998H

Field and line rate converter with noise reduction and embedded memory

Product speciﬁcation 2004 Feb 18

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise reduction and embedded memory

CONTENTS

1 FEATURES 2 GENERAL DESCRIPTION

2.1 Patent notice

2.2 Latch-up test 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAMS 6 PINNING 7 CONTROL REGISTER DESCRIPTION 8 LIMITING VALUES 9 THERMAL CHARACTERISTICS

SAA4998H

10 CHARACTERISTICS 11 PACKAGE OUTLINE 12 SOLDERING

12.1 Introduction to soldering surface mount packages

12.2 Reflow soldering

12.3 Wave soldering

12.4 Manual soldering

12.5 Suitability of surface mount IC packages for wave and reflow soldering methods

12.6 Additional soldering information

13 DATA SHEET STATUS 14 DEFINITIONS 15 DISCLAIMERS

2004 Feb 18 2

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise reduction and embedded memory

1 FEATURES

• Motion compensated framerateupconversion of all 1f film and video standards up to 292 active input lines per field:

– 50 Hz interlaced to 60 Hz progressive

{(60p mode for LCD and Plasma Display (PDP) TV}

– 50 Hz interlaced to 75 Hz interlaced

{75i mode for jumbo screens, Projection TV (PTV)}

– 50 Hz interlaced to 100 Hz interlaced

(high-end 100 Hz TV)

– 50 Hz interlaced to 50 Hz progressive

(progressive scan TV and LCD and PDP TV)

– 60 Hz interlaced to 60 Hz progressive

(progressive scan TV and LCD and PDP TV)

– 60 Hz interlaced to 90 Hz interlaced

(jumbo screens, PTV)

– 60 Hz interlaced to 120 Hz interlaced

(multistandard high-end 100 Hz TV)

• 480 active lines (NTSC like) or 506 active lines in 50 Hz interlaced to 60 Hz progressive mode

• Motion compensated and Edge Dependent De-Interlacing (EDDI)

• Motion estimated film mode detection

• Motion compensated movie judder cancellation:

– 25 Hz 2 : 2 pull-down (PAL) to 60 Hz progressive or

75 Hz interlaced or 100 Hz interlaced or 50 Hz progressive

– 30 Hz2 : 2pull-down(NTSC)to60 Hzprogressiveor

90 Hz interlaced or 120 Hz interlaced

– 24 Hz3 : 2pull-down(NTSC)to60 Hzprogressiveor

90 Hz interlaced or 120 Hz interlaced

• Variable vertical sharpness enhancement

• High quality vertical zoom

• Motion compensated temporal noise reduction with

after-imaging cancellation

• Split screen demonstration mode

• 2 Mbaud serial interface (SNERT)

• Embedded 2 × 2.9-Mbit DRAM

• Full 8-bit accuracy

• Memory buffer for Picture-In-Picture (PIP)

• Lead-free package.

(1)

SAA4998H

2 GENERAL DESCRIPTION

The SAA4998H is a high performance video processor

featuring Natural Motion (PAL, NTSC and SECAM). It is used together with the picture improvement processor SAA4978H and SAA4979H.

The SAA4998H is an advanced versionof the SAA4993H. By embedding the fieldmemories it reducesthe part count oftherealized concept from 4 to 6 parts to only 2 partsand reduces the package size from a QFP160 to a QFP100.

The full FALCONIC mode uses full motion estimation and motion compensation on1/4pixel accuracy to perform

• Frame rate upconversion

• Film mode detection

• Movie judder cancellation

• Dynamic Noise Reduction (DNR)

• Edge Dependent De-Interlacing (EDDI).

The motion compensated de-interlacer is improved with a new patented Edge Dependent De-Interlacing (EDDI) method. This avoids jagged edges of diagonal lines. The better de-interlacer leads to a significant better performance of progressive as well as interlaced output formats.

A 60 Hz progressive output frame rate can be generated for 50 Hz PAL sources to enable the use of 60 Hz LCD or PDP panels in PAL regions.

50 Hz interlaced to 75 Hz interlaced and 60 Hz interlaced to 90 Hz interlaced can be generated to achieve an increased number of lines and hence a reduction of line visibility for jumbo screens and PTV applications.

The embedded memory can be used to synchronize the main channel and the 2nd channel for PIP and double window applications. This avoids to add additional buffer memory devices to the application.

For demonstration purposes a split screen mode to show the Dynamic Noise Reduction (DNR) function, natural motion, and EDDI is available. The estimated motion vectors can be made visible by colour overlay mode.

The SAA4998H supports a Boundary Scan Test (BST) circuit in accordance with

(2)

, for all global TV standards

“IEEE Std. 1149.1”

(1) EDDI is protected with two patents of Koninklijke Philips

Electronics N.V.

2004 Feb 18 3

(2) Natural Motion is a trademark of Koninklijke Philips

Electronics N.V.

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

2.1 Patent notice

Notice is herewith given that the subject integrated circuit uses one or more of the following US patents and that each of these patents may have corresponding patents in other jurisdictions.

US 4740842, US 5929919, US 6034734, US 5534946, US 5532750, US 5495300, US 5903680, US 5365280, US 5148269, US 5072293, US 5771074, and US 5302909.

3 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V V V V V V I

DDD DDA DDM DDS DDE DDP

core supply voltage (internal rail) 1.65 1.8 1.95 V analog supply voltage ﬁeld memory supply voltage SRAM supply voltage external supply voltage (output pads) 3.0 3.3 3.6 V high supply voltage of internal ﬁeld memories sum of supply current

at 1.8 V supply voltage pins − 180 − mA at 3.3 V supply voltage pins − 6 − mA

CLK

amb

operating clock frequency − 32 33.3 MHz ambient temperature 0 − 70 °C

2.2 Latch-up test

Latch-up test in accordance with

“Latch-up Resistance

and Maximum Ratings Test; SNW-FQ-303

SAA4998H fulfils the requirements.

”; the

4 ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

SAA4998H QFP100 plastic quad ﬂat package; 100 leads (lead length 1.95 mm);

body 14 × 20 × 2.8 mm

SOT317-2

2004 Feb 18 4

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2004 Feb 18 5

5 BLOCK DIAGRAMS

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

YA0 to YA7

SNCL

SNDA

SNRST

ACV

RST

PIPON

TWOFMON

REA

REF

TCK

TDO

TDI

TMS

TRSTN

CLK32

55 to 62

94 41 34

SNERT

INTERFACE

25 32 36

CONTROL

63 64

31 30 29

BST/TEST

28 27

DYNAMIC

NOISE

REDUCTION

MPR

LEFT

FIELD MEMORY 2

COMPRESS

MUX

DE-INTERLACER

WITH EDDI

vectors

SPM TPM ESM

MOTION ESTIMATOR

vectors

UPCONVERSION

MEMORY CONTROL

DECOMPRESS

MPR

RIGHT

FIELD MEMORY 3

VERTICAL

PEAKING

68, 69,

71 to 76

VERTICAL

ZOOM

95, 100,

SAA4998H

LUMINANCE PART

1, 2,

5 to 8

YF7 to YF0

YG7 to YG0

Fig.1 Block diagram luminance part in full FALCONIC mode.

coc001

SAA4998H

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2004 Feb 18 6

FIELD MEMORY 2 FIELD MEMORY 3

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

UVA0 to UVA7

42 to 47, 53, 54

DECOMPRESS/

REFORMAT

DNR

MPR LEFT

COMPRESS/

FORMAT

UPCONVERSION

vectors

DECOMPRESS/

REFORMAT

MPR

RIGHT

VERTICAL

ZOOM

78 to 81,

88, 89,

FORMAT

92, 93

9 to 13,

17 to 19

SAA4998H

CHROMINANCE PART

coc002

UVF7 to UVF0

UVG7 to UVG0

SAA4998H

Fig.2 Block diagram chrominance part in full FALCONIC mode.

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise reduction and embedded memory

6 PINNING

SYMBOL PIN TYPE DESCRIPTION

YG5/DPIP5 1 output/input PIP mode disabled: bus G luminance output bit 5;

PIP mode enabled: PIP data input bit 5

YG4/DPIP4 2 output/input PIP mode disabled: bus G luminance output bit 4;

PIP mode enabled: PIP data input bit 4

DDE

SSE

YG3/DPIP3 5 output/input PIP mode disabled: bus G luminance output bit 3;

YG2/DPIP2 6 output/input PIP mode disabled: bus G luminance output bit 2;

YG1/DPIP1 7 output/input PIP mode disabled: bus G luminance output bit 1;

YG0/DPIP0 8 output/input PIP mode disabled: bus G luminance output bit 0 (LSB);

UVG7/QPIP7 9 output PIP mode disabled: bus G chrominance output bit 7 (MSB);

UVG6/QPIP6 10 output PIP mode disabled: bus G chrominance output bit 6;

UVG5/QPIP5 11 output PIP mode disabled: bus G chrominance output bit 5;

UVG4/QPIP4 12 output PIP mode disabled: bus G chrominance output bit 4;

UVG3/QPIP3 13 output PIP mode disabled: bus G chrominance output bit 3;

n.c./LLC 14 input PIP mode disabled: not connected;

SSE

n.c./SWCK2 16 input PIP mode disabled: not connected;

UVG2/QPIP2 17 output PIP mode disabled: bus G chrominance output bit 2;

UVG1/QPIP1 18 output PIP mode disabled: bus G chrominance output bit 1;

UVG0/QPIP0 19 output PIP mode disabled: bus G chrominance output bit 0 (LSB);

n.c./RSTW2 20 input PIP mode disabled: not connected;

n.c./OIE2 21 input PIP mode disabled: not connected;

n.c./IE2 22 input PIP mode disabled: not connected;

DDP

n.c./WE2 24 input PIP mode disabled: not connected;

3 supply supply voltage of output pads (3.3 V) 4 ground ground of output pads

PIP mode enabled: PIP data input bit 3

PIP mode enabled: PIP data input bit 2

PIP mode enabled: PIP data input bit 1

PIP mode enabled: PIP data input bit 0 (LSB)

PIP mode enabled: PIP data output bit 7 (MSB)

PIP mode enabled: PIP data output bit 6

PIP mode enabled: PIP data output bit 5

PIP mode enabled: PIP data output bit 4

PIP mode enabled: PIP data output bit 3

PIP mode enabled: line locked clock signal for PIP mode

15 ground ground of output pads

PIP mode enabled: serial write clock for PIP memory

PIP mode enabled: PIP data output bit 2

PIP mode enabled: PIP data output bit 1

PIP mode enabled: PIP data output bit 0 (LSB)

PIP mode enabled: write reset clock for PIP memory

PIP mode enabled: output enable for PIP memory output QPIPx

PIP mode enabled: input enable for PIP memory

23 supply high supply voltage of the internal ﬁeld memories (3.3 V)

PIP mode enabled: write enable for PIP memory

(1)(2)(3)

SAA4998H

2004 Feb 18 7

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

SYMBOL PIN TYPE DESCRIPTION

ACV/RE2 25 output/input PIP mode disabled: active video output;

PIP mode enabled: read enable for PIP memory

n.c./RSTR2 26 input PIP mode disabled: not connected;

PIP mode enabled: read reset for PIP memory TRSTN 27 input boundary scan test reset input (active LOW); with internal pull-up resistor TMS 28 input boundary scan test mode select input; with internal pull-up resistor TDI 29 input boundary scan test data input; with internal pull-up resistor TDO 30 3-state boundary scan test data output TCK 31 input boundary scan test clock input; with internal pull-up resistor RST 32 input reset input; see Fig.4 SNRST 33 input SNERT bus reset input; with internal pull-down resistor SNDA 34 input/output SNERT bus data input and output; with internal pull-down resistor V

DDE

35 supply supply voltage of output pads (3.3 V) PIPON 36 input PIP mode enable input V V V V

SSM DDM SSM DDM

37 ground ﬁeld memory ground

38 supply supply voltage of the internal ﬁeld memories (1.8 V)

39 ground ﬁeld memory ground

40 supply supply voltage of the internal ﬁeld memories (1.8 V) SNCL 41 input SNERT bus clock input; with internal pull-down resistor UVA0 42 input bus A chrominance input bit 0 (LSB) UVA1 43 input bus A chrominance input bit 1 UVA2 44 input bus A chrominance input bit 2 UVA3 45 input bus A chrominance input bit 3 UVA4 46 input bus A chrominance input bit 4 UVA5 47 input bus A chrominance input bit 5 V V

DDD SSD

48 supply core supply voltage (1.8 V)

49 ground core ground TWOFMON 50 input to be connected to ground V V

DDS SSS

51 supply supply voltage of the internal SRAMs (1.8 V)

52 ground ground of the internal SRAMs UVA6 53 input bus A chrominance input bit 6 UVA7 54 input bus A chrominance input bit 7 (MSB) YA0 55 input bus A luminance input bit 0 (LSB) YA1 56 input bus A luminance input bit 1 YA2 57 input bus A luminance input bit 2 YA3 58 input bus A luminance input bit 3 YA4 59 input bus A luminance input bit 4 YA5 60 input bus A luminance input bit 5 YA6 61 input bus A luminance input bit 6 YA7 62 input bus A luminance input bit 7 (MSB) REA 63 output read enable output for bus A

(1)(2)(3)

2004 Feb 18 8

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

SYMBOL PIN TYPE DESCRIPTION

IE 64 input input enable for PIP mode V V

DDD SSD

65 supply core supply voltage (1.8 V)

66 ground core ground REF 67 input read enable input for bus F and G; note 4 YF7 68 output bus F luminance output bit 7 (MSB) YF6 69 output bus F luminance output bit 6 V

SSE

70 ground ground of output pads YF5 71 output bus F luminance output bit 5 YF4 72 output bus F luminance output bit 4 YF3 73 output bus F luminance output bit 3 YF2 74 output bus F luminance output bit 2 YF1 75 output bus F luminance output bit 1 YF0 76 output bus F luminance output bit 0 (LSB) V

DDE

77 supply supply voltage of output pads (3.3 V) UVF7 78 output bus F chrominance output bit 7 (MSB) UVF6 79 output bus F chrominance output bit 6 UVF5 80 output bus F chrominance output bit 5 UVF4 81 output bus F chrominance output bit 4 V

SSE

82 ground ground of output pads CLK32 83 input system clock input (32 MHz) V V V V

DDS SSS DDD SSD

84 supply supply voltage of the internal SRAMs (1.8 V)

85 ground ground of the internal SRAMs

86 supply core supply voltage (1.8 V)

87 ground core ground UVF3 88 output bus F chrominance output bit 3 UVF2 89 output bus F chrominance output bit 2 V V

SSA DDA

90 ground analog ground of the internal PLL

91 supply analog supply voltage of the internal PLL (1.8 V) UVF1 92 output bus F chrominance output bit 1 UVF0 93 output bus F chrominance output bit 0 (LSB) VD 94 input vertical display synchronization input (reset for ﬁeld memories) YG7/DPIP7 95 output/input PIP mode disabled: bus G luminance output bit 7 (MSB);

PIP mode enabled: PIP data input bit 7 (MSB) V V

DDM SSM

96 supply supply voltage of the internal ﬁeld memories (1.8 V) 97 ground ﬁeld memory ground

(1)(2)(3)

2004 Feb 18 9

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise reduction and embedded memory

SYMBOL PIN TYPE DESCRIPTION

V V

DDM SSM

98 supply supply voltage of the internal ﬁeld memories (1.8 V) 99 ground ﬁeld memory ground

YG6/DPIP6 100 output/input PIP mode disabled: bus G luminance output bit 6;

PIP mode enabled: PIP data input bit 6

Notes

1. Not used input pins should be connected to ground.

2. Because of the noisy characteristic of the supply voltage of output pads (V V

directly at the high supply voltageof the intern field memories (V

DDE

as possible to the device. V separated from V

by an external filter structure. Because of the high working frequency of the device, it is also

DDE

recommended to filter the core supply voltage (V

needs a low noise supply voltage, therefore, it is recommended that V

DDP

). All pins V

DDD

). All pins V

DDP

should be buffered as close as possible to the

device.

3. V

SSD

, V

SSM

and V

are connected internally.

SSS

4. REF rising edge must be after rising edge of SNRST in order to be detected.

(1)(2)(3)

), it is recommended not to connect

DDE

SAA4998H

should be buffered as close

has to be

DDP

2004 Feb 18 10

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise reduction and embedded memory

SSMVDDMVSSMVDDM

YG6/DPIP6

YG5/DPIP5 YG4/DPIP4

DDE

SSE

YG3/DPIP3 YG2/DPIP2 YG1/DPIP1

YG0/DPIP0 UVG7/QPIP7 UVG6/QPIP6 UVG5/QPIP5 UVG4/QPIP4 UVG3/QPIP3

n.c./LLC

SSE

n.c./SWCK2 UVG2/QPIP2 UVG1/QPIP1 UVG0/QPIP0

n.c./RSTW2

n.c./OIE2

n.c./IE2

DDP

n.c./WE2

ACV/RE2

n.c./RSTR2

TRSTN

TMS

TDI

TDO

99989796959493929190898887

100

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

YG7/DPIP7VDUVF0

SAA4998H

UVF1

DDAVSSA

UVF2

UVF3

SSDVDDDVSSSVDDS

8685848382

SSE

CLK32

UVF4 81

SAA4998H

UVF5

80 79

UVF6

UVF7 V

DDE

YF0

YF1

YF2

YF3

YF4

YF5 V

SSE

YF6

YF7

REF V

SSD

DDD

REA

YA7

YA6

YA5

YA4

YA3

YA2

YA1

YA0

UVA7

UVA6 V

SSS

DDS

31323334353637383940414243

DDE

SSM

TCK

RST

SNDA

SNRST

PIPON

DDM

Fig.3 Pin configuration.

2004 Feb 18 11

DDM

SNCL

UVA0

UVA1

UVA2

4546474849

DDD

UVA4

UVA5

UVA3

SSD

TWOFMON

001aaa057

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2004 Feb 18 12

7 CONTROL REGISTER DESCRIPTION

SNERT

NAME

DNR/peaking/colour Kstep10 010 write; S

Kstep0 XXXXset LUT value: k =1⁄16 if difference below (0to15) Kstep1 X X X X set LUT value: k =1⁄8 if difference below (0to15)

Kstep32 011 write; S

Kstep2 XXXXset LUT value: k =2⁄8 if difference below (0 to 30 in multiples of 2) Kstep3 X X X X set LUT value: k =3⁄8 if difference below (0 to 30 in multiples of 2)

Kstep54 012 write; S

Kstep4 XXXXset LUT value: k =4⁄8 if difference below (0 to 60 in multiples of 4) Kstep5 X X X X set LUT value: k =5⁄8 if difference below (0 to 60 in multiples of 4)

Kstep76 013 write; S

Kstep6 XXXXset LUT value: k =6⁄8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,

Kstep7 X X X X set LUT value: k =7⁄8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,

Gain_ﬁx_y 014 write; S

FixvalY XXXXset ﬁxed Y value; used when FixY = 1 or in left part of split screen

GainY X X X set gain in difference signal for adaptive DNRY (1⁄8,1⁄4,1⁄2, 1, 2 or 4) FixY X select ﬁxed Y (adaptive or ﬁxed) (full screen)

Gain_ﬁx_uv 015 write; S

FixvalUV XXXXset ﬁxed UV value; used when FixUV = 1 or in left part of split screen

GainUV X X X set gain in difference signal for adaptive DNR UV (1⁄8,1⁄4,1⁄2, 1, 2 or 4) FixUV X select ﬁxed UV (adaptive or ﬁxed) (full screen)

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

64, 72, 80, 88, 96, 104, 112 or 120)

(0,1⁄16to14⁄16or16⁄16)

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

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