Philips SAA4998H Technical data

INTEGRATED CIRCUITS

DATA SHEET

SAA4998H

Field and line rate converter with noise reduction and embedded memory

Product specification			2004 Feb 18

Philips Semiconductors	Product specification

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

CONTENTS

1FEATURES

2GENERAL DESCRIPTION

2.1Patent notice

2.2Latch-up test

3QUICK REFERENCE DATA

4ORDERING INFORMATION

5BLOCK DIAGRAMS

6PINNING

7CONTROL REGISTER DESCRIPTION

8LIMITING VALUES

9THERMAL CHARACTERISTICS

10CHARACTERISTICS

11PACKAGE OUTLINE

12SOLDERING

12.1Introduction to soldering surface mount packages

12.2Reflow soldering

12.3Wave soldering

12.4Manual soldering

12.5Suitability of surface mount IC packages for wave and reflow soldering methods

12.6Additional soldering information

13DATA SHEET STATUS

14DEFINITIONS

15DISCLAIMERS

2004 Feb 18

2

Philips Semiconductors	Product specification

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

1 FEATURES

·Motion compensated frame rate upconversion of all 1fH film and video standards up to 292 active input lines per field:

–50 Hz interlaced to 60 Hz progressive

{(60p mode for LCD and Plasma Display (PDP) TV}

–50 Hz interlaced to 75 Hz interlaced

{75i mode for jumbo screens, Projection TV (PTV)}

–50 Hz interlaced to 100 Hz interlaced (high-end 100 Hz TV)

–50 Hz interlaced to 50 Hz progressive (progressive scan TV and LCD and PDP TV)

–60 Hz interlaced to 60 Hz progressive (progressive scan TV and LCD and PDP TV)

–60 Hz interlaced to 90 Hz interlaced (jumbo screens, PTV)

–60 Hz interlaced to 120 Hz interlaced (multistandard high-end 100 Hz TV)

·480 active lines (NTSC like) or 506 active lines in 50 Hz interlaced to 60 Hz progressive mode

·Motion compensated and Edge Dependent De-Interlacing (EDDI)(1)

·Motion estimated film mode detection

·Motion compensated movie judder cancellation:

–25 Hz 2 : 2 pull-down (PAL) to 60 Hz progressive or 75 Hz interlaced or 100 Hz interlaced or 50 Hz progressive

–30 Hz 2 : 2 pull-down (NTSC) to 60 Hz progressive or 90 Hz interlaced or 120 Hz interlaced

–24 Hz 3 : 2 pull-down (NTSC) to 60 Hz progressive or 90 Hz interlaced or 120 Hz interlaced

·Variable vertical sharpness enhancement

·High quality vertical zoom

·Motion compensated temporal noise reduction with after-imaging cancellation

·Split screen demonstration mode

·2 Mbaud serial interface (SNERT)

·Embedded 2 ´ 2.9-Mbit DRAM

·Full 8-bit accuracy

·Memory buffer for Picture-In-Picture (PIP)

·Lead-free package.

2 GENERAL DESCRIPTION

The SAA4998H is a high performance video processor featuring Natural Motionä(2), for all global TV standards (PAL, NTSC and SECAM). It is used together with the picture improvement processor SAA4978H and SAA4979H.

The SAA4998H is an advanced version of the SAA4993H. By embedding the field memories it reduces the part count of the realized concept from 4 to 6 parts to only 2 parts and reduces the package size from a QFP160 to a QFP100.

The full FALCONIC mode uses full motion estimation and motion compensation on 1/4 pixel accuracy to perform

·Frame rate upconversion

·Film mode detection

·Movie judder cancellation

·Dynamic Noise Reduction (DNR)

·Edge Dependent De-Interlacing (EDDI).

The motion compensated de-interlacer is improved with a new patented Edge Dependent De-Interlacing (EDDI) method. This avoids jagged edges of diagonal lines. The better de-interlacer leads to a significant better performance of progressive as well as interlaced output formats.

A 60 Hz progressive output frame rate can be generated for 50 Hz PAL sources to enable the use of 60 Hz LCD or PDP panels in PAL regions.

50 Hz interlaced to 75 Hz interlaced and 60 Hz interlaced to 90 Hz interlaced can be generated to achieve an increased number of lines and hence a reduction of line visibility for jumbo screens and PTV applications.

The embedded memory can be used to synchronize the main channel and the 2nd channel for PIP and double window applications. This avoids to add additional buffer memory devices to the application.

For demonstration purposes a split screen mode to show the Dynamic Noise Reduction (DNR) function, natural motion, and EDDI is available. The estimated motion vectors can be made visible by colour overlay mode.

The SAA4998H supports a Boundary Scan Test (BST) circuit in accordance with “IEEE Std. 1149.1”.

(1) EDDI is protected with two patents of Koninklijke Philips	(2) Natural Motion is a trademark of Koninklijke Philips
Electronics N.V.	Electronics N.V.

2004 Feb 18

3

Philips Semiconductors	Product specification

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

2.1Patent notice

Notice is herewith given that the subject integrated circuit uses one or more of the following US patents and that each of these patents may have corresponding patents in other jurisdictions.

US 4740842, US 5929919, US 6034734, US 5534946, US 5532750, US 5495300, US 5903680, US 5365280, US 5148269, US 5072293, US 5771074, and

US 5302909.

3 QUICK REFERENCE DATA

2.2Latch-up test

Latch-up test in accordance with “Latch-up Resistance and Maximum Ratings Test; SNW-FQ-303”; the SAA4998H fulfils the requirements.

SYMBOL	PARAMETER	MIN.	TYP.	MAX.	UNIT
VDDD	core supply voltage (internal rail)	1.65	1.8	1.95	V
VDDA	analog supply voltage
VDDM	field memory supply voltage
VDDS	SRAM supply voltage
VDDE	external supply voltage (output pads)	3.0	3.3	3.6	V
VDDP	high supply voltage of internal field memories
IDD	sum of supply current
	at 1.8 V supply voltage pins	−	180	−	mA
	at 3.3 V supply voltage pins	−	6	−	mA
fCLK	operating clock frequency	−	32	33.3	MHz
Tamb	ambient temperature	0	−	70	°C

4 ORDERING INFORMATION

TYPE		PACKAGE
NUMBER	NAME	DESCRIPTION	VERSION
SAA4998H	QFP100	plastic quad flat package; 100 leads (lead length 1.95 mm);	SOT317-2
		body 14 × 20 × 2.8 mm

2004 Feb 18

4

	_
18 Feb 2004											BLOCK 5
	55 to 62		DYNAMIC	FIELD MEMORY 2			MEMORY CONTROL	FIELD MEMORY 3			DIAGRAMS
	YA0 to YA7		NOISE
		REDUCTION
	94
	VD
	41
	SNCL
	34	SNERT
	SNDA	INTERFACE
	33			COMPRESS		DECOMPRESS
	SNRST
	25
	ACV
	32			MUX	MUX
	RST
	36
	PIPON
	50	CONTROL
	TWOFMON			DE-INTERLACER
	63
					WITH EDDI
5	REA									68, 69,
	64
										71 to 76
	IE				vectors						YF7 to YF0
	67
	REF		MPR					VERTICAL	VERTICAL	95, 100,
							MPR
			LEFT	SPM	TPM	ESM	RIGHT	PEAKING	ZOOM	1, 2,
										5 to 8
	31										YG7 to YG0
	TCK			MOTION ESTIMATOR
	30
	TDO				vectors
	29	BST/TEST
	TDI
	28
	TMS			UPCONVERSION					SAA4998H
	27
	TRSTN								LUMINANCE PART
	83
	CLK32
										coc001

Fig.1 Block diagram luminance part in full FALCONIC mode.

reduction	and Field
memory embedded and	noise with converter rate line

SAA4998H

Semiconductors Philips

specification Product

_

18 Feb 2004

FIELD MEMORY 2

FIELD MEMORY 3

COMPRESS/

DECOMPRESS/

FORMAT

REFORMAT

42 to 47,

53, 54

DECOMPRESS/

UVA0 to UVA7

REFORMAT

DNR

6		vectors

MPR

MPR

78 to 81,

LEFT

RIGHT

88, 89,

UPCONVERSION

VERTICAL

FORMAT

92, 93

UVF7 to UVF0

9 to 13,

ZOOM

17 to 19

UVG7 to UVG0

SAA4998H

CHROMINANCE PART

coc002

Fig.2 Block diagram chrominance part in full FALCONIC mode.

reduction	and Field
memory embedded and	noise with converter rate line

SAA4998H

Semiconductors Philips

specification Product

Philips Semiconductors	Product specification

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

6 PINNING

SYMBOL	PIN	TYPE	DESCRIPTION(1)(2)(3)
YG5/DPIP5	1	output/input	PIP mode disabled: bus G luminance output bit 5;
			PIP mode enabled: PIP data input bit 5
YG4/DPIP4	2	output/input	PIP mode disabled: bus G luminance output bit 4;
			PIP mode enabled: PIP data input bit 4
VDDE	3	supply	supply voltage of output pads (3.3 V)
VSSE	4	ground	ground of output pads
YG3/DPIP3	5	output/input	PIP mode disabled: bus G luminance output bit 3;
			PIP mode enabled: PIP data input bit 3
YG2/DPIP2	6	output/input	PIP mode disabled: bus G luminance output bit 2;
			PIP mode enabled: PIP data input bit 2
YG1/DPIP1	7	output/input	PIP mode disabled: bus G luminance output bit 1;
			PIP mode enabled: PIP data input bit 1
YG0/DPIP0	8	output/input	PIP mode disabled: bus G luminance output bit 0 (LSB);
			PIP mode enabled: PIP data input bit 0 (LSB)
UVG7/QPIP7	9	output	PIP mode disabled: bus G chrominance output bit 7 (MSB);
			PIP mode enabled: PIP data output bit 7 (MSB)
UVG6/QPIP6	10	output	PIP mode disabled: bus G chrominance output bit 6;
			PIP mode enabled: PIP data output bit 6
UVG5/QPIP5	11	output	PIP mode disabled: bus G chrominance output bit 5;
			PIP mode enabled: PIP data output bit 5
UVG4/QPIP4	12	output	PIP mode disabled: bus G chrominance output bit 4;
			PIP mode enabled: PIP data output bit 4
UVG3/QPIP3	13	output	PIP mode disabled: bus G chrominance output bit 3;
			PIP mode enabled: PIP data output bit 3
n.c./LLC	14	input	PIP mode disabled: not connected;
			PIP mode enabled: line locked clock signal for PIP mode
VSSE	15	ground	ground of output pads
n.c./SWCK2	16	input	PIP mode disabled: not connected;
			PIP mode enabled: serial write clock for PIP memory
UVG2/QPIP2	17	output	PIP mode disabled: bus G chrominance output bit 2;
			PIP mode enabled: PIP data output bit 2
UVG1/QPIP1	18	output	PIP mode disabled: bus G chrominance output bit 1;
			PIP mode enabled: PIP data output bit 1
UVG0/QPIP0	19	output	PIP mode disabled: bus G chrominance output bit 0 (LSB);
			PIP mode enabled: PIP data output bit 0 (LSB)
n.c./RSTW2	20	input	PIP mode disabled: not connected;
			PIP mode enabled: write reset clock for PIP memory
n.c./OIE2	21	input	PIP mode disabled: not connected;
			PIP mode enabled: output enable for PIP memory output QPIPx
n.c./IE2	22	input	PIP mode disabled: not connected;
			PIP mode enabled: input enable for PIP memory
VDDP	23	supply	high supply voltage of the internal field memories (3.3 V)
n.c./WE2	24	input	PIP mode disabled: not connected;
			PIP mode enabled: write enable for PIP memory

2004 Feb 18

7

Philips Semiconductors	Product specification

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

SYMBOL	PIN	TYPE	DESCRIPTION(1)(2)(3)
ACV/RE2	25	output/input	PIP mode disabled: active video output;
			PIP mode enabled: read enable for PIP memory
n.c./RSTR2	26	input	PIP mode disabled: not connected;
			PIP mode enabled: read reset for PIP memory
TRSTN	27	input	boundary scan test reset input (active LOW); with internal pull-up resistor
TMS	28	input	boundary scan test mode select input; with internal pull-up resistor
TDI	29	input	boundary scan test data input; with internal pull-up resistor
TDO	30	3-state	boundary scan test data output
TCK	31	input	boundary scan test clock input; with internal pull-up resistor
RST	32	input	reset input; see Fig.4
SNRST	33	input	SNERT bus reset input; with internal pull-down resistor
SNDA	34	input/output	SNERT bus data input and output; with internal pull-down resistor
VDDE	35	supply	supply voltage of output pads (3.3 V)
PIPON	36	input	PIP mode enable input
VSSM	37	ground	field memory ground
VDDM	38	supply	supply voltage of the internal field memories (1.8 V)
VSSM	39	ground	field memory ground
VDDM	40	supply	supply voltage of the internal field memories (1.8 V)
SNCL	41	input	SNERT bus clock input; with internal pull-down resistor
UVA0	42	input	bus A chrominance input bit 0 (LSB)
UVA1	43	input	bus A chrominance input bit 1
UVA2	44	input	bus A chrominance input bit 2
UVA3	45	input	bus A chrominance input bit 3
UVA4	46	input	bus A chrominance input bit 4
UVA5	47	input	bus A chrominance input bit 5
VDDD	48	supply	core supply voltage (1.8 V)
VSSD	49	ground	core ground
TWOFMON	50	input	to be connected to ground
VDDS	51	supply	supply voltage of the internal SRAMs (1.8 V)
VSSS	52	ground	ground of the internal SRAMs
UVA6	53	input	bus A chrominance input bit 6
UVA7	54	input	bus A chrominance input bit 7 (MSB)
YA0	55	input	bus A luminance input bit 0 (LSB)
YA1	56	input	bus A luminance input bit 1
YA2	57	input	bus A luminance input bit 2
YA3	58	input	bus A luminance input bit 3
YA4	59	input	bus A luminance input bit 4
YA5	60	input	bus A luminance input bit 5
YA6	61	input	bus A luminance input bit 6
YA7	62	input	bus A luminance input bit 7 (MSB)
REA	63	output	read enable output for bus A

2004 Feb 18

8

Philips Semiconductors	Product specification

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

SYMBOL	PIN	TYPE	DESCRIPTION(1)(2)(3)
IE	64	input	input enable for PIP mode
VDDD	65	supply	core supply voltage (1.8 V)
VSSD	66	ground	core ground
REF	67	input	read enable input for bus F and G; note 4
YF7	68	output	bus F luminance output bit 7 (MSB)
YF6	69	output	bus F luminance output bit 6
VSSE	70	ground	ground of output pads
YF5	71	output	bus F luminance output bit 5
YF4	72	output	bus F luminance output bit 4
YF3	73	output	bus F luminance output bit 3
YF2	74	output	bus F luminance output bit 2
YF1	75	output	bus F luminance output bit 1
YF0	76	output	bus F luminance output bit 0 (LSB)
VDDE	77	supply	supply voltage of output pads (3.3 V)
UVF7	78	output	bus F chrominance output bit 7 (MSB)
UVF6	79	output	bus F chrominance output bit 6
UVF5	80	output	bus F chrominance output bit 5
UVF4	81	output	bus F chrominance output bit 4
VSSE	82	ground	ground of output pads
CLK32	83	input	system clock input (32 MHz)
VDDS	84	supply	supply voltage of the internal SRAMs (1.8 V)
VSSS	85	ground	ground of the internal SRAMs
VDDD	86	supply	core supply voltage (1.8 V)
VSSD	87	ground	core ground
UVF3	88	output	bus F chrominance output bit 3
UVF2	89	output	bus F chrominance output bit 2
VSSA	90	ground	analog ground of the internal PLL
VDDA	91	supply	analog supply voltage of the internal PLL (1.8 V)
UVF1	92	output	bus F chrominance output bit 1
UVF0	93	output	bus F chrominance output bit 0 (LSB)
VD	94	input	vertical display synchronization input (reset for field memories)
YG7/DPIP7	95	output/input	PIP mode disabled: bus G luminance output bit 7 (MSB);
			PIP mode enabled: PIP data input bit 7 (MSB)
VDDM	96	supply	supply voltage of the internal field memories (1.8 V)
VSSM	97	ground	field memory ground

2004 Feb 18

9

Philips Semiconductors	Product specification

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

SYMBOL	PIN	TYPE	DESCRIPTION(1)(2)(3)
VDDM	98	supply	supply voltage of the internal field memories (1.8 V)
VSSM	99	ground	field memory ground
YG6/DPIP6	100	output/input	PIP mode disabled: bus G luminance output bit 6;
			PIP mode enabled: PIP data input bit 6
Notes

1.Not used input pins should be connected to ground.

2.Because of the noisy characteristic of the supply voltage of output pads (VDDE), it is recommended not to connect VDDE directly at the high supply voltage of the intern field memories (VDDP). All pins VDDE should be buffered as close as possible to the device. VDDP needs a low noise supply voltage, therefore, it is recommended that VDDP has to be separated from VDDE by an external filter structure. Because of the high working frequency of the device, it is also recommended to filter the core supply voltage (VDDD). All pins VDDD should be buffered as close as possible to the device.

3.VSSD, VSSM and VSSS are connected internally.

4.REF rising edge must be after rising edge of SNRST in order to be detected.

2004 Feb 18

10

Philips Semiconductors	Product specification

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

YG5/DPIP5 1 YG4/DPIP4 2 VDDE 3

VSSE 4

YG3/DPIP3 5 YG2/DPIP2 6 YG1/DPIP1 7 YG0/DPIP0 8 UVG7/QPIP7 9 UVG6/QPIP6 10 UVG5/QPIP5 11 UVG4/QPIP4 12 UVG3/QPIP3 13 n.c./LLC 14

VSSE 15

n.c./SWCK2 16 UVG2/QPIP2 17 UVG1/QPIP1 18 UVG0/QPIP0 19 n.c./RSTW2 20 n.c./OIE2 21 n.c./IE2 22

VDDP 23

n.c./WE2 24 ACV/RE2 25

n.c./RSTR2 26

TRSTN 27

TMS 28

TDI 29

TDO 30

YG6/DPIP6

V

V

V

V

YG7/DPIP7

VD

UVF0

UVF1

V

V

UVF2

UVF3

V

V

V

V

CLK32

V

UVF4

SSM

DDM

SSM

DDM

DDA

SSA

SSD

DDD

SSS

DDS

SSE

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

SAA4998H

31		32		33		34		35		36		37		38		39		40		41		42		43		44		45		46		47		48		49		50
TCK		RST		SNRST		SNDA		V		PIPON		V		V		V		V		SNCL		UVA0		UVA1		UVA2		UVA3		UVA4		UVA5		V		V		TWOFMON
								DDE				SSM		DDM		SSM		DDM																DDD		SSD

80	UVF5
79	UVF6
78	UVF7
	VDDE
77
76	YF0
75	YF1
74	YF2
73	YF3
72	YF4
71	YF5
	VSSE
70
69	YF6
68	YF7
67	REF
	VSSD
66
	VDDD
65
64	IE
63	REA
62	YA7
61	YA6
60	YA5
59	YA4
58	YA3
57	YA2
56	YA1
55	YA0
54	UVA7
53	UVA6
	VSSS
52
51	VDDS

001aaa057

Fig.3 Pin configuration.

2004 Feb 18

11

18 Feb 2004

12

_

7 CONTROL REGISTER DESCRIPTION

SNERT

READ/

NAME

ADDRESS

7

6

5

4

3

2

1

0

DESCRIPTION(2)

WRITE(1)

(HEX)

DNR/peaking/colour

Kstep10

010

write; S

Kstep0

X

X

X

X

set LUT value: k = 1¤16 if difference below (0 to 15)

Kstep1

X

X

X

X

set LUT value: k = 1¤8 if difference below (0 to 15)

Kstep32

011

write; S

Kstep2

X

X

X

X

set LUT value: k = 2¤8 if difference below (0 to 30 in multiples of 2)

Kstep3

X

X

X

X

set LUT value: k = 3¤8 if difference below (0 to 30 in multiples of 2)

Kstep54

012

write; S

Kstep4

X

X

X

X

set LUT value: k = 4¤8 if difference below (0 to 60 in multiples of 4)

Kstep5

X

X

X

X

set LUT value: k = 5¤8 if difference below (0 to 60 in multiples of 4)

Kstep76

013

write; S

Kstep6

X

X

X

X

set LUT value: k = 6¤8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,

64, 72, 80, 88, 96, 104, 112 or 120)

Kstep7

X

X

X

X

set LUT value: k = 7¤8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,

64, 72, 80, 88, 96, 104, 112 or 120)

Gain_fix_y

014

write; S

FixvalY

X

X

X

X

set fixed Y value; used when FixY = 1 or in left part of split screen

(0, 1¤16 to 14¤16 or 16¤16)

GainY

X

X

X

set gain in difference signal for adaptive DNR Y (1¤8, 1¤4, 1¤2, 1, 2 or 4)

FixY

X

select fixed Y (adaptive or fixed ) (full screen)

Gain_fix_uv

015

write; S

FixvalUV

X

X

X

X

set fixed UV value; used when FixUV = 1 or in left part of split screen

(0, 1¤16 to 14¤16 or 16¤16)

GainUV

X

X

X

set gain in difference signal for adaptive DNR UV (1¤8, 1¤4, 1¤2, 1, 2 or 4)

FixUV

X

select fixed UV (adaptive or fixed ) (full screen)

reduction	and Field
memory embedded and	noise with converter rate line

SAA4998H

Semiconductors Philips

specification Product