Philips SAA4998H Technical data

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SAA4998H

Field and line rate converter with noise reduction and embedded memory

Product speciﬁcation 2004 Feb 18

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise reduction and embedded memory

CONTENTS

1 FEATURES 2 GENERAL DESCRIPTION

2.1 Patent notice

2.2 Latch-up test 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAMS 6 PINNING 7 CONTROL REGISTER DESCRIPTION 8 LIMITING VALUES 9 THERMAL CHARACTERISTICS

SAA4998H

10 CHARACTERISTICS 11 PACKAGE OUTLINE 12 SOLDERING

12.1 Introduction to soldering surface mount packages

12.2 Reflow soldering

12.3 Wave soldering

12.4 Manual soldering

12.5 Suitability of surface mount IC packages for wave and reflow soldering methods

12.6 Additional soldering information

13 DATA SHEET STATUS 14 DEFINITIONS 15 DISCLAIMERS

2004 Feb 18 2

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise reduction and embedded memory

1 FEATURES

• Motion compensated framerateupconversion of all 1f film and video standards up to 292 active input lines per field:

– 50 Hz interlaced to 60 Hz progressive

{(60p mode for LCD and Plasma Display (PDP) TV}

– 50 Hz interlaced to 75 Hz interlaced

{75i mode for jumbo screens, Projection TV (PTV)}

– 50 Hz interlaced to 100 Hz interlaced

(high-end 100 Hz TV)

– 50 Hz interlaced to 50 Hz progressive

(progressive scan TV and LCD and PDP TV)

– 60 Hz interlaced to 60 Hz progressive

(progressive scan TV and LCD and PDP TV)

– 60 Hz interlaced to 90 Hz interlaced

(jumbo screens, PTV)

– 60 Hz interlaced to 120 Hz interlaced

(multistandard high-end 100 Hz TV)

• 480 active lines (NTSC like) or 506 active lines in 50 Hz interlaced to 60 Hz progressive mode

• Motion compensated and Edge Dependent De-Interlacing (EDDI)

• Motion estimated film mode detection

• Motion compensated movie judder cancellation:

– 25 Hz 2 : 2 pull-down (PAL) to 60 Hz progressive or

75 Hz interlaced or 100 Hz interlaced or 50 Hz progressive

– 30 Hz2 : 2pull-down(NTSC)to60 Hzprogressiveor

90 Hz interlaced or 120 Hz interlaced

– 24 Hz3 : 2pull-down(NTSC)to60 Hzprogressiveor

90 Hz interlaced or 120 Hz interlaced

• Variable vertical sharpness enhancement

• High quality vertical zoom

• Motion compensated temporal noise reduction with

after-imaging cancellation

• Split screen demonstration mode

• 2 Mbaud serial interface (SNERT)

• Embedded 2 × 2.9-Mbit DRAM

• Full 8-bit accuracy

• Memory buffer for Picture-In-Picture (PIP)

• Lead-free package.

(1)

SAA4998H

2 GENERAL DESCRIPTION

The SAA4998H is a high performance video processor

featuring Natural Motion (PAL, NTSC and SECAM). It is used together with the picture improvement processor SAA4978H and SAA4979H.

The SAA4998H is an advanced versionof the SAA4993H. By embedding the fieldmemories it reducesthe part count oftherealized concept from 4 to 6 parts to only 2 partsand reduces the package size from a QFP160 to a QFP100.

The full FALCONIC mode uses full motion estimation and motion compensation on1/4pixel accuracy to perform

• Frame rate upconversion

• Film mode detection

• Movie judder cancellation

• Dynamic Noise Reduction (DNR)

• Edge Dependent De-Interlacing (EDDI).

The motion compensated de-interlacer is improved with a new patented Edge Dependent De-Interlacing (EDDI) method. This avoids jagged edges of diagonal lines. The better de-interlacer leads to a significant better performance of progressive as well as interlaced output formats.

A 60 Hz progressive output frame rate can be generated for 50 Hz PAL sources to enable the use of 60 Hz LCD or PDP panels in PAL regions.

50 Hz interlaced to 75 Hz interlaced and 60 Hz interlaced to 90 Hz interlaced can be generated to achieve an increased number of lines and hence a reduction of line visibility for jumbo screens and PTV applications.

The embedded memory can be used to synchronize the main channel and the 2nd channel for PIP and double window applications. This avoids to add additional buffer memory devices to the application.

For demonstration purposes a split screen mode to show the Dynamic Noise Reduction (DNR) function, natural motion, and EDDI is available. The estimated motion vectors can be made visible by colour overlay mode.

The SAA4998H supports a Boundary Scan Test (BST) circuit in accordance with

(2)

, for all global TV standards

“IEEE Std. 1149.1”

(1) EDDI is protected with two patents of Koninklijke Philips

Electronics N.V.

2004 Feb 18 3

(2) Natural Motion is a trademark of Koninklijke Philips

Electronics N.V.

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

2.1 Patent notice

Notice is herewith given that the subject integrated circuit uses one or more of the following US patents and that each of these patents may have corresponding patents in other jurisdictions.

US 4740842, US 5929919, US 6034734, US 5534946, US 5532750, US 5495300, US 5903680, US 5365280, US 5148269, US 5072293, US 5771074, and US 5302909.

3 QUICK REFERENCE DATA

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

V V V V V V I

DDD DDA DDM DDS DDE DDP

core supply voltage (internal rail) 1.65 1.8 1.95 V analog supply voltage ﬁeld memory supply voltage SRAM supply voltage external supply voltage (output pads) 3.0 3.3 3.6 V high supply voltage of internal ﬁeld memories sum of supply current

at 1.8 V supply voltage pins − 180 − mA at 3.3 V supply voltage pins − 6 − mA

CLK

amb

operating clock frequency − 32 33.3 MHz ambient temperature 0 − 70 °C

2.2 Latch-up test

Latch-up test in accordance with

“Latch-up Resistance

and Maximum Ratings Test; SNW-FQ-303

SAA4998H fulfils the requirements.

”; the

4 ORDERING INFORMATION

TYPE

NUMBER

NAME DESCRIPTION VERSION

PACKAGE

SAA4998H QFP100 plastic quad ﬂat package; 100 leads (lead length 1.95 mm);

body 14 × 20 × 2.8 mm

SOT317-2

2004 Feb 18 4

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2004 Feb 18 5

5 BLOCK DIAGRAMS

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

YA0 to YA7

SNCL

SNDA

SNRST

ACV

RST

PIPON

TWOFMON

REA

REF

TCK

TDO

TDI

TMS

TRSTN

CLK32

55 to 62

94 41 34

SNERT

INTERFACE

25 32 36

CONTROL

63 64

31 30 29

BST/TEST

28 27

DYNAMIC

NOISE

REDUCTION

MPR

LEFT

FIELD MEMORY 2

COMPRESS

MUX

DE-INTERLACER

WITH EDDI

vectors

SPM TPM ESM

MOTION ESTIMATOR

vectors

UPCONVERSION

MEMORY CONTROL

DECOMPRESS

MPR

RIGHT

FIELD MEMORY 3

VERTICAL

PEAKING

68, 69,

71 to 76

VERTICAL

ZOOM

95, 100,

SAA4998H

LUMINANCE PART

1, 2,

5 to 8

YF7 to YF0

YG7 to YG0

Fig.1 Block diagram luminance part in full FALCONIC mode.

coc001

SAA4998H

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2004 Feb 18 6

FIELD MEMORY 2 FIELD MEMORY 3

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

UVA0 to UVA7

42 to 47, 53, 54

DECOMPRESS/

REFORMAT

DNR

MPR LEFT

COMPRESS/

FORMAT

UPCONVERSION

vectors

DECOMPRESS/

REFORMAT

MPR

RIGHT

VERTICAL

ZOOM

78 to 81,

88, 89,

FORMAT

92, 93

9 to 13,

17 to 19

SAA4998H

CHROMINANCE PART

coc002

UVF7 to UVF0

UVG7 to UVG0

SAA4998H

Fig.2 Block diagram chrominance part in full FALCONIC mode.

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise reduction and embedded memory

6 PINNING

SYMBOL PIN TYPE DESCRIPTION

YG5/DPIP5 1 output/input PIP mode disabled: bus G luminance output bit 5;

PIP mode enabled: PIP data input bit 5

YG4/DPIP4 2 output/input PIP mode disabled: bus G luminance output bit 4;

PIP mode enabled: PIP data input bit 4

DDE

SSE

YG3/DPIP3 5 output/input PIP mode disabled: bus G luminance output bit 3;

YG2/DPIP2 6 output/input PIP mode disabled: bus G luminance output bit 2;

YG1/DPIP1 7 output/input PIP mode disabled: bus G luminance output bit 1;

YG0/DPIP0 8 output/input PIP mode disabled: bus G luminance output bit 0 (LSB);

UVG7/QPIP7 9 output PIP mode disabled: bus G chrominance output bit 7 (MSB);

UVG6/QPIP6 10 output PIP mode disabled: bus G chrominance output bit 6;

UVG5/QPIP5 11 output PIP mode disabled: bus G chrominance output bit 5;

UVG4/QPIP4 12 output PIP mode disabled: bus G chrominance output bit 4;

UVG3/QPIP3 13 output PIP mode disabled: bus G chrominance output bit 3;

n.c./LLC 14 input PIP mode disabled: not connected;

SSE

n.c./SWCK2 16 input PIP mode disabled: not connected;

UVG2/QPIP2 17 output PIP mode disabled: bus G chrominance output bit 2;

UVG1/QPIP1 18 output PIP mode disabled: bus G chrominance output bit 1;

UVG0/QPIP0 19 output PIP mode disabled: bus G chrominance output bit 0 (LSB);

n.c./RSTW2 20 input PIP mode disabled: not connected;

n.c./OIE2 21 input PIP mode disabled: not connected;

n.c./IE2 22 input PIP mode disabled: not connected;

DDP

n.c./WE2 24 input PIP mode disabled: not connected;

3 supply supply voltage of output pads (3.3 V) 4 ground ground of output pads

PIP mode enabled: PIP data input bit 3

PIP mode enabled: PIP data input bit 2

PIP mode enabled: PIP data input bit 1

PIP mode enabled: PIP data input bit 0 (LSB)

PIP mode enabled: PIP data output bit 7 (MSB)

PIP mode enabled: PIP data output bit 6

PIP mode enabled: PIP data output bit 5

PIP mode enabled: PIP data output bit 4

PIP mode enabled: PIP data output bit 3

PIP mode enabled: line locked clock signal for PIP mode

15 ground ground of output pads

PIP mode enabled: serial write clock for PIP memory

PIP mode enabled: PIP data output bit 2

PIP mode enabled: PIP data output bit 1

PIP mode enabled: PIP data output bit 0 (LSB)

PIP mode enabled: write reset clock for PIP memory

PIP mode enabled: output enable for PIP memory output QPIPx

PIP mode enabled: input enable for PIP memory

23 supply high supply voltage of the internal ﬁeld memories (3.3 V)

PIP mode enabled: write enable for PIP memory

(1)(2)(3)

SAA4998H

2004 Feb 18 7

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

SYMBOL PIN TYPE DESCRIPTION

ACV/RE2 25 output/input PIP mode disabled: active video output;

PIP mode enabled: read enable for PIP memory

n.c./RSTR2 26 input PIP mode disabled: not connected;

PIP mode enabled: read reset for PIP memory TRSTN 27 input boundary scan test reset input (active LOW); with internal pull-up resistor TMS 28 input boundary scan test mode select input; with internal pull-up resistor TDI 29 input boundary scan test data input; with internal pull-up resistor TDO 30 3-state boundary scan test data output TCK 31 input boundary scan test clock input; with internal pull-up resistor RST 32 input reset input; see Fig.4 SNRST 33 input SNERT bus reset input; with internal pull-down resistor SNDA 34 input/output SNERT bus data input and output; with internal pull-down resistor V

DDE

35 supply supply voltage of output pads (3.3 V) PIPON 36 input PIP mode enable input V V V V

SSM DDM SSM DDM

37 ground ﬁeld memory ground

38 supply supply voltage of the internal ﬁeld memories (1.8 V)

39 ground ﬁeld memory ground

40 supply supply voltage of the internal ﬁeld memories (1.8 V) SNCL 41 input SNERT bus clock input; with internal pull-down resistor UVA0 42 input bus A chrominance input bit 0 (LSB) UVA1 43 input bus A chrominance input bit 1 UVA2 44 input bus A chrominance input bit 2 UVA3 45 input bus A chrominance input bit 3 UVA4 46 input bus A chrominance input bit 4 UVA5 47 input bus A chrominance input bit 5 V V

DDD SSD

48 supply core supply voltage (1.8 V)

49 ground core ground TWOFMON 50 input to be connected to ground V V

DDS SSS

51 supply supply voltage of the internal SRAMs (1.8 V)

52 ground ground of the internal SRAMs UVA6 53 input bus A chrominance input bit 6 UVA7 54 input bus A chrominance input bit 7 (MSB) YA0 55 input bus A luminance input bit 0 (LSB) YA1 56 input bus A luminance input bit 1 YA2 57 input bus A luminance input bit 2 YA3 58 input bus A luminance input bit 3 YA4 59 input bus A luminance input bit 4 YA5 60 input bus A luminance input bit 5 YA6 61 input bus A luminance input bit 6 YA7 62 input bus A luminance input bit 7 (MSB) REA 63 output read enable output for bus A

(1)(2)(3)

2004 Feb 18 8

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

SYMBOL PIN TYPE DESCRIPTION

IE 64 input input enable for PIP mode V V

DDD SSD

65 supply core supply voltage (1.8 V)

66 ground core ground REF 67 input read enable input for bus F and G; note 4 YF7 68 output bus F luminance output bit 7 (MSB) YF6 69 output bus F luminance output bit 6 V

SSE

70 ground ground of output pads YF5 71 output bus F luminance output bit 5 YF4 72 output bus F luminance output bit 4 YF3 73 output bus F luminance output bit 3 YF2 74 output bus F luminance output bit 2 YF1 75 output bus F luminance output bit 1 YF0 76 output bus F luminance output bit 0 (LSB) V

DDE

77 supply supply voltage of output pads (3.3 V) UVF7 78 output bus F chrominance output bit 7 (MSB) UVF6 79 output bus F chrominance output bit 6 UVF5 80 output bus F chrominance output bit 5 UVF4 81 output bus F chrominance output bit 4 V

SSE

82 ground ground of output pads CLK32 83 input system clock input (32 MHz) V V V V

DDS SSS DDD SSD

84 supply supply voltage of the internal SRAMs (1.8 V)

85 ground ground of the internal SRAMs

86 supply core supply voltage (1.8 V)

87 ground core ground UVF3 88 output bus F chrominance output bit 3 UVF2 89 output bus F chrominance output bit 2 V V

SSA DDA

90 ground analog ground of the internal PLL

91 supply analog supply voltage of the internal PLL (1.8 V) UVF1 92 output bus F chrominance output bit 1 UVF0 93 output bus F chrominance output bit 0 (LSB) VD 94 input vertical display synchronization input (reset for ﬁeld memories) YG7/DPIP7 95 output/input PIP mode disabled: bus G luminance output bit 7 (MSB);

PIP mode enabled: PIP data input bit 7 (MSB) V V

DDM SSM

96 supply supply voltage of the internal ﬁeld memories (1.8 V) 97 ground ﬁeld memory ground

(1)(2)(3)

2004 Feb 18 9

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise reduction and embedded memory

SYMBOL PIN TYPE DESCRIPTION

V V

DDM SSM

98 supply supply voltage of the internal ﬁeld memories (1.8 V) 99 ground ﬁeld memory ground

YG6/DPIP6 100 output/input PIP mode disabled: bus G luminance output bit 6;

PIP mode enabled: PIP data input bit 6

Notes

1. Not used input pins should be connected to ground.

2. Because of the noisy characteristic of the supply voltage of output pads (V V

directly at the high supply voltageof the intern field memories (V

DDE

as possible to the device. V separated from V

by an external filter structure. Because of the high working frequency of the device, it is also

DDE

recommended to filter the core supply voltage (V

needs a low noise supply voltage, therefore, it is recommended that V

DDP

). All pins V

DDD

). All pins V

DDP

should be buffered as close as possible to the

device.

3. V

SSD

, V

SSM

and V

are connected internally.

SSS

4. REF rising edge must be after rising edge of SNRST in order to be detected.

(1)(2)(3)

), it is recommended not to connect

DDE

SAA4998H

should be buffered as close

has to be

DDP

2004 Feb 18 10

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise reduction and embedded memory

SSMVDDMVSSMVDDM

YG6/DPIP6

YG5/DPIP5 YG4/DPIP4

DDE

SSE

YG3/DPIP3 YG2/DPIP2 YG1/DPIP1

YG0/DPIP0 UVG7/QPIP7 UVG6/QPIP6 UVG5/QPIP5 UVG4/QPIP4 UVG3/QPIP3

n.c./LLC

SSE

n.c./SWCK2 UVG2/QPIP2 UVG1/QPIP1 UVG0/QPIP0

n.c./RSTW2

n.c./OIE2

n.c./IE2

DDP

n.c./WE2

ACV/RE2

n.c./RSTR2

TRSTN

TMS

TDI

TDO

99989796959493929190898887

100

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

YG7/DPIP7VDUVF0

SAA4998H

UVF1

DDAVSSA

UVF2

UVF3

SSDVDDDVSSSVDDS

8685848382

SSE

CLK32

UVF4 81

SAA4998H

UVF5

80 79

UVF6

UVF7 V

DDE

YF0

YF1

YF2

YF3

YF4

YF5 V

SSE

YF6

YF7

REF V

SSD

DDD

REA

YA7

YA6

YA5

YA4

YA3

YA2

YA1

YA0

UVA7

UVA6 V

SSS

DDS

31323334353637383940414243

DDE

SSM

TCK

RST

SNDA

SNRST

PIPON

DDM

Fig.3 Pin configuration.

2004 Feb 18 11

DDM

SNCL

UVA0

UVA1

UVA2

4546474849

DDD

UVA4

UVA5

UVA3

SSD

TWOFMON

001aaa057

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2004 Feb 18 12

7 CONTROL REGISTER DESCRIPTION

SNERT

NAME

DNR/peaking/colour Kstep10 010 write; S

Kstep0 XXXXset LUT value: k =1⁄16 if difference below (0to15) Kstep1 X X X X set LUT value: k =1⁄8 if difference below (0to15)

Kstep32 011 write; S

Kstep2 XXXXset LUT value: k =2⁄8 if difference below (0 to 30 in multiples of 2) Kstep3 X X X X set LUT value: k =3⁄8 if difference below (0 to 30 in multiples of 2)

Kstep54 012 write; S

Kstep4 XXXXset LUT value: k =4⁄8 if difference below (0 to 60 in multiples of 4) Kstep5 X X X X set LUT value: k =5⁄8 if difference below (0 to 60 in multiples of 4)

Kstep76 013 write; S

Kstep6 XXXXset LUT value: k =6⁄8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,

Kstep7 X X X X set LUT value: k =7⁄8 if difference below (0, 8, 16, 24, 32, 40, 48, 56,

Gain_ﬁx_y 014 write; S

FixvalY XXXXset ﬁxed Y value; used when FixY = 1 or in left part of split screen

GainY X X X set gain in difference signal for adaptive DNRY (1⁄8,1⁄4,1⁄2, 1, 2 or 4) FixY X select ﬁxed Y (adaptive or ﬁxed) (full screen)

Gain_ﬁx_uv 015 write; S

FixvalUV XXXXset ﬁxed UV value; used when FixUV = 1 or in left part of split screen

GainUV X X X set gain in difference signal for adaptive DNR UV (1⁄8,1⁄4,1⁄2, 1, 2 or 4) FixUV X select ﬁxed UV (adaptive or ﬁxed) (full screen)

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

64, 72, 80, 88, 96, 104, 112 or 120)

(0,1⁄16to14⁄16or16⁄16)

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

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2004 Feb 18 13

SNERT

NAME

Peak_Vcomp 016 write; S

VecComp X X X set degree of horizontal vector compensation in Y DNR:

NoiseShape X noise shaping enable; this bit is set to logic 1 after reset or power-up PeakCoef X X X X set vertical peaking level: (0, +2, +3.5, +5, +6, x, x, x, x, x, x, x, x,

DNR_Colour_mode 017 write; S

ColourIn X X select colour input format: (4:1:1, 4:2:2, 4:2:2DPCM or

ColourOut X select colour output format: (4:1:1or4:2:2) NrofFMs X set number of ﬁeld memories used for motion compensation: (1or2) ColOvl X select vector overlay on colour output: (vector overlay or colour

SlaveUVtoY X slave UV noise reduction to K factor of Y: (separate or slaved) DnrSplit X select split screen mode for DNR: (normal or split screen) DnrHpon X switch DNR high-pass on (DNR only active on low frequent spectrum:

Vertical zoom Zoom1 018 write; F

ZoomSt98 X X zoom line step bits 9 and 8; line step = vertical distance between

ZoomPo98 X X zoom start position bits 9 and 8; start position = vertical position of the

Zoom2 019 write; F

ZoomSt70 X XXXXXXXzoom line step bits 7 to 0 (see above)

Zoom3 01A write; F

ZoomPo70 X XXXXXXXzoom start position bits 7 to 0 (see above)

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

(0,1⁄8,2⁄8,3⁄8,4⁄8,5⁄8,6⁄8or7⁄8) of the vector

−12, −6or−2.5)dB

4:2:2)

from video path)

(all through DNR or high bypassed)

successive output lines; usable range = 0 to 2 frame lines;

⁄

resolution

top display line; usable range = 1 to 3 frame lines; resolution frame line

frame line

256

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

⁄

256

SAA4998H

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2004 Feb 18 14

SNERT

NAME

Zoom4 01B write; F

ZoomEnVal XXXXzoom run in value = number of lines without zoom active

ZoomDiVal X X X X zoom run out value = number of lines without zoom active

De-interlacer Proscan1 01C write; S

KlfLim XXXXlimitation of recursion factor in calculation of original line positions:

KlfOfs X X X X The transfer curve of the de-interlacing ﬁlter coefﬁcient is determined

Proscan2 01D write; S

PlfLim XXXXlimitation of recursion factor in calculation of interpolated line

PlfOfs X X X X see KlfOfs; this offset applies to interpolated lines

Proscan3 01E write; S

PeakLim XXXXMaximumthat the peakedpixel is allowedto deviate from original pixel

DeiOfs X X X X offset to bias between average and median in the initial de-interlacing,

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

(0to15lines)

(−8to+7lines)

(1to16); 1 limits to almost full recursion, 16 limits to no recursion

by the difference (Diff) between a line in the input ﬁeld and the counterpart in the previous ﬁeld shifted over the estimated motion vector. KlfOfs determines the bias of the transfer curve for the original input line, such that coefﬁcient = KlfOfs + F(Diff), where the function F is calculated in the SAA4998H. The bias can take a value in the range (0to15), representing decreasing ﬁlter strength.

positions: (1to16); 1 limits to almost full recursion, 16 limits to no recursion

value: deviation (0 to 30 in steps of 2). Above this deviation, the peaked pixel is clipped to (original pixel + or − PeakLim).

if the KplFad = MIX option is chosen

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

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2004 Feb 18 15

SNERT

NAME

Proscan4 01F write; F

PlfThr X X X Multiplier threshold at which to switch the lower limit of the ﬁlter

AdRecOut X select adaptive recursive or order statistic output (order statistic or

ProDiv X X Scaling factor to control the strength of the ﬁltering for the interpolated

KplOff X disable all recursion in calculating pixels for frame memory (recursive

Proscan5 0CB write; S

VecRbf XXXXRoll back factor on vectors used for motion-compensated

FadDiv X X X sensitivity scaling factor in transition from average to median in initial

KplFad X choosesbetween majority selection and median/average mix for initial

Proscan6 0F0 write; S

EddiOut X turns EDDI on and off (off or on) EddiDemo X activates split screen demonstration mode for EDDI (off or on) EddiCmp X X Factor to specify the size of the additional compensation area left and

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

coefﬁcient for interpolated lines. Above this threshold, the differences corresponding to the two neighbouring lines are used as clipping parameters, below this threshold, the interpolated line difference is used as clipping level. This parameter can be used to optimize the de-interlacing quality in slowly moving edges; it is not likely to have effect if PlfLim is high.

adaptive)

lines. A value 0 means no scaling (normal ﬁltering), while 3 means scaling by factor 8 (very strong ﬁltering). This parameter can be used to adjust the de-interlacing to varying level of noise in the input picture; use higher scaling for higher noise.

or non recursive)

de-interlacing. Values 0to14 (on a scale of 16) indicate attenuation. A value of 15 indicates no attenuation.

de-interlacing

de-interlacing (majority or mix); when KplFad = 0, FadDiv and DeiOfs are don’t cares

right of the ‘real’ edge. A high factor (e.g. 1) can increase the compensation in regions far away from the true edge (1,1⁄2,1⁄4or1⁄8).

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

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2004 Feb 18 16

SNERT

NAME

Proscan7 0F1 write; S

EddiMR X X Factorfor the comparison of the monotonous regions belonging to two

EddiED X X Factor for the comparison of the monotonous regions belonging to two

EddiDif X X X X minimal required Y difference at edge point position to be a reliable

Proscan8 0F2 write; S

EddiFil XXXXminimal required edge ﬁlter value at start and end of the monotonous

EddiLng X X minimal required length of monotonous region to be reliable; higher

Proscan9 0F3 write; S

EddiOfs XXXXoffset to increase or decrease the amount of EDDI compensation;

EddiLim X X X X limitation of the compensation factor of EDDI; 1 limits to full EDDI

General NrBlks 020 write; S

NrBlks XXXXXXnumber of blocks in active video (6to53, corresponds to

TotalLnsAct98 X X total number of output lines (bits 9 and 8)

TotalLnsAct70 021 write; S X XXXXXXXtotal number of output lines (bits 7 to 0)

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

edge points to verify an edge (1,1⁄2,1⁄4or1⁄8).

edge points and the edge point distance to verify an edge (1,1⁄2,1⁄4or1⁄8).

edge point; higher values result in higher reliability of EDDI, but less edges will be detected (0 to 60 in multiples of 4)

region to be a reliable edge point; should be set higher in pictures with noise (0 to 60 in multiples of 4)

values result in higher reliability of EDDI, but less steep edges will be detected (2, 3, 4 or 5)

lower values increase the amount of compensation (1to16)

compensation, 16 limits to almost no EDDI compensation (1to16)

96 to 848 pixels), to be set as1⁄16 (number of active pixels per line + 15); take remarks on TotalPxDiv8 into consideration

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

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2004 Feb 18 17

SNERT

NAME

TotalPxDiv8 022 write; S X XXXXXXXTotal number of pixels per line divided-by-8(80 to 128, corresponds to

REaShift 023 write; S X X X shift of REA signal in number of pixels (0, +1, +2, +3, −4, −3, −2or−1) WEbdREceShift 024 write; S

WEbdShift X X X reserved REceShift X X X reserved

POR 025 write; S X power-on reset command, to be set high temporarily during start-up

ScalingFactor 0D6 write; S X XXXXXXX8-bit scaling factor for EggSliceMix, EggSliceRgt and global activity

FieldMemoryControl 000 write; F

PIPON X Picture-In-Picture (PIP) ﬁeld memory mode enable TWOFMON 0 has to be set to logic 0 PIPDataDelay X input data will be delayed by one clock cycle with respect to WE2

PIPStillPicture X no new data will be written into the ﬁeld memory

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

640 to 1024 pixels). The horizontal blanking interval is calculated as TotalPxDiv8 − 2 × NrBlks and has to be in the range from 12 to 124 (corresponds to 96 to 992 pixels). Conclusion: TotalPxDiv8 has to be set to 12 + 2 × NrBlks < TotalPxDiv8 < 124 + 2 × NrBlks and NrBlks

has to be set to

(normal or reset); note 3

(the same factor for all registers).

output value (n+1)

(write enable)

TotalPxDiv8 124–

-----------------------------------------------2

ScalingFactor

-----------------------------------128

(2)

NrBlks

output value (n)×=

TotalPxDiv8 12–

-------------------------------------------- 2

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

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2004 Feb 18 18

SNERT

NAME

Mode control Control1 026 write; F

EstMode X Set estimator mode; 0 = line alternating use of left and right estimator:

FilmMode X set ﬁlm mode; 0 = video camera mode; 1 = ﬁlm mode UpcMode X X select upconversion quality; 00 = full, 01 = economy (DPCM),

MatrixOn X set matrix output mode; 1 = double output, disabling vertical peaking;

EmbraceOn X Master enable for embrace mode (off or on); SwapMpr in control2

MemComp X set memory compression (luminance DPCM) (off or on) MemDecom X set memory decompression (luminance DPCM) (off or on)

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

use in progressive scan except with vertical compress. 1 = ﬁeld alternating use of left and right estimator: use in ﬁeld doubling and progressive scan with vertical compress.

10 = single memory with motion compensation, 11 = single memory without motion compensation

0 = normal single output mode; this bit setting is the AND function of BusGControl bits

should be at ‘swap’ position to really cross-switch FM1 and FM3 ﬁeld outputs. Should be set to logic 0 except in ﬁlm mode and FM3 is present.

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

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2004 Feb 18 19

SNERT

NAME

Control2 027 write; F

QQcurr X Quincunx phase of current ﬁeld (in TPM) (phase0 or phase1); this

QQprev X Quincunx phase of previous ﬁeld (in TPM) (phase0 or phase1); this is

FldStat X Field status (same input ﬁeld or new input ﬁeld); reﬂects whether

FieldWeYUV X enable writing FM2 and FM3 for both luminance and chrominance

OddFM1 X odd input ﬁeld (even or odd), this is to be set equal to the detected

SwapMpr X Swap multi port RAMs (normal or swap); this bit needs to be set to

VecOffs X X Set vertical vector offset (0, +1, − or −1) frame lines; vertical offset of

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

needs to toggle each time a new ﬁeld comes from FM1. In phase0 the estimator operates on a checker-board pattern that starts with the left upper block; in phase1 the other blocks are estimated.

the value of QQcurr during the last estimate written into the temporal prediction memory

the output of FM1 is a new or a repeated ﬁeld. This bit will toggle ﬁeld by ﬁeld in ﬁeld doubling mode and is continuously HIGH in progressive output mode.

(recirculation of data for luminance alone can be controlled with OrigFmEnY and IntpFmEnY in Control3) (off or on)

ﬁeld interlace for the ﬁeld that comes out of FM1

get real frame data at the temporal position from FM1. If swapped, the current ﬁeld (FM1) will be stored in the right line memory tree, while the original lines from the stored frame (FM2/3) are stored in the left memory tree. Should be set only in ﬁlm mode if FM3 is present; EmbraceOn must be set as well.

the right line memory tree with respect to the left line memory tree. A higher offset value means: on the right memory tree access to less delayed video lines is taken; in interlaced video operation, the vertical offset will be −1 with an odd ﬁeld on the left side and +1 with an even ﬁeld on the left. With non-interlaced input, vertical offset should be constantly 0. In ﬁlm mode, vertical offset is dynamically switched between +1, 0 and −1.

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

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2004 Feb 18 20

SNERT

NAME

Control3 028 write

OddLeft F X interlace (even or odd) phase of the ﬁeld which is written to the left

OrigFmEnY X enables writing luminance from de-interlacer in original ﬁeld memory

IntpFmEnY X enables writing luminance from de-interlacer in interpolated ﬁeld

FillTPM X Enables writing in temporal prediction memory (keep or update);

VertOffsDNR X X Set vertical vector offset of DNR (0, +1, − or −1) frame lines; vertical

BusGControl S X X Select output mode of bus G; 00 = normal single output mode (bus G

Upconversion Upconv1 029 write; F

UpcShFac XXXXXXtemporal interpolation factor used in luminance upconverter; value

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

line memory tree (left MPRAM)

(FM2), otherwise recirculation of luminance that is just read from FM2 (recirculate or update)

memory (FM3), otherwise recirculation of luminance that is just read from FM3 (recirculate or update)

FillTPM should be set to ‘keep’ in single memory ﬁlm mode, in those output ﬁelds where FM1 and FM2 contain the same motion phase. FillTPM should be set to ‘update’ in all other situations.

offset of the right line memory tree with respect to the left line memory tree, before the swap action. A higher offset value means: on the right memory tree access to less delayed video lines is taken; in interlaced video operation, the vertical offset will be −1 with an odd ﬁeld on the left side and +1 with an even ﬁeld on the left. With non-interlaced input, vertical offset should be constantly logic 0; in ﬁlm mode, vertical offset is dynamically switched between +1, 0 and −1. It should be noted that the signal OddFM1 is used to determine this offset.

in 3-state), 01 = output of motion vectors to UVG (motion_x on U and motion_y on V), 10 = copy bus F to G, 11 = double output, disabling vertical peaking. Only when double output is selected, the MatrixOn bit in register Control1 should be set, otherwise it needs to be cleared.

ranges from 0 (for current ﬁeld position) to 32 (for previous ﬁeld position)

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

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2004 Feb 18 21

SNERT

NAME

Upconv2 02A write

YVecClip S XXXvalue used for coring the vertical vector component before application

RollBack F X XXXX roll back factor ranging from 0 (use 0% of estimated vectors) to 16

Upconv3 02B write; S

MelzLfbm X single memory type local fallback method instead of more robust local

Melzmemc X singlememory ﬁlm mode control (double memory or single memory

MelDeint X use horizontal motion compensated median for upconverter

MixCtrl X XXXX Bits 3 and 4 are used to control sensitivity to local vector smoothness

UpcColShiFac 0C4 write; F XXXXXXtemporal interpolation factor used in chrominance upconverter; value

Upconv4 0C5 write; S

LfIndex X X X Number of consecutive lines to have bad egg-slice values before

MCDemo X mode switch on left side of the screen; 0 (natural motion); 1 (digital

EggSlice1 0C6 write; S

EggStartLine X XXXXXXXReference line number at which the egg slice measurement should

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

in the upconverter; range: 0 to 3.5 in steps of 0.5 line; should remain at logic 0 in normal operation

(use 100% of estimated vectors)

fallback (double memory or single memory type fallback)

type); should be set in single memory ﬁlm mode to ensure that only original lines are selected as output when UpcShFac is 0 or 32

de-interlacing (full FALCONIC or single memory type de-interlacing)

(0 = sensitive to unsmoothness, 3 = hardly sensitive to unsmoothness). Bits 5 to 7 deﬁne the maximum contribution of non-motion compensated pixels to the output (0,1⁄8,2⁄8,3⁄8,4⁄8,5⁄8,6⁄8or7⁄8).

ranges from 0 (for current ﬁeld position) to 32 (for previous ﬁeld position)

upconverter goes into protection mode (0, 1, 2, 4, 8, 16, 32 or 64). A value of 0 switches off the possibility to go into protection.

scan-like processing)

start. SAA4998H deﬁnes a window internally as number of lines between EggStartLine and (MaxRefLine − EggStartLine).

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

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2004 Feb 18 22

SNERT

NAME

EggSlice2 0C7 write; S

EggSlcThr XXXXXXMinimum line egg slice right value to activate reliability measurement.

EggRelInd X X The egg slice reliability is computed internally as

SafeShiFac 0C8 write; F XXXXXXupconverter shift factor to be used in protection mode; 0 (for current

Motion estimator Motest1 02C write; S

PenOdd X X X additional penalty on vector candidates with odd vertical component

SpcThr X X X Active when EstMode = 0; replace the spatial prediction of one

BmsThr X X Active when EstMode = 0; select as estimated vector the output of the

Motest2 02D write; S

TavLow X If the difference between the current vector and the previous one in

TavUpp X X see above; TavUpp is the upper threshold (0, 4, 8 or 16) MedEns X X scaling factor to reduce all sizes of update vectors in the ensemble

LarEns X X scaling factor to reduce all sizes of update vectors in the ensemble

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

The parameter is multiplied internally by 4.

EggSliceRgt (ESR) > RelFactor × EggSliceMix (ESM). RelFactor is determined by EggRelInd (2⁄8,3⁄8,4⁄8or6⁄8).

ﬁeld position) to 32 (for previous ﬁeld position)

(0, 8, 16, 32, 64, 128, 256 or 511)

estimator (left or right) by that of the other if the match error of the former exceeds that of the latter by more than (0, 8, 16, 32, 64, 128, 256 or 511). A higher threshold means the two estimators are very independent.

right estimator unless its match error exceeds that of the left estimator by more than (0, 8, 16 or 32). This parameter should normally be set to logic 0.

the same spatial location is within a small window, then the two vectors are averaged to improve temporal consistency. TavLow is the lower threshold of this window (1or2).

with medium sized vector templates (1,1⁄2,1⁄4or1⁄8)

with large sized vector templates (1,1⁄2,1⁄4or1⁄8)

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

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2004 Feb 18 23

SNERT

NAME

Motest3 02E write; F

MotShiFac XXXXXXMotion estimator shift factor, being the temporal position used in the

Motest4 02F write; S

PenRng X Penalty for vectors estimated on the ﬁrst row and the ﬁrst column (if

CndSet X choice of candidate set (left or right) for which data (Candidate1 to

ErrThr X X X threshold on block match error for considering a block to be bad

ErrHbl X X number of horizontally adjacent blocks that have to be all bad before

TstMod X to be kept to logic 1 for normal operation

Motest5 0CC write; S

ActOption X X selection of the vector component to take in the activity count

ClearTPM X write zeros in the temporal prediction memory

LoActThr 0CD write; S X XXXXXXXblocks having an activity value below or equal to this threshold are

HiActThr 0CE write; S X XXXXXXXblocks having an activity value above this threshold are counted as

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

estimator at which the matching is done; value 32 for matching at previous ﬁeld position down to 0 for matching at current ﬁeld position. Keeping MotShiFac equal to UpShiFac in the next upconverted output ﬁeld estimates for minimum matching errors (minimum Halo’s). MotShiFac at value 16 gives the largest natural vector range (twice as large as with value 0 or 32). Going above the range with MotShiFac ≠ 16 is dealt with in SAA4998H by shifting towards 16, but for the horizontal and vertical component separately (consequence is that vector candidates tend to rotate towards the diagonal directions).

left estimator is used) or the right column (if right estimator is used), whenever the spatial prediction candidate is selected (64 or 511). For noisy pictures, this register could be set to logic 1 to improve border processing in the estimator.

Candidate8) is written in this ﬁeld (becomes active in next ﬁeld); note 3

(16, 32, 64, 128, 256, 512, 1024 or 2032)

considering an occurrence of a burst error (1, 2, 4 or 8) (counting of burst errors is read out with BlockErrCnt, address 0A8H)

(x + y, x, y or −)

(no writing or writing zeros)

counted as having LOW activity

having HIGH activity

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

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2004 Feb 18 24

SNERT

NAME

LeftBorder 0CF write; S

LeftBorder XXXXXXXestimator left border (in 8-pixel blocks) WinNullWrite X enable writing of null vectors outside estimators’ active window

RightBorder 0D0 write; S XXXXXXXestimator right border (in 8-pixel blocks) TopBorder 0D1 write; S XXXXXXXestimator top border (in 4-line blocks) BottomBorder 0D2 write; S XXXXXXXestimator bottom border (in 4-line blocks) Candidate1 090 write; S

Candidat1 X X X selection Candidate1 (SpatLeft, SpatRight, TemporalRight,

Update1 X X update for Candidate1 (zero update, medium update, large update

Penalty1 X X X penalty for Candidate1 (0, 8, 16, 32, 64, 128, 256 or 511)

Candidate2 091 write; S

Candidat2 X X X selection Candidate2 (SpatLeft, SpatRight, TemporalRight,

Update2 X X update for Candidate2 (zero update, medium update, large update

Penalty2 X X X penalty for Candidate2 (0, 8, 16, 32, 64, 128, 256 or 511)

Candidate3 092 write; S

Candidat3 X X X selection Candidate3 (SpatLeft, SpatRight, TemporalRight,

Update3 X X update for Candidate3 (zero update, medium update, large update

Penalty3 X X X penalty for Candidate3 (0, 8, 16, 32, 64, 128, 256 or 511)

Candidate4 093 write; S

Candidat4 X X X selection Candidate4 (SpatLeft, SpatRight, TemporalRight,

Update4 X X update for Candidate4 (zero update, medium update, large update

Penalty4 X X X penalty for Candidate4 (0, 8, 16, 32, 64, 128, 256 or 511)

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

(off or on)

TemporalLeft, TemporalCentre, Null, Panzoom or Max)

or zero update)

TemporalLeft, TemporalCentre, Null, Panzoom or Max)

or zero update)

TemporalLeft, TemporalCentre, Null, Panzoom or Max)

or zero update)

TemporalLeft, TemporalCentre, Null, Panzoom or Max)

or zero update)

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

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2004 Feb 18 25

SNERT

NAME

Candidate5 094 write; S

Candidat5 X X X selection Candidate5 (SpatLeft, SpatRight, TemporalRight,

Update5 X X update for Candidate5 (zero update, medium update, large update

Penalty5 X X X penalty for Candidate5 (0, 8, 16, 32, 64, 128, 256 or 511)

Candidate6 095 write; S

Candidat6 X X X selection Candidate6 (SpatLeft, SpatRight, TemporalRight,

Update6 X X update for Candidate6 (zero update, medium update, large update

Penalty6 X X X penalty for Candidate6 (0, 8, 16, 32, 64, 128, 256 or 511)

Candidate7 096 write; S

Candidat7 X X X selection Candidate7 (SpatLeft, SpatRight, TemporalRight,

Update7 X X update for Candidate7 (zero update, medium update, large update

Penalty7 X X X penalty for Candidate7 (0, 8, 16, 32, 64, 128, 256 or 511)

Candidate8 097 write; S

Candidat8 X X X selection Candidate8 (SpatLeft, SpatRight, TemporalRight,

Update8 X X update for Candidate8 (zero update, medium update, large update

Penalty8 X X X penalty for Candidate8 (0, 8, 16, 32, 64, 128, 256 or 511)

PZpositionLeftUppX 098 write; S XXXXXXXposition of LeftUpp measurement point for pan-zoom calculations

PZpositionLeftUppY 099 write; S XXXXXXXYposition of LeftUpp measurement point for pan-zoom calculations

PZpositionRightLowX 09A write; S XXXXXXXposition of RightLow measurement point for pan-zoom calculations

PZpositionRightLowY 09B write; S XXXXXXXYposition of RightLow measurement point for pan-zoom calculations

PZvectorStartX 09C write; F X XXXXXXXXstart value of pan-zoom vectors

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

TemporalLeft, TemporalCentre, Null, Panzoom or Max)

or zero update)

TemporalLeft, TemporalCentre, Null, Panzoom or Max)

or zero update)

TemporalLeft, TemporalCentre, Null, Panzoom or Max)

or zero update)

TemporalLeft, TemporalCentre, Null, Panzoom or Max)

or zero update)

(resolution: 16 pixels)

(resolution: 4 lines)

(resolution: 16 pixels)

(resolution: 4 lines)

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

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2004 Feb 18 26

SNERT

NAME

PZvectorDeltaX 09D write; F X XXXXXXXXdelta value of pan-zoom vectors PZvectorStartY 09E write; F X XXXXXXXYstart value of pan-zoom vectors PZvectorDeltaY 09F write; F X XXXXXXXYdelta value of pan-zoom vectors

Read data; note 3 GlobalMSEmsb 0A0 read; F X XXXXXXXGlobal Mean Square Error (MSE) = summation within a ﬁeld period of

GlobalMSElsb 0A1 read; F X XXXXXXX

GlobalMTImsb 0A2 read; F X XXXXXXXGlobal Motion Trajectory Inconsistency (MTI) = summation within a GlobalMTIlsb 0A3 read; F X XXXXXXX

GlobalACTmsb 0A4 read; F X XXXXXXXglobal activity (ACT) = summation over a ﬁeld period of the horizontal GlobalACTlsb 0A5 read; F X XXXXXXX VectTempCons 0A6 read; F X XXXXXXXVector temporal consistency = summation over a ﬁeld period of

VectSpatCons 0A7 read; F X XXXXXXXVectorspatial consistency = summation over a ﬁeld period of absolute

BlockErrCnt 0A8 read; F X XXXXXXXburst error count (number of burst errors)

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

squared differences in comparing vector shifted video from frame memory (FM2/3) with new ﬁeld input (FM1) in those lines coinciding with new ﬁeld lines. The window for the measurement is kept at 40 pixels horizontal and 20 ﬁeld lines vertical from the border of the video. Measurements is only done in ﬁelds where the de-interlacer is active, otherwise reading is zero. In ﬁeld doubling mode, MSE is zero at the end of every new input ﬁeld.

ﬁeld period of squared differences comparing shifted video from frame memory (FM2/3 output) with ﬁltered data that is rewritten to the frame memory (FM2/3 input) in those lines coinciding with new ﬁeld lines. The window for the measurement is kept at 40 pixels horizontal and 20 ﬁeld lines vertical from the border of the video. Measurement is done only in ﬁelds where de-interlacer is active, otherwise reading is zero; in ﬁeld doubling mode, MTI is zero at the end of every new input ﬁeld.

plus the vertical components of the vectors of all blocks

absolute differences of horizontal plus vertical components of vectors newly estimated for each block compared with those vectors estimated in the previous run at the same spatial block position. It should be noted that a lower ﬁgure implies better consistency.

differencesof horizontal and vertical components of vectors compared with those of the neighbour blocks(L, R, U and D); in the comparison, all vector data is used from the previous estimator run. It should be noted that a lower ﬁgure implies better consistency.

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

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2004 Feb 18 27

SNERT

NAME

LeastErrSum 0A9 read; F X XXXXXXXleast error sum (summation over a ﬁeld period of the smallest match

YvecRangeErrCntmsb 0AA read; F X XXXXXXXYvector range error count (number of vectors that have a vertical

YvecRangeErrCntlsb 0AB read; F X XXXXXXXYvector range error count (7 to 0) RefLineCountPrev 0AC read; F X XXXXXXXread out of [number of input (run-) lines − 40] used in previous ﬁeld RefLineCountNew 0AD write; F X XXXXXXXWrite of [number of input (run-) lines − 40] to be used in new ﬁeld

PanZoomVec0-X 0B0 read; F X XXXXXXXpan-zoom vector 0 (8-bit X value) PanZoomVec0-Y 0B1 read

FalconIdent S 0 SAA4998H identiﬁcation: ﬁxed bit, reading this bit as zero means

PanZoomVec0-Y F XXXXXXXpan-zoom vector 0 (7-bit Y value)

PanZoomVec1-X 0B2 read; F X XXXXXXXpan-zoom vector 1 (8-bit X value) PanZoomVec1-Y 0B3 read

StatusJump0 S X 1: both ﬁeld memories are in use by the motion estimation and motion

PanZoomVec1-Y F XXXXXXXpan-zoom vector 1 (7-bit Y value)

PanZoomVec2-X 0B4 read; F X XXXXXXXpan-zoom vector 2 (8-bit X value) PanZoomVec2-Y 0B5 read

StatusJump1 S 1 logic 1 PanZoomVec2-Y F XXXXXXXpan-zoom vector 2 (7-bit Y value)

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

error that the estimator has found for each block: indicates reliability of the estimation process)

component that is out of range for upconversion at the chosen temporal position) (15 to 8)

(actual maximum number of input lines in normal operation: 292; register value 252). Nominally this is to be set as an exact copy of the value read from RefLineCountPrev before a new ﬁeld starts. In case the effective number of input (run-) lines has increased, RefLineCountNew should, for one ﬁeld, be set to 255. This will occur e.g. with decreasing vertical zoom magniﬁcation or changing from 525 lines video standard to 625 lines standard. If this is not done, a deadlock will occur with too few lines processed correctly by the motion estimator.

SAA4998H is present

compensation function; see Fig.1 0: ﬁeld memory 2 is in use by the motion estimation and motion compensation function; ﬁeld memory 3 for PIP application; see Fig.1

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

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2004 Feb 18 28

SNERT

NAME

PanZoomVec3-X 0B6 read; F X XXXXXXXpan-zoom vector 2 (8-bit X value) PanZoomVec3-Y 0B7 read; F XXXXXXXpan-zoom vector 3 (7-bit Y value) PanZoomVec4-X 0B8 read; F X XXXXXXXpan-zoom vector 4 (8-bit X value) PanZoomVec4-Y 0B9 read; F XXXXXXXpan-zoom vector 4 (7-bit Y value) PanZoomVec5-X 0BA read; F X XXXXXXXpan-zoom vector 5 (8-bit X value) PanZoomVec5-Y 0BB read; F XXXXXXXpan-zoom vector 5 (7-bit Y value) PanZoomVec6-X 0BC read; F X XXXXXXXpan-zoom vector 6 (8-bit X value) PanZoomVec6-Y 0BD read; F XXXXXXXpan-zoom vector 6 (7-bit Y value) PanZoomVec7-X 0BE read; F X XXXXXXXpan-zoom vector 7 (8-bit X value) PanZoomVec7-Y 0BF read; F XXXXXXXpan-zoom vector 7 (7-bit Y value) PanZoomVec8-X 0AE read; F X XXXXXXXpan-zoom vector 8 (8-bit X value) PanZoomVec8-Y 0AF read; F XXXXXXXpan-zoom vector 8 (7-bit Y value) EggSliceRgtMSB 0C0 read; F X XXXXXXXresult of right pixels egg-slice detector (15 to 8) EggSliceRgtLSB 0C1 read; F X XXXXXXXresult of right pixels egg-slice detector (7 to 0) EggSliceMixMSB 0C2 read; F X XXXXXXXresult of mixed pixels egg-slice detector (15 to 8) EggSliceMixLSB 0C3 read; F X XXXXXXXresult of mixed pixels egg-slice detector (7 to 0) SafeFbLine 0C9 read; F X XXXXXXXreference line number (divided by two) at which the upconverter goes

EggBinGoodness 0CA read; F X XXXXXXXGoodness of the four egg-slice sections, from top to bottom, 2 bits per

LoActCnt 0D3 read; F X XXXXXXXnumber of blocks having low activity HiActCnt 0D4 read; F X XXXXXXXnumber of blocks having high activity NullErrSum 0D5 read; F X XXXXXXXsum of errors for the null candidate over the complete ﬁeld; when no

ADDRESS

(HEX)

READ/

WRITE

76543210 DESCRIPTION

(1)

into protection mode

section. Each section is represented with 2 bits in this register, where bits 0 and 1 represent the top section and bits 6 and 7 represent the lowest of the 4 sections. Each pair of bits indicate

00 = (ESR >3⁄4ESM), 01 =(1⁄2ESM < ESR ≤3⁄4ESM), 10 =(1⁄4ESM < ESR ≤1⁄2ESM), 11 = (ESR ≤1⁄4ESM).

null candidate is selected a value of FFH will be read

(2)

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

reduction and embedded memory

SAA4998H

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

Notes

1. S means semi static, used at initialization or mode changes; F means field frequent, in general updated in each display field.

2. Selectable items are marked bold.

3. Almost all of the R(ead) and W(rite) registers of SAA4998H are double buffered. The write registers are latched by a signal called New_field. New_field gets set, when REF rises after SNRST (New_field is effectively at the start of active video). The read registers are latched by a signal called Reg_upd. Reg_upd gets set, when half the number of active pixels of the fourth line of vertical blanking have entered the SAA4998H (Reg_upd will effectively be active 31⁄2lines after the REA has ended). The only exception are the registers which are not double buffered, these are as follows:

a) Write register 025H: power_on_reset b) Write register 02FH, bit 1: CndSet c) Read register 0B0H to 0BFH, 0AEH and 0AFH: pan_zoom_vectors, including FalconIdent (= 0), StatusJump0

and StatusJump1.

8 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

V V V V V V V I T T V

DDD DDA DDM DDS DDE DDP i

stg j esd

core supply voltage (internal rail) −0.5 +2.5 V analog supply voltage ﬁeld memory supply voltage SRAM supply voltage external supply voltage (output pads) −0.5 +4.6 V high supply voltage of internal ﬁeld memories input voltage of all I/O pins −0.5 +6

(1)

V output current − 4mA storage temperature −40 +125 °C junction temperature 0 125 °C electrostatic discharge voltage on all pins MM; note 2 −400 +400 V

HBM; note 3 −3000 +3000 V

Notes

1. Only valid, if V

2. In accordance with

is present.

DDE

“Transient energy (ESD machine model); SNW-FQ-302B”

class C, discharging a 200 pF

capacitor via a 0.75 µH series inductance.

3. In accordance with

“Transient energy (ESD human body model); SNW-FQ-302A”

class 2, discharging a 100 pF

capacitor via a 1.5 kΩ series resistor.

9 THERMAL CHARACTERISTICS

SYMBOL PARAMETER CONDITIONS VALUE UNIT

R R

th(j-a) th(j-c)

thermal resistance from junction to ambient in free air 45 K/W thermal resistance from junction to case 10 K/W

2004 Feb 18 29

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

10 CHARACTERISTICS

= 3.0 to 3.6 V; T

DDE

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V V V V V V

DDD DDA DDM DDS DDE DDP

memories

sum of supply current

at 1.8 V supply voltage pins − 180 − mA at 3.3 V supply voltage pins − 6 − mA

General

HIGH-level output voltage V LOW-level output voltage −−0.4 V HIGH-level input voltage 2 −−V LOW-level input voltage −−0.8 V HIGH-level output current 10 ns slew rate output;

LOW-level output current 10 ns slew rate output;

input capacitance −−8pF

input leakage current note 1 −−1 µA Outputs; see Fig.5; note 2 I

t t

OZ d(o) h(o)

output current in 3-state mode −0.5<Vo< 3.6 −−1 µA

output delay time −−23 ns

output hold time 4 −−ns

Inputs

su(i)

h(i)

rise time −−30 ns

fall time −−30 ns

input set-up time see Fig.5; note 3 6 −−ns

input hold time see Fig.5; note 3 2 −−ns Input CLK32; see Fig.5 t

rise time −−4ns

fall time −−4ns δ duty factor 40 − 60 % T

cycle time 30 − 39 ns

=0to70°C; unless otherwise speciﬁed.

amb

VOH=V

VOL= 0.4 V

DDE

− 0.4 V

− 0.4 −−V

DDE

−4 −−mA

−−4mA

2004 Feb 18 30

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

BST interface; see Fig.6

cy(BST)

su(i)(BST)

h(i)(BST)

h(o)(BST)

d(o)(BST)

SNERT interface; see Fig.7 t

SNRST(H)

d(SNRST-SNCL)

cy(SNCL)

su(i)(SNCL)

h(i)(SNCL)

h(o)

d(o)

o(en)

Notes

1. All inputs except inputs with internal pull-up or pull-down resistor. These inputs have an absolute leakage current of maximum 50 µA.

2. Timing characteristics are measured with CL=15pF.

3. All inputs except SNERT interface inputs, CLK32 input and BST/TEST inputs.

BST cycle time − 1 −µs input set-up time 3 −−ns input hold time 6 −−ns output hold time 4 −−ns output delay −−30 ns

SNRST pulse HIGH time 500 −−ns delay SNRST pulse to SNCL LOW

200 −−ns

time SNCL cycle time 0.5 − 1 µs input set-up time to SNCL 53 −−ns input hold time to SNCL 10 −−ns output hold time 30 −−ns output delay −−330 ns output enable time 210 −−ns

stable power supply

CLK32

RST

Fig.4 Timing for RST input.

2004 Feb 18 31

≥10 cycles of CLK32

coc003

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise reduction and embedded memory

handbook, full pagewidth

h(i)

h(o)

90%

10%

data transition

CLOCK

INPUT

DATA

OUTPUT

DATA

su(i)

data valid

d(o)

period

10%

90%

SAA4998H

1.5 V

MHB175

handbook, full pagewidth

TCK

TDI, TMS

TDO

Fig.5 Data input/output timing diagram.

su(i)(BST)

h(o)(BST)

h(i)(BST)

d(o)(BST)

cy(BST)

MHB649

Fig.6 Boundary scan test interface timing diagram.

2004 Feb 18 32

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise reduction and embedded memory

SNCL

write sequence:

SNDA

read sequence:

SNDA driven by master

SNDA driven by SAA4998H

SNCL

write sequence:

SNDA

a0 a1 a2 a3 a4 a5 a6 a7 w0 w1 w2 w3 w4 w5 w6 w7

a1 a2 a3 a4 a5 a6 a7

50 %

su(i)(SNCL)

h(i)(SNCL)

a7 w0 w1

SAA4998H

r0 r1 r2 r3 r4 r5 r6 r7

50 % 50 %

read sequence:

SNDA driven by master

SNDA driven by SAA4998H

o(en)

d(o)

Fig.7 SNERT interface timing diagram.

90 %

10 %

h(o)

r0 r1

d(o)

coc004

2004 Feb 18 33

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

Table 1 YUV formats

I/O PIN

(1)

4:1:1 4:2:2 4:2:2 DPCM

Yx7 Y07 Y17 Y27 Y37 Y07 Y17 Y07 Y17 Yx6 Y06 Y16 Y26 Y36 Y06 Y16 Y06 Y16 Yx5 Y05 Y15 Y25 Y35 Y05 Y15 Y05 Y15 Yx4 Y04 Y14 Y24 Y34 Y04 Y14 Y04 Y14 Yx3 Y03 Y13 Y23 Y33 Y03 Y13 Y03 Y13 Yx2 Y02 Y12 Y22 Y32 Y02 Y12 Y02 Y12 Yx1 Y01 Y11 Y21 Y31 Y01 Y11 Y01 Y11

Yx0 Y00 Y10 Y20 Y30 Y00 Y10 Y00 Y10 UVx7 U07 U05 U03 U01 U07 V07 UC03 VC03 UVx6 U06 U04 U02 U00 U06 V06 UC02 VC02 UVx5 V07 V05 V03 V01 U05 V05 UC01 VC01 UVx4 V06 V04 V02 V00 U04 V04 UC00 VC00 UVx3 X X X X U03 V03 X X UVx2 X X X X U02 V02 X X UVx1 X X X X U01 V01 X X UVx0 X X X X U00 V00 X X

FORMAT

(2)(3)

Notes

1. Digit x refers to different I/O buses: a) A = input from 1st field memory b) F = main output c) G = 2nd output for matrix purposes.

2. The first index digit defines the sample number and the second defines the bit number.

3. X = don’t care or not available.

2004 Feb 18 34

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise reduction and embedded memory

11 PACKAGE OUTLINE

QFP100: plastic quad flat package; 100 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm

80 51

SAA4998H

SOT317-2

pin 1 index

100

0.25

0.40

0.25

DIMENSIONS (mm are the original dimensions)

max.

3.2

0.25

0.05

2.90

2.65

UNIT A1A2A3bpcE

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0 5 10 mm

(1)

(1) (1)(1)

20.1

0.25

0.14

19.9

14.1

13.9

scale

eHELL

24.2

0.65

23.6

18.2

17.6

1.0

0.6

detail X

Zywv θ

0.8

0.15 0.10.21.95

0.4

1.0

0.6

(A )

OUTLINE VERSION

SOT317-2 MO-112

IEC JEDEC JEITA

REFERENCES

2004 Feb 18 35

EUROPEAN

PROJECTION

ISSUE DATE

99-12-27 03-02-25

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise reduction and embedded memory

12 SOLDERING

12.1 Introduction to soldering surface mount

packages

Thistextgives a very brief insight to a complextechnology. A more in-depth account of soldering ICs can be found in our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011). There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for certainsurfacemountICs,but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.

12.2 Reﬂow soldering

Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied tothe printed-circuit board by screenprinting,stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing.

Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.

Typical reflow peak temperatures range from 215 to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:

• below 225 °C (SnPb process) or below 245 °C (Pb-free

process) – for all BGA, HTSSON-T and SSOP-T packages – for packages with a thickness ≥ 2.5 mm – for packages with a thickness < 2.5 mm and a

volume ≥ 350 mm3 so called thick/large packages.

• below 240 °C (SnPb process) or below 260 °C (Pb-free

process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages.

Moisture sensitivity precautions, as indicated on packing, must be respected at all times.

SAA4998H

To overcome these problems the double-wave soldering method was specifically developed.

If wave soldering is used the following conditions must be observed for optimal results:

• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave.

• For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the printed-circuit board.

The footprint must incorporate solder thieves at the downstream end.

• Forpackageswithleadson four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.

During placement and before soldering, thepackage must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.

Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively.

A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.

12.4 Manual soldering

Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.

When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C.

12.3 Wave soldering

Conventional single wave soldering is not recommended forsurfacemountdevices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.

2004 Feb 18 36

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

12.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

(1)

(3)

, TFBGA,

not suitable suitable

BGA, HTSSON..T

PACKAGE

(3)

, LBGA, LFBGA, SQFP, SSOP..T

USON, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON,

not suitable

HTQFP, HTSSOP, HVQFN, HVSON, SMS

(5)

PLCC

, SO, SOJ suitable suitable LQFP, QFP, TQFP not recommended SSOP, TSSOP, VSO, VSSOP not recommended CWQCCN..L

(8)

, PMFP

(9)

, WQCCN..L

(8)

not suitable not suitable

Notes

1. Formore detailed information on the BGApackagesrefer to the

“(LF)BGAApplication Note

from your Philips Semiconductors sales office.

2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.

4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface.

5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners.

6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than

0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request.

9. Hot bar or manual soldering is suitable for PMFP packages.

SOLDERING METHOD

WAVE REFLOW

(4)

(5)(6) (7)

suitable

suitable suitable

”(AN01026); order a copy

(2)

12.6 Additional soldering information

The package QFP100 (lead-free; SOT317GC11, subpackage of the SOT317-2) is granted the Moisture Sensitivity Level (MSL) 3.

Soldering temperature of > 215 °C is recommended or RMA flux.

2004 Feb 18 37

Philips Semiconductors Product speciﬁcation

Field and line rate converter with noise

SAA4998H

reduction and embedded memory

13 DATA SHEET STATUS

LEVEL

I Objective data Development This data sheet contains data from the objective speciﬁcation for product

II Preliminary data Qualiﬁcation This data sheet contains data from the preliminary speciﬁcation.

III Product data Production This data sheet contains data from the product speciﬁcation. Philips

Notes

1. Please consult the most recently issued data sheet before initiating or completing a design.

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was

3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

DATA SHEET

STATUS

published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

(1)

PRODUCT

STATUS

(2)(3)

development. Philips Semiconductors reserves the right to change the speciﬁcation in any manner without notice.

Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the speciﬁcation without notice, in order to improve the design and supply the best possible product.

Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notiﬁcation (CPCN).

DEFINITION

14 DEFINITIONS Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook.

Limiting values definition  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device attheseor at any other conditions above thosegiveninthe Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make norepresentationorwarrantythatsuchapplicationswillbe suitable for the specified use without further testing or modification.

15 DISCLAIMERS Life support applications  These products are not

designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected toresult in personalinjury. Philips Semiconductorscustomersusingorsellingtheseproducts for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes  Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product isin full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

2004 Feb 18 38

Philips Semiconductors – a w orldwide compan y

Contact information

For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales ofﬁces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.

Printed in The Netherlands R24/01/pp39 Date of release: 2004 Feb 18 Document order number: 9397 750 12217

SCA76

Philips SAA4998H Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

1 FEATURES

2 GENERAL DESCRIPTION

2.1 Patent notice

3 QUICK REFERENCE DATA

2.2 Latch-up test

4 ORDERING INFORMATION

5 BLOCK DIAGRAMS

6 PINNING

7 CONTROL REGISTER DESCRIPTION

8 LIMITING VALUES

9 THERMAL CHARACTERISTICS

10 CHARACTERISTICS

11 PACKAGE OUTLINE

12 SOLDERING

12.4 Manual soldering

12.3 Wave soldering

12.6 Additional soldering information

13 DATA SHEET STATUS

14 DEFINITIONS Short-form specification  The data in a short-form

15 DISCLAIMERS Life support applications  These products are not