Philips PCF8576CU-5-F1, PCF8576CU-7-F1, PCF8576CU-F1, PCF8576CU-10-F1, PCF8576CU-12-F1 Datasheet

DATA SH EET

Product specification
Supersedes data of 1997 Nov 14
File under Integrated Circuits, IC12

1998 Jul 30

INTEGRATED CIRCUITS

PCF8576C

Universal LCD driver for low
multiplex rates

1998 Jul 30 2

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 BLOCK DIAGRAM
5 PINNING
6 FUNCTIONAL DESCRIPTION

6.1 Power-on reset

6.2 LCD bias generator

6.3 LCD voltage selector

6.4 LCD drive mode waveforms

6.4.1 Static drive mode

6.4.2 1 : 2 multiplex drive mode

6.4.3 1 : 3 multiplex drive mode

6.4.4 1 : 4 multiplex drive mode

6.5 Oscillator

6.5.1 Internal clock

6.5.2 External clock

6.6 Timing

6.7 Display latch

6.8 Shift register

6.9 Segment outputs

6.10 Backplane outputs

6.11 Display RAM

6.12 Data pointer

6.13 Subaddress counter

6.14 Output bank selector

6.15 Input bank selector

6.16 Blinker
7 CHARACTERISTICS OF THE I2C-BUS

7.1 Bit transfer (see Fig.12)

7.2 Start and stop conditions (see Fig.13)

7.3 System configuration (see Fig.14)

7.4 Acknowledge (see Fig.15)

7.5 PCF8576C I2C-bus controller

7.6 Input filters

7.7 I2C-bus protocol

7.8 Command decoder

7.9 Display controller

7.10 Cascaded operation

8 LIMITING VALUES
9 HANDLING
10 DC CHARACTERISTICS
11 AC CHARACTERISTICS

11.1 Typical supply current characteristics

11.2 Typical characteristics of LC D outputs
12 APPLICATION INFORMATION

12.1 Chip-on-glass cascadability in single plane
13 BONDING PAD LOCATIONS
14 PACKAGE OUTLINES
15 SOLDERING

15.1 Introduction

15.2 Reflow soldering

15.3 Wave soldering

15.3.1 LQFP

15.3.2 VSO

15.3.3 Method (LQFP and VSO)

15.4 Repairing soldered joints
16 DEFINITIONS
17 LIFE SUPPORT APPLICATIONS
18 PURCHASE OF PHILIPS I2C COMPONENTS

1998 Jul 30 3

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

1 FEATURES

• Single-chip LCD controller/driver

• Selectable backplane drive configuration: static or 2/3/4

backplane multiplexing

• Selectable display bias configuration: static, 1/2 or 1/3

• Internal LCD bias generation with voltage-follower

buffers

• 40 segment drives: up to twenty 8-segment numeric
characters; up to ten 15-segment alphanumeric
characters; or any graphics of up to 160 elements

• 40 × 4-bit RAM for display data storage

• Auto-incremented display data loading across device

subaddress boundaries

• Display memory bank switching in static and duplex
drive modes

• Versatile blinking modes

• LCD and logic supplies may be separated

• Wide power supply range: from 2 V for low-threshold

LCDs and up to 6 V for guest-host LCDs and
high-threshold (automobile) twisted nematic LCDs.

A 9 V version is also available on request.

• Low power consumption

• Power-saving mode for extremely low power

consumption in battery-operated and telephone
applications

• I

2

C-bus interface

• TTL/CMOS compatible

• Compatible with any 4-bit, 8-bit or 16-bit

microprocessors/microcontrollers

• May be cascaded for large LCD applications (up to
2560 segments possible)

• Cascadable with 24-segment LCD driver PCF8566

• Optimized pinning for plane wiring in both and multiple

PCF8576C applications

• Space-saving 56-lead plastic very small outline package
(VSO56) or 64-lead low profile quad flat package
(LQFP64)

• No external components

• Compatible with chip-on-glass technology

• Manufactured in silicon gate CMOS process.

2 GENERAL DESCRIPTION

The PCF8576C is a peripheral device which interfaces to
almost any Liquid Crystal Display (LCD) with low multiplex
rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up
to 40 segments and can easily be cascaded for larger LCD
applications. The PCF8576C is compatible with most
microprocessors/microcontrollers and communicates via a
two-line bidirectional I2C-bus. Communication overheads
are minimized by a display RAM with auto-incremented
addressing, by hardware subaddressing and by display
memory switching (static and duplex drive modes).

3 ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

PCF8576CT VSO56 plastic very small outline package; 56 leads SOT190-1
PCF8576CU − chip in tray −
PCF8576CU/2 − chip with bumps in tray −
PCF8576CU/5 − unsawn wafer −
PCF8576CU/7 − chip with bumps on tape −
PCF8576CU/10 FFC chip-on-film frame carrier −
PCF8576CU/12 FFC chip with bumps on film frame carrier −
PCF8576CH LQFP64 plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm SOT314-2

1998 Jul 30 4

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

rates

PCF8576C

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

4 BLOCK DIAGRAM

handbook, full pagewidth

MLD332

LCD

VOLTAGE

SELECTOR

V

LCD

12

V

DD

5

TIMING BLINKER

OSCILLATOR

INPUT

FILTERS

I C - BUS

CONTROLLER

2

POWER-

ON

RESET

CLK

4

SYNC

3

OSC

6

V

SS

11

SCL

2

SDA

1

SA0

10

DISPLAY

CONTROLLER

COMMAND

DECODER

BACKPLANE

OUTPUTS

13

BP014BP215BP116BP3

INPUT

BANK

SELECTOR

DISPLAY

RAM

40 x 4 BITS

OUTPUT

BANK

SELECTOR

DATA

POINTER

SUB­ADDRESS
COUNTER

DISPLAY SEGMENT OUTPUTS

DISPLAY LATCH

SHIFT REGISTER

17 to 56

S0 to S39

A07A18A2

9

PCF8576C

LCD BIAS

GENERATOR

40

Fig.1 Block diagram; VSO56.

1998 Jul 30 5

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

5 PINNING

SYMBOL

PIN

DESCRIPTION

SOT190 SOT314

SDA 1 10 I

2

C-bus serial data input/output

SCL 2 11 I

2

C-bus serial clock input
SYNC 3 12 cascade synchronization input/output
CLK 4 13 external clock input
V

DD

5 14 supply voltage
OSC 6 15 oscillator input
A0 to A2 7 to 9 16 to 18 I

2

C-bus subaddress inputs

SA0 10 19 I

2

C-bus slave address input; bit 0

V

SS

11 20 logic ground

V

LCD

12 21 LCD supply voltage
BP0, BP2, BP1, BP3 13 to 16 25 to 28 LCD backplane outputs
S0 to S39 17 to 56 29 to 32, 34 to 47, 49 to 64, 2 to 7 LCD segment outputs
n.c. − 1, 8, 9, 22 to 24, 33 and 48 not connected

1998 Jul 30 6

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

Fig.2 Pin configuration; VSO56.

handbook, halfpage

PCF8576CT

MLD334

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

SDA

SCL

SYNC

CLK

V

OSC

A0
A1
A2

SA0

V

V

BP0
BP2
BP1
BP3

S0
S1
S2
S3
S4
S5
S6
S7
S8

S9
S10
S11

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12

DD

SS

LCD

1998 Jul 30 7

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

handbook, full pagewidth

PCF8576CH

MLD333

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

n.c.
S34
S35
S36
S37
S38
S39

n.c.

n.c.

SDA

SCL

SYNC

CLK

V

OSC

A0

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

n.c.
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
n.c.

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

A1

A2

SA0

V

V

n.c.

n.c.

n.c.

BP0

BP2

BP1

BP3

S0

S1

S2

S3

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

S33

S32

S31

S30

S29

S28

S27

S26

S25

S24

S23

S22

S21

S20

S19

S18

DD

SS

LCD

Fig.3 Pin configuration; LQFP64.

1998 Jul 30 8

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

6 FUNCTIONAL DESCRIPTION

The PCF8576C is a versatile peripheral device designed
to interface to any microprocessor/microcontroller to a
wide variety of LCDs. It can directly drive any static or
multiplexed LCD containing up to four backplanes and up
to 40 segments. The display configurations possible with
the PCF8576C depend on the number of active backplane
outputs required; a selection of display configurations is
given in Table 1.

All of the display configurations given in Table 1 can be
implemented in the typical system shown in Fig.4.

The host microprocessor/microcontroller maintains the
2-line I

2

C-bus communication channel with the
PCF8576C. The internal oscillator is selected by tying
OSC (pin 6) to VSS (pin 11). The appropriate biasing
voltages for the multiplexed LCD waveforms are
generated internally. The only other connections required
to complete the system are to the power supplies (VDD,
VSS and V

LCD

) and the LCD panel chosen for the

application.

Table 1 Selection of display configurations

NUMBER OF 7-SEGMENTS NUMERIC

14-SEGMENTS

ALPHANUMERIC

DOT MATRIX

BACKPLANES SEGMENTS DIGITS

INDICATOR

SYMBOLS

CHARACTERS

INDICATOR

SYMBOLS

4 160 20 20 10 20 160 dots (4 × 40)
3 120 15 15 8 8 120 dots (3 × 40)
2 80 10 10 5 10 80 dots (2 × 40)
1 40 5 5 2 12 40 dots (1 × 40)

Fig.4 Typical system configuration.

handbook, full pagewidth

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

R

t

r

2C

B

SDA

SCL

OSC

1 17 to 56

13 to 16

2
6

78

512

91011

40 segment drives

4 backplanes

LCD PANEL

(up to 160

elements)

PCF8576CT

A0 A1 A2SSSA0 V

SS

V

DD

V

DD

V

LCD

V

MBE524

1998 Jul 30 9

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

6.1 Power-on reset

At power-on the PCF8576C resets to a starting condition
as follows:

1. All backplane outputs are set to VDD.

2. All segment outputs are set to VDD.

3. The drive mode ‘1 : 4 multiplex with1⁄3bias’ is selected.

4. Blinking is switched off.

5. Input and output bank selectors are reset (as defined
in Table 5).

6. The I2C-bus interface is initialized.

7. The data pointer and the subaddress counter are
cleared.

Data transfers on the I

2

C-bus should be avoided for 1 ms

following power-on to allow completion of the reset action.

6.2 LCD bias generator

The full-scale LCD voltage (V

op

) is obtained from

VDD− V

LCD

. The LCD voltage may be temperature

compensated externally through the V

LCD

supply to pin 12.
Fractional LCD biasing voltages are obtained from an
internal voltage divider of the three series resistors
connected between VDD and V

LCD

. The centre resistor can
be switched out of the circuit to provide a1⁄2bias voltage
level for the 1 : 2 multiplex configuration.

6.3 LCD voltage selector

The LCD voltage selector co-ordinates the multiplexing of
the LCD in accordance with the selected LCD drive
configuration. The operation of the voltage selector is
controlled by MODE SET commands from the command
decoder. The biasing configurations that apply to the
preferred modes of operation, together with the biasing
characteristics as functions of V

op=VDD

− V

LCD

and the

resulting discrimination ratios (D), are given in Table 2.
A practical value for Vop is determined by equating V

off(rms)

with a defined LCD threshold voltage (Vth), typically when
the LCD exhibits approximately 10% contrast. In the static
drive mode a suitable choice is Vop>3Vth approximately.

Multiplex drive ratios of 1 : 3 and 1 : 4 with

1

⁄2bias are

possible but the discrimination and hence the contrast
ratios are smaller ( = 1.732 for 1 : 3 multiplex or

= 1.528 for 1 : 4 multiplex).

The advantage of these modes is a reduction of the LCD
full-scale voltage V

op

as follows:

• 1 : 3 multiplex (

1

⁄2bias):

Vop= = 2.449 V

off(rms)

• 1 : 4 multiplex (1⁄2bias):

V

op

= = 2.309 V

off(rms)

These compare with Vop=3V

off(rms)

when1⁄3bias is used.

3

21
3

----------

6V

off rms〈〉

×

43×()

3

----------------------- -

Table 2 Preferred LCD drive modes: summary of characteristics

LCD DRIVE MODE

NUMBER OF

LCD BIAS

CONFIGURATION

BACKPLANES LEVELS

static 1 2 static 0 1 ∞

1:2 2 3

1

⁄

2

0.354 0.791 2.236

1:2 2 4

1

⁄

3

0.333 0.745 2.236

1:3 3 4

1

⁄

3

0.333 0.638 1.915

1:4 4 4

1

⁄

3

0.333 0.577 1.732

V

off(rms)

V

op

-------------------- -

V

on(rms)

V

op

-------------------- -

D

V

on(rms)

V

off(rms)

-------------------- -

=

1998 Jul 30 10

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

6.4 LCD drive mode waveforms

6.4.1 S

TATIC DRIVE MODE

The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive
waveforms for this mode are shown in Fig.5.

Fig.5 Static drive mode waveforms (Vop=VDD− V

LCD

).

V

state1

t() V

S

n

t() V

BP0

t()–=

V

on(rms)Vop

=

V

state2

t() V

S

n1+

t() V

BP0

t()–=

V

off(rms)

0V=

MBE539

V

DD

V

LCD

V

LCD

V

DD

V

LCD

V

op

V

op

state 1 0

BP0

S

n

S

n 1

V

op

V

op

state 2 0

(a) waveforms at driver

(b) resultant waveforms

at LCD segment

LCD segments

state 1

(on)

state 2

(off)

T

frame

V

DD

1998 Jul 30 11

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

6.4.2 1 : 2 MULTIPLEX DRIVE MODE
When two backplanes are provided in the LCD, the 1 : 2 multiplex mode applies. The PCF8576C allows use of1⁄2bias or

1

⁄3bias in this mode as shown in Figs 6 and 7.

Fig.6 Waveforms for the 1 : 2 multiplex drive mode with1⁄2bias (Vop=VDD− V

LCD

).

V

state1

t() V

S

n

t() V

BP0

t()–=

V

on(rms)

0.791V

op

=

V

state2

t() V

S

n

t() V

BP1

t()–=

V

off(rms)

0.354V

op

=

MBE540

V

(V )/2V

DD

V /2

op

V

op

state 1 0

BP0

S

n 1

(a) waveforms at driver

(b) resultant waveforms

at LCD segment

LCD segments

state 2

T

frame

DD LCD

V

LCD

BP1

S

n

V

op

V /2

op

V /2

op

V

op

state 2

0

V

op

V /2

op

state 1

V

(V )/2V

DD
DD

LCD

V

LCD

V

LCD

V

LCD

V

DD

V

DD

1998 Jul 30 12

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

Fig.7 Waveforms for the 1 : 2 multiplex drive mode with1⁄3bias (Vop=VDD− V

LCD

).

V

state1

t() V

S

n

t() V

BP0

t()–=

V

on(rms)

0.745V

op

=

V

state2

t() V

S

n

t() V

BP1

t()–=

V

off(rms)

0.333V

op

=

MBE541

V

DD

2V /3

op

V

op

state 1 0

BP0

S

n 1

(a) waveforms at driver

(b) resultant waveforms

at LCD segment

LCD segments

state 2

T

frame

V V /3

DD

op

V

LCD

BP1

S

n

V

op

state 1

V 2V /3

DD

op

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

V /3

op

2V /3

op

V /3

op

2V /3

op

V

op

state 2 0

V

op

V /3

op

2V /3

op

V /3

op

1998 Jul 30 13

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

6.4.3 1 : 3 MULTIPLEX DRIVE MODE
When three backplanes are provided in the LCD, the 1 : 3 multiplex drive mode applies, as shown in Fig.8.

Fig.8 Waveforms for the 1 : 3 multiplex drive mode (Vop=VDD− V

LCD

).

V

state1

t() V

S

n

t() V

BP0

t()–=

V

on(rms)

0.638V

op

=

V

state2

t() V

S

n

t() V

BP1

t()–=

V

off(rms)

0.333V

op

=

MBE542

2V /3

op

V

op

state 1 0

BP0

(b) resultant waveforms

at LCD segment

LCD segments

state 2

T

frame

BP1

V

op

state 1

V /3

op

2V /3

op

V /3

op

2V /3

op

V

op

state 2 0

V

op

V /3

op

2V /3

op

V /3

op

S

n 1

S

n 2

(a) waveforms at driver

S

n

BP2/S23

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

1998 Jul 30 14

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

6.4.4 1 : 4 MULTIPLEX DRIVE MODE
When four backplanes are provided in the LCD, the 1 : 4 multiplex drive mode applies, as shown in Fig.9.

MBE543

2V /3

op

V

op

state 1 0

BP0

(b) resultant waveforms

at LCD segment

LCD segments

state 2

T

frame

BP1

V

op

state 1

V /3

op

2V /3

op

V /3

op

2V /3

op

V

op

state 2 0

V

op

V /3

op

2V /3

op

V /3

op

S

n 1

BP2

S

n 2

S

n 3

(a) waveforms at driver

S

n

BP3

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

V

DD

V V /3

DD

op

V

LCD

V 2V /3

DD

op

Fig.9 Waveforms for the 1 : 4 multiplex drive mode (Vop=VDD− V

LCD

).

V

state1

t() V

S

n

t() V

BP0

t()–=

V

on(rms)

0.577V

op

=

V

state2

t() V

S

n

t() V

BP1

t()–=

V

off(rms)

0.333V

op

=

1998 Jul 30 15

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

6.5 Oscillator

6.5.1 I

NTERNAL CLOCK

The internal logic and the LCD drive signals of the
PCF8576C are timed either by the built-in oscillator or from
an external clock. When the internal oscillator is used,
OSC (pin 6) should be connected to VSS (pin 11). In this
event, the output from CLK (pin 4) provides the clock
signal for cascaded PCF8566s or PCF8576Cs in the
system.

Note that the PCF8576C is backwards compatible with the
PCF8576. Where resistor R

osc

to VSS is present, the

internal oscillator is selected.

6.5.2 E

XTERNAL CLOCK

The condition for external clock is made by tying OSC
(pin 6) to VDD; CLK (pin 4) then becomes the external
clock input.

The clock frequency (f

clk

) determines the LCD frame
frequency and the maximum rate for data reception from
the I2C-bus. To allow I2C-bus transmissions at their
maximum data rate of 100 kHz, f

clk

should be chosen to be

above 125 kHz.
A clock signal must always be supplied to the device;

removing the clock may freeze the LCD in a DC state.

6.6 Timing

The timing of the PCF8576C organizes the internal data
flow of the device. This includes the transfer of display data
from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal

SYNC
maintains the correct timing relationship between the
PCF8576Cs in the system. The timing also generates the
LCD frame frequency which it derives as an integer
multiple of the clock frequency (see Table 3). The frame
frequency is set by the MODE SET commands when
internal clock is used, or by the frequency applied to pin 4
when external clock is used.

The ratio between the clock frequency and the LCD frame
frequency depends on the mode in which the device is
operating. In the power-saving mode the reduction ratio is
six times smaller; this allows the clock frequency to be
reduced by a factor of six. The reduced clock frequency
results in a significant reduction in power dissipation.
The lower clock frequency has the disadvantage of
increasing the response time when large amounts of
display data are transmitted on the I2C-bus.

When a device is unable to digest a display data byte
before the next one arrives, it holds the SCL line LOW until
the first display data byte is stored. This slows down the
transmission rate of the I

2

C-bus but no data loss occurs.

6.7 Display latch

The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and one column of the
display RAM.

6.8 Shift register

The shift register serves to transfer display information
from the display RAM to the display latch while previous
data is displayed.

6.9 Segment outputs

The LCD drive section includes 40 segment outputs
S0 to S39 (pins 17 to 56) which should be connected
directly to the LCD. The segment output signals are
generated in accordance with the multiplexed backplane
signals and with data resident in the display latch. When
less than 40 segment outputs are required the unused
segment outputs should be left open-circuit.

6.10 Backplane outputs

The LCD drive section includes four backplane outputs
BP0 to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than
four backplane outputs are required the unused outputs
can be left open-circuit. In the 1 : 3 multiplex drive mode
BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced
drive capabilities. In the 1 : 2 multiplex drive mode BP0
and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.

1998 Jul 30 16

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

6.11 Display RAM

The display RAM is a static 40 × 4-bit RAM which stores
LCD data. A logic 1 in the RAM bit-map indicates the on
state of the corresponding LCD segment; similarly, a
logic 0 indicates the off state. There is a one-to-one
correspondence between the RAM addresses and the
segment outputs, and between the individual bits of a RAM
word and the backplane outputs. The first RAM column
corresponds to the 40 segments operated with respect to
backplane BP0 (see Fig.10). In multiplexed LCD
applications the segment data of the second, third and
fourth column of the display RAM are time-multiplexed
with BP1, BP2 and BP3 respectively.

When display data is transmitted to the PCF8576C the
display bytes received are stored in the display RAM in
accordance with the selected LCD drive mode.
To illustrate the filling order, an example of a 7-segment
numeric display showing all drive modes is given in Fig.11;
the RAM filling organization depicted applies equally to
other LCD types.

With reference to Fig.11, in the static drive mode the eight
transmitted data bits are placed in bit 0 of eight successive
display RAM addresses.

In the 1 : 2 multiplex drive mode the eight transmitted data
bits are placed in bits 0 and 1 of four successive display
RAM addresses. In the 1 : 3 multiplex drive mode these
bits are placed in bits 0, 1 and 2 of three successive
addresses, with bit 2 of the third address left unchanged.
This last bit may, if necessary, be controlled by an
additional transfer to this address but care should be taken
to avoid overriding adjacent data because full bytes are
always transmitted. In the 1 : 4 multiplex drive mode the
eight transmitted data bits are placed in bits 0, 1, 2 and 3
of two successive display RAM addresses.

Table 3 LCD frame frequencies

PCF8576C MODE

FRAME

FREQUENCY

NOMINAL

FRAME

FREQUENCY

(Hz)

Normal mode

64

Power-saving mode

64

f

clk

2880

------------ -

f

clk

480

--------- -

Fig.10 Display RAM bit-map showing direct relationship between display RAM addresses

and segment outputs, and between bits in a RAM word and backplane outputs.

0

0
1
2
3

1234 3536373839

display RAM addresses (rows) / segment outputs (S)

display RAM bits

(columns) /

backplane outputs

(BP)

MBE525

1998 Jul 30 17

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

6.12 Data pointer

The addressing mechanism for the display RAM is
realized using the data pointer. This allows the loading of
an individual display data byte, or a series of display data
bytes, into any location of the display RAM. The sequence
commences with the initialization of the data pointer by the
LOAD DATA POINTER command. Following this, an
arriving data byte is stored starting at the display RAM
address indicated by the data pointer thereby observing
the filling order shown in Fig.11. The data pointer is
automatically incremented in accordance with the chosen
LCD configuration. That is, after each byte is stored, the
contents of the data pointer are incremented by eight
(static drive mode), by four (1 : 2 multiplex drive mode) or
by two (1 : 4 multiplex drive mode).

6.13 Subaddress counter

The storage of display data is conditioned by the contents
of the subaddress counter. Storage is allowed to take
place only when the contents of the subaddress counter
agree with the hardware subaddress applied to
A0, A1 and A2. The subaddress counter value is defined
by the DEVICE SELECT command. If the contents of the
subaddress counter and the hardware subaddress do not
agree then data storage is inhibited but the data pointer is
incremented as if data storage had taken place.
The subaddress counter is also incremented when the
data pointer overflows.

The storage arrangements described lead to extremely
efficient data loading in cascaded applications. When a
series of display bytes are sent to the display RAM,
automatic wrap-over to the next PCF8576C occurs when
the last RAM address is exceeded. Subaddressing across
device boundaries is successful even if the change to the
next device in the cascade occurs within a transmitted
character (such as during the 14th display data byte
transmitted in 1 : 3 multiplex mode).

6.14 Output bank selector

This selects one of the four bits per display RAM address
for transfer to the display latch. The actual bit chosen
depends on the particular LCD drive mode in operation
and on the instant in the multiplex sequence.
In 1 : 4 multiplex, all RAM addresses of bit 0 are the first to
be selected, these are followed by the contents of
bit 1, bit 2 and then bit 3. Similarly in 1 : 3 multiplex,
bits 0, 1 and 2 are selected sequentially. In 1 : 2 multiplex,
bits 0 and 1 are selected and, in the static mode, bit 0 is
selected.

The PCF8576C includes a RAM bank switching feature in
the static and 1 : 2 multiplex drive modes. In the static
drive mode, the BANK SELECT command may request
the contents of bit 2 to be selected for display instead of
bit 0 contents. In the 1 : 2 drive mode, the contents of
bits 2 and 3 may be selected instead of bits 0 and 1. This
gives the provision for preparing display information in an
alternative bank and to be able to switch to it once it is
assembled.

6.15 Input bank selector

The input bank selector loads display data into the display
RAM in accordance with the selected LCD drive
configuration. Display data can be loaded in bit 2 in static
drive mode or in bits 2 and 3 in 1 : 2 drive mode by using
the BANK SELECT command. The input bank selector
functions independent of the output bank selector.

1998 Jul 30 18

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

6.16 Blinker

The display blinking capabilities of the PCF8576C are very
versatile. The whole display can be blinked at frequencies
selected by the BLINK command. The blinking frequencies
are integer multiples of the clock frequency; the ratios
between the clock and blinking frequencies depend on the
mode in which the device is operating, as shown in
Table 4.

An additional feature is for an arbitrary selection of LCD
segments to be blinked. This applies to the static and
1 : 2 LCD drive modes and can be implemented without
any communication overheads.

By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the
blinking frequency. This mode can also be specified by the
BLINK command.

In the 1 : 3 and 1 : 4 multiplex modes, where no alternate
RAM bank is available, groups of LCD segments can be
blinked by selectively changing the display RAM data at
fixed time intervals.

If the entire display is to be blinked at a frequency other
than the nominal blinking frequency, this can be effectively
performed by resetting and setting the display enable bit E
at the required rate using the MODE SET command.

Table 4 Blinking frequencies

BLINKING MODE

NORMAL OPERATING

MODE RATIO

POWER-SAVING MODE

RATIO

NOMINAL BLINKING

FREQUENCY

Off −−blinking off

2Hz

2Hz

1Hz

1Hz

0.5 Hz

0.5 Hz

f

clk

92160

----------------

f

clk

15360

----------------

f

clk

84320

------------------ -

f

clk

30720

----------------

f

clk

368640

------------------- -

f

clk

61440

----------------

1998 Jul 30 19

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

rates

PCF8576C

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

handbook, full pagewidth

MBE534

S

2

n

S

1

n

S

7

n

S

n

S

n

S

3

n

S

5

n

S

2

n

S

3

n

S

1

n

S

1

n

S

1

n

S

2

n

S

n

S

6

n

S

n

S

4

n

DP

DP

DP

DP

a

f

b

g

e

c

d

a

f

b

g

e

c

d

a

f

b

g

e

c

d

a

f

b

g

e

c

d

BP0

BP0

BP0

BP1

BP1

BP2

BP1

BP2

BP3

BP0

n

c
x
x
x

0
1
2
3

b
x
x
x

a
x
x
x

f
x
x
x

g
x
x
x

e
x
x
x

d
x
x
x

DP

x
x
x

n1

n2 n3 n4 n5 n6 n7

bit/
BP

n

a
b
x
x

0
1
2
3

f
g
x
x

e
c
x
x

d

DP

x
x

n1

n2 n3

bit/
BP

n

b

DP

c
x

0
1
2
3

a
d
g
x

f
e
x
x

n1

n2

bit/
BP

n

a
c
b

DP

0
1
2
3

f
e
g
d

n1

bit/
BP

cbaf gedDP

abf gecdDP

bDPcadgf e

acbDPf egd

MSB LSB

MSB LSB

MSB LSB

MSB LSB

drive mode

static

1 : 2

multiplex

1 : 3

multiplex

1 : 4

multiplex

LCD segments LCD backplanes display RAM filling order transmitted display byte

Fig.11 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus.

x = data bit unchanged.

1998 Jul 30 20

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

7 CHARACTERISTICS OF THE I2C-BUS

The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not
busy.

7.1 Bit transfer (see Fig.12)
One data bit is transferred during each clock pulse.

The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal.

7.2 Start and stop conditions (see Fig.13)
Both data and clock lines remain HIGH when the bus is not

busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P).

7.3 System configuration (see Fig.14)
A device generating a message is a ‘transmitter’, a device

receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’.

7.4 Acknowledge (see Fig.15)
The number of data bytes transferred between the START

and STOP conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.

7.5 PCF8576C I

2

C-bus controller

The PCF8576C acts as an I2C-bus slave receiver. It does
not initiate I2C-bus transfers or transmit data to an I2C-bus
master receiver. The only data output from the PCF8576C
are the acknowledge signals of the selected devices.
Device selection depends on the I2C-bus slave address,
on the transferred command data and on the hardware
subaddress.

In single device application, the hardware subaddress
inputs A0, A1 and A2 are normally tied to VSS which
defines the hardware subaddress 0. In multiple device
applications A0, A1 and A2 are tied to VSS or VDD in
accordance with a binary coding scheme such that no two
devices with a common I2C-bus slave address have the
same hardware subaddress.

In the power-saving mode it is possible that the PCF8576C
is not able to keep up with the highest transmission rates
when large amounts of display data are transmitted. If this
situation occurs, the PCF8576C forces the SCL line LOW
until its internal operations are completed. This is known
as the ‘clock synchronization feature’ of the I2C-bus and
serves to slow down fast transmitters. Data loss does not
occur.

7.6 Input filters

To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.

7.7 I

2

C-bus protocol

Two I2C-bus slave addresses (0111000 and 0111001) are
reserved for the PCF8576C. The least significant bit of the
slave address that a PCF8576C will respond to is defined
by the level tied at its input SA0 (pin 10). Therefore, two
types of PCF8576C can be distinguished on the same
I2C-bus which allows:

1. Up to 16 PCF8576Cs on the same I2C-bus for very
large LCD applications.

2. The use of two types of LCD multiplex on the same
I2C-bus.

The I2C-bus protocol is shown in Fig.16. The sequence is
initiated with a START condition (S) from the I2C-bus
master which is followed by one of the two PCF8675C
slave addresses available. All PCF8576Cs with the
corresponding SA0 level acknowledge in parallel with the
slave address but all PCF8576Cs with the alternative SA0
level ignore the whole I2C-bus transfer.

1998 Jul 30 21

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

After acknowledgement, one or more command bytes (m)
follow which define the status of the addressed
PCF8576Cs.

The last command byte is tagged with a cleared most
significant bit, the continuation bit C. The command bytes
are also acknowledged by all addressed PCF8576Cs on
the bus.

After the last command byte, a series of display data bytes
(n) may follow. These display bytes are stored in the
display RAM at the address specified by the data pointer
and the subaddress counter. Both data pointer and
subaddress counter are automatically updated and the
data is directed to the intended PCF8576C device.
The acknowledgement after each byte is made only by the
(A0, A1 and A2) addressed PCF8576C. After the last
display byte, the I2C-bus master issues a STOP
condition (P).

7.8 Command decoder

The command decoder identifies command bytes that
arrive on the I

2

C-bus. All available commands carry a
continuation bit C in their most significant bit position
(Fig.17). When this bit is set, it indicates that the next byte
of the transfer to arrive will also represent a command.
If this bit is reset, it indicates the last command byte of the
transfer. Further bytes will be regarded as display data.

The five commands available to the PCF8576C are
defined in Table 5.

Fig.12 Bit transfer.

MBA607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig.13 Definition of START and STOP conditions.

handbook, full pagewidth

MBC622

SDA

SCL

P

STOP condition

SDA

SCL

S

START condition

1998 Jul 30 22

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

Fig.14 System configuration.

MGA807

SDA

SCL

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

SLAVE

TRANSMITTER/

RECEIVER

SLAVE

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

Fig.15 Acknowledgement on the I2C-bus.

handbook, full pagewidth

MBC602

S

START

condition

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

1998 Jul 30 23

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

Fig.16 I2C-bus protocol.

handbook, full pagewidth

MBE538

S
A
0

S

011100 0AC

COMMAND

A

P

ADISPLAY DATA

slave address

/RW

acknowledge by

all addressed

PCF8576Cs

acknowledge

by A0, A1 and A2

selected

PCF8576C only

n 0 byte(s)n 1 byte(s)1 byte

update data pointers

and if necessary,

subaddress counter

Fig.17 General format of command byte.

MSA833

REST OF OPCODE

C

MSB LSB

C = 0; last command.
C = 1; commands continue.

1998 Jul 30 24

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

Table 5 Definition of PCF8576C commands

COMMAND OPCODE OPTIONS DESCRIPTION

MODE SET C 1 0 LP E B M1 M0 Table 6 Defines LCD drive mode.

Table 7 Defines LCD bias configuration.
Table 8 Defines display status. The possibility to

disable the display allows implementation
of blinking under external control.

Table 9 Defines power dissipation mode.

LOAD DATA
POINTER

C 0 P5 P4 P3 P2 P1 P0 Table 10 Six bits of immediate data, bits P5 to P0,

are transferred to the data pointer to
define one of forty display RAM
addresses.

DEVICE
SELECT

C1100A2A1A0Table 11 Three bits of immediate data, bits A0 to

A3, are transferred to the subaddress
counter to define one of eight hardware
subaddresses.

BANK
SELECT

C11110IOTable 12 Defines input bank selection (storage of

arriving display data).

Table 13 Defines output bank selection (retrieval of

LCD display data).
The BANK SELECT command has no

effect in 1 : 3 and 1 : 4 multiplex drive
modes.

BLINK C 1110ABF1BF0Table 14 Defines the blinking frequency.

Table 15 Selects the blinking mode; normal

operation with frequency set by BF1, BF0
or blinking by alternation of display RAM
banks. Alternation blinking does not apply
in 1 : 3 and 1 : 4 multiplex drive modes.

Table 6 Mode set option 1

Table 7 Mode set option 2

LCD DRIVE MODE BITS

DRIVE
MODE

BACKPLANE M1 M0

Static 1 BP 0 1
1 : 2 MUX (2 BP) 1 0
1 : 3 MUX (3 BP) 1 1
1 : 4 MUX (4 BP) 0 0

LCD BIAS BIT B

1

⁄3bias 0

1

⁄2bias 1

Table 8 Mode set option 3

Table 9 Mode set option 4

DISPLAY STATUS BIT E

Disabled (blank) 0
Enabled 1

MODE BIT LP

Normal mode 0
Power-saving mode 1

1998 Jul 30 25

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

Table 10 Load data pointer option 1

Table 11 Device select option 1

Table 12 Bank select option 1

Table 13 Bank select option 2

DESCRIPTION BITS

6 bit binary value of 0 to 39 P5 P4 P3 P2 P1 P0

DESCRIPTION BITS

3 bit binary value of 0 to 7 A0 A1 A2

STATIC 1 : 2 MUX BIT I

RAM bit 0 RAM bits 0 and 1 0
RAM bit 2 RAM bits 2 and 3 1

STATIC 1 : 2 MUX BIT O

RAM bit 0 RAM bits 0 and 1 0
RAM bit 2 RAM bits 2 and 3 1

Table 14 Blink option 1

Table 15 Blink option 2

BLINK FREQUENCY

BITS

BF1 BF0

Off 0 0
2Hz 0 1
1Hz 1 0

0.5 Hz 1 1

BLINK MODE BIT A

Normal blinking 0
Alternation blinking 1

7.9 Display controller

The display controller executes the commands identified
by the command decoder. It contains the status registers
of the PCF8576C and co-ordinates their effects.
The controller is also responsible for loading display data
into the display RAM as required by the filling order.

7.10 Cascaded operation

In large display configurations, up to 16 PCF8576Cs can
be distinguished on the same I

2

C-bus by using the 3-bit
hardware subaddress (A0, A1 and A2) and the
programmable I2C-bus slave address (SA0). When
cascaded PCF8576Cs are synchronized so that they can
share the backplane signals from one of the devices in the
cascade. Such an arrangement is cost-effective in large
LCD applications since the backplane outputs of only one
device need to be through-plated to the backplane
electrodes of the display. The other PCF8576Cs of the
cascade contribute additional segment outputs but their
backplane outputs are left open-circuit (Fig.18).

The

SYNC line is provided to maintain the correct
synchronization between all cascaded PCF8576Cs. This
synchronization is guaranteed after the power-on reset.
The only time that SYNC is likely to be needed is if
synchronization is accidentally lost (e.g. by noise in
adverse electrical environments; or by the definition of a
multiplex mode when PCF8576Cs with differing SA0
levels are cascaded). SYNC is organized as an
input/output pin; the output selection being realized as an
open-drain driver with an internal pull-up resistor.
A PCF8576C asserts the SYNC line at the onset of its last
active backplane signal and monitors the SYNC line at all
other times. Should synchronization in the cascade be
lost, it will be restored by the first PCF8675C to assert
SYNC. The timing relationship between the backplane
waveforms and the SYNC signal for the various drive
modes of the PCF8576C are shown in Fig.19.

For single plane wiring of packaged PCF8576Cs and
chip-on-glass cascading, see Chapter “Application
information”.

1998 Jul 30 26

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

Fig.18 Cascaded PCF8576C configuration.

handbook, full pagewidth

HOST

MICRO-

PROCESSOR/

MICRO-

CONTROLLER

SDA

SCL

CLK

OSC

SYNC

1

17 to 56

13,15,

14,16

13,15,

14,16

2
3
4
6

78

512

91011

40 segment drives

4 backplanes

40 segment drives

LCD PANEL

(up to 2560

elements)

PCF8576CT

A0 A1 A2SSSA0 V

SS

V

DD

V

LCD

V

DD

V

LCD

V

MBE533

SDA
SCL

SYNC

CLK
OSC

15 12
2
3
4

6

17 to 56

BP0 to BP3
(open-circuit)

A0 A1 A2 SAO V

SS

V

DDVLCD

PCF8576CT

BP0 to BP3

R

t

r

2C

B

1998 Jul 30 27

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

Fig.19 Synchronization of the cascade for the various PCF8576C drive modes.

Excessive capacitive coupling between SCL or CLK and SYNC may cause erroneous synchronization. If this proves to be a problem, the capacitance of
the

SYNC line should be increased (e.g. by an external capacitor between SYNC and VDD). Degradation of the positive edge of the SYNC pulse may be

countered by an external pull-up resistor.
(a) static drive mode.
(b) 1 : 2 multiplex drive mode.
(c) 1 : 3 multiplex drive mode.
(d) 1 : 4 multiplex drive mode.

handbook, full pagewidth

T=

framefframe

1

BP0

SYNC

BP1

(1/2 bias)

SYNC

BP2

(a) static drive mode.

(b) 1 : 2 multiplex drive mode.

(c) 1 : 3 multiplex drive mode.

(d) 1 : 4 multiplex drive mode.

BP3

SYNC

SYNC

BP1

(1/3 bias)

MBE535

1998 Jul 30 28

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

8 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

9 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see

“Handling MOS Devices”

).

SYMBOL PARAMETER MIN. MAX. UNIT

V

DD

supply voltage −0.5 +8.0 V

V

LCD

LCD supply voltage VDD− 8.0 V

DD

V

V

I1

input voltage CLK, SYNC, SA0, OSC, A0 to A2 VSS− 0.5 VDD+ 0.5 V

V

I2

input voltage SDA, SCL VSS− 0.5 +8.0 V

V

O

output voltage S0 to S39, BP0 to BP3 V

LCD

− 0.5 VDD+ 0.5 V

I

I

DC input current −20 +20 mA

I

O

DC output current −25 +25 mA

I

DD

, ISS, I

LCDVDD

, VSS or V

LCD

current −50 +50 mA

P

tot

total power dissipation − 400 mW

P

O

power dissipation per output − 100 mW

T

stg

storage temperature −65 +150 °C

1998 Jul 30 29

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

10 DC CHARACTERISTICS

V

DD

= 2 to 6 V; VSS=0V;V

LCD=VDD

− 2VtoVDD− 6V;T

amb

= −40 to +85 °C; unless otherwise specified.

Notes

1. V

LCD

≤ VDD− 3 V for1⁄3bias.

2. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive.

3. Resets all logic when VDD< V

POR

.

4. Periodically sampled, not 100% tested.

5. Outputs measured one at a time.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

V

DD

supply voltage 2 − 6V

V

LCD

LCD supply voltage note 1 VDD− 6 − VDD− 2V

I

DD

supply current note 2

normal mode f

clk

= 200 kHz −−120 µA

power-saving mode f

clk

= 35 kHz;

VDD= 3.5 V; V

LCD

=0V;

A0, A1 and A2 tied to V

SS

−−60 µA

Logic

V

IL

LOW-level input voltage SDA, SCL,
CLK, SYNC, SA0, OSC, A0 to A2

V

SS

− 0.3V

DD

V

V

IH1

HIGH-level input voltage CLK, SYNC,
SA0, OSC, A0 to A2

0.7V

DD

− V

DD

V

V

IH2

HIGH-level input voltage SDA, SCL 0.7V

DD

− 6.0 V

V

OL

LOW-level output voltage IOL=0mA −−0.05 V

V

OH

HIGH-level output voltage IOH= 0 mA VDD− 0.05 −− V

I

OL1

LOW-level output current CLK, SYNC VOL=1V; VDD=5V 1 −− mA

I

OH1

HIGH-level output current CLK VOH=4V; VDD=5V −1 −− mA

I

OL2

LOW-level output current SDA, SCL VOL= 0.4 V; VDD=5V 3 −− mA

I

L1

leakage current SA0, A0 to A2, CLK,
SDA and SCL

VI=VDD or V

SS

−1 − +1 µA

I

L2

leakage current OSC VI=V

DD

−1 − +1 µA

I

pd

A0, A1, A2 and OSC pull-down
current

VI=1V; VDD= 5 V 15 50 150 µA

R

SYNC

pull-up resistor (SYNC) 20 50 150 kΩ

V

POR

power-on reset voltage level note 3 − 1.0 1.6 V

t

SW

tolerable spike width on bus −−100 ns

C

I

input capacitance note 4 −−7pF

LCD outputs

V

BP

DC voltage component BP0 to BP3 CBP=35nF −20 − +20 mV

V

S

DC voltage component S0 to S39 CS=5nF −20 − +20 mV

R

BP

output resistance BP0 to BP3 note 5; V

LCD=VDD

− 5V −−5kΩ

R

S

output resistance S0 to S39 note 5; V

LCD=VDD

− 5V −−7.5 kΩ

1998 Jul 30 30

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

11 AC CHARACTERISTICS

V

DD

= 2 to 6 V; VSS=0V; V

LCD=VDD

− 2VtoVDD− 6V;T

amb

= −40 to + 85 °C; unless otherwise specified.

Notes

1. At f

clk

< 125 kHz, I2C-bus maximum transmission speed is derated.

2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSSto VDD.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

f

clk

oscillator frequency

normal mode V

DD

= 5 V; note 1 125 200 315 kHz

power-saving mode V

DD

= 3.5 V 21 31 48 kHz

t

clkH

CLK HIGH time 1 −−µs

t

clkL

CLK LOW time 1 −−µs

t

PSYNC

SYNC propagation delay time −−400 ns

t

SYNCL

SYNC LOW time 1 −−µs

t

PLCD

driver delays with test loads V

LCD=VDD

− 5V −−30 µs

Timing characteristics: I

2

C-bus; note 2

t

BUF

bus free time 4.7 −−µs

t

HD;STA

START condition hold time 4.0 −−µs

t

SU;STA

set-up time for a repeated START condition 4.7 −−µs

t

LOW

SCL LOW time 4.7 −−µs

t

HIGH

SCL HIGH time 4.0 −−µs

t

r

SCL and SDA rise time −−1µs

t

f

SCL and SDA fall time −−0.3 µs

C

B

capacitive bus line load −−400 pF

t

SU;DAT

data set-up time 250 −−ns

t

HD;DAT

data hold time 0 −−ns

t

SU;STO

set-up time for STOP condition 4.0 −−µs

Fig.20 Test loads.

MBE544

Ω3.3 k Ω1.5 k

0.5V

DD

V

DD

V

DD

SDA,
SCL

CLK

1 nF

BP0 to BP3, and
S0 to S39

(2%)(2%)

Ω6.8

V

DD

SYNC

(2%)

1998 Jul 30 31

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

Fig.21 Driver timing waveforms.

handbook, full pagewidth

MBE545

0.7V

DD

0.3V

DD

1/ f

clk

t

PSYNC

t

clkH

t

clkL

0.7V

DD

0.3V

DD

SYNC

CLK

0.5 V

0.5 V

t

PLCD

BP0 to BP3,

and S0 to S39

t

PSYNC

t

SYNCL

(VDD = 5 V)

Fig.22 I2C-bus timing waveforms.

handbook, full pagewidth

SDA

MGA728

SDA

SCL

t

SU;STA

t

SU;STO

t

HD;STA

t

BUF

t

LOW

t

HD;DAT

t

HIGH

t

r

t

f

t

SU;DAT

1998 Jul 30 32

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

11.1 Typical supply current characteristics

Fig.23 −ISS as a function of f

frame

.

VDD= 5 V; V

LCD

= 0 V; T

amb

=25°C.

0 200

50

0

10

MBE530

20

30

40

100

I

SS

(µA)

f (Hz)

frame

normal
mode

power-saving
mode

Fig.24 −I

LCD

as a function of f

frame

.

VDD= 5 V; V

LCD

= 0 V; T

amb

=25°C.

0 200

50

0

10

MBE529

20

30

40

100

I

LCD

(µA)

f (Hz)

frame

Fig.25 ISS as a function of VDD.

V

LCD

= 0 V; external clock; T

amb

=25°C.

handbook, halfpage

010

50

0

10

MBE528 - 1

20

30

40

5

I

SS

(µA)

V (V)

DD

power-saving mode

f = 35 kHz

clk

normal mode

f = 200 kHz

clk

Fig.26 I

LCD

as a function of VDD.

V

LCD

= 0 V; external clock; f

clk

= nominal frequency.

handbook, halfpage

010

50

0

10

MBE527 - 1

20

30

40

5

V (V)

DD

I

LCD

(µA)

85 C

o

25 C

o

40 C

o

1998 Jul 30 33

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

11.2 Typical characteristics of LC D outputs

Fig.27 R

O(max)

as a function of VDD.

V

LCD

= 0 V; T

amb

=25°C.

handbook, halfpage

60

10

-1

MBE532 - 1

1

10

3

V (V)

DD

R

S

R

BP

R

O(max)

(kΩ)

Fig.28 R

O(max)

as a function of T

amb

.

VDD= 5 V; V

LCD

=0V.

40 0 40 120

2.5

0

2.0

MBE526

80

1.5

1.0

0.5

R

S

R

BP

R

O(max)

(kΩ)

T

amb

( C)

o

1998 Jul 30 34

Philips Semiconductors Product specification

Universal LCD driver for low multiplex

rates

PCF8576C

This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in

_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in

white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...

12 APPLICATION INFORMATION

n

dbook, full pagewidth

PCF

8576CT

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

SDA
SCL

SYNC

CLK
V

OSC

A0
A1
A2

SA0
V

V

BP0

BP2
BP1
BP3

S0
S1
S2
S3

24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38

S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21

34
33

S17
S7
S8
S9

S10
S11

32
31
30
29

S16

S15

S13

S14

S12

DD

SS

LCD

PCF

8576CT

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20

BP0
BP2
BP1
BP3
S40
S41
S42
S43

24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38

S79
S78
S77
S76
S75
S74
S73
S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61

34
33

S57
S47
S48
S49
S50
S51

S51 S52 S53

32
31
30
29

S56

S55

S53

S54

S52

S50S39 S40S13S12

open

S10 S11S0 S79

backplanes segments

MBE537

SDA
SCL
SYNC
CLK

V
V
V

DD
SS

LCD

Fig.29 Single plane wiring of packaged PCF8576CTs.

1998 Jul 30 35

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

12.1 Chip-on-glass cascadability in single plane

In chip-on-glass technology, where driver devices are
bonded directly onto glass of the LCD, it is important that
the devices may be cascaded without the crossing of
conductors, but the paths of conductors can be continued
on the glass under the chip. All of this is facilitated by the
PCF8576C bonding pad layout (Fig.30). Pads needing bus
interconnection between all PCF8576Cs of the cascade
are VDD, VSS, V

LCD

, CLK, SCL, SDA and SYNC. These
lines may be led to the corresponding pads of the next
PCF8576C through the wide opening between V

LCD

pad

and the backplane output pads.

The only bus line that does not require a second opening
to lead through to the next PCF8576C is V

LCD

, being the

cascade centre. The placing of V

LCD

adjacent to V

SS

allows the two supplies to be tied together.
When an external clocking source is to be used, OSC of all

devices should be tied to VDD. The pads OSC, A0, A1, A2
and SA0 have been placed between VSS and VDD to
facilitate wiring of oscillator, hardware subaddress and
slave address.

13 BONDING PAD LOCATIONS

Fig.30 Bonding pad locations.

Chip dimensions: approximately 2.92 × 3.20 mm.
Pad area: 0.0121 mm2.
Bonding pad dimensions: 110 × 110 µm.

S33

S32

S31

S29
S30

S28

S26

S25

S27

S24

S23

S22

S20
S21

S19

S18

S4

S6

S5

S7

S9

S10

S8

S11

S12

S13

S15

S14

S16

S17

OSC

A0

V

SYNC

SCL

CLK

SDA

S39

S38

S36

S37

S35

S34

A1

A2

2.92 mm

SA0

V

V

BP0

BP2

BP1

BP3

S1
S0

S2

S3

PCF8576C

DD

LCD

SS

3.20
mm

MBE536

1565554535251

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

29 28 27 26 25 24 23 22 21

20

19

18

17

16

15

14

13

11

10

9

8

12

3031323334

234567

x

y

0

0

1998 Jul 30 36

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

Table 16 Bonding pad locations (dimensions in µm)
All x/y coordinates are referenced to the centre of the chip

(see Fig.30).

SYMBOL PAD x y

SDA 1 −74 −1380
SCL 2 148 −1380
SYNC 3 355 −1380
CLK 4 534 −1380
V

DD

5 742 −1380
OSC 6 913 −1380
A0 7 1087 −1380
A1 8 1290 −1284
A2 9 1290 −1116
SA0 10 1290 −945
V

SS

11 1290 −751

V

LCD

12 1290 −485
BP0 13 1290 125
BP2 14 1290 285
BP1 15 1290 458
BP3 16 1290 618
S0 17 1290 791
S1 18 1290 951
S2 19 1290 1124
S3 20 1290 1284
S4 21 1074 1380
S5 22 914 1380
S6 23 741 1380
S7 24 581 1380
S8 25 408 1380
S9 26 248 1380
S10 27 75 1380
S11 28 −85 1380
S12 29 −258 1380
S13 30 −418 1380
S14 31 −591 1380

S15 32 −751 1380
S16 33 −924 1380
S17 34 −1084 1380
S18 35 −1290 1243
S19 36 −1290 1083
S20 37 −1290 910
S21 38 −1290 750
S22 39 −1290 577
S23 40 −1290 417
S24 41 −1290 244
S25 42 −1290 84
S26 43 −1290 −89
S27 44 −1290 −249
S28 45 −1290 −422
S29 46 −1290 −582
S30 47 −1290 −755
S31 48 −1290 −915
S32 49 −1290 −1088
S33 50 −1290 −1248
S34 51 −1083 −1380
S35 52 −923 −1380
S36 53 −750 −1380
S37 54 −590 −1380
S38 55 −417 −1380
S39 56 −257 −1380

Alignment marks

C1 −−1290 1385
C2 −−1295 −1385
F − 1305 −1405

SYMBOL PAD x y

1998 Jul 30 37

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

14 PACKAGE OUTLINES

UNIT A1A2A3b

p

cD

(1)E(2)

(1)

eHELLpQZywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

inches

0.3

0.1

3.0

2.8

0.25

0.42

0.30

0.22

0.14

21.65

21.35

11.1

11.0

0.75

15.8

15.2

1.45

1.30

0.90

0.55

7
0

o
o

0.1 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

1.6

1.4

SOT190-1

96-04-02
97-08-11

w M

θ

A

A

1

A

2

b

p

D

H

E

L

p

Q

detail X

E

Z

e

c

L

v M

A

X

(A )

3

A

y

56

29

281

pin 1 index

0.012

0.004

0.12

0.11

0.017

0.012

0.0087

0.0055

0.85

0.84

0.44

0.43

0.0295

2.25

0.089

0.62

0.60

0.057

0.051

0.035

0.022

0.004

0.2

0.008 0.004

0.063

0.055

0.01

0 5 10 mm

scale

VSO56: plastic very small outline package; 56 leads

SOT190-1

A

max.

3.3

0.13

Note

1. Plastic or metal protrusions of 0.3 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

1998 Jul 30 38

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

UNIT

A

max.

A1A2A3b

p

cE

(1)

eH

E

LL

p

Zywv θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC JEDEC EIAJ

mm

1.60

0.20

0.05

1.45

1.35

0.25

0.27

0.17

0.18

0.12

10.1

9.9

0.5

12.15

11.85

1.45

1.05

7
0

o
o

0.12 0.11.0 0.2

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.75

0.45

SOT314-2

95-12-19
97-08-01

D

(1) (1)(1)

10.1

9.9

H

D

12.15

11.85

E

Z

1.45

1.05

D

b

p

e

θ

E

A

1

A

L

p

detail X

L

(A )

3

B

16

c

D

H

b

p

E

H

A

2

v M

B

D

Z

D

A

Z

E

e

v M

A

X

1

64

49

48 33

32

17

y

pin 1 index

w M

w M

0 2.5 5 mm

scale

LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm

SOT314-2

1998 Jul 30 39

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

15 SOLDERING

15.1 Introduction

There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.

This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our

“Data Handbook IC26; Integrated Circuit Packages”

(order code 9398 652 90011).

15.2 Reflow soldering

Reflow soldering techniques are suitable for all LQFP and
VSO packages.

Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 50 and 300 seconds depending on heating
method. Typical reflow peak temperatures range from
215 to 250 °C.

15.3 Wave soldering

15.3.1 LQFP
Wave soldering is not recommended for LQFP packages.

This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.

CAUTION

Wave soldering is NOT applicable for all LQFP
packages with a pitch (e) equal or less than 0.5 mm.

If wave soldering cannot be avoided, for LQFP
packages with a pitch (e) larger than 0.5 mm, the
following conditions must be observed:

• A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)
soldering technique should be used.

• The footprint must be at an angle of 45° to the board

direction and must incorporate solder thieves
downstream and at the side corners.

15.3.2 VSO
Wave soldering techniques can be used for all VSO

packages if the following conditions are observed:

• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.

• The longitudinal axis of the package footprint must be
parallel to the solder flow.

• The package footprint must incorporate solder thieves at
the downstream end.

15.3.3 M

ETHOD (LQFP AND VSO)

During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.

Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.

15.4 Repairing soldered joints

Fix the component by first soldering two diagonally­opposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.

1998 Jul 30 40

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

16 DEFINITIONS

17 LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.

18 PURCHASE OF PHILIPS I

2

C COMPONENTS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I

2

C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.

1998 Jul 30 41

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

NOTES

1998 Jul 30 42

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

NOTES

1998 Jul 30 43

Philips Semiconductors Product specification

Universal LCD driver for low multiplex
rates

PCF8576C

NOTES

Internet: http://www.semiconductors.philips.com

Philips Semiconductors – a worldwide company

© Philips Electronics N.V. 1998 SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.

Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,

Tel. [phone], Fax. [phone]
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. [phone], Fax. [phone]
Norway: Box 1, Manglerud 0612, OSLO,

Tel. [phone], Fax. [phone]

Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. [phone], Fax. [phone]

Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. [phone], Fax. [phone]

Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,

Tel. [phone], Fax. [phone]
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,

Tel. [phone], Fax. [phone]

Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,

2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000,
Tel. [phone], Fax. [phone]

South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. [phone], Fax. [phone]

Spain: Balmes 22, 08007 BARCELONA,
Tel. [phone], Fax. [phone]

Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. [phone], Fax. [phone]

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. [phone] Fax. [phone]

Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. [phone], Fax. [phone]

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. [phone], Fax. [phone]

Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,
Tel. [phone], Fax. [phone]

Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. [phone], Fax. [phone]

United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. [phone], Fax. [phone]

United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. [phone]

Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,

Tel. [phone], Fax.[phone]

For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. [phone]

Argentina: see South America
Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. [phone], Fax. [phone]
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. [phone],

Fax. [phone]
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,

220050 MINSK, Tel. [phone], Fax. [phone]

Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,

51 James Bourchier Blvd., 1407 SOFIA,
Tel. [phone], Fax. [phone]

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. [phone]

China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
72 Tat Chee Avenue, Kowloon Tong, HONG KONG,
Tel. [phone], Fax. [phone]

Colombia: see South America
Czech Republic: see Austria
Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S,

Tel. [phone], Fax. [phone]
Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. [phone], Fax. [phone]
France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex,

Tel. [phone], Fax. [phone]
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,

Tel. [phone], Fax. [phone]
Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS,

Tel. [phone], Fax. [phone]

Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,

254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. [phone], Fax. [phone]

Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. [phone] ext. 2501, Fax. [phone]

Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. [phone], Fax. [phone]

Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. [phone], Fax. [phone]

Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. [phone], Fax. [phone]

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. [phone], Fax. [phone]

Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. [phone], Fax. [phone]

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. [phone], Fax. [phone]

Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. [phone]

Printed in The Netherlands 415106/1200/06/pp44 Date of release: 1998 Jul 30 Document order number: 9397 750 04196