Philips PCF8574T, PCF8574TS-F3, PCF8574U-10, PCF8574U-9, PCF8574AP Datasheet

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DATA SH EET

Product speciﬁcation Supersedes data of September 1994 File under Integrated Circuits, IC12

1997 Apr 02

INTEGRATED CIRCUITS

PCF8574

Remote 8-bit I/O expander for I

C-bus

1997 Apr 02 2

Philips Semiconductors Product speciﬁcation

Remote 8-bit I/O expander for I2C-bus

PCF8574

CONTENTS

1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING 6 CHARACTERISTICS OF THE I2C-BUS

6.1 Bit transfer

6.2 Start and stop conditions

6.3 System configuration

6.4 Acknowledge 7 FUNCTIONAL DESCRIPTION

7.1 Addressing

7.2 Interrupt

7.3 Quasi-bidirectional I/Os 8 LIMITING VALUES 9 HANDLING 10 DC CHARACTERISTICS 11 I2C-BUS TIMING CHARACTERISTICS 12 PACKAGE OUTLINES 13 SOLDERING

13.1 Introduction

13.2 DIP

13.2.1 Soldering by dipping or by wave

13.2.2 Repairing soldered joints

13.3 SO and SSOP

13.3.1 Reflow soldering

13.3.2 Wave soldering

13.3.3 Repairing soldered joints 14 DEFINITIONS 15 LIFE SUPPORT APPLICATIONS 16 PURCHASE OF PHILIPS I2C COMPONENTS

1997 Apr 02 3

Philips Semiconductors Product speciﬁcation

Remote 8-bit I/O expander for I2C-bus

PCF8574

1 FEATURES

• Operating supply voltage 2.5 to 6 V

• Low standby current consumption of 10 µA maximum

• I2C to parallel port expander

• Open-drain interrupt output

• 8-bit remote I/O port for the I2C-bus

• Compatible with most microcontrollers

• Latched outputs with high current drive capability for

directly driving LEDs

• Address by 3 hardware address pins for use of up to 8 devices (up to 16 with PCF8574A)

• DIP16, or space-saving SO16 or SSOP20 packages.

2 GENERAL DESCRIPTION

The PCF8574 is a silicon CMOS circuit. It provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I2C).

The device consists of an 8-bit quasi-bidirectional port and an I2C-bus interface. The PCF8574 has a low current consumption and includes latched outputs with high current drive capability for directly driving LEDs. It also possesses an interrupt line (INT) which can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. This means that the PCF8574 can remain a simple slave device.

The PCF8574 and PCF8574A versions differ only in their slave address as shown in Fig.9.

3 ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME DESCRIPTION VERSION

PCF8574P; PCF8574AP

DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-1

PCF8574T; PCF8574AT

SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1

PCF8574TS SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1

1997 Apr 02 4

Philips Semiconductors Product speciﬁcation

Remote 8-bit I/O expander for I2C-bus

PCF8574

4 BLOCK DIAGRAM

Fig.1 Block diagram (SOT38-1 and SOT162-1).

handbook, full pagewidth

MBD980

I C BUS

CONTROL

INPUT

FILTER

1 2 3

14 15

INTERRUPT

LOGIC

8 BIT

I/O

PORT

SHIFT

LP FILTER

WRITE pulse

READ pulse

POWER-ON

RESET

16 8

SDA

SCL

INT

PCF8574

1997 Apr 02 5

Philips Semiconductors Product speciﬁcation

Remote 8-bit I/O expander for I2C-bus

PCF8574

5 PINNING

SYMBOL

DESCRIPTION

DIP16; SO16 SSOP20

A0 1 6 address input 0 A1 2 7 address input 1 A2 3 9 address input 2 P0 4 10 quasi-bidirectional I/O 0 P1 5 11 quasi-bidirectional I/O 1 P2 6 12 quasi-bidirectional I/O 2 P3 7 14 quasi-bidirectional I/O 3 V

8 15 supply ground P4 9 16 quasi-bidirectional I/O 4 P5 10 17 quasi-bidirectional I/O 5 P6 11 19 quasi-bidirectional I/O 6 P7 12 20 quasi-bidirectional I/O 7 INT 13 1 interrupt output (active LOW) SCL 14 2 serial clock line SDA 15 4 serial data line V

16 5 supply voltage n.c. − 3 not connected n.c. − 8 not connected n.c. − 13 not connected n.c. − 18 not connected

handbook, halfpage

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

INT

A0 A1

A2 P0 P1 P2 P3

SDA

SCL

P7 P6 P5 P4

PCF8574

PCF8574A

MBD979

Fig.2 Pin configuration (DIP16; SO16).

handbook, halfpage

1 2 3 4 5 6 7 8 9

20 19 18 17 16 15 14 13 12 11

INT

SCL

n.c.

SDA V

A0 A1

n.c.

A2 P0

P7 P6 n.c. P5

P3 n.c. P2 P1

PCF8574TS

MBD978

Fig.3 Pin configuration (SSOP20).

1997 Apr 02 6

Philips Semiconductors Product speciﬁcation

Remote 8-bit I/O expander for I2C-bus

PCF8574

6 CHARACTERISTICS OF THE I2C-BUS

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

6.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Fig.4).

6.2 Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Fig.5).

6.3 System conﬁguration

A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Fig.6).

Fig.4 Bit transfer.

MBC621

data line

stable;

data valid

change

of data

allowed

SDA

SCL

Fig.5 Definition of start and stop conditions.

MBC622

SDA

SCL

STOP condition

SDA

SCL

START condition

Fig.6 System configuration.

MBA605

MASTER

TRANSMITTER /

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER /

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER /

RECEIVER

SDA SCL

1997 Apr 02 7

Philips Semiconductors Product speciﬁcation

Remote 8-bit I/O expander for I2C-bus

PCF8574

6.4 Acknowledge

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave

transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.

Fig.7 Acknowledgment on the I2C-bus.

MBC602

START

CONDITION

9821

clock pulse for

acknowledgement

not acknowledge

acknowledge

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

SCL FROM

MASTER

1997 Apr 02 8

Philips Semiconductors Product speciﬁcation

Remote 8-bit I/O expander for I2C-bus

PCF8574

7 FUNCTIONAL DESCRIPTION

7.1 Addressing

For addressing see Figs 9, 10 and 11.

Fig.8 Simplified schematic diagram of each I/O.

handbook, full pagewidth

MBD977

100

µA

to interrupt

logic

P0 to P7

write pulse

data from shift register

power-on reset

read pulse

data to shift register

Fig.9 PCF8574 and PCF8574A slave addresses.

handbook, full pagewidth

MBD973

S 0 1 0 0 A2 A1 A0 0 A 1 0

slave address

S 0 1 1 A2 A1 A0

a. b.

(a) PCF8574. (b) PCF8574A.

Each of the PCF8574’s eight I/Os can be independently used as an input or output. Input data is transferred from the port to the microcontroller by the READ mode (see Fig.11). Output data is transmitted to the port by the WRITE mode (see Fig.10).

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