Philips pcf8574 DATASHEETS

INTEGRATED CIRCUITS

DATA SH EET

PCF8574

Remote 8-bit I/O expander for

C-bus

Product speciﬁcation Supersedes data of May 1989 File under Integrated Circuits, IC12

Philips Semiconductors

September 1994

Philips Semiconductors Product speciﬁcation

Remote 8-bit I/O expander for I2C-bus

FEATURES

• Operating supply voltage 2.5 to 6 V

• Low standby current consumption of 10 µA maximum

• I2C to parallel port expander

• Open-drain interrupt output

• 8-bit remote I/O Port for the I2C-bus

• Compatible with most microcontrollers

• Latched outputs with high current drive capability for

directly driving LEDs

• Address by 3 hardware address pins for use of up to 8 devices (up to 16 with PCF8574A)

• DIP16, space-saving SO16 or SSOP20 package.

GENERAL DESCRIPTION

The PCF8574 is a silicon CMOS circuit. It provides general purpose remote I/O expansion for most microcontroller families via the two-line bidirectional bus (I

C).

PCF8574

The device consists of an 8-bit quasi-bidirectional Port and

an I

C interface. The PCF8574 has a low current consumption and includes latched outputs with high current drive capability for directly driving LEDs. It also possesses an interrupt line (INT) which can be connected to the interrupt logic of the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C-bus. This means that the PCF8574 can remain a simple slave device.

The PCF8574 and PCF8574A versions differ only in their slave address as shown in Fig.9.

ORDERING INFORMATION

TYPE NUMBER

PCF8574P; PCF8574AP

PCF8574T; PCF8574AT

PCF8574TS SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1

NAME DESCRIPTION VERSION

DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-1

SO16 plastic small outline package; 16 leads; body width 7.5 mm SOT162-1

PACKAGE

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Philips Semiconductors Product speciﬁcation

Remote 8-bit I/O expander for I2C-bus

BLOCK DIAGRAM

handbook, full pagewidth

INT

A0 A1

SCL SDA

1 2 3

14 15

INPUT

FILTER

INTERRUPT

LOGIC

I C BUS

CONTROL

PCF8574

SHIFT

LP FILTER

8 BIT

I/O

PORTS

PCF8574

4 5 6 7

9 10 11 12

P0 P1 P2 P3 P4 P5 P6 P7

WRITE pulse

DD SS

16 8

POWER-ON

RESET

V V

READ pulse

MBD980

Fig.1 Block diagram (SOT38-1 and SOT162-1).

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Philips Semiconductors Product speciﬁcation

Remote 8-bit I/O expander for I2C-bus

PINNING

SYMBOL

DIP16; SO16 SSOP20

A0 1 6 address input 0 A1 2 7 address input 1 A2 3 9 address input 2 P0 4 10 quasi-bidirectional I/O Port 0 P1 5 11 quasi-bidirectional I/O Port 1 P2 6 12 quasi-bidirectional I/O Port 2 P3 7 14 quasi-bidirectional I/O Port 3 V

P4 9 16 quasi-bidirectional I/O Port 4 P5 10 17 quasi-bidirectional I/O Port 5 P6 11 19 quasi-bidirectional I/O Port 6 P7 12 20 quasi-bidirectional I/O Port 7 INT 13 1 interrupt output (active LOW) SCL 14 2 serial clock line SDA 15 4 serial data line V

16 5 supply voltage n.c. − 3 not connected n.c. − 8 not connected n.c. − 13 not connected n.c. − 18 not connected

8 15 supply ground

PCF8574

DESCRIPTION

handbook, halfpage

A1 A2

3 4

P0 P1 P2 P3

5 6 7 8

PCF8574

PCF8574A

MBD979

SDA

SCL

INT

P7 P6

11 10

Fig.2 Pin configuration (DIP16; SO16).

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handbook, halfpage

Fig.3 Pin configuration (SSOP20).

INT

SCL

n.c.

SDA V

A0 A1

n.c.

A2 P0

1 2 3 4 5

PCF8574TS

6 7 8 9

MBD978

19 18

n.c.

P4 V

14 13

n.c. P2



Philips Semiconductors Product speciﬁcation

Remote 8-bit I/O expander for I2C-bus

CHARACTERISTICS OF THE I2C-BUS

The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Fig.4).

SDA

SCL

PCF8574

Start and stop conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P) (see Fig.5).

System conﬁguration

A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Fig.6).

SCL

SDA SCL

start condition

MASTER

TRANSMITTER /

RECEIVER

data line

stable;

data valid

change

of data

allowed

MBA607

Fig.4 Bit transfer.

stop condition

MBA608

Fig.5 Definition of start and stop conditions.

SLAVE

RECEIVER

SLAVE

TRANSMITTER /

RECEIVER

Fig.6 System configuration.

MASTER

TRANSMITTER

MASTER

TRANSMITTER /

RECEIVER

MBA60

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Philips Semiconductors Product speciﬁcation

Remote 8-bit I/O expander for I2C-bus

Acknowledge

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave

ok, full pagewidth

SCL FROM

MASTER

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

START

condition

PCF8574

transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set-up and hold times must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.

clock pulse for

acknowledgement

MBA606 - 1

Fig.7 Acknowledgement on the I2C-bus.

September 1994 6

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