INTEGRATED CIRCUITS
DATA SHEET
PCF8570
256 × 8-bit static low-voltage RAM with I2C-bus interface
Product specification |
1999 Jan 06 |
Supersedes data of 1997 Sep 02
File under Integrated Circuits, IC12
Philips Semiconductors |
Product specification |
|
|
256 × 8-bit static low-voltage RAM with
PCF8570
I2C-bus interface
CONTENTS
1FEATURES
2APPLICATIONS
3GENERAL DESCRIPTION
4QUICK REFERENCE DATA
5ORDERING INFORMATION
6BLOCK DIAGRAM
7PINNING
8CHARACTERISTICS OF THE I2C-BUS
8.1Bit transfer
8.2Start and stop conditions
8.3System configuration
8.4Acknowledge
8.5I2C-bus protocol
9LIMITING VALUES
10HANDLING
11DC CHARACTERISTICS
12AC CHARACTERISTICS
13APPLICATION INFORMATION
13.1Application example
13.2Slave address
13.3Power-saving mode
14PACKAGE OUTLINES
15SOLDERING
15.1Introduction
15.2Through-hole mount packages
15.2.1Soldering by dipping or by solder wave
15.2.2Manual soldering
15.3Surface mount packages
15.3.1Reflow soldering
15.3.2Wave soldering
15.3.3Manual soldering
15.4Suitability of IC packages for wave, reflow and dipping soldering methods
16DEFINITIONS
17LIFE SUPPORT APPLICATIONS
18PURCHASE OF PHILIPS I2C COMPONENTS
1999 Jan 06 |
2 |
Philips Semiconductors |
Product specification |
256 × 8-bit static low-voltage RAM with
PCF8570
I2C-bus interface
1 FEATURES
∙Operating supply voltage 2.5 to 6.0 V
∙Low data retention voltage; minimum 1.0 V
∙Low standby current; maximum 15 μA
∙Power-saving mode; typical 50 nA
∙Serial input/output bus (I2C-bus)
∙Address by 3 hardware address pins
∙Automatic word address incrementing
∙Available in DIP8 and SO8 packages.
2 APPLICATIONS
∙Telephony:
–RAM expansion for stored numbers in repertory dialling (e.g. PCD33xxA applications)
∙General purpose RAM for applications requiring extremely low current and low-voltage RAM retention, such as battery or capacitor-backed.
∙Radio, television and video cassette recorder:
–channel presets
∙General purpose:
3 GENERAL DESCRIPTION
The PCF8570 is a low power static CMOS RAM, organized as 256 words by 8-bits.
Addresses and data are transferred serially via a two-line bidirectional bus (I2C-bus). The built-in word address register is incremented automatically after each written or read data byte. Three address pins, A0, A1 and A2 are used to define the hardware address, allowing the use of up to 8 devices connected to the bus without additional hardware.
–RAM expansion for the microcontroller families PCD33xxA, PCF84CxxxA, P80CLxxx and most other microcontrollers.
4 QUICK REFERENCE DATA
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
MAX. |
UNIT |
|
|
|
|
|
|
VDD |
supply voltage |
|
2.5 |
6.0 |
|
IDD |
supply current (standby) |
fSCL = 0 Hz |
− |
15 |
μA |
IDDR |
supply current (power-saving mode) |
Tamb = 25 °C |
− |
400 |
nA |
Tamb |
operating ambient temperature |
|
−40 |
+85 |
°C |
Tstg |
storage temperature |
|
−65 |
+150 |
°C |
5 ORDERING INFORMATION
TYPE |
|
PACKAGE |
|
|
|
|
|
NUMBER |
NAME |
DESCRIPTION |
VERSION |
|
|||
|
|
|
|
PCF8570P |
DIP8 |
plastic dual in-line package; 8 leads (300 mil) |
SOT97-1 |
|
|
|
|
PCF8570T |
SO8 |
plastic small outline package; 8 leads; body width 7.5 mm |
SOT176-1 |
|
|
|
|
1999 Jan 06 |
3 |
Philips Semiconductors |
Product specification |
256 × 8-bit static low-voltage RAM with
PCF8570
I2C-bus interface
6 BLOCK DIAGRAM
|
PCF8570 |
WORD |
|
ROW |
MEMORY |
|
ADDRESS |
|
CELL |
||
|
7 |
SELECT |
|||
|
|
REGISTER |
ARRAY |
||
|
|
|
|
||
1 |
|
|
|
|
|
A0 |
|
|
|
|
|
2 |
|
|
|
|
|
A1 |
|
|
|
|
|
3 |
|
|
|
|
|
A2 |
|
|
|
|
|
6 |
|
|
|
|
|
SCL |
INPUT |
I2C BUS |
|
COLUMN |
MULTIPLEXER |
5 |
FILTER |
CONTROL |
|
SELECT |
|
SDA |
|
|
|||
8 |
POWER |
SHIFT |
8 |
|
R/W |
REGISTER |
|
|
CONTROL |
||
ON |
|
|
|||
VDD |
|
|
|
|
|
4 |
RESET |
|
|
|
|
VSS |
|
|
|
|
|
7 |
|
|
|
|
|
TEST |
|
|
|
|
|
|
|
|
|
|
MLB928 |
|
|
Fig.1 |
Block diagram. |
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
7 PINNING |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SYMBOL |
PIN |
DESCRIPTION |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A0 |
1 |
hardware address input 0 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A1 |
2 |
hardware address input 1 |
|
|
|
|
|
|
|
A2 |
3 |
hardware address input 2 |
|
|
page |
|
|
|
VDD |
|
|
A0 |
1 |
|
8 |
||||
VSS |
4 |
negative supply |
|
|
A1 |
2 |
PCF8570 |
7 |
TEST |
SDA |
5 |
serial data input/output |
|
|
A2 |
3 |
6 |
SCL |
|
|
|
|
|
|
|
||||
SCL |
6 |
serial clock input |
|
||||||
|
|
VSS |
4 |
|
5 |
SDA |
|||
|
|
|
|
|
|
||||
TEST |
7 |
Input for power-saving mode (see section |
|||||||
|
|
“Power-saving mode”). Also used as a test output |
|
|
|
MLB929 |
|
||
|
|
during manufacture. TEST should be tied to VSS |
|
|
|
|
|
|
|
|
|
during normal operation. |
|
|
Fig.2 |
Pin configuration. |
|||
|
|
|
|
|
|||||
VDD |
8 |
positive supply |
|
||||||
|
|
|
|
|
|
|
|||
1999 Jan 06 |
4 |
Philips Semiconductors |
Product specification |
256 × 8-bit static low-voltage RAM with
PCF8570
I2C-bus interface
8 CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy.
8.1Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal.
SDA
SCL
data line |
|
change |
|
|
|
|
|
||
stable; |
|
of data |
|
|
|
|
|
||
data valid |
|
allowed |
|
MBA607 |
|
|
|||
|
|
Fig.3 Bit transfer.
8.2Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P).
SDA |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SDA |
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||
SCL |
|
|
|
S |
|
|
|
|
|
|
|
|
|
|
|
|
P |
|
SCL |
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
START condition |
|
|
|
|
|
|
|
STOP condition |
|||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MBA608 |
Fig.4 Definition of start and stop conditions.
1999 Jan 06 |
5 |
Philips Semiconductors |
Product specification |
256 × 8-bit static low-voltage RAM with
PCF8570
I2C-bus interface
8.3System configuration
A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
SDA
SCL
MASTER |
|
SLAVE |
|
SLAVE |
|
MASTER |
|
MASTER |
TRANSMITTER / |
|
|
TRANSMITTER / |
|
|
TRANSMITTER / |
||
|
RECEIVER |
|
|
TRANSMITTER |
|
|||
RECEIVER |
|
|
RECEIVER |
|
|
RECEIVER |
||
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MBA605 |
Fig.5 System configuration.
8.4Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
|
START |
|
|
clock pulse for |
||
|
condition |
|
|
acknowledgement |
||
SCL FROM |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1 |
2 |
8 |
9 |
||
|
||||||
MASTER |
|
|||||
|
|
|
|
|
|
|
DATA OUTPUT
BY TRANSMITTER
S
DATA OUTPUT
BY RECEIVER
MBA606 - 1
Fig.6 Acknowledgement on the I2C-bus.
1999 Jan 06 |
6 |
Loading...