Philips P87CL881H-000, P87CL881H-xxx Datasheet

DATA SH EET

Product speciﬁcation File under Integrated Circuits, IC17

1999 Apr 16

INTEGRATED CIRCUITS

P87CL881H

Low-voltage microcontroller with 63-kbyte OTP program memory and 2-kbyte RAM

1999 Apr 16 2

Philips Semiconductors Product speciﬁcation

Low-voltage microcontroller with 63-kbyte OTP program memory and 2-kbyte RAM

P87CL881H

CONTENTS

1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING INFORMATION

5.1 Pinning

5.2 Pin description 6 FUNCTIONAL DESCRIPTION

6.1 Special Function Registers

6.2 I/O facilities

6.3 Internal data memory

6.4 OTP programming

6.5 Oscillator circuitry

6.6 Non-conformance 7 LIMITING VALUES 8 DC CHARACTERISTICS 9 AC CHARACTERISTICS

9.1 AC testing 10 PACKAGE OUTLINE 11 SOLDERING

11.1 Introduction to soldering surface mount packages

11.2 Reflow soldering

11.3 Wave soldering

11.4 Manual soldering

11.5 Suitability of surface mount IC packages for wave and reflow soldering methods

12 DEFINITIONS 13 LIFE SUPPORT APPLICATIONS 14 PURCHASE OF PHILIPS I2C COMPONENTS

1999 Apr 16 3

Philips Semiconductors Product speciﬁcation

Low-voltage microcontroller with 63-kbyte OTP program memory and 2-kbyte RAM

P87CL881H

1 FEATURES

• Full static 80C51 CPU; enhanced 8-bit architecture with:

– Minimum 6 cycles per instruction (twice as fast as a

standard 80C51 core) – Non-page oriented instructions – Direct addressing – Four 8-byte RAM register banks – Stack depth limited only by available internal RAM

(maximum 256 bytes) – Multiply, divide, subtract and compare instructions.

• Very low current consumption

• Single supply voltage of 2.7 to 3.6 V

• Frequency: 1 to 10 MHz

• Operating temperature: −25 to +70 °C

• 44-pin LQFP package

• Four 8-bit ports (32 I/O lines)

• 63-kbyte One-Time Programmable (OTP) program

memory; programmable in parallel mode or in-system via I

2

C-bus interface.

• 256-byte internal RAM

• 1792-byte internal AUX-RAM

• External address range: 64 kbytes of ROM and

64 kbytes of RAM

• Amplitude Controlled Oscillator (ACO) suitable for use with a quartz crystal or ceramic resonator

• Improved Power-on/Power-off reset circuitry (POR)

• Low Voltage Detection (LVD) with 11 software

programmable levels

• 8 interrupts on Port 1, edge or level sensitive triggering selectable via software power-saving use for keyboard control

• Twenty source, twenty vector interrupt structure with two priority levels

• Wake-up from Power-down mode via LVD or external interrupts at Port 1

• Two 16-bit timer/event counters

• Additional 16-bit timer/event counters, with capture,

compare and PWM function

• Watchdog Timer

• Full duplex enhanced UART with double buffering

• I

2

C-bus interface for serial transfer on two lines,

maximum operating frequency 400 kHz.

2 GENERAL DESCRIPTION

The P87CL881 is an 8-bit microcontroller especially suited for pager applications.

The P87CL881 is manufactured in an advanced CMOS technology and is based on single chip technology.

The device is optimized for low power consumption and has two software selectable features for power reduction: Idle and Power-down modes. In addition, all derivative blocks switch off their clock if they are inactive.

The instruction set of the P87CL881 is based on that of the 80C51. The P87CL881 also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte, 46 two-byte, and 16 three-byte.

This data sheet details the specific properties of the P87CL881; for details of the P87CL881 core and the derivative functions see the

“TELX family”

data sheet and

“8051-Based 8-bit Microcontrollers; Data Handbook IC20”

.

3 ORDERING INFORMATION

Note

1. Please refer to the Order Entry Form (OEF) for this device for the full type number to use when ordering. This type number will also specify the required program and options.

TYPE

NUMBER

(1)

PRODUCT TYPE

PACKAGE

NAME DESCRIPTION VERSION

P87CL881H/000 Blank OTP LQFP44 plastic low proﬁle quad ﬂat package;

44 leads; body 10 × 10 × 1.4 mm

SOT389-1

P87CL881H/xxx Factory-programmed OTP

1999 Apr 16 4

Philips Semiconductors Product speciﬁcation

Low-voltage microcontroller with 63-kbyte

OTP program memory and 2-kbyte RAM

P87CL881H

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4 BLOCK DIAGRAM

handbook, full pagewidth

MGL617

XTAL1 XTAL2 ACO

80C51

core

excluding

ROM/RAM

TWO 16-BIT

TIMER/ EVENT

COUNTERS

(T0, T1)

CLK

(2)

PARALLEL I/O PORTS

P0 P1 P3P2 TXD

(4)

T2COMP

(2)

SDA

(2)

SCL

(2)

RXD

(4)

AD0 to AD7

(1)

A8 to A15

(3)

T2

(2)

RST PORENABLE

T2EX

(2)

CPU

SERIAL

UART PORT

DATA

MEMORY

RAM

DATA MEMORY AUX-RAM

V

DD

V

SS

8-bit

internal bus

PROGRAM

MEMORY

ROM

16-BIT

TIMER/EVENT

COUNTER WITH

CAPTURE/ COMPARE/

(T2)

EEPROM

I2C-BUS

INTERFACE

WATCHDOG

TIMER

(T3)

POR

LVD

P87CL881H

T0

(4)T1 (4)

INT0

(4)

INT1

(4)

INT2 to INT8

(2)

7

RD

(4)

WR

(4)

EA

PSEN

ALE

EW

V

DDP

V

SSPVPP

(5)

Fig.1 Block diagram.

(1) Alternative function of Port 0. (2) Alternative function of Port 1. (3) Alternative function of Port 2. (4) Alternative function of Port 3. (5) Alternative function of pin 6.

1999 Apr 16 5

Philips Semiconductors Product speciﬁcation

Low-voltage microcontroller with 63-kbyte OTP program memory and 2-kbyte RAM

P87CL881H

5 PINNING INFORMATION

5.1 Pinning

Fig.2 Pin configuration.

handbook, full pagewidth

P87CL881H

MGL616

1 2 3 4 5 6 7 8

9 10 11

33 32 31 30 29 28 27 26 25 24 23

12

13

14

15

16

17

18

19

20

21

22

44

43

42

41

40

39

38

37

36

35

34

P1.5/INT7 P1.6/INT8/SCL P1.7/INT9/SDA

RST

P3.0/RXD/data

PORENABLE/V

PP

P3.1/TXD/clock

P3.2/INT0

P3.3/INT1

P3.4/T0 P3.5/T1 P2.5/A13

P2.6/A14

P2.7/A15

PSEN

ALE

EW

EA

P0.7/AD7

P0.6/AD6

P0.5/AD5

P0.4/AD4

P0.3/AD3

P0.2/AD2

P0.1/AD1

P0.0/AD0

V

DDP

V

DD

P1.0/INT2/T2

P1.1/INT3/T2EX

P1.2/INT4/T2COMP

P1.3/INT5

P1.4/INT6/CLK

P3.6/WR

P3.7/RD

XTAL2

XTAL1

V

SSP

V

SS

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11

P2.4/A12

1999 Apr 16 6

Philips Semiconductors Product speciﬁcation

Low-voltage microcontroller with 63-kbyte OTP program memory and 2-kbyte RAM

P87CL881H

5.2 Pin description Table 1 LQFP package

SYMBOL PIN DESCRIPTION

V

DD

39 Power supply for core.

V

DDP

38 Power supply for I/O ring.

V

SS

17 Ground for core.

V

SSP

16 Ground for I/O ring.

RST 4 RESET. A LOW level on this pin for two machine cycles while the oscillator is running,

resets the device. The RST pin is also an output which can be used to reset other ICs.

PORENABLE/V

PP

6 PORENABLE. If set to a logic 1, the internal Power-on reset circuit is enabled. If external

reset circuitry is used, it is recommended to keep PORENABLE LOW in order to achieve the lowest power consumption. This pin is also used for the OTP programming voltage

VPP. EW 28 Enable Watchdog Timer. XTAL2 14 Crystal output. Output of the amplitude controlled oscillator. If an external oscillator

clock is used this pin not used. XTAL1 15 Crystal input. Input to the amplitude controlled oscillator. Also the input for an externally

generated clock source. PSEN 26 Program Store Enable. Read strobe to external program memory. When executing

code out of external program memory, PSEN is activated twice each machine cycle.

However, during each access to external data memory two PSEN activations are

skipped. During Power-down mode the PSEN pin stays HIGH. ALE 27 Address Latch Enable. Latches the low byte of the address during accesses to external

memory . It is activated every six oscillator periods and may be used for external timing or

clocking purposes. For improved EMC behaviour, the toggle of the ALE pin can be

disabled by setting the RFI bit in the PCON register by software. This bit is cleared on

reset and can be set and cleared by software. When set, the ALE pin will be pulled-down

internally , switching an external address latch to a quiet state. The MOVX instruction will

still toggle ALE if external memory is accessed. ALE will retain its normal HIGH state

during Idle mode and a LOW state during the Power-down mode while in the EMC mode.

Additionally, during internal access (

EA = 1) ALE will toggle normally when the address exceeds the internal program memory size. During external access (EA = 0) ALE will always toggle normally, whether the RFI bit is set or not.

EA 29 External Access. When EA is held HIGH, the CPU executes out of the internal program

memory (unless the program counter exceeds the highest address for internal program memory). When EA is held LOW, the CPU executes out of external program memory regardless of the value of the program counter. The state of the EA pin is internally latched at reset.

1999 Apr 16 7

Philips Semiconductors Product speciﬁcation

Low-voltage microcontroller with 63-kbyte OTP program memory and 2-kbyte RAM

P87CL881H

P0.0/AD0 37 Port 0. 8-bit bidirectional I/O port with alternative functions. Every port pin can be used

as open-drain, standard port, high-impedance input or push-pull output, according to Section 6.2. AD7 to AD0 provide the multiplexed low-order address and data bus during accesses to external memory.

P0.1/AD1 36 P0.2/AD2 35 P0.3/AD3 34 P0.4/AD4 33 P0.5/AD5 32 P0.6/AD6 31 P0.7/AD7 30 P1.0/INT2/T2 40 Port 1. 8-bit bidirectional I/O port with alternative functions. Every port pin except P1.6

and P1.7 (I

2

C-bus pins) can be used as open-drain, standard port, high-impedance input or push-pull output, according to Section 6.2. Port 1 also serves the alternative functions INT2 to INT9 interrupts, Timer 2 external input and Timer 2 compare output, external clock output CLK and I2C-bus clock and I2C-bus data in/outputs.

P1.1/INT3/T2EX 41 P1.2/INT4/

T2COMP

42

P1.3/INT5 43 P1.4/INT6/CLK 44 P1.5/INT7 1 P1.6/INT8/SCL 2 P1.7/INT9/SDA 3 P2.0/A8 18 Port 2. 8-bit bidirectional I/O port with alternative functions. Every port pin can be used

as open-drain, standard port, high-impedance input or push-pull output, according to Section 6.2. Port 2 emits the high order address byte during accesses to external memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses the strong internal pull-ups when emitting logic 1's. During accesses to external memory that use 8-bit addresses (MOVX @ Ri), Port 2 emits the contents of the P2 Special Function Register.

P2.1/A9 19 P2.2/A10 20 P2.3/A11 21 P2.4/A12 22 P2.5/A13 23 P2.6/A14 24 P2.7/A15 25 P3.0/RXD/data 5 Port 3. 8-bit bidirectional I/O port with alternative functions. Every port pin can be used

as open-drain, standard port, high-impedance input or push-pull output, according to Section 6.2. RXD/data is the serial port receiver data input (asynchronous) or data I/O (synchronous). TXD/clock is the serial port transmitter data output (asynchronous) or clock output (synchronous).

INT0 and INT1 are external interrupt lines. T0 and T1 are external inputs for Timers 0 and 1 respectively. WR is the external memory write strobe and RD is the external memory read strobe.

P3.1/TXD/clock 7 P3.2/INT0 8 P3.3/

INT1 9 P3.4/T0 10 P3.5/T1 11 P3.6/

WR 12 P3.7/

RD 13

SYMBOL PIN DESCRIPTION

1999 Apr 16 8

Philips Semiconductors Product speciﬁcation

Low-voltage microcontroller with 63-kbyte OTP program memory and 2-kbyte RAM

P87CL881H

6 FUNCTIONAL DESCRIPTION

For the functional and block descriptions of the P87CL881, refer to the

“TELX family”

data sheet.

6.1 Special Function Registers Table 2 Special Function Registers memory map and reset values; note 1

REGISTER NAME REGISTER MNEMONIC SFR ADDRESS RESET VALUE

(2)

80C51 core

Accumulator ACC E0H 0000 0000 B Register B F0H 0000 0000 Data Pointer Low byte DPL 82H 0000 0000 Data Pointer High byte DPH 83H 0000 0000 Program Counter High byte PCH no SFR 0000 0000 Program Counter Low byte PCL no SFR 0000 0000 Power Control Register PCON 87H 0000 0000 Prescaler Register PRESC F3H 0000 0000 Program Status Word PSW D0H 0000 0000 Stack Pointer SP 81H 0000 0111 XRAM Page Register XRAMP FAH XXXXX000

Timers 0 and 1

Timer/Counter Control Register TCON 88H 0000 0000 Timer/Counter 0 High byte TH0 8CH 0000 0000 Timer/Counter 1 High byte TH1 8DH 0000 0000 Timer/Counter 0 Low byte TL0 8AH 0000 0000 Timer/Counter 1 Low byte TL1 8BH 0000 0000 Timer/Counter Mode Control Register TMOD 89H 0000 0000

Ports

Alternative Port Function Control Register ALTP A3H 0000 0000 Port P0 output data Register P0 80H 1111 1111 Port P0 Conﬁguration A Register P0CFGA 8EH 1111 1111 Port P0 Conﬁguration B Register P0CFGB 8FH 0000 0000 Port P1 output data Register P1 90H 0111 1111 Port P1 Conﬁguration A Register P1CFGA 9EH 0000 1000 Port P1 Conﬁguration B Register P1CFGB 9FH 0111 1111 Port P2 output data Register P2 A0H 1111 1111 Port P2 Conﬁguration A Register P2CFGA AEH 1111 1111 Port P2 Conﬁguration B Register P2CFGB AFH 0000 0000 Port P3 output data Register P3 B0H 1111 1111 Port P3 Conﬁguration A Register P3CFGA BEH 1111 1110 Port P3 Conﬁguration B Register P3CFGB BFH 1111 1111

1999 Apr 16 9

Philips Semiconductors Product speciﬁcation

Low-voltage microcontroller with 63-kbyte OTP program memory and 2-kbyte RAM

P87CL881H

Timer 2

Timer 2 Compare High byte COMP2H ABH 0000 0000 Timer 2 Compare Low byte COMP2L AAH 0000 0000 Timer 2 Reload/Capture High byte RCAP2H CBH 0000 0000 Timer 2 Reload/Capture Low byte RCAP2L CAH 0000 0000 Timer/Counter 2 Control Register T2CON C8H 0000 0000 Timer/Counter 2 High byte TH2 CDH 0000 0000 Timer/Counter 2 Low byte TL2 CCH 0000 0000

Interrupt logic

Interrupt Enable Register 0 IEN0 A8H 0000 0000 Interrupt Enable Register 1 IEN1 E8H 0000 0000 Interrupt Enable Register 2 IEN2 F1H 0000 0000 Interrupt Priority Register 0 IP0 B8H 0000 0000 Interrupt Priority Register 1 IP1 F8H 0000 0000 Interrupt Priority Register 2 IP2 F9H 0000 0000 Interrupt Sensitivity Register 1 ISE1 E1H 0000 0000 Interrupt Polarity Register IX1 E9H 0000 0000 Interrupt Request Flag Register 1 IRQ1 C0H 0000 0000

Low Voltage Detection

LVD Control Register LVDCON F2H 0000 0000

PORACO

Reset Status Register RSTAT E6H XXX1 1000

UART

Serial Port Buffer S0BUF 99H 0000 0000 Serial Port Control Register S0CON 98H 0000 0000

I

2

C-bus interface

Address Register S1ADR DBH 0000 0000 Serial Control Register S1CON D8H 0000 0000 Data Shift Register S1DAT DAH 0000 0000 Serial Status Register S1STA D9H 1111 1000

Watchdog timer

Watchdog Timer Control Register WDCON A5H 1010 0101 Watchdog Timer Interval Register WDTIM FFH 0000 0000

REGISTER NAME REGISTER MNEMONIC SFR ADDRESS RESET VALUE

(2)

1999 Apr 16 10

Philips Semiconductors Product speciﬁcation

Low-voltage microcontroller with 63-kbyte OTP program memory and 2-kbyte RAM

P87CL881H

Notes

1. E7H and FDH are reserved locations and must not be written to.

2. Where: X = undefined state.

OTP interface

OTP Address High Register OAH D5 X00X XXXX OTP Address Low Register OAL D4 XXXX XXXX OTP Data Register ODATA D6 XXXX XXXX OTP In-System Programming Register OISYS DC 000X 0000 OTP Test Register OTEST D7 0000 0000

REGISTER NAME REGISTER MNEMONIC SFR ADDRESS RESET VALUE

(2)

6.2 I/O facilities

6.2.1 P

ORTS

The P87CL881 has 32 I/O lines treated as 32 individually addressable bits or as four parallel 8-bit addressable ports. Ports 0, 1, 2 and 3 perform the following alternative functions:

Port 0 Provides the multiplexed low-order address and

data bus for expanding the device with standard memories and peripherals.

Port 1 Used for a number of special functions:

• P1.0 to P1.7 provides the inputs for the external interrupts INT2 to INT9

• P1.0/T2 and P1.1/T2EX for external inputs of Timer 2

• P1.2/T2COMP for external activation and compare

output of Timer 2

• P1.4/CLK for the clock output

• P1.6/SCL and P1.7/SDA for the I2C-bus interface are

real open-drain outputs or high-impedance; no other port configurations are available.

Port 2 Provides the high-order address bus when

expanding the device with external program memory and/or external data memory.

Port 3 Pins can be configured individually to provide:

• P3.0/RXD/data and P3.1/TXD/clock which are serial port receiver input and transmitter output (UART)

• P3.2/INT0 and P3.3/INT1 are external interrupt request inputs

• P3.4/T0 and P3.5/T1 as counter inputs

• P3.6/WR and P3.7/RD are control signals to write and

read to external memories.

To enable a port pin alternative function, the port bit latch in its SFR must contain a logic 1.

Each port consists of a latch (Special Function Registers P0 to P3), an output driver and input buffer. All ports have internal pull-ups. Figure 3(a) shows that the strong transistor P1 is turned on for only 1 oscillator period after a LOW-to-HIGH transition in the port latch. When on, it turns on P3 (a weak pull-up) through the inverter IN1. This inverter and transistor P3 form a latch which holds the logic 1.

6.2.2 P

ORT I/O CONFIGURATION

I/O port output configurations are determined by the settings in the port configuration SFRs. Each port has two associated SFRs: PnCFGA and PnCFGB, where ‘n’ indicates the specific port number (0 to 3). One bit in each of the 2 SFRs relates to the output setting for the corresponding port pin, allowing any combination of the 2 output types to be mixed on those port pins. For example, the output type of P1.3 is controlled by setting bit 3 in the SFRs P1CFGA and P1CFGB.

The port pins may be individually configured via the SFRs with one of the following modes (P1.6 and P1.7 can be open-drain or high-impedance but never have any diodes against VDD).

Mode 0 Open-drain; quasi-bidirectional I/O with

n-channel open-drain output. Use as an output (e.g. Port 0 for external memory accesses (EA = 0) or access above the built-in memory boundary) requires the connection of an external pull-up resistor. The ESD protection diodes against VDD and VSS are still present. Except for the I2C-bus pins P1.6 and P1.7, ports which are configured as open-drain still have a protection diode to VDD. See Fig.3a.

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