INTEGRATED CIRCUITS
DATA SHEET
P87CL881H
Low-voltage microcontroller with 63-kbyte OTP program memory and 2-kbyte RAM
Product specification |
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1999 Apr 16 |
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File under Integrated Circuits, IC17 |
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Philips Semiconductors |
Product specification |
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Low-voltage microcontroller with 63-kbyte
P87CL881H
OTP program memory and 2-kbyte RAM
CONTENTS
1FEATURES
2GENERAL DESCRIPTION
3ORDERING INFORMATION
4BLOCK DIAGRAM
5PINNING INFORMATION
5.1Pinning
5.2Pin description
6 |
FUNCTIONAL DESCRIPTION |
6.1Special Function Registers
6.2I/O facilities
6.3Internal data memory
6.4OTP programming
6.5Oscillator circuitry
6.6Non-conformance
7LIMITING VALUES
8DC CHARACTERISTICS
9AC CHARACTERISTICS
9.1AC testing
10PACKAGE OUTLINE
11SOLDERING
11.1Introduction to soldering surface mount packages
11.2Reflow soldering
11.3Wave soldering
11.4Manual soldering
11.5Suitability of surface mount IC packages for wave and reflow soldering methods
12DEFINITIONS
13LIFE SUPPORT APPLICATIONS
14PURCHASE OF PHILIPS I2C COMPONENTS
1999 Apr 16 |
2 |
Philips Semiconductors |
Product specification |
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Low-voltage microcontroller with 63-kbyte
P87CL881H
OTP program memory and 2-kbyte RAM
1 FEATURES
∙Full static 80C51 CPU; enhanced 8-bit architecture with:
–Minimum 6 cycles per instruction (twice as fast as a standard 80C51 core)
–Non-page oriented instructions
–Direct addressing
–Four 8-byte RAM register banks
–Stack depth limited only by available internal RAM (maximum 256 bytes)
–Multiply, divide, subtract and compare instructions.
∙Very low current consumption
∙Single supply voltage of 2.7 to 3.6 V
∙Frequency: 1 to 10 MHz
∙Operating temperature: −25 to +70 °C
∙44-pin LQFP package
∙Four 8-bit ports (32 I/O lines)
∙63-kbyte One-Time Programmable (OTP) program memory; programmable in parallel mode or in-system via I2C-bus interface.
∙256-byte internal RAM
∙1792-byte internal AUX-RAM
∙External address range: 64 kbytes of ROM and 64 kbytes of RAM
∙Amplitude Controlled Oscillator (ACO) suitable for use with a quartz crystal or ceramic resonator
∙Improved Power-on/Power-off reset circuitry (POR)
∙Low Voltage Detection (LVD) with 11 software programmable levels
∙8 interrupts on Port 1, edge or level sensitive triggering selectable via software power-saving use for keyboard control
∙Twenty source, twenty vector interrupt structure with two priority levels
∙Wake-up from Power-down mode via LVD or external interrupts at Port 1
∙Two 16-bit timer/event counters
∙Additional 16-bit timer/event counters, with capture, compare and PWM function
∙Watchdog Timer
∙Full duplex enhanced UART with double buffering
∙I2C-bus interface for serial transfer on two lines, maximum operating frequency 400 kHz.
2 GENERAL DESCRIPTION
The P87CL881 is an 8-bit microcontroller especially suited for pager applications.
The P87CL881 is manufactured in an advanced CMOS technology and is based on single chip technology.
The device is optimized for low power consumption and has two software selectable features for power reduction: Idle and Power-down modes. In addition, all derivative blocks switch off their clock if they are inactive.
The instruction set of the P87CL881 is based on that of the 80C51. The P87CL881 also functions as an arithmetic processor having facilities for both binary and BCD arithmetic plus bit-handling capabilities. The instruction set consists of over 100 instructions: 49 one-byte,
46 two-byte, and 16 three-byte.
This data sheet details the specific properties of the P87CL881; for details of the P87CL881 core and the derivative functions see the “TELX family” data sheet and
“8051-Based 8-bit Microcontrollers; Data Handbook IC20”.
3 ORDERING INFORMATION
TYPE |
PRODUCT TYPE |
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PACKAGE |
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NUMBER(1) |
NAME |
DESCRIPTION |
VERSION |
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P87CL881H/000 |
Blank OTP |
LQFP44 |
plastic low profile quad flat package; |
SOT389-1 |
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44 leads; body 10 × 10 × 1.4 mm |
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P87CL881H/xxx |
Factory-programmed OTP |
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Note
1.Please refer to the Order Entry Form (OEF) for this device for the full type number to use when ordering. This type number will also specify the required program and options.
1999 Apr 16 |
3 |
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16Apr1999 |
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INT1 (4) |
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BLOCK4 |
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T0 (4) |
T1 (4) |
INT0 (4) INT2 to INT8 (2) |
VDD VDDP |
VSS |
VSSP |
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VPP(5) |
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7 |
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DIAGRAM |
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TWO 16-BIT |
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PROGRAM |
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DATA |
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DATA |
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EA |
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TIMER/ |
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EVENT |
CPU |
MEMORY |
MEMORY |
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MEMORY |
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P87CL881H |
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COUNTERS |
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ROM |
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RAM |
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AUX-RAM |
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(T0, T1) |
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XTAL1 |
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80C51 |
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core |
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XTAL2 |
ACO |
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excluding |
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8-bit |
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CLK (2) |
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ROM/RAM |
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PSEN |
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internal bus |
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ALE |
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WR (4) |
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RD (4) |
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4 |
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16-BIT |
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LVD |
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AD0 to AD7 (1) |
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PARALLEL |
SERIAL |
TIMER/EVENT |
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I2C-BUS |
WATCHDOG |
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COUNTER WITH |
EEPROM |
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I/O PORTS |
UART |
CAPTURE/ |
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INTERFACE |
TIMER |
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A8 to A15 (3) |
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PORT |
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(T3) |
POR |
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COMPARE/ |
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(T2) |
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MGL617 |
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RXD (4) |
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T2EX (2) |
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SDA (2) |
SCL (2) |
RST |
EW |
PORENABLE |
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P0 |
P1 |
P2 P3 |
TXD (4) |
T2 (2) |
T2COMP (2) |
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(1)Alternative function of Port 0.
(2)Alternative function of Port 1.
(3)Alternative function of Port 2.
(4)Alternative function of Port 3.
(5)Alternative function of pin 6.
Fig.1 Block diagram.
kbyte-2 and memory program OTP |
63 with microcontroller voltage-Low |
RAM |
kbyte- |
P87CL881H
Semiconductors Philips
specification Product
Philips Semiconductors |
Product specification |
|
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Low-voltage microcontroller with 63-kbyte
P87CL881H
OTP program memory and 2-kbyte RAM
5 PINNING INFORMATION
5.1Pinning
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P1.4/INT6/CLK |
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P1.3/INT5 |
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P1.2/INT4/T2COMP |
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P1.1/INT3/T2EX |
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P1.0/INT2/T2 |
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V |
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V |
P0.0/AD0 |
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P0.1/AD1 |
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P0.2/AD2 |
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P0.3/AD3 |
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DD |
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DDP |
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44 |
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41 |
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34 |
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P1.5/INT7 |
1 |
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P1.6/INT8/SCL |
2 |
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P1.7/INT9/SDA |
3 |
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RST |
4 |
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P3.0/RXD/data |
5 |
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PORENABLE/VPP |
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P87CL881H |
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6 |
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P3.1/TXD/clock |
7 |
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P3.2/INT0 |
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8 |
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P3.3/INT1 |
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P3.4/T0 |
10 |
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P3.5/T1 |
11 |
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12 |
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P3.6/WR |
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P3.7/RD |
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XTAL2 |
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XTAL1 |
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SSP |
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SS |
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P2.0/A8 |
P2.1/A9 |
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P2.2/A10 |
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P2.3/A11 |
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P2.4/A12 |
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V |
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33 P0.4/AD4
32 P0.5/AD5
31 P0.6/AD6
30 P0.7/AD7
29 EA
28 EW
27 ALE
26 PSEN
25 P2.7/A15
24 P2.6/A14
23 P2.5/A13
MGL616
Fig.2 Pin configuration.
1999 Apr 16 |
5 |
Philips Semiconductors |
Product specification |
|
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Low-voltage microcontroller with 63-kbyte
P87CL881H
OTP program memory and 2-kbyte RAM
5.2 Pin description Table 1 LQFP package
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SYMBOL |
PIN |
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DESCRIPTION |
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VDD |
39 |
Power supply for core. |
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VDDP |
38 |
Power supply for I/O ring. |
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VSS |
17 |
Ground for core. |
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VSSP |
16 |
Ground for I/O ring. |
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4 |
RESET. A LOW level on this pin for two machine cycles while the oscillator is running, |
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RST |
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resets the device. The |
RST |
pin is also an output which can be used to reset other ICs. |
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PORENABLE/VPP |
6 |
PORENABLE. If set to a logic 1, the internal Power-on reset circuit is enabled. If external |
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reset circuitry is used, it is recommended to keep PORENABLE LOW in order to achieve |
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the lowest power consumption. This pin is also used for the OTP programming voltage |
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VPP. |
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28 |
Enable Watchdog Timer. |
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EW |
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XTAL2 |
14 |
Crystal output. Output of the amplitude controlled oscillator. If an external oscillator |
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clock is used this pin not used. |
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XTAL1 |
15 |
Crystal input. Input to the amplitude controlled oscillator. Also the input for an externally |
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generated clock source. |
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26 |
Program Store Enable. Read strobe to external program memory. When executing |
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PSEN |
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code out of external program memory, |
PSEN |
is activated twice each machine cycle. |
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However, during each access to external data memory two |
PSEN |
activations are |
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skipped. During Power-down mode the |
PSEN |
pin stays HIGH. |
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ALE |
27 |
Address Latch Enable. Latches the low byte of the address during accesses to external |
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memory. It is activated every six oscillator periods and may be used for external timing or |
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clocking purposes. For improved EMC behaviour, the toggle of the ALE pin can be |
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disabled by setting the RFI bit in the PCON register by software. This bit is cleared on |
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reset and can be set and cleared by software. When set, the ALE pin will be pulled-down |
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internally, switching an external address latch to a quiet state. The MOVX instruction will |
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still toggle ALE if external memory is accessed. ALE will retain its normal HIGH state |
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during Idle mode and a LOW state during the Power-down mode while in the EMC mode. |
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Additionally, during internal access |
(EA |
= 1) ALE will toggle normally when the address |
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exceeds the internal program memory size. During external access |
(EA |
= 0) ALE will |
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always toggle normally, whether the RFI bit is set or not. |
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External Access. When |
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memory (unless the program counter exceeds the highest address for internal program |
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memory). When |
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regardless of the value of the program counter. The state of the |
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latched at reset. |
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1999 Apr 16 |
6 |
Philips Semiconductors |
Product specification |
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Low-voltage microcontroller with 63-kbyte
P87CL881H
OTP program memory and 2-kbyte RAM
SYMBOL |
PIN |
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DESCRIPTION |
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P0.0/AD0 |
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Port 0. 8-bit bidirectional I/O port with alternative functions. Every port pin can be used |
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as open-drain, standard port, high-impedance input or push-pull output, according to |
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P0.1/AD1 |
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P0.2/AD2 |
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P0.4/AD4 |
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P0.5/AD5 |
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P0.6/AD6 |
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P0.7/AD7 |
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P1.0/INT2/T2 |
40 |
Port 1. 8-bit bidirectional I/O port with alternative functions. Every port pin except P1.6 |
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and P1.7 (I2C-bus pins) can be used as open-drain, standard port, high-impedance input |
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P1.1/INT3/T2EX |
41 |
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P1.2/INT4/ |
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T2COMP |
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P1.3/INT5 |
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P1.4/INT6/CLK |
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P1.5/INT7 |
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P1.6/INT8/SCL |
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P1.7/INT9/SDA |
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P2.0/A8 |
18 |
Port 2. 8-bit bidirectional I/O port with alternative functions. Every port pin can be used |
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as open-drain, standard port, high-impedance input or push-pull output, according to |
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P2.1/A9 |
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Section 6.2. Port 2 emits the high order address byte during accesses to external |
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P2.2/A10 |
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memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses the |
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P2.3/A11 |
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P2.4/A12 |
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use 8-bit addresses (MOVX @ Ri), Port 2 emits the contents of the P2 Special Function |
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Register. |
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P2.5/A13 |
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P2.6/A14 |
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P2.7/A15 |
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P3.0/RXD/data |
5 |
Port 3. 8-bit bidirectional I/O port with alternative functions. Every port pin can be used |
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as open-drain, standard port, high-impedance input or push-pull output, according to |
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P3.1/TXD/clock |
7 |
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Section 6.2. RXD/data is the serial port receiver data input (asynchronous) or data I/O |
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P3.2/INT0 |
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(synchronous). TXD/clock is the serial port transmitter data output (asynchronous) or |
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P3.3/INT1 |
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clock output (synchronous). INT0 and INT1 are external interrupt lines. T0 and T1 are |
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P3.4/T0 |
10 |
external inputs for Timers 0 and 1 respectively. |
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WR |
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and |
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P3.5/T1 |
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P3.6/WR |
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P3.7/RD |
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1999 Apr 16 |
7 |
Philips Semiconductors |
Product specification |
|
|
Low-voltage microcontroller with 63-kbyte
P87CL881H
OTP program memory and 2-kbyte RAM
6 FUNCTIONAL DESCRIPTION
For the functional and block descriptions of the P87CL881, refer to the “TELX family” data sheet.
6.1Special Function Registers
Table 2 Special Function Registers memory map and reset values; note 1
REGISTER NAME |
REGISTER MNEMONIC |
SFR ADDRESS |
RESET VALUE(2) |
80C51 core |
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Accumulator |
ACC |
E0H |
0000 0000 |
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B Register |
B |
F0H |
0000 0000 |
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Data Pointer Low byte |
DPL |
82H |
0000 0000 |
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Data Pointer High byte |
DPH |
83H |
0000 0000 |
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Program Counter High byte |
PCH |
no SFR |
0000 0000 |
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Program Counter Low byte |
PCL |
no SFR |
0000 0000 |
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Power Control Register |
PCON |
87H |
0000 0000 |
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Prescaler Register |
PRESC |
F3H |
0000 0000 |
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Program Status Word |
PSW |
D0H |
0000 0000 |
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Stack Pointer |
SP |
81H |
0000 0111 |
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XRAM Page Register |
XRAMP |
FAH |
XXXX X000 |
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Timers 0 and 1 |
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Timer/Counter Control Register |
TCON |
88H |
0000 0000 |
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Timer/Counter 0 High byte |
TH0 |
8CH |
0000 0000 |
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Timer/Counter 1 High byte |
TH1 |
8DH |
0000 0000 |
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Timer/Counter 0 Low byte |
TL0 |
8AH |
0000 0000 |
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Timer/Counter 1 Low byte |
TL1 |
8BH |
0000 0000 |
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Timer/Counter Mode Control Register |
TMOD |
89H |
0000 0000 |
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Ports |
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Alternative Port Function Control Register |
ALTP |
A3H |
0000 0000 |
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Port P0 output data Register |
P0 |
80H |
1111 1111 |
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Port P0 Configuration A Register |
P0CFGA |
8EH |
1111 1111 |
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Port P0 Configuration B Register |
P0CFGB |
8FH |
0000 0000 |
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Port P1 output data Register |
P1 |
90H |
0111 1111 |
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Port P1 Configuration A Register |
P1CFGA |
9EH |
0000 1000 |
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Port P1 Configuration B Register |
P1CFGB |
9FH |
0111 1111 |
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Port P2 output data Register |
P2 |
A0H |
1111 1111 |
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Port P2 Configuration A Register |
P2CFGA |
AEH |
1111 1111 |
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Port P2 Configuration B Register |
P2CFGB |
AFH |
0000 0000 |
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Port P3 output data Register |
P3 |
B0H |
1111 1111 |
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Port P3 Configuration A Register |
P3CFGA |
BEH |
1111 1110 |
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Port P3 Configuration B Register |
P3CFGB |
BFH |
1111 1111 |
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1999 Apr 16 |
8 |
Philips Semiconductors Product specification
Low-voltage microcontroller with 63-kbyte |
|
P87CL881H |
|
OTP program memory and 2-kbyte RAM |
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REGISTER NAME |
REGISTER MNEMONIC |
SFR ADDRESS |
RESET VALUE(2) |
Timer 2 |
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Timer 2 Compare High byte |
COMP2H |
ABH |
0000 0000 |
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Timer 2 Compare Low byte |
COMP2L |
AAH |
0000 0000 |
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Timer 2 Reload/Capture High byte |
RCAP2H |
CBH |
0000 0000 |
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Timer 2 Reload/Capture Low byte |
RCAP2L |
CAH |
0000 0000 |
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Timer/Counter 2 Control Register |
T2CON |
C8H |
0000 0000 |
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Timer/Counter 2 High byte |
TH2 |
CDH |
0000 0000 |
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Timer/Counter 2 Low byte |
TL2 |
CCH |
0000 0000 |
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Interrupt logic |
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Interrupt Enable Register 0 |
IEN0 |
A8H |
0000 0000 |
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Interrupt Enable Register 1 |
IEN1 |
E8H |
0000 0000 |
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Interrupt Enable Register 2 |
IEN2 |
F1H |
0000 0000 |
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Interrupt Priority Register 0 |
IP0 |
B8H |
0000 0000 |
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Interrupt Priority Register 1 |
IP1 |
F8H |
0000 0000 |
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Interrupt Priority Register 2 |
IP2 |
F9H |
0000 0000 |
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Interrupt Sensitivity Register 1 |
ISE1 |
E1H |
0000 0000 |
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Interrupt Polarity Register |
IX1 |
E9H |
0000 0000 |
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Interrupt Request Flag Register 1 |
IRQ1 |
C0H |
0000 0000 |
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Low Voltage Detection |
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LVD Control Register |
LVDCON |
F2H |
0000 0000 |
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PORACO |
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Reset Status Register |
RSTAT |
E6H |
XXX1 1000 |
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UART |
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Serial Port Buffer |
S0BUF |
99H |
0000 0000 |
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Serial Port Control Register |
S0CON |
98H |
0000 0000 |
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I2C-bus interface |
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Address Register |
S1ADR |
DBH |
0000 0000 |
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Serial Control Register |
S1CON |
D8H |
0000 0000 |
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Data Shift Register |
S1DAT |
DAH |
0000 0000 |
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Serial Status Register |
S1STA |
D9H |
1111 1000 |
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Watchdog timer |
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Watchdog Timer Control Register |
WDCON |
A5H |
1010 0101 |
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Watchdog Timer Interval Register |
WDTIM |
FFH |
0000 0000 |
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1999 Apr 16 |
9 |
Philips Semiconductors Product specification
Low-voltage microcontroller with 63-kbyte |
|
P87CL881H |
|
OTP program memory and 2-kbyte RAM |
|
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REGISTER NAME |
REGISTER MNEMONIC |
SFR ADDRESS |
RESET VALUE(2) |
OTP interface |
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OTP Address High Register |
OAH |
D5 |
X00X XXXX |
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OTP Address Low Register |
OAL |
D4 |
XXXX XXXX |
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OTP Data Register |
ODATA |
D6 |
XXXX XXXX |
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OTP In-System Programming Register |
OISYS |
DC |
000X 0000 |
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OTP Test Register |
OTEST |
D7 |
0000 0000 |
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Notes
1.E7H and FDH are reserved locations and must not be written to.
2.Where: X = undefined state.
6.2I/O facilities
6.2.1PORTS
The P87CL881 has 32 I/O lines treated as 32 individually addressable bits or as four parallel 8-bit addressable ports. Ports 0, 1, 2 and 3 perform the following alternative functions:
Port 0 Provides the multiplexed low-order address and data bus for expanding the device with standard memories and peripherals.
Port 1 Used for a number of special functions:
To enable a port pin alternative function, the port bit latch in its SFR must contain a logic 1.
Each port consists of a latch (Special Function Registers P0 to P3), an output driver and input buffer. All ports have internal pull-ups. Figure 3(a) shows that the strong transistor P1 is turned on for only 1 oscillator period after a LOW-to-HIGH transition in the port latch. When on, it turns on P3 (a weak pull-up) through the inverter IN1. This inverter and transistor P3 form a latch which holds the logic 1.
6.2.2PORT I/O CONFIGURATION
∙P1.0 to P1.7 provides the inputs for the external interrupts INT2 to INT9
∙P1.0/T2 and P1.1/T2EX for external inputs of Timer 2
∙P1.2/T2COMP for external activation and compare output of Timer 2
∙P1.4/CLK for the clock output
∙P1.6/SCL and P1.7/SDA for the I2C-bus interface are real open-drain outputs or high-impedance; no other port configurations are available.
Port 2 Provides the high-order address bus when expanding the device with external program memory and/or external data memory.
Port 3 Pins can be configured individually to provide:
∙P3.0/RXD/data and P3.1/TXD/clock which are serial port receiver input and transmitter output (UART)
∙P3.2/INT0 and P3.3/INT1 are external interrupt request inputs
∙P3.4/T0 and P3.5/T1 as counter inputs
∙P3.6/WR and P3.7/RD are control signals to write and read to external memories.
I/O port output configurations are determined by the settings in the port configuration SFRs. Each port has two associated SFRs: PnCFGA and PnCFGB, where ‘n’ indicates the specific port number (0 to 3). One bit in each of the 2 SFRs relates to the output setting for the corresponding port pin, allowing any combination of the 2 output types to be mixed on those port pins.
For example, the output type of P1.3 is controlled by setting bit 3 in the SFRs P1CFGA and P1CFGB.
The port pins may be individually configured via the SFRs with one of the following modes (P1.6 and P1.7 can be open-drain or high-impedance but never have any diodes against VDD).
Mode 0 Open-drain; quasi-bidirectional I/O with n-channel open-drain output. Use as an output (e.g. Port 0 for external memory accesses (EA = 0) or access above the built-in memory
boundary) requires the connection of an external pull-up resistor. The ESD protection diodes against VDD and VSS are still present. Except for the I2C-bus pins P1.6 and P1.7, ports which are configured as open-drain still have a protection diode to VDD. See Fig.3a.
1999 Apr 16 |
10 |
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