Philips P87CE598EFB-01, P80CE598FFB-00, P80CE598FHB-00 Datasheet

INTEGRATED CIRCUITS

P8xCE598

8-bit microcontroller with on-chip CAN

Product specification

1996 Jun 27

Supersedes data of 1995 Oct 24

File under Integrated Circuits, IC18

Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

CONTENTS

1FEATURES

2GENERAL DESCRIPTION

2.1Electromagnetic Compatibility (EMC)

2.2Recommendation on ALE

3ORDERING INFORMATION

4BLOCK DIAGRAM

5PINNING

6FUNCTIONAL DESCRIPTION

7MEMORY ORGANIZATION

7.1Program Memory

7.2Internal Data Memory

7.3External Data Memory

8I/O PORT STRUCTURE

9PULSE WIDTH MODULATED OUTPUTS (PWM)

9.1Prescaler frequency control register (PWMP)

9.2Pulse Width Register 0 (PWM0)

9.3Pulse Width Register 1 (PWM1)

10 ANALOG-TO-DIGITAL CONVERTER (ADC)

10.1ADC Control register (ADCON)

11 TIMERS/COUNTERS

11.1Timer 0 and Timer 1

11.2Timer T2 Capture and Compare Logic

11.3Watchdog Timer (T3)

12SERIAL I/O PORT: SIO0 (UART)

13SERIAL I/O PORT: SIO1 (CAN)

13.1On-chip CAN-controller

13.2CAN Features

13.3Interface between CPU and CAN

13.4Hardware blocks of the CAN-controller

13.5Control Segment and Message Buffer description

13.6CAN 2.0A Protocol description

14 INTERRUPT SYSTEM

14.1Interrupt Enable and Priority Registers

14.2Interrupt Vectors

14.3Interrupt Priority

15 POWER REDUCTION MODES

15.1Power Control Register (PCON)

15.2CAN Sleep Mode

15.3Idle Mode

15.4Power-down Mode

16OSCILLATOR CIRCUITRY

17RESET CIRCUITRY

17.1Power-on Reset

18 INSTRUCTION SET

18.1Addressing Modes

18.2Instruction Set

19ABSOLUTE MAXIMUM RATINGS

20DC CHARACTERISTICS

21AC CHARACTERISTICS

22CAN APPLICATION INFORMATION

22.1Latency time requirements

22.2Connecting a P8xCE598 to a bus line (physical layer)

23PACKAGE OUTLINES

24SOLDERING

24.1Introduction

24.2Reflow soldering

24.3Wave soldering

24.4Repairing soldered joints

25DEFINITIONS

26LIFE SUPPORT APPLICATIONS

1996 Jun 27

2

Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

1 FEATURES

·80C51 central processing unit (CPU)

·32 kbytes on-chip ROM, externally expandible to 64 kbytes

·2 ´ 256 bytes on-chip RAM, externally expandible to 64 kbytes

·Two standard 16-bit timers/counters

·One additional 16-bit timer/counter coupled to four capture and three compare registers

·10-bit ADC with 8 multiplexed analog inputs

·Two 8-bit resolution Pulse Width Modulated outputs

·15 interrupt sources with 2 priority levels (2 to 6 external interrupt sources possible)

·Five 8-bit I/O ports, plus one 8-bit input port shared with analog inputs

·CAN-controller (CAN = Controller Area Network) with DMA data transfer facility to internal RAM

·1 Mbit/s CAN-controller with bus failure management facility

·1¤2AVDD reference voltage

·Full-duplex UART compatible with the standard 80C51

·On-chip Watchdog Timer (WDT)

·1.2 to 16 MHz clock frequency

·Improved Electromagnetic Compatibility (EMC).

2 GENERAL DESCRIPTION

The P8xCE598 is a single-chip 8-bit high-performance microcontroller with on-chip CAN-controller, derived from the 80C51 microcontroller family.

It uses the powerful 80C51 instruction set.

Figure 1 shows a block diagram of the P8xCE598.

The P8xCE598 is manufactured in an advanced CMOS process, and is designed for use in automotive and general industrial applications. In addition to the 80C51 standard features, the device provides a number of dedicated hardware functions for these applications.

Two versions of the P8xCE598 will be offered:

·P80CE598 (without ROM)

·P83CE598 (with ROM)

Hereafter these versions will be referred to as P8xCE598.

The temperature range includes (max. fCLK = 16 MHz):

·-40 to +85 °C version, for general applications

·-40 to +125 °C version for automotive applications.

The P8xCE598 combines the functions of P8XC552 (microcontroller) and the PCA82C200 (Philips CAN-controller) with the following enhanced features:

·32 kbytes Program Memory

·2 ´ 256 bytes Data Memory

·DMA between CAN Transmit/Receive Buffer and internal RAM.

The main differences to the P8xC552 microcontroller are:

·32 kbytes programmable ROM (P8xC552 has 8 kbytes)

·Additional 256 bytes RAM

·A CAN-controller instead of the I2C-serial interface.

2.1Electromagnetic Compatibility (EMC)

Primary attention is paid to the reduction of electromagnetic emission of the microcontroller P8xCE598. The following features reduce the electromagnetic emission and additionally improve the electromagnetic susceptibility:

·One analog part power supply pin (AVDD) and one analog part ground pin (AVSS), placed as a pair of pins on one side of the package (see Fig.3), providing power supply (+5V) and ground for ADC, CAN receiver and reference voltage.

·Four digital part supply voltage pins (VDD1 to VDD4) and four digital part ground pins (VSS1 to VSS4) are provided on the package. These pins, one VDD and one VSS as a pair of pins are placed on each of the four sides of the package to provide:

–VDD1/VSS1 for internal logic (CPU, Timers/counters, Memory, CAN, UART, ADC)

–VDD2/VSS2 for Port 1, Port 3 and Port 4, and PWM0 and PWM1 outputs

–VDD3/VSS3 for the on-chip oscillator

–VDD4/VSS4 for the Port 0, Port 2, ALE output and PSEN output.

·External capacitors should be connected across

associated VDDx and VSSx pins (i.e. VDD1 and VSS1). Lead length should be as short as possible. Ceramic chip capacitors are recommended (100 nF).

·One CAN supply voltage pin (CVDD) and one CAN ground pin (CVSS) as a pair of pins placed on one side of the package providing (digital part) power supply (+5V) and ground for the CAN transmitter outputs.

·Internal decoupling capacitance improves the EMC radiation behaviour and the EMC immunity.

1996 Jun 27

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Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

2.2Recommendation on ALE

For application that require no external memory or temporarily no external memory: the ALE output signal (pulses at a frequency of 1¤6 fOSC) can be disabled under software control (bit 5 in PCON SFR: ‘RFI’); if disabled, no ALE pulse will occur. ALE pin will be pulled down internally, switching an external address latch to a quiet state. The MOVX instruction will still toggle ALE as a normal MOVX.

3 ORDERING INFORMATION

ALE will retain its normal HIGH value during Idle mode and a LOW value during Power-down mode while in the ‘RFI reduction mode’.

Additionally during internal access (EA = 1) ALE will toggle normally when the address exceeds the internal Program Memory size. During external access (EA = 0) ALE will always toggle normally, whether the flag ‘RFI’ is set or not.

TYPE		PACKAGE		TEMPERATURE	FREQ.
NUMBER	NAME	DESCRIPTION	VERSION	RANGE (°C)	(MHz)
Without ROM
P80CE598FFB		plastic quad flat package; 80 leads (lead		-40 to +85
	QFP80	length 1.95 mm); body 14 ´ 20 ´ 2.7 mm;	SOT318-1		1.2 to 16
P80CE598FHB				-40 to +125
		high stand-off height
With ROM
P83CE598FFB		plastic quad flat package; 80 leads (lead		-40 to +85
	QFP80	length 1.95 mm); body 14 ´ 20 ´ 2.7 mm;	SOT318-1		1.2 to 16
P83CE598FHB				-40 to +125
		high stand-off height

1996 Jun 27

4

1996

ADC0 to ADC7

REF

Jun

PWM0

AVSS

VDD

VSS

PWM1

STADC

AV ref

CRX1

CTX1

27

T0

T1

INT0

INT1

AVDD

CRX0

CTX0

(4)

(4)

(4)

(4)

(6)

(2)

(2)

1/2AVDD

XTAL1

T0, T1

PROGRAM

AUXILIARY

DATA

CVSS

XTAL2

TWO 16 - BIT

CPU

MEMORY

MEMORY

MEMORY

DUAL

ADC

CAN

TIMER/

32K x 8

256 x 8

256 x 8

PWM

EVENT

ROM

RAM

RAM

CVDD

COUNTERS

(7)

EA

80C51

DMA - BUS

core

PSEN

excluding

ROM/RAM

INTERNAL BUS

WR

(4)

16

P8xCE598

RD

5

(4)

AD0 to AD7

T2

THREE

PARALLEL

SERIAL

8-BIT

FOUR

16-BIT

COMPARATOR

T3

(1)

16-BIT

16

I/O PORTS

16-BIT

COMPARATORS

UART

I/O

TIMER/

OUTPUT

WATCHDOG

&

CAPTURE

WITH

PORT

PORTS

EVENT

SELECTION

TIMER

A8 to A15

EXT. BUS

LATCHES

REGISTERS

COUNTER

(3)

(4)

(4)

(2)

(2)

(5)

P0 P1 P2 P3

TXD

RXD

P5 P4

CT0I to CT3I

T2

RT2

CMSR0 to CMSR5

RST

EW

CMT0, CMT1

MLB228

(1)Alternative function of Port 0.

(2)Alternative function of Port 1.

(3)Alternative function of Port 2.

(4)Alternative function of Port 3.

(5)Alternative function of Port 4.

(6)Alternative function of Port 5.

(7)Not present in P80CE598.

Fig.1 Block diagram.

DIAGRAM BLOCK 4

CAN chip-on with microcontroller bit-8

P8xCE598

Semiconductors Philips

specification Product

Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598
5 PINNING

XTAL1

XTAL2

EA

PSEN

ALE

PWM0

PWM1

CRX0

CRX1

REF

AVSS

AV DD

AVref+

alternative function

AV ref –

STADC

ADC0

0

ADC1

1

ADC2

2

ADC3

3

PORT 5

ADC4

4

ADC5

5

ADC6

6

ADC7

7

CMSR0

0

CMSR1

1

CMSR2

2

CMSR3

3

PORT 4

CMSR4

4

CMSR5

5

CMT0

6

CMT1

7

RST

EW

P8xCE598

MBD036

		alternative function
	0	AD0
	1	AD1
	2	AD2	LOW ORDER
	3	AD3
			ADDRESS
	PORT 0		AND
	4	AD4
			DATA BUS
	5	AD5
	6	AD6
	7	AD7
	0	CT0I/INT2
	1	CT1I/INT3
	2	CT2I/INT4
	3	CT3I/INT5
	PORT 1	T2
	4
	5	RT2
	6	CTX0
	7	CTX1
	0	A8
	1	A9
	2	A10	HIGH ORDER
	3	A11
			ADDRESS
	PORT 2	A12
	4		BUS
	5	A13
	6	A14
	7	A15
	0	RXD/DATA
	1	TXD/CLOCK
	2	INT0
	3	INT1
	PORT 3	T0
	4
	5	T1
	6	WR
	7	RD
	CVSS

CVDD

VSS

VDD

Fig.2 Pin functions.

1996 Jun 27

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Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

AVref 1

AVref 2

AVSS 3

AVDD 4 P5.7/ADC7 5 P5.6/ADC6 6

P5.5/ADC5 7

P5.4/ADC4 8 P5.3/ADC3 9

P5.2/ADC2 10 P5.1/ADC1 11 P5.0/ADC0 12 VSS1 13 VDD1 14

STADC 15

PWM0 16

PWM1 17

EW 18

P4.0/CMSR0 19

P4.1/CMSR1 20 P4.2/CMSR2 21

P4.3/CMSR3 22 n.c. 23 P4.4/CMSR4 24

CRX0		CRX1		REF		V		V		P0.0/AD0		P0.1/AD1		P0.2/AD2		P0.3/AD3		P0.4/AD4		P0.5/AD5		P0.6/AD6		P0.7/AD7		n.c.		n.c.		EA
						SS4		DD4
80		79		78		77		76		75		74		73		72		71		70		69		68		67		66		65

P8xCE598

	25		26		27		28		29		30		31		32		33		34		35		36		37		38		39		40
	P4.5/CMSR5		P4.6/CMT0		P4.7/CMT1		V		V		RST		P1.0/CT0I/INT2		P1.1/CT1I/INT3		P1.2/CT2I/INT4		P1.3/CT3I/INT5		P1.4/T2		P1.5/RT2		CV		P1.6/CTX0		P1.7/CTX1		CV
							DD2		SS2																SS						DD

64			ALE
63
			PSEN
62		P2.7/A15
61		P2.6/A14
60		P2.5/A13
59		P2.4/A12
58		P2.3/A11
57		P2.2/A10
56		P2.1/A09
55		P2.0/A08
54		VSS3
53		VDD3
52		XTAL1
51		XTAL2
50		n.c.
49		n.c.
48
		P3.7/RD
47		P3.6/WR
46		P3.5/T1
45		P3.4/T0
44
		P3.3/INT1
43
		P3.2/INT0
42		P3.1/TXD
41		P3.0/RXD
		MLB229

Fig.3 Pin configuration QFP80/SOT318-1.

1996 Jun 27

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Philips Semiconductors

Product specification

8-bit microcontroller with on-chip CAN

P8xCE598

Table 1 Pin description for single function pins (SOT318-1 and SOT351-1; see note 1)

SYMBOL

PIN

DESCRIPTION

VDD1

14

Power supply, digital part: for internal logic (CPU, Timers/counters, Memory, CAN, UART, ADC).

VDD2

28

Power supply, digital part: for Port 1, Port 3, Port 4,

and

outputs.

PWM0

PWM1

VDD3

53

Power supply, digital part: for the on-chip oscillator.

VDD4

76

Power supply, digital part: for Port 0, Port 2, ALE output and

output.

PSEN

STADC

15

Start ADC operation. Input starting analog-to-digital conversion (note 2). This pin must not float.

16

Pulse width modulation output 0.

PWM0

17

Pulse width modulation output 1.

PMW1

18

Enable Watchdog Timer (WDT): enable for T3 Watchdog Timer and disable Power-down mode.

EW

This pin must not float.

RST

30

Reset: input to reset the P8xCE598 (note 3).

CVSS

37

Ground potential for the CAN transmitter outputs.

CVDD

40

Power supply (+5V) for the CAN transmitter outputs.

XTAL2

51

Crystal pin 2: output of the inverting amplifier that forms the oscillator.

When an external clock oscillator is used this pin is left open-circuit.

XTAL1

52

Crystal pin 1: input to the inverting amplifier that forms the oscillator, and input to the internal clock

generator. Receives the external clock oscillator signal, when an external oscillator is used.

VSS1

13

Ground, digital part: for internal logic (CPU, Timers/Counters, Memory, CAN, UART, ADC).

VSS2

29

Ground, digital part: for Port 1, Port 3 and Port 4, and

and

outputs.

PWM0

PWM1

VSS3

54

Ground, digital part: for the on-chip oscillator.

VSS4

77

Ground, digital part: for the Port 0, Port 2, ALE output and

output.

PSEN

63

Program Store Enable: Read strobe to external Program Memory (active LOW).

PSEN

Drive: 8 ´ LSTTL inputs.

ALE

64

Address Latch Enable: latches the Low-byte of the address during accesses to external memory

(note 4). Drive: 8 ´ LSTTL inputs; handles CMOS inputs without an external pull-up.

65

External Access input. See note 5.

EA

REF

78

1¤2AVDD reference voltage output respectively input (note 6).

CRX1

79

Inputs from the CAN-bus line to the differential input comparator of the on-chip CAN-controller

(note 7).

CRX0

80

AVREF−

1

Low-end of ADC (analog-to-digital conversion) reference resistor.

AVREF+

2

High-end of ADC (analog-to-digital conversion) reference resistor (note 8).

AVSS

3

Ground, analog part. For ADC, CAN receiver and reference voltage.

AVDD

4

Power supply, analog part (+5 V). For ADC, CAN receiver and reference voltage.

n.c.

23,

No connection.

49,

50,

66,

67

Notes

1.To avoid a ‘latch up’ effect at power-on: VSS - 0.5 V < ‘voltage on any pin at any time’ < VDD + 0.5 V.

2.Triggered by a rising edge. ADC operation can also be started by software.

3.RST also provides a reset pulse as output when timer T3 overflows or after a CAN wake-up from Power-down.

1996 Jun 27

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Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

4.ALE is activated every six oscillator periods. During an external data memory access one ALE pulse is skipped.

5.See Section 7.1, Table 3 for EA operation. For P83CE598 microcontrollers specified with the option ‘ROM-code protection’, the EA pin is latched during reset and is ‘don't care’ after reset, regardless of whether the ROM-code protection is selected or not.

6.Pin 78, REF:

a)Selection of input respectively output dependent of CAN Control Register bit 5 (CR.5; see Section 13.5.3 Table 32).

b)If the internal reference is used, then REF should be connected to AVSS via a capacitor with a value of ³ 10 nF.

c)After an external reset (RST = HIGH) the internal 1¤2AVDD source is activated and, REF is a reference output.

d)If the CAN-controller is in the reset state, e.g. after an external reset, then the 1¤2AVDD source is switched off during Power-down mode.

7.CAN Bus line:

a)CRX0 level > CRX1 level is interpreted as a logic 1 (recessive).

b)CRX0 level < CRX1 level is interpreted as a logic 0 (dominant).

8.The level of AVREF+ must be higher than that of AVREF−.

Table 2 Pin description for pins with alternative functions (SOT318-2 and SOT351-1; see note 1)

		SYMBOL	PIN	DESCRIPTION
	DEFAULT	ALTERNATIVE
	Port 4
	P4.0 to P4.7		19 to 22, 24 to 27	8-bit quasi-bidirectional I/O port.
		CMSR0	19	Compare and Set/Reset outputs for Timer T2.
		CMSR1	20
		CMSR2	21
		CMSR3	22
		CMSR4	24
		CMSR5	25
		CMT0	26	Compare and toggle outputs for Timer T2.
		CMT1	27
	Port 1
	P1.0 to P1.7		31 to 36, 38 to 39	8-bit quasi-bidirectional I/O port.
		CT0I/INT2	31	Capture timer inputs for Timer T2,
		CT1I/INT3	32	or
				External interrupt inputs 2 to 5.
		CT2I/INT4	33
		CT3I/INT5	34
		T2	35	T2 event input (rising edge triggered).
		RT2	36	T2 timer reset input (rising edge triggered).
		CTX0	38	CAN transmitter output 0 (note 2).
		CTX1	39	CAN transmitter output 1 (note 2).

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Philips Semiconductors									Product specification
8-bit microcontroller with on-chip CAN									P8xCE598
	SYMBOL						PIN		DESCRIPTION
DEFAULT			ALTERNATIVE
Port 3
P3.0 to P3.7							41 to 48		8-bit quasi-bidirectional I/O port.
	RXD						41		Serial Input Port.
	TXD						42		Serial Output Port.
							43		External interrupt input 0.
		INT0
							44		External interrupt input 1.
		INT1
		T0					45		Timer 0 external input.
		T1					46		Timer 1 external input.
							47		External Data Memory Write strobe.
		WR
							48		External Data Memory Read strobe.
		RD
Port 2 (Sink/source: 1 × TTL = 4 × LSTTL inputs)
P2.0 to P2.7							55 to 62		8-bit quasi-bidirectional I/O port.
		A08 to A15							High-order address byte for external memory.
Port 0 (Sink/source: 8 × LSTTL inputs)
P0.7 to P0.0							68 to 75		8-bit open drain bidirectional I/O port.
		AD7 to AD0							Multiplexed Low-order address and Data bus for
									external memory.
Port 5
P5.7 to P5.0							5 to 12		8-bit input port.
	ADC7 to ADC0								8 input channels to ADC.
Notes

1.To avoid a ‘latch up’ effect at power-on: VSS − 0.5 V < ‘voltage on any pin at any time’ < VDD + 0.5 V.

2.If the CAN-controller is in the reset state (e.g. after a power-up reset; CAN Control Register bit CR.0; see Section 13.5.3 Table 32, the CAN transmitter outputs are floating and the pins P1.6 and P1.7 can be used as open-drain port pins. After a power-up reset the port data is HIGH, leaving the pins P1.6 and P1.7 floating.

1996 Jun 27

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Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

6 FUNCTIONAL DESCRIPTION

The P8xCE598 functions will be described as shown in the following overview:

∙Memory organization

∙I/O Port structure

∙Pulse Width Modulated outputs

∙Analog-to-Digital Converter

∙Timers/Counters

∙Serial I/O Ports

∙Interrupt system

∙Power reduction modes

∙Oscillator circuitry

∙Reset circuitry

∙Instruction Set

∙EMC (see Section 2.1).

7 MEMORY ORGANIZATION

The Central Processing Unit (CPU) manipulates operands in three memory spaces (see Fig.4) as follows:

∙32 kbytes internal, resp. 64 kbytes external Program Memory

∙512 bytes internal Data Memory MAINand AUXILIARY RAM.

∙Up to 64 kbytes external Data Memory

(with 256 bytes residing in the internal AUXILIARY RAM).

handbook, full pagewidth 64K

64K

EXTERNAL

32768

32767

OVERLAPPED SPACE

INTERNAL

EXTERNAL

255

256

INDIRECT ONLY

SFRs

AUXILIARY

(EA = 1)

(EA = 0)

127

RAM

DIRECT AND

INDIRECT

0

0

MAIN RAM

PROGRAM MEMORY

INTERNAL DATA MEMORY

EXTERNAL

MLB230	DATA MEMORY

Fig.4 Memory map.

1996 Jun 27

11

Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

7.1Program Memory

The Program Memory of the P8xCE598 consists of 32 kbytes ROM on-chip, externally expandible up to 64 kbytes.

Table 3 Instruction fetch controlled by EA

	PIN EA (note 1)					ADDRESS
					INSTRUCTIONS FETCHED FROM:
	DURING RESET
				AFTER RESET		LOCATION
	LATCHED TO:
	H			−	internal Program Memory (note 2)	0000H → 7FFFH
	H			−	external Program Memory	8000H → FFFFH
	L			−		0000H → FFFFH
	−			‘don’t care’	−	−

Notes

1.This implementation prevents reading of the internal program code by switching from external Program Memory during a MOVC instruction.

2.By setting a security bit the internal Program Memory content is protected, which means it cannot be read out. If the security bit has been set to LOW there are no restrictions for the MOVC instruction.

7.2Internal Data Memory

The internal Data Memory is physically built-up and accessible as shown in Table 4 (see Fig.5).

Table 4 Internal Data Memory size and address mode

	INTERNAL	SIZE	LOCATION	ADDRESS MODE		POINTERS
	DATA MEMORY			DIRECT	INDIRECT
	MAIN RAM	256 bytes	0 to 127	X	X	Address pointers are R0 and R1 of the
	(note 1)					selected register bank.
			128 to 255	−	X
	AUXILIARY RAM	256 bytes	0 to 255	−	X	Address pointers are R0 and R1 of the
	(note 2)					selected register bank and the DPTR.
	SFRs (note 3)	128 bytes	128 to 255	X	−	−

Notes

1.MAIN RAM can be addressed directly and indirectly as in the 80C51.

2.AUXILIARY RAM (0 to 255):

a)Is indirectly addressable in the same way as the external Data Memory with MOVX instructions.

b)Access will not affect the ports P0, P2, P3.6 and P3.7 during internal program execution.

3.SFRs = Special Function Registers.

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Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

7.2.1MAIN RAM

Four 8-bit register banks occupy the lower RAM area,

∙BANK 0: location 0 to 7

∙BANK 1: location 8 to 15

∙BANK 2: location 16 to 23

∙BANK 4: location 24 to 31.

Only one of these banks may be enabled at the same time.

The next 16 bytes, locations 32 through 45, contains 128 directly addressable bit locations.

The stack can be located anywhere in the internal Main RAM address space. The stack depth is only limited by the internal RAM space available. All registers except the program counter and the four 8-bit register banks reside in the SFR address space.

7.3External Data Memory

An access to external Data Memory locations higher than 255 will be performed with the MOVX @DPTR instructions in the same way as in the 80C51 structure,

i.e.with P0 and P2 as data/address bus and P3.6 and P3.7 as Write and Read strobe signals.

Note that these external Data Memory locations cannot be accessed with R0 or R1 as address pointer.

7FH	(MSB)	(LSB)	127

2FH
	7F	7E	7D	7C	7B	7A	79	78	47
2EH	77	76	75	74	73	72	71	70	46
2DH
	6F	6E	6D	6C	6B	6A	69	68	45
2CH	67	66	65	64	63	62	61	60	44
2BH
	5F	5E	5D	5C	5B	5A	59	58	43
2AH	57	56	55	54	53	52	51	50	42
29H
	4F	4E	4D	4C	4B	4A	49	48	41
28H
	47	46	45	44	43	42	41	40	40
27H	3F	3E	3D	3C	3B	3A	39	38	39
26H	37	36	35	34	33	32	31	30	38
25H	2F	2E	2D	2C	2B	2A	29	28	37
24H	27	26	25	24	23	22	21	20	36
23H
	1F	1E	1D	1C	1B	1A	19	18	35
22H	17	16	15	14	13	12	11	10	34
21H
	0F	0E	0D	0C	0B	0A	09	08	33
20H	07	06	05	04	03	02	01	00	32
1FH									31
				BANK 3
18H									24
17H									23
				BANK 2
10H									16
0FH									15
				BANK 1
08H									8
07H									7
				BANK 0
00H									0
							MGA152

Fig.5 Internal MAIN RAM bit addresses.

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Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

DIRECT

handbook, full pagewidth

REGISTER

BYTE

MNEMONIC

BIT ADDRESS

ADDRESS (HEX)

T3

FFH

PWMP

FEH

PWM1

FDH

PWM0

FCH

IP1									F8H
	FF	FE	FD	FC	FB	FA	F9	F8
B									F0H
	F7	F6	F5	F4	F3	F2	F1	F0
RTE									EFH
STE									EEH
# TMH2									EDH
# TML2									ECH
CTCON									EBH
TM2CON									EAH
IEN1	EF	EE	ED	EC	EB	EA	E9	E8	E8H
ACC	E7	E6	E5	E4	E3	E2	E1	E0	E0H
CANADR									DBH
CANDAT									DAH
CANCON									D9H
CANSTA	DF	DE	DD	DC	DB	DA	D9	D8	D8H
									D0H
PSW	D7	D6	D5	D4	D3	D2	D1	D0
# CTH3									CFH
# CTH2									CEH
# CTH1									CDH
# CTH0									CCH
CMH2									CBH
CMH1									CAH
CMH0									C9H
									C8H
TM2IR	CF	CE	CD	CC	CB	CA	C9	C8
# ADCH									C6H
ADCON									C5H
# P5									C4H
									C0H
P4	C7	C6	C5	C4	C3	C2	C1	C0

SFRs containing directly addressable bits

MGA150

# denotes read-only registers

Fig.6 Special Function Register memory map (a).

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Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

DIRECT

handbook, full pagewidth

REGISTER

BYTE

MNEMONIC

BIT ADDRESS

ADDRESS (HEX)

IP0

B8H

BF

BE

BD

BC

BB

BA

B9

B8

P3

B0H

B7

B6

B5

B4

B3

B2

B1

B0

# CTL3

AFH

# CTL2

AEH

# CTL1

ADH

# CTL0

ACH

CML2

ABH

CML1

AAH

CML0

A9H

IEN0

AF

AE

AD

AC

AB

AA

A9

A8

A8H

P2

A7

A6

A5

A4

A3

A2

A1

A0

A0H

SFRs containing

S0BUF

99H

directly addressable

bits

S0CON

9F

9E

9D

9C

9B

9A

99

98

98H

P1

97

96

95

94

93

92

91

90

90H

TH1

8DH

TH0

8CH

TL1

8BH

TL0

8AH

TMOD

89H

88H

TCON

8F

8E

8D

8C

8B

8A

89

88

PCON

87H

DPH

83H

DPL

82H

SP

81H

P0

87

86

85

84

83

82

81

80

80H

# denotes read-only registers

MGA151

Fig.7 Special Function Register memory map (b).

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15

Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

8 I/O PORT STRUCTURE

The P8xCE598 has six 8-bit parallel ports: Port 0 to Port 5. In addition to the standard 8-bit parallel ports, the I/O facilities also include a number of special I/O lines. The use of a Port 1, Port 3 or Port 4 pins as an alternative function is carried out automatically provided the associated SFR bit is set HIGH.

Table 5 Default Port functions

PORT	TYPE	FUNCTION								REMARKS
Port 0	I/O	The same as in the 80C51								Except for the additional functions of P1.6 and
										P1.7.
Port 1	I/O
Port 2	I/O
Port 3	I/O
Port 4	I/O	Parallel I/O port								Parallel I/O function is identical to Port1, 2 and 3.
Port 5	I	Parallel input port with an input function only								May be used as normal inputs if the ADC function
										is inoperative.
Table 6 Alternative Port functions
PORT	TYPE	FUNCTION								REMARKS
Port 0	I/O	Multiplexed Low-order address and								Provides the multiplexed Low-order address and
		Data bus for external memory (AD7 to AD0)								data bus used for expanding the P8xCE598 with
										standard memories and peripherals.
Port 1	I/O	Capture timer inputs for Timer T2								External interrupt request inputs, if capture
		(CT0I to CT3I), or								information is not utilized.
		External interrupt request inputs
		(INT2 to INT5)
		T2 event input (T2)								External counter input.
		T2 timer reset input (RT2)								External counter reset input.
		CAN transmitter output 0 (CTX0)								CTX0 and CTX1 outputs of the CAN interface
										(note 1).
		CAN transmitter output 1 (CTX1)
Port 2	I/O	High-order address byte for external memory								Port 2 provides the High-order address bus when
		(A08 to A15)								the P8xCE598 is expanded with external Program
										Memory and/or external Data Memory.
Port 3	I/O	Serial Input Port (RXD)								Receiver input of serial port SIO0 (UART).
		Serial Output Port (TXD)								Transmitter output of serial port SIO0 (UART).
		External interrupt								External interrupt request inputs.
			(INT0)
		External interrupt
				(INT1)
		Timer 0 external input (T0)								Counter inputs.
		Timer 1 external input (T1)
		External data memory Write strobe								Control signal to write to external Data Memory.
						(WR)
		External data memory Read strobe								Control signal to read from external Data Memory.
							(RD)
Port 4	I/O	Compare and Set/Reset outputs								Can be configured to provide signals indicating a
		(CMSR0 to CMSR5)								match between Timer counter T2 and its compare
										registers.
		Compare and toggle outputs (CMT0, CMT1)
Port 5	I	Input channels to ADC (ADC7 to ADC0)								Port 5 may be used in conjunction with the ADC
										interface (note 2).

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Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

Notes to the Alternative Port functions

1.Port lines P1.6 and P1.7 may be selected as CTX0 and CTX1 outputs of the serial port SIO1 (CAN). After reset P1.6 and P1.7 may be used as normal I/O ports, if the CAN interface is not used.

2.Unused analog inputs can be used as digital inputs. As Port 5 lines may be used as inputs to the ADC, these digital inputs have an inherent hysteresis to prevent the input logic from drawing too much current from the power lines when driven by analog signals.

Channel-to-channel crosstalk should be taken into consideration when both digital and analog signals are simultaneously input to Port 5 (see Chapter 20).

handbook, full pagewidth	strong pull-up	+5 V
	2 oscillator
	periods	p2
	p1	p3
		I/O PIN
		PORT
Q		1, 2, 3 or 4
from port latch	n
		I1
input data
	INPUT	MGA153
read port pin	BUFFER

Fig.8 I/O buffers in the P8xCE598 (P1.0 to P1.5, Ports 2, 3, and 4).

9 PULSE WIDTH MODULATED OUTPUTS (PWM)

Two Pulse Width Modulated (PWM) output channels are available with the P8xCE598. These channels provide output pulses of programmable length and interval.

The repetition frequency is defined by an 8-bit prescaler PWMP which generates the clock for the counter.

Both the prescaler and counter are common to both PWM channels. The 8-bit counter counts modulo 255 i.e. from 0 to 254 inclusive. The value of the 8-bit counter is compared to the contents of two registers:

PWM0 and PWM1.

Provided the contents of either of these registers is greater than the counter value, the output of PWM0 or PWM1 is set LOW. If the contents of these register are equal to, or less than the counter value, the output will be HIGH. The pulse-width-ratio is therefore defined by the contents of the register PWM0 and PWM1. The pulse-width-ratio is in the range of 0 to 255¤255 and may be programmed in increments of 1¤255.

The repetition frequency fPWM, at the PWMn outputs is

	given by: fPWM	=	fCLK
			´ (PWMP + 1) ´ 255
		2

When using an oscillator frequency of 16 MHz, for example, the above formula would give a repetition frequency range of 123 Hz to 31.4 kHz.

By loading the PWM registers with either 00H or FFH, the PWM outputs can be retained at a constant HIGH or LOW level respectively. When loading FFH to the PWM registers, the 8-bit counter will never actually reach this (FFH) value.

Both output pins PWMn are driven by push-pull drivers, and are not shared with any other function.

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Philips Semiconductors

Product specification

8-bit microcontroller with on-chip CAN

P8xCE598

9.1 Prescaler frequency control register (PWMP)

Table 7 Prescaler frequency control register (address FEH)

7

6

5

4

3

2

1

0

PWMP.7

PWMP.6

PWMP.5

PWMP.4

PWMP.3

PWMP.2

PWMP.1

PWMP.0

Table 8 Description of PWMP bits

BIT

SYMBOL

FUNCTION

7 to 0

PWMP.7

Prescaler division factor.

to

The Prescaler division factor = (PWMP) + 1

PWMP.0

9.2 Pulse Width Register 0 (PWM0)

Table 9 Pulse Width Register (address FCH)

7

6

5

4

3

2

1

0

PWM0.7

PWM0.6

PWM0.5

PWM0.4

PWM0.3

PWM0.2

PWM0.1

PWM0.0

Table 10 Description of PWM0 bits

BIT

SYMBOL

FUNCTION

7 to 0

PWM0.7

Pulse width ratio.

( PWMn)

to

LOW/HIGH ratio of PWMn signals

PWM0.0

= -----------------------------------------

255

–( PWMn)

9.3 Pulse Width Register 1 (PWM1)

Table 11 Pulse width register (address FDH)

7	6	5	4			3		2		1	0
PWM1.7	PWM1.6	PWM1.5	PWM1.4			PWM1.3			PWM1.2	PWM1.1	PWM1.0
Table 12 Description of PWM1 bits
BIT	SYMBOL						FUNCTION
7 to 0	PWM1.7	Pulse width ratio.						( PWMn)
	to
		LOW/HIGH ratio of PWMn signals
	PWM1.0						= 255-----------------------------------------–( PWMn)

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Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

handbook, full pagewidth
			PWM0
I				OUTPUT
N			8-BIT COMPARATOR		PWM0
				BUFFER
T
	fclk
E
R
N
A	1/2	PRESCALER	8-BIT COUNTER
L
B		PWMP
U
S				OUTPUT
			8-BIT COMPARATOR		PWM1
				BUFFER
			PWM1		MGA154

Fig.9 Functional diagram of Pulse Width Modulated outputs.

10 ANALOG-TO-DIGITAL CONVERTER (ADC)

The analog input circuitry consists of an 8-input analog multiplexer and an ADC with 10-bit resolution. The analog reference voltage and analog power supplies are connected via separate input pins. The conversion takes 50 machine cycles i.e. 37.5 μs at 16 MHz oscillator frequency. The input voltage swing is from 0 V to AVDD. The ADC is controlled using the ADCON control register. Register bits ADCON.0 to ADCON.2 select the input channels of the analog multiplexer (see Fig.10).

The completion of the 10-bit analog-to-digital conversion is flagged by ADCI in the ADCON register and the result is stored in the SFR ADCH (upper 8-bits) and the 2 lower bits (ADC.1 and ADC.0) in register ADCON.

An analog-to-digital conversion in progress is unaffected by an external or software ADC start. The result of a completed conversion remains unchanged provided ADCI = HIGH. While ADCI or ADCS are HIGH, a new ADC START will be blocked and consequently lost. An analog-to-digital conversion already in progress is aborted when the Idle or Power-down mode is entered.

The result of a completed conversion (ADCI = HIGH) remains unaffected during the Idle mode.

The LOW-to-HIGH transition of STADC is recognized at the end of a machine cycle and the conversion commences at the beginning of the next cycle. When a conversion is initiated by software, the conversion starts at the beginning of the machine cycle following the instruction that sets ADCS.

The next two machine cycles are used to initiate the converter. At the end of this first cycle, the ADCS status flag is set to HIGH while the conversion is in progress. Sampling of the analog input commences at the end of the second cycle.

During the next eight machine cycles, the voltage at the previously selected pin of Port 5 is sampled and this input voltage should be stable in order to obtain a useful sample. In any case, the input voltage slew rate must be less than 10 V/ms (5 V conversion range) in order to prevent an undefined result. The conversion takes four machine cycles per bit.

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	Philips Semiconductors								Product specification
	8-bit microcontroller with on-chip CAN								P8xCE598
	10.1 ADC Control register (ADCON)
	Table 13 ADC Control register (address C5H)
	7	6	5		4		3	2	1	0
	ADC.1	ADC.0	ADEX		ADCI		ADCS	AADR2	AADR1	AADR0
	Table 14 Description of the ADCON bits
	BIT	SYMBOL					FUNCTION
	7	ADC.1	Bit 1 of ADC converted value.
	6	ADC.0	Bit 0 of ADC converted value.
	5	ADEX	Enable external start of conversion by STADC. If ADEX is:
			LOW, then conversion cannot be started externally by STADC (only by software by
			setting ADCS)
			HIGH, then conversion can be started externally by a rising edge on STADC or
			externally.
	4	ADCI	ADC interrupt flag. This flag is set when an analog-to-digital conversion result is ready
			to be read.
			If enabled, an interrupt is invoked. The flag must be cleared by software.
			It cannot be set by software (see Table 15).
	3	ADCS	ADC start and status. Setting this bit starts an analog-to-digital conversion. It may be
			set by software or by the external signal STADC. The ADC logic ensures that this signal
			is HIGH while the ADC is busy. On completion of the conversion, ADCS is reset at the
			same time the interrupt flag ADCI is set. ADCS can not be reset by software (see
			Table 15).
	2	AADR2	Analog input select. This binary coded address selects one of the eight analog port
			pins of P5 to be input to the converter. It can only be changed when ADCI and ADCS
	1	AADR1
			are both LOW. AADR2 is the MSB (e.g. 100B selects the analog input channel ADC4).
	0	AADR0

Table 15 ADCI and ADCS operating modes

If ADCI is cleared by software while ADCS is set at the same time a new analog-to-digital conversion with the same channel-number may be started. It is recommended to reset ADCI before ADCS is set.

ADCI	ADCS	OPERATION
0	0	ADC not busy, a conversion can be started.
0	1	ADC busy, start of a new conversion is blocked.
1	X (don’t care)	Conversion completed (note 1).

Note

1. Start of a new conversion requires ADCI = 0.

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Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

andbook, full pagewidth

STADC

ADC0

ADC1

analog reference

ADC2

ADC3

ANALOG INPUT

10-BIT A/D

ADC4

MULTIPLEXER

CONVERTER

supply (analog part)

ADC5

ADC6

ground (analog part)

ADC7

ADCON	0	1	2	3		4		5	6	7		0	1	2	3		4		5	6	7	ADCH

INTERNAL BUS	MGA155

Fig.10 Functional diagram of analog input.

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21

Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

11 TIMERS/COUNTERS

The P8xCE598 contains:

·Three 16-bit timer/event counters: Timer 0, Timer 1 and Timer 2

·One 8-bit timer, T3 (Watchdog WDT).

11.1Timer 0 and Timer 1

Timer 0 and Timer 1 may be programmed to carry out the following functions:

·Measure time intervals and pulse durations

·Count events

·Generate interrupt requests.

Timer 0 and Timer 1 can be programmed independently to operate in 3 modes:

Mode 0 8-bit timer or 8-bit counter each with divide-by-32 prescaler.

Mode 1 16-bit timer-interval or event counter.

Mode 2 8-bit timer-interval or event counter with automatic reload upon overflow.

Timer 0 can be programmed to operate in an additional mode as follows:

Mode 3 one 8-bit time-interval or event counter and one 8-bit timer-interval counter.

When Timer 0 is in Mode 3, Timer 1 can be programmed to operate in Modes 0, 1 or 2 but cannot set an interrupt flag or generate an interrupt. However, the overflow from Timer 1 can be used to pulse the Serial Port baud-rate generator.

The frequency handling range of these counters with a 16 MHz crystal is as follows:

·In the timer function, the timer is incremented at a frequency of 1.33 MHz (1¤12 of the oscillator frequency)

·0 Hz to an upper limit of 0.66 MHz (1¤24 of the oscillator frequency) when programmed for external inputs.

Both internal and external inputs can be gated to the counter by a second external source for directly measuring pulse durations. When configured as a counter, the register is incremented on every falling edge on the corresponding input pin, T0 or T1.

The earliest moment, when the incremented register value can be read is during the second machine cycle following the machine cycle within which the incrementing pulse occurred.The counters are started and stopped under software control. Each one sets its interrupt request flag

when it overflows from all HIGHs to all LOWs

(or automatic reload value), with the exception of Mode 3 as previously described.

11.2Timer T2 Capture and Compare Logic

Timer T2 is a 16-bit timer/counter which has capture and compare facilities (see Fig.11).

The 16-bit timer/counter is clocked via a prescaler with a programmable division factor of 1, 2, 4 or 8. The input of the prescaler is clocked with 1¤12 of the oscillator frequency, or by an external source connected to the T2 input, or it is switched off. The maximum repetition rate of the external clock source is 1¤12fCLK, twice that of Timer 0 and Timer 1. The prescaler is incremented on a rising edge. It is cleared if its division factor or its input source is changed, or if the timer/counter is reset.

T2 is readable ‘on the fly’, without any extra read latches; this means that software precautions have to be taken against misinterpretation at overflow from least to most significant byte while T2 is being read. T2 is not loadable and is reset by the RST signal or at the positive edge of the input signal RT2, if enabled. In the Idle mode the timer/counter and prescaler are reset and halted.

T2 is connected to four 16-bit Capture Registers: CT0, CT1, CT2 and CT3. A rising or falling edge on the inputs CT0I, CT1I, CT2I or CT3I (alternative function of Port 1) results in loading the contents of T2 into the respective Capture Registers and an interrupt request.

Using the Capture Register CTCON, these inputs may invoke capture and interrupt request on a positive edge, a negative edge or on both edges. If neither a positive nor a negative edge is selected for capture input, no capture or interrupt request can be generated by this input.

The contents of the Compare Registers CM0, CM1 and CM2 are continually compared with the counter value of Timer T2. When a match occurs, an interrupt may be invoked. A match of CM0 sets the bits 0 to 5 of Port 4, a CM1 match resets these bits and a CM2 match toggles bits 6 and 7 of Port 4, provided these functions are enabled by the STE/RTE registers. A match of CM0 and CM1 at the same time results in resetting bits 0 to 5 of Port 4. CM0, CM1 and CM2 are reset by the RST signal.

Port 4 can be read and written by software without affecting the toggle, set and reset signals. At a byte overflow of the least significant byte, or at a 16-bit overflow of the timer/counter, an interrupt sharing the same interrupt vector is requested. Either one or both of these overflows can be programmed to request an interrupt. All interrupt flags must be reset by software.

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Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

handbook, full pagewidth		CT0I	INT	CT1I	INT	CT2I		INT	CT3I	INT
		CTI0			CTI1			CTI2		CTI3
		CT0			CT1		CT2			CT3
off
f CLK		1/12						8-bit overflow interrupt
				PRESCALER	T2 COUNTER
								16-bit overflow interrupt
T2
RT2
T2ER	external reset
		enable
						COMP	INT	COMP	INT	COMP	INT
	S	R	P4.0
	S	R	P4.1			CM0 (S)		CM1 (R)	CM2 (T)
	S	R	P4.2	I/O port 4
	S	R	P4.3
	S	R	P4.4							MGA156
	S	R	P4.5
	TG	T	P4.6
	TG	T	P4.7
STE		RTE
S	= set		T2 SFR address: TML2 = lower 8 bits
R	= reset			TMH2 = higher 8 bits
T	= toggle
TG = toggle status

Fig.11 Block diagram of Timer T2 configuration.

1996 Jun 27

23

Philips Semiconductors							Product specification
8-bit microcontroller with on-chip CAN							P8xCE598
11.2.1 COUNTER CONTROL REGISTER (TM2CON)
Table 16 Counter Control register (address EAH)
7	6	5	4		3	2	1	0
T2IS1	T2IS0	T2ER	T2B0		T2P1	T2P0	T2MS1	T2MS0
Table 17 Description of the TM2CON bits
BIT	SYMBOL				FUNCTION
7	T2IS1	Timer 2 16-bit overflow interrupt select.
6	T2IS0	Timer 2 byte overflow interrupt select.
5	T2ER	Timer 2 external reset enable.
4	T2B0	Timer 2 byte overflow interrupt flag.
3	T2P1	Timer 2 prescaler select (see Table 18).
2	T2P0
1	T2MS1	Timer 2 mode select (see Table 19).
0	T2MS0

Table 18 Timer 2 prescaler select

T2P1	T2P0	T2 CLOCK
0	0	Clock source
0	1	1¤2 Clock source
1	0	1¤4 Clock source
1	1	1¤8 Clock source

11.2.2CAPTURE CONTROL REGISTER (CTCON)

Table 19 Timer 2 mode select

T2MS1	T2MS0	MODE
0	0	Timer T2 is halted
0	1	T2 clock source = 1¤12fCLK
1	0	Test mode; do not use
1	1	T2 clock source = pin T2

Table 20 Capture Control register (address EBH)
7	6	5	4		3	2			1	0
CTN3	CTP3	CTN2	CTP2		CTN1		CTP1		CTN0	CTP0
Table 21 Description of the CTCON bits
BIT	SYMBOL				FUNCTION
		CAPTURE				INTERRUPT ON
7	CTN3	CT3I	negative edge
6	CTP3	CT3I	positive edge
5	CTN2	CT2I	negative edge
4	CTP2	CT2I	positive edge
3	CTN1	CT1I	negative edge
2	CTP1	CT1I	positive edge
1	CTN0	CT0I	negative edge
0	CTP0	CT0I	positive edge

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Philips Semiconductors								Product specification
8-bit microcontroller with on-chip CAN									P8xCE598
11.2.3 TIMER INTERRUPT FLAG REGISTER (TM2IR)
Table 22 Timer Interrupt Flag register (address C8H)
7	6	5		4		3	2	1	0
T2OV	CMI2	CMI1		CMI0		CTI3	CTI2	CTI1		CTI0
Table 23 Description of the TM2IR bits (see notes 1 and 2)
BIT	SYMBOL					FUNCTION
7	T2OV	T2: 16-bit overflow interrupt flag.
6	CMI2	CM2: interrupt flag.
5	CMI1	CM1: interrupt flag.
4	CMI0	CM0: interrupt flag.
3	CTI3	CT3: interrupt flag.
2	CTI2	CT2: interrupt flag.
1	CTI1	CT1: interrupt flag.
0	CTI0	CT0: interrupt flag.

Notes

1.Interrupt Enable IEN1 is used to enable/disable Timer 2 interrupts (see Section 14.1.2).

2.Interrupt Priority Register IP1 is used to determine the Timer 2 interrupt priority (see Section 14.1.4).

11.2.4SET ENABLE REGISTER (STE)

Table 24 Set Enable register (address EEH)

7	6	5	4	3	2	1	0
TG47	TG46	SP45	SP44	SP43	SP42	SP41	SP40
Table 25 Description of the STE bits (see notes 1 and 2)
BIT	SYMBOL			FUNCTION
7	TG47	if HIGH then P4.7 is reset on the next toggle, if LOW P4.7 is set on the next toggle.
6	TG46	if HIGH then P4.6 is reset on the next toggle, if LOW P4.6 is set on the next toggle.
5	SP45	if HIGH then P4.5 is set on a match of CM0 and T2.
4	SP44	if HIGH then P4.4 is set on a match of CM0 and T2.
3	SP43	if HIGH then P4.3 is set on a match of CM0 and T2.
2	SP42	if HIGH then P4.2 is set on a match of CM0 and T2.
1	SP41	if HIGH then P4.1 is set on a match of CM0 and T2.
0	SP40	if HIGH then P4.0 is set on a match of CM0 and T2.

Notes

1.If STE.n is LOW then P4.n is not affected by a match of CM0 and T2 (n = 0, 1, 2, 3, 4, 5).

2.STE.6 and STE.7 are read only.

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Philips Semiconductors								Product specification
8-bit microcontroller with on-chip CAN									P8xCE598
11.2.5 RESET/TOGGLE ENABLE REGISTER (RTE)
Table 26 Reset/Toggle Enable register (address EFH)
7	6	5		4		3	2	1	0
TP47	TP46	RP45		RP44		RP43	RP42	RP41		RP40
Table 27 Description of the RTE bits (note 1)
BIT	SYMBOL					FUNCTION
7	TP47	if HIGH then P4.7 toggles on a match of CM2 and T2.
6	TP46	if HIGH then P4.6 toggles on a match of CM2 and T2.
5	RP45	if HIGH then P4.5 is reset on a match of CM1 and T2.
4	RP44	if HIGH then P4.4 is reset on a match of CM1 and T2.
3	RP43	if HIGH then P4.3 is reset on a match of CM1 and T2.
2	RP42	if HIGH then P4.2 is reset on a match of CM1 and T2.
1	RP41	if HIGH then P4.1 is reset on a match of CM1 and T2.
0	RP40	if HIGH then P4.0 is reset on a match of CM1 and T2.

Note

1.If RTE.n is LOW then P4.n is not affected by a match of CM1 and T2 or CM2 and T2.

For more information, refer to the 8051-based “8-bit Microcontrollers Data Handbook IC20”.

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8-bit microcontroller with on-chip CAN	P8xCE598

11.3Watchdog Timer (T3)

In addition to Timer T2 and the standard timers (Timer 0 and Timer 1), a Watchdog Timer (WDT) comprising an 11-bit prescaler and an 8-bit timer (T3) is also provided (see Fig.12).

The timer T3 is incremented every 1.5 ms, derived from the oscillator frequency of 16 MHz by the following

fCLK

formula: f = -------------------------

timer 12 × 2048

When a timer T3 overflow occurs, the microcontroller is reset and a reset-output-pulse is generated at pin RST. This short output pulse (3 machine cycles) may be suppressed if the RST pin is connected to a capacitor.

To prevent a system reset (by an overflow of the WDT), the user program has to reload T3 within periods that are shorter than the programmed Watchdog time interval.

If the processor suffers a hardware/software malfunction, the software will fail to reload the timer. This failure will produce a reset upon overflow thus preventing the processor running out of control.

The Watchdog Timer can only be reloaded if the condition flag WLE = PCON.4 has been previously set by software. At the moment the counter is loaded the condition flag is automatically cleared.

The timer interval between the timer's reloading and the occurrence of a reset depends on the reloaded value. For example, this may range from 1.5 ms to 0.375 s when using an oscillator frequency of 16 MHz.

In the Idle state the Watchdog Timer and reset circuitry remain active.

The Watchdog Timer (WDT) is controlled by the Enable Watchdog pin (EW); see Table 28.

Table 28 EW controlling WDT and Power-down mode

PIN EW			WDT	POWER-DOWN MODE
LOW			enabled	disabled
HIGH			disabled	enabled

handbook, full pagewidth

INTERNAL BUS

VDD

1/12 fCLK	PRESCALER	TIMER T3 (8-BIT)		overflow	P
	11-BIT
	CLEAR	LOAD	LOADEN		RST
				internal
				reset
	write	CLEAR			R RST
		WLE		PD
	T3
				LOADEN
		PCON.4		PCON.1
EW
		INTERNAL BUS			MGA157

Fig.12 Functional diagram of T3 Watchdog Timer.

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8-bit microcontroller with on-chip CAN	P8xCE598

12 SERIAL I/O PORT: SIO0 (UART)

The Serial Port SIO0 is a full duplex (UART) serial I/O port i.e. it can transmit and receive simultaneously. This Serial Port is also receive-buffered. It can commence reception of a second byte before the previously received byte has been read from the receive register. However, if the first byte has still not been read by the time reception of the second byte is complete, one of these (first or second) bytes will be lost. The SIO0 receive and transmit registers are both accessed via the S0BUF SFR. Writing to S0BUF loads the transmit register, and reading S0BUF accesses to a physically separate receive register. SIO0 can operate in 4 modes:

Mode 0 Serial data is transmitted and received through RXD. TXD outputs the shift clock. 8 data bits are transmitted/received (LSB first). The baud rate is fixed at 1¤12 of the oscillator frequency.

Mode 1 10 bits are transmitted via TXD or received through RXD: a start bit (0), 8 data bits (LSB first), and a stop bit (1). On receive, the stop bit is put into RB8 of the S0CON SFR. The baud rate is variable.

Mode 2 11 bits are transmitted through TXD or received through RXD: a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1).

On transmit, the 9th data bit (TB8 in S0CON) can be assigned the value of 0 or 1. With nominal software, TB8 can be the parity bit (P in PSW). During a receive, the 9th data bit is stored in RB8 (S0CON), and the stop bit is ignored. The baud rate is programmable to either 1¤32 or 1¤64 of the oscillator frequency.

Mode 3 11 bits are transmitted through TXD or received through RXD: a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1).

Mode 3 is the same as Mode 2 except for the baud rate which is variable in Mode 3.

In all four modes, transmission is initiated by any instruction that writes to the S0BUF SFR.

Reception is initiated in Mode 0 when RI = 0 and REN = 1. In the other three modes, reception is initiated by the incoming start bit provided that REN = 1.

Modes 2 and 3 are provided for multiprocessor communications. In these modes, 9 data bits are received with the 9th bit written to RB8 (S0CON). The 9th bit is followed by the stop bit. The port can be programmed so that with receiving the stop bit, the Serial Port interrupt will be activated if, and only if RB8 = 1.

This feature is enabled by setting bit SM2 in S0CON. This feature may be used in multiprocessor systems.

For more information about how to use the UART in combination with the registers S0CON, PCON, IE, SBUF and the Timer register, refer to the 8051-based

“8-bit Microcontrollers Data Handbook IC20”.

13 SERIAL I/O PORT: SIO1 (CAN)

SIO1 (CAN) provides the CAN (Controller Area Network) serial-bus data communication interface. SIO1 (CAN) replaces the SIO1 (I2C) serial interface as provided in the microcontroller derivative P8xC552.

13.1On-chip CAN-controller

CAN is the definition of a high performance communication protocol for serial data communication. The P8xCE598 on-chip CAN-controller is a full implementation of the CAN 2.0A protocol. With the P8xCE598 powerful local networks can be built, both for automotive and general industrial environments. This results in a much reduced wiring harness and enhanced diagnostic and supervisory capabilities.

13.2CAN Features

·Multi-master architecture

·Bus access priority determined by the message identifier

·2032 message identifier (211 standard frame CAN 2.0A)

·Guaranteed latency time for high priority messages

·Powerful error handling capability

·Data length from 0 up to 8 bytes

·Multicast and broadcast message facility

·Non destructive bit-wise arbitration

·Non-return-to-zero (NRZ) coding/decoding with bit-stuffing

·Programmable transfer rate (up to 1 Mbit/s)

·Programmable output driver configuration

·Suitable for use in a wide range of networks including the SAE's network classes A, B and C

·DMA providing high-speed on-chip data exchange

·Bus failure management facility

·1¤2AVDD reference voltage.

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8-bit microcontroller with on-chip CAN	P8xCE598

13.3Interface between CPU and CAN

The internal interface between the P8xCE598's CPU and on-chip CAN-controller is achieved via the following four SFRs (see Fig.13):

∙CANADR, to point to a register of the CAN-controller

∙CANDAT, to read or write data

∙CANCON, to read interrupt flags and to write commands

∙CANSTA, to read status information and to write DMA pointer.

Additionally, the DMA-logic allows a high-speed data exchange between the CAN-controller and the CPU's on-chip Main RAM. For more information, see Section 13.5.15 “Handling of the CPU-CAN interface”.

13.4Hardware blocks of the CAN-controller

The P8xCE598 CAN-controller contains all necessary hardware for high performance serial network communications (see Fig.14 and Table 29).

It controls the communication flow through the area network using the CAN-protocol. The CAN-controller meets the following requirements:

∙Short message length

∙Bus access priority, determined by the message identifier

∙Powerful error handling capability

∙Configuration flexibility to allow area network expansion

∙Guaranteed latency time for urgent messages;

–The latency time defines the period between the initiation (Transmission Request) and the start of the transmission on the bus. The latency time strongly depends on a large variety of bus-related conditions. In the case of a message being transmitted on the bus and one distortion, the latency time can be up to 149 bit times (worst case). For more information see Chapter 22, “CAN application information”.

handbook, full pagewidth		internal
		bus			4 special function
					registers

	DBH	ADDRESS
	CANADR
	DAH	DATA
	CANDAT
CPU
		CAN
	D9H	CONTROLLER
	CANCON
	D8H
	CANSTA
MAIN	DMA bus	DMA
RAM		LOGIC
		MGA158

Fig.13 Interface between CPU and CAN-controller.

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Philips Semiconductors	Product specification
8-bit microcontroller with on-chip CAN	P8xCE598

address			2	CRX0
	INTERFACE			and
		BIT TIMING
	MANAGEMENT			CRX1
		LOGIC
data	LOGIC
			2	CTX0
				and
	TRANSMIT	TRANSCEIVER
				CTX1
	BUFFER	LOGIC
	ON - CHIP	CAN
		CONTROLLER
	RECEIVE	ERROR
		MANAGEMENT
	BUFFER 0
		LOGIC
	RECEIVE	BIT STREAM
	BUFFER 1	PROCESSOR
			MGA159

Fig.14 Block diagram of the P8xCE598 on-chip CAN-controller.

Table 29 Hardware blocks of the CAN-controller (see Fig.14)

NAME	BLOCK	DESCRIPTION
Interface Management Logic	IML	Interprets commands from the CPU, allocates the message buffers
		(TBF, RBF0 and RBF1) and provides interrupts and status information to the
		microcontroller.
Transmit Buffer	TBF	10 bytes memory into which the CPU writes messages which are to be
		transmitted over the CAN network.
Receive Buffers (0 and 1)	RBF0	RBF0 and RBF1 are each 10 bytes memories which are alternatively used to
		store messages received from the CAN network.
	RBF1
		The CPU can process one message while another is being received.
Bit Stream Processor	BSP	Is a sequencer, controlling the data stream between the Transmit Buffer,
		Receive Buffers (parallel data) and the CAN-bus (serial data).
Bit Timing Logic	BTL	Synchronizes the CAN-controller to the bitstream on the CAN-bus.
Transceiver Control Logic	TCL	Controls the output driver.
Error Management Logic	EML	Performs the error confinement according to the CAN-protocol.

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