Philips P87C770AAR-04 Datasheet

DATA SH EET

Product specification
Supersedes data of 1999 May 17
File under Integrated Circuits, IC20

1999 Jun 11

INTEGRATED CIRCUITS

P8xCx70 family

Microcontrollers for NTSC TVs with
On-Screen Display (OSD) and
Closed Caption (CC)

1999 Jun 11 2

Philips Semiconductors Product specification

Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)

P8xCx70 family

CONTENTS

1 FEATURES
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 BLOCK DIAGRAM
5 PINNING INFORMATION
6 MEMORY ORGANIZATION
7 I/O FACILITY
8 WATCHDOG TIMER (T3)
9 REDUCED POWER MODES
10 I2C-BUS SERIAL I/O
11 INTERRUPT SYSTEM
12 OSCILLATOR CIRCUITRY
13 RESET
14 PIN FUNCTION SELECTION
15 7-BIT PWM DAC
16 AFT INPUTS (ADC)
17 DATA SLICER AND CC COMMAND

INTERPRETER
18 CC/OSD DISPLAY FUNCTION
19 MEMORY DATA BIT ALLOCATION
20 PROGRAMMER
21 LIMITING VALUES
22 DC CHARACTERISTICS
23 AC CHARACTERISTICS
24 APPLICATION INFORMATION
25 RELEASE LETTER OF ERRATA
26 PACKAGE OUTLINE
27 SOLDERING
28 DEFINITIONS
29 LIFE SUPPORT APPLICATIONS
30 PURCHASE OF PHILIPS I2C COMPONENTS

1999 Jun 11 3

Philips Semiconductors Product specification

Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)

P8xCx70 family

1 FEATURES

• Fully static 80C51 CPU

• 64-kbyte programmable ROM

• 1-kbyte RAM

• On-chip 12 MHz crystal oscillator

• Eight 7-bit PWM outputs for analog controls

• Three input 4-bit software Analog-to-Digital Converters

(ADC)

• Power-on reset and Watchdog Timer

• 29 I/O lines via individual addressable controls

• Eight port lines (Port 2) with 10 mA LED sink (<1 V)

capability

• On-Screen Display (OSD) and Closed Caption (CC)

with V-chip function

• Byte-level I

2

C-bus interface up to 400 kHz

• Three power reduction modes: Standby, Idle and

Power-down

• Power supply: 5.0 V ±10%

• Operating temperature: −20 to +70 °C

• 52-pin shrink dual in-line package (SDIP52).

2 GENERAL DESCRIPTION

The P8xCx70 family consists of the following devices:

• P83C270

• P83C370

• P83C570

• P83C770

• P87C770.

The term P8xCx70 is used throughout this data sheet to
refer to all family members; differences between devices
are highlighted in the text.

The P8xCx70 family of microcontrollers are 8-bit,
80C51-based microcontrollers specifically designed for
the NTSC TV market. Each device has an On-Screen
Display, control functions and Closed Caption that
extracts, decodes (software) and displays caption signals
from NTSC TV signals. Extended Data Service (XDS) is
via the software command interpreter and the V-chip is
also implemented.

3 ORDERING INFORMATION

TYPE NUMBER

PACKAGE

ROM RAM

NAME DESCRIPTION VERSION

P83C270AAR SDIP52 plastic shrink dual in-line package;

52 leads (600 mil)

SOT247-1 24-kbyte 512-byte
P83C370AAR 32-kbyte 512-byte
P83C570AAR 48-kbyte 1-kbyte
P83C770AAR 64-kbyte 1-kbyte
P87C770AAR 64-kbyte

(OTP)

1-kbyte

1999 Jun 11 4

Philips Semiconductors Product specification

Microcontrollers for NTSC TVs with On-Screen

Display (OSD) and Closed Caption (CC)

P8xCx70 family

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4 BLOCK DIAGRAM

b

ook, full pagewidth

MGR380

2

8-bit internal bus

8-BIT

WATCHDOG

TIMER

(T3)

ROM

64-KBYTES

9 × 7-BIT

DACS

CC DATA SLICER

ON-SCREEN DISPLAY

(OSD)

P2

external

interrupts

8

P0

8

P3

PWM0 to PWM8

(1)

FBRG

B VSYNC

HSYNC

VPP/EA

RESET

ALE/PROG

PSEN

RAM

1-KBYTE

3 × 4-BIT

ADCS

TWO 16-BIT

TIMER/
COUNTERS
(T0 AND T1)

V

SSD

V

SSA

V

DDP

V

DDC

V

DDA

FUNCTION
COMBINED
PARALLEL
I/O PORTS

PARALLEL

I/O PORT

CPU

80C51 CORE
EXCLUDING

ROM/RAM

XI

XO

REFH

CVBS

I2C-BUS

INTERFACE

SDA

(3)

SCL

(3)

IREF

BLK

STN

8 5

P1

AFT0

(2)

AFT1

(2)

AFT2

(2)

Fig.1 Block diagram.

(1) Alternative functions of Port 0 except PWM0 which is an alternative function of Port 1.
(2) Alternative functions of Port 1.
(3) Alternative functions of Port 3.

1999 Jun 11 5

Philips Semiconductors Product specification

Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)

P8xCx70 family

5 PINNING INFORMATION

5.1 Pinning

Fig.2 Pinning configuration.

handbook, halfpage

P83C270
P83C370
P83C570
P83C770
P87C770

MGR372

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27

P0.0/PWM8
P0.1/PWM7
P0.2/PWM6
P0.3/PWM5
P0.4/PWM4
P0.5/PWM3
P0.6/PWM2
P0.7/PWM1

P1.0/AFT0
P1.1/AFT1
P1.2/AFT2

P1.3/PWM0

V

SSD
P2.7

P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0

V

SSA

CVBS

STN

BLK

IREF

P3.7
P3.6
P3.5/SDA
P3.4/SCL
P3.3/T1
P3.2/INT0
P3.1/T0
P3.0/INT1
V

DDC

RESET
XI
XO
V

SSD

V

DDP

V

DDA

VSYNC
HSYNC
FB
R
G
B
REFH
P1.4
ALE/PROG
VPP/EA
PSEN

1999 Jun 11 6

Philips Semiconductors Product specification

Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)

P8xCx70 family

5.2 Pin description
Table 1 SDIP52 package

SYMBOL PIN I/O DESCRIPTION

P0.0/PWM8
to P0.7/PWM1

1 to 8 I/O Port 0 lines P0.0 to P0.7 (open-drain, bidirectional); alternative functions 7-bit

PWM outputs.
P1.0/AFT0 9 I/O Port 1 line P1.0; alternative function as 4-bit AFT0 input.
P1.1/AFT1 10 I/O Port 1 line P1.1; alternative function as 4-bit AFT1 input.
P1.2/AFT2 11 I/O Port 1 line P1.2; alternative function as 4-bit AFT2 input.
P1.3/PWM0 12 I/O Port 1 I/O line P1.3 (open-drain, bidirectional); alternative function as 7-bit PWM0

output.
V

SSD

13 − Ground line for digital circuits.
P2.7 to P2.0 14 to 21 I/O Port 2 lines P2.7 to P2.0 (open-drain, bidirectional).
V

SSA

22 − Ground line for analog circuits.
CVBS 23 I Composite video input.
STN 24 I Data Slicer decoupling capacitor input, connect to V

SSA

via a 100 nF capacitor.

BLK 25 I CVBS signal black level reference, connect to V

SSA

via a 100 nF capacitor.

IREF 26 I CVBS signal reference current input, connect to V

SSA

via a 27 kΩ resistor.
PSEN 27 O Program Store Enable (active LOW); bonded out for testing purpose only.
V

PP

/EA 28 I External Access (active LOW); bonded out for testing purpose only. This pin is also

used for the 12.75 V programming voltage supply in OTP programming modes.

ALE/

PROG 29 I/O Address Latch Enable; bonded out for testing purpose only. This pin is also used

for programming pulses input in OTP programming modes.
P1.4 30 I/O Port 1 line P1.4 (open-drain, bidirectional).
REFH 31 I Data Slicer reference high capacitor input, connect to V

SSA

via a 100 nF capacitor.
B 32 O CC/OSD Blue colour current output.
G 33 O CC/OSD Green colour current output.
R 34 O CC/OSD Red colour current output.
FB 35 O CC/OSD fast blanking output.
HSYNC 36 I TV horizontal sync input (for OSD synchronization).
VSYNC 37 I TV vertical sync input (for OSD synchronization).
V

DDA

38 − +5 V analog power supply.

V

DDP

39 − +5 V digital power supply for peripherals.

V

SSD

40 I Ground line for digital circuits.
XO 41 O System oscillator crystal output.
XI 42 I System oscillator crystal input.
RESET 43 I Reset input (active HIGH).
V

DDC

44 − +5 V digital power supply for CPU core.
P3.0/

INT1 45 I/O Port 3 line P3.0; alternative function as external interrupt 1 input.
P3.1/T0 46 I/O Port 3 line P3.1; alternative function as Counter 0 input.
P3.2/

INT0 47 I/O Port 3 line P3.2; alternative function as external interrupt 0 input.
P3.3/T1 48 I/O Port 3 line P3.3; alternative function as Counter 1 input.

1999 Jun 11 7

Philips Semiconductors Product specification

Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)

P8xCx70 family

P3.4/SCL 49 I/O Port 3 line P3.4 (open-drain, bidirectional); alternative function as I2C-bus clock

line (open-drain).

P3.5/SDA 50 I/O Port 3 line P3.5 (open-drain, bidirectional); alternative function as I

2

C-bus data line

(open-drain).
P3.6 51 I/O Port 3 line P3.6 (open-drain, bidirectional).
P3.7 52 I/O Port 3 line P3.7 (open-drain, bidirectional).

SYMBOL PIN I/O DESCRIPTION

1999 Jun 11 8

Philips Semiconductors Product specification

Microcontrollers for NTSC TVs with On-Screen

Display (OSD) and Closed Caption (CC)

P8xCx70 family

6 MEMORY ORGANIZATION

The P8xCx70 family offers a choice of different RAM and ROM configurations; see “Ordering information”. The device has no external memory
capability, consequently the RD (read) and WR (write) signals are not bonded out. EA (External Access), PSEN (Program Store Enable) and ALE
(Address Latch Enable) are bonded out for testing purposes only.

For the complete memory map of the P8xC770 family refer to the 80C51 architecture in

“Data Handbook IC20”

.

6.1 SFR address map summary

The SFRs are presented in ascending address order.

Table 2 SFR address map summary

ADDRESS REGISTER NAME 76543210

80H

(1)

P0 (latch) P07 P06 P05 P04 P03 P02 P01 P00

81H

(1)

Stack Pointer (SP) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
86H PWM0 (7-bit PWM) PWM0E data6 data5 data4 data3 data2 data1 data0
87H

(1)

Power Control Register (PCON) −−−WLE GF1 GF0 PD IDL
88H

(1)

Timer/Counter Control Register (TCON) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
89H

(1)

Timer/Counter Mode Control Register (TMOD) Gate C/T M1 M0 Gate C/T M1 M0
8AH

(1)

Timer 0 Low byte (TL0) TL07 TL06 TL05 TL04 TL03 TL02 TL01 TL00
8BH

(1)

Timer 1 Low byte (TL1) TL17 TL16 TL15 TL14 TL13 TL12 TL11 TL10
8CH

(1)

Timer 0 High byte (TH0) TH07 TH06 TH05 TH04 TH03 TH02 TH01 TH00
8DH

(1)

Timer 1 High byte (TH1) TH17 TH16 TH15 TH14 TH13 TH12 TH11 TH10
90H

(1)

P1 (latch) P17 P16 P15 P14 P13 P12 P11 P10
92H Standby Control Register (STBCON) −−−−−−−STBY
96H PWM1 (7-bit PWM) PWM1E data6 data5 data4 data3 data2 data1 data0
98H Interrupt Request Register 1 (IRQ1) − RCC RBUSY −−−−−
A0H

(1)

P2 (latch) P27 P26 P25 P24 P23 P22 P21 P20
A6H PWM2 (7-bit PWM) PWM2E data6 data5 data4 data3 data2 data1 data0
A8H

(1)

Interrupt Enable Register 0 (IEN0) EA − ES1 − ET1 EX1 ET0 EX0
B0H

(1)

P3 (latch) P37 P36 P35 P34 P33 P32 P31 P30
B6H PWM3 (7-bit PWM) PWM3E data6 data5 data4 data3 data2 data1 data0
B7H Slice Line Register (SL) −−−CS4 CS3 CS2 CS1 CS0
B8H

(1)

Interrupt Priority Register 0 (IP0) −−PS1 − PT1 PX1 PT0 PX0
C6H PWM4 (7-bit PWM) PWM4E data6 data5 data4 data3 data2 data1 data0

1999 Jun 11 9

Philips Semiconductors Product specification

Microcontrollers for NTSC TVs with On-Screen

Display (OSD) and Closed Caption (CC)

P8xCx70 family

Notes

1. Standard 80C51 registers.

2. Read only registers.

D0H

(1)

Program Status Word (PSW) CY AC F0 RS1 RS0 OV − P
D6H PWM5 (7-bit PWM) PWM5E data6 data5 data4 data3 data2 data1 data0
D7H Closed Caption Data1 (CCData1) D7 D6 D5 D4 D3 D2 D1 D0
D8H Serial Control Register (S1CON) CR2 ENS1 STA STO SI AA CR1 CR0
D9H

(2)

Status Register (S1STA) SC4 SC3 SC2 SC1 SC0 0 0 0
DAH Data Shift Register (S1DAT) D7 D6 D5 D4 D3 D2 D1 D0
DBH Slave Address Register (S1ADR) SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0 GC
E0H Accumulator (ACC) ACC7 ACC6 ACC5 ACC4 ACC3 ACC2 ACC1 ACC0
E6H PWM6 (7-bit PWM) PWM6E data6 data5 data4 data3 data2 data1 data0
E7H Closed Caption Data 2 (CCData2) D7 D6 D5 D4 D3 D2 D1 D0
E8H

(1)

Interrupt Enable Register 1 (IEN1) − ECC EBUSY −−−−−
EAH AFT Control Register (AFCON) − AFTH1 AFTH0 AFTL3 AFTL2 AFTL1 AFTL0 AFTC
EBH Busy Interrupt and Watchdog Control Register

(BWC)

−−−−−−EW BUSY

F0H

(1)

B Register (B) B7 B6 B5 B4 B3 B2 B1 B0
F4H Port 1 Selection Register (P1SEL) −−− I

2

CE − AFT2E AFT1E AFT0E
F5H PWM8(7-bit PWM) PWM8E data6 data5 data4 data3 data2 data1 data0
F6H PWM7(7-bit PWM) PWM7E data6 data5 data4 data3 data2 data1 data0
F8H Interrupt Priority Register 1 (IP1) − PCC PBUSY −−−−−
FFH Watchdog Timer Register (WDT) data7 data6 data5 data4 data3 data2 data1 data0

ADDRESS REGISTER NAME 76543210

1999 Jun 11 10

Philips Semiconductors Product specification

Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)

P8xCx70 family

6.2 Display control registers map

The display control registers can only be addressed using MOVX instructions.

Table 3 Display control register map

ADDRESS

(HEX)

REGISTER NAME 76543210

87F0 Display Control SRC3 SRC2 SRC1 SRC0 FLF MSH MOD1 MOD0
87F1 Text Vertical Position VPOL HPOL VOL5 VOL4 VOL3 VOL2 VOL1 VOL0
87F2 Text Horizontal Position HOP1 HOP0 TAS5 TAS4 TAS3 TAS2 TAS1 TAS0
87F3 Fringing Control FRC3 FRC2 FRC1 FRC0 FRDN FRDE FRDS FRDW
87F4 Text Area End −−TAE5 TAE4 TAE3 TAE2 TAE1 TAE0
87F5 Scroll Area SSH3 SSH2 SSH1 SSH0 SSP3 SSP2 SSP1 SSP0
87F6 Scroll Range SPS3 SPS2 SPS1 SPS0 STS3 STS2 STS1 STS0
87F7 RGB Brightness FBPOL −−−BRI3 BRI2 BRI1 BRI0
87F8 Status (Read) BUSY − FIELD SCRL SCR3 SCR2 SCR1 SCR0

Status (Write) − H/V SCON SCRL −−−−
87FC HSYNC Delay − HSD6 HSD5 HSD4 HSD3 HSD2 HSD1 HSD0
87FD Odd/Even Align − OEA6 OEA5 OEA4 OEA3 OEA2 OEA1 OEA0
87FE reserved −−−−−−−−
87FF Configuration CC PLUS ADJ MIN −−−−

7 I/O FACILITY

7.1 I/O ports

The P8xCx70 has 29 I/O lines treated as 29 individual
addressable bits or as 4 parallel 8-bit addressable ports,
e.g. Ports 0, 1, 2 and 3, with the exception of Port 1 which
has only 5 lines available.

7.2 Port type

All I/O port pins are open-drain, bidirectional and require
external pull-up resistors. No port options are available for
masking.

Fig.3 Open-drain I/O port.

handbook, halfpage

MGK547

n

Q

from port latch

input data

read port pin

INPUT

BUFFER

I/O pin

1999 Jun 11 11

Philips Semiconductors Product specification

Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)

P8xCx70 family

8 WATCHDOG TIMER (T3)

In addition to the standard timers, an 8-bit Watchdog Timer
is also incorporated. When a timer overflow occurs, the
microcontroller is reset. To prevent a system reset the
timer must be reloaded in time by the application software.
If the processor suffers a hardware/software malfunction,
the software will fail to reload the timer. This failure will
result in a reset upon overflow thus preventing the
processor running out of control.

The timer is incremented every 2 ms. The timer interval
between the timer reloading and the occurrence of a reset
depends on the reloaded value. This may range from
2 to 512 ms according to the following formula:

T

timer

256 T3 value–()2ms×=

The Watchdog Timer can only be reloaded if the condition
flag WLE in SFR PCON has been previously set HIGH by
software. At the moment the counter is loaded WLE is
automatically cleared.

The Watchdog Timer is controlled by the EW bit in SFR
BWC (see Section 11.5). If EW = 1, the Watchdog Timer is
enabled and the Power-down mode disabled. If EW = 0,
the Watchdog Timer is disabled and the Power-down
mode enabled.

In the Idle mode the Watchdog Timer and reset circuitry
remain active.

8.1 Watchdog Timer Register (WDT)
Table 4 Watchdog Timer Register (SFR address FFH)

Table 5 Description of the T3 bits

76543210

D7 D6 D5 D4 D3 D2 D1 D0

BIT SYMBOL DESCRIPTION

7 to 0 D7 to D0 Watchdog Timer reload value. These 8 bits determine the timer interval. If WDT holds

FFH the timer interval is 2 ms. If WDT holds 00H the timer interval is 512 ms.

handbook, full pagewidth

MGL298

INTERNAL BUS

1/12 f

osc

PRESCALER

11-BIT

WDT REGISTER

(8-BIT)

LOADCLEAR LOADEN

write T3

LOADEN

PCON.4

PCON.0

CLEAR

WLE IDL

internal reset

INTERNAL BUS

RESET

R

RESET

Fig.4 Watchdog Timer block diagram.

1999 Jun 11 12

Philips Semiconductors Product specification

Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)

P8xCx70 family

9 REDUCED POWER MODES

In order to reduce power consumption three reduced
power modes are available: Standby, Idle and
Power-down.

9.1 Standby mode

In Standby mode full CPU functionality is available but all
analog functions (including the OSD) are disabled.
Power-on reset and the oscillator remain active.
The following also remain active during Standby mode.

• CPU

• External interrupts

INT0 and INT1

• T0, T1 and T3

• I2C-bus interface

• PWM outputs.

The Standby mode is entered by setting the STBY bit in
the STBCON register to a logic 1. Recovering from the
Standby mode is achieved by setting the STBY bit back to
a logic 0. After entering the normal mode a waiting time of
10 µs has to be taken into account in order to allow the
analog circuitry to stabilize.

9.2 Idle mode

Idle mode operation permits all functions to continue to
work with the exception that the CPU clock is halted.
The following functions remain active during Idle mode:

• T0, T1 and T3 (Watchdog Timer)

• I

2

C-bus

• External interrupts.

9.2.1 E

NTERING IDLE MODE

The instruction that sets the IDL bit in the PCON register is
the last instruction executed before entering Idle mode.
Once in the Idle mode the system oscillator keeps running
but the internal clock is gated away from the CPU, but not
gated away from the interrupts, timers and serial port
functions. The CPU status is preserved along with the
Stack Pointer, Program Counter, Program Status Word
and Accumulator. The RAM and all other registers
maintain their data during Idle mode. The port pins retain
the logical states they were holding at Idle mode activation.

9.2.2 R

ECOVERING FROM IDLE MODE

There are two methods used to terminate the Idle mode.
Assertion of any enabled interrupt will cause the IDL bit to
be cleared by hardware, thus terminating the Idle mode.
The interrupt is serviced, and following the instruction

RETI, the next instruction to be executed will be the one
following the instruction that put the device into the Idle
mode.

Flag bits GF0 and GF1 may be used to determine whether
the interrupt was received during normal execution or
during Idle mode. For example, the instruction that writes
to the IDL bit can also set or clear one or both flag bits.
When Idle mode is terminated by an interrupt, the service
routine can examine the status of the flag bits.

The second method of terminating the Idle mode is with an
external hardware reset. Since the oscillator is still
running, the hardware reset is required to be active for only
two machine cycles to complete the reset operation. Reset
redefines all SFRs, but does not affect the on-chip RAM.

9.3 Power-down mode

The Power-down operation freezes the oscillator and all
on-chip operations stop. The Power-down mode can only
be entered if the EW bit in SFR BWC is LOW; then the
Power-down mode is entered by setting the PD bit in the
PCON register to a logic 1.

The instruction which sets the PD bit in PCON is the last
instruction executed prior to going into the Power-down
mode. The contents of the on-chip RAM and SFRs are
preserved. The port pins output the values held by their
respective SFRs.

In the Power-down mode VDD may be reduced to minimize
power consumption. However, the supply voltage must not
be reduced until Power-down mode is active, and must be
restored before the hardware reset is applied and frees the
oscillator. An on-chip delay counter will count 2048 system
oscillator cycles before enabling the internal clock.

9.3.1 W

AKE-UP FROM POWER-DOWN USING EXTERNAL

INTERRUPTS

If either of the external interrupts INT0 and INT1 is
switched to level-sensitive and enabled then the interrupt
can be used to wake-up the P8xCx70 from the
Power-down mode. To ensure that the oscillator is stable
before the controller restarts, the internal clock will remain
inactive for 2048 system oscillator cycles.

9.3.2 W

AKE-UP FROM POWER-DOWN USING RESET

The Power-down mode can be terminated by holding the
RESET pin HIGH for two machine cycles, this clears the
PD bit. The on-chip delay counter will count 2048 system
oscillator cycles before enabling the internal clock.

1999 Jun 11 13

Philips Semiconductors Product specification

Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)

P8xCx70 family

9.4 Control registers

9.4.1 S

TANDBY CONTROL REGISTER (STBCON)

Table 6 Standby Control Register (SFR address 92H)

Table 7 Description of STBCON bits

9.4.2 POWER CONTROL REGISTER (PCON)
Idle and Power-down modes are activated by software via the Special Function Register PCON.

Table 8 Power Control Register (SFR address 87H)

Table 9 Description of PCON bits

76543210

−−−−−−−STBY

BIT SYMBOL DESCRIPTION

7to1 − These 7-bits are reserved.

0 STBY Standby mode selection. When STBY = 1, the device enters Standby mode.

76543210

−−−WLE GF1 GF0 PD IDL

BIT SYMBOL DESCRIPTION

7to5 − These 3 bits are reserved.

4 WLE Watchdog Load Enable. If WLE = 1, the Watchdog Timer can be loaded. If WLE= 0,

the Watchdog Timer cannot be loaded.
3 GF1 General purpose flag 1.
2 GF0 General purpose flag 0.
1PDPower-down mode selection. If PD = 1, the Power-down mode is entered (provided

that the EW bit in SFR BWC is LOW).
0 IDL Idle mode selection. If IDL = 1, the Idle mode is entered. If IDL = 0, the Idle mode is

inhibited, i.e.normal operation.

1999 Jun 11 14

Philips Semiconductors Product specification

Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)

P8xCx70 family

Fig.5 Idle and Power-down circuit.

handbook, full pagewidth

MGL595

OSCILLATOR

CLOCK

GENERATOR

interrupts
serial ports
timer blocks
CC

CPU

IDL

PD

XIXO

P8xCx70 family

1999 Jun 11 15

Philips Semiconductors Product specification

Microcontrollers for NTSC TVs with On-Screen
Display (OSD) and Closed Caption (CC)

P8xCx70 family

10 I2C-BUS SERIAL I/O

10.1 The I

2

C-bus

This serial port supports the twin line I2C-bus. The I2C-bus
consists of a serial data line (SDA) and a serial clock line
(SCL). These lines also function as I/O port lines
P3.5 and P3.4 respectively.

The system is unique because data transport, clock
generation, address recognition and bus control arbitration
are all controlled by hardware.

Full details of the I2C-bus are given in the document

“The I2C-bus and how to use it”

. This document may be

ordered using the code 9398 393 40011.

10.2 Operation modes

The I

2

C-bus serial I/O has complete autonomy in byte

handling and operates in four modes.

• Master transmitter

• Master receiver

• Slave transmitter

• Slave receiver.

These functions are controlled by the S1CON register.
S1STA is the Status Register whose contents may also be
used as a vector to various service routines. S1DAT is the
Data Shift Register and S1ADR the Slave Address
Register. Slave address recognition is performed by
hardware.

Fig.6 Block diagram of the I2C-bus serial I/O.

handbook, full pagewidth

MBC749 - 1

SLAVE ADDRESS

S1ADR

GC

SHIFT REGISTER

S1DAT

SDA

ARBITRATION LOGIC

SCL BUS CLOCK GENERATOR

S1STA

INTERNAL BUS

76543210

S1CON

76543210

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10.3 Serial Control Register (S1CON)
Table 10 Serial Control Register (SFR address D8H)

Table 11 Description of S1CON bits

76543210

CR2 ENS1 STA STO SI AA CR1 CR0

BIT SYMBOL DESCRIPTION

6 ENS1 Enable Serial I/O. When ENS1 = 0, the SIO is disabled and reset. The SDA and SCL

outputs are in a high-impedance state; P3.4 and P3.5 function as open-drain ports.

When ENS1 = 1, the SIO is enabled. The P3.4 and P3.5 port latches must be set to

logic 1.
5 STA START flag. When the STA bit is set in Slave mode, the SIO hardware checks the

status of the I

2

C-bus and generates a START condition if the bus is free. If STA is set

while the SIO is in Master mode, SIO transmits a repeated START condition.
4STOSTOP flag. With this bit set while in Master mode a STOP condition is generated. When

a STOP condition is detected on the bus, the SIO hardware clears the STO flag. In the

Slave mode, the STO flag may also be set to recover from an error condition. In this

case, no STOP condition is transmitted to the I

2

C-bus interface. However, the SIO
hardware behaves as if a STOP condition has been received and releases SDA and
SCL. The SIO then switches to the ‘not addressed’ slave receiver mode. The STO flag
is automatically cleared by hardware.

3SISIO interrupt flag. When the SI flag is set, an acknowledge is returned after any one of

the following conditions:

• A START condition is generated in Master mode

• Own slave address received during AA = 1

• General call address received while S1ADR.0 = 1 and AA = 1

• Data byte received or transmitted in Master mode (even if arbitration is lost)

• Data byte received or transmitted as selected slave

• STOP or START condition received as selected slave receiver or transmitter.

2AAAssert Acknowledge. When the AA flag is set, an acknowledge (LOW level to SDA)

will be returned during the acknowledge clock pulse on the SCL line when:

• Own slave address is received

• General call address is received (S1ADR.0 = 1)

• Data byte received while device is programmed as a Master receiver

• Data byte received while device is a selected Slave receiver.

With AA = 0, no acknowledge will be returned. Consequently, no interrupt is requested
when the ‘own slave address’ or general call address is received.

7 CR2 Clock Rate selection. These three bits determine the serial clock frequency when SIO

is in Master mode; see Table 12. The maximum I

2

C-bus frequency is 400 kHz.

1 CR1
0 CR0

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Table 12 Selection of SCL frequency in Master mode

10.4 Status Register (S1STA)

S1STA is an 8-bit read-only Special Function Register. The contents of S1STA may be used as a vector to a service
routine. This optimizes response time of the software and consequently that of the I

2

C-bus. The status codes for all
possible modes of the I2C-bus interface are given in Table 16. The abbreviations used in Table 16 are defined in
Table 15.

Table 13 Status Register (SFR address D9H)

Table 14 Description of S1STA bits

Table 15 Abbreviations used in Table 16

CR2 CR1 CR0 f

osc

DIVISOR BIT RATE (kHz) at f

osc

= 12 MHz

0 0 0 60 200
0 0 1 1600 7.5
0 1 0 40 300
0 1 1 30 400
1 0 0 240 50
1 0 1 3200 3.75
1 1 0 160 75
1 1 1 120 100

76543210

SC4 SC3 SC2 SC1 SC0 0 0 0

BIT SYMBOL DESCRIPTION

7 to 3 SC4 to SC0 5-bit status code; see Table 16.
2to0 − These 3 bits are held LOW.

SYMBOL DESCRIPTION

SLA 7-bit slave address

R read bit

W write bit
ACK acknowledgment (Acknowledge bit = 0)
ACK not acknowledge (Acknowledge bit = 1)

DATA 8-bit byte to or from the I

2

C-bus

MST master

SLV slave

TRX transmitter

REC receiver

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P8xCx70 family

Table 16 Status codes

S1STA VALUE DESCRIPTION

MST/TRX mode

08H a START condition has been transmitted
10H a repeated START condition has been transmitted
18H SLA and W have been transmitted; ACK received
20H SLA and W have been transmitted;

ACK received
28H DATA of S1DAT has been transmitted; ACK received
30H DATA of S1DAT has been transmitted;

ACK received

38H arbitration lost in SLA, R/W or DATA

MST/REC mode

38H arbitration lost while returning

ACK
40H SLA and R have been transmitted; ACK received
48H SLA and R have been transmitted;

ACK received
50H DATA has been received; ACK returned
58H DATA has been received;

ACK returned

SLV/REC mode

60H own SLA and W have been received; ACK returned
68H arbitration lost in SLA, R/W as MST; own SLA and W have been received;

ACK

returned
70H general CALL has been received; ACK returned
78H arbitration lost in SLA, R/W as MST; general CALL has been received
80H previously addressed with own SLA; DATA byte received; ACK returned
88H previously addressed with own SLA; DATA byte received;

ACK returned
90H previously addressed with general CALL; DATA byte has been received; ACK returned
98H previously addressed with general CALL; DATA byte has been received;

ACK returned

A0H a STOP condition or repeated START condition has been received while still addressed

as SLV/REC or SLV/TRX

SLV/TRX mode

A8H own SLA and R have been received. ACK returned
B0H arbitration lost in SLA, R/W as MST; own SLA and R have been received; ACK returned
B8H DATA byte has been transmitted; ACK received
C0H DATA byte has been transmitted;

ACK received

C8H last DATA byte has been transmitted (AA = logic 0) ACK received

Miscellaneous

00H bus error during MST mode or SLV mode, due to an erroneous START or STOP

condition

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P8xCx70 family

10.5 Data Shift Register (S1DAT)

This register contains the serial data to be transmitted or data has just been received. Bit 7 is transmitted or received first.

Table 17 Data Shift Register (DAH)

10.6 Slave Address Register (S1ADR)

This 8-bit register may be loaded with the 7-bit slave address to which the controller will respond when programmed as
slave receiver/transmitter. The LSB bit (GC) is used to determine whether the general CALL address is recognized.

Table 18 Slave Address Register (SFR address DBH)

Table 19 Description of S1ADR bits

76543210

D7 D6 D5 D4 D3 D2 D1 D0

76543210

SLA6 SLA5 SLA4 SLA3 SLA2 SLA1 SLA0 GC

BIT SYMBOL DESCRIPTION

7 to 1 SLA<6-0> own slave address

0 GC If GC = 0, the general CALL address is not recognized. If GC = 1, the general CALL

address is recognized.

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11 INTERRUPT SYSTEM

The P8xCx70 has seven interrupt sources, each of which
can be assigned one of two priority levels as shown in
Fig.7. The four interrupt sources common to the 80C51 are
the external interrupts (INT0 and INT1) and the Timer 0
and Timer 1 interrupts. The SIO1 (I2C-bus) interrupt is
generated by the S1 flag in the Serial Control Register
(S1CON). This flag is set when SFR S1STA is loaded with
a valid status code. The CC interrupt is generated by the
RCC flag in SFR IRQ1; this flag is set at the end of the
selected CVBS slice line. The

BUSY interrupt is generated
by the RBUSY flag which also resides in SFR IRQ1 and is
set by the OSD.

11.1 How interrupts are handled

The interrupt flags are sampled at S5P2 of every machine
cycle. The samples are polled during the following
machine cycle. If one of the flags was in a set condition at
S5P2 of the preceding cycle, the polling cycle will find it
and the interrupt system will generate a LCALL to the
appropriate service routine, provided that LCALL is not
blocked by any of the following conditions:

1. An interrupt of equal priority or higher priority level is

already in progress.

2. The current machine cycle is not the final cycle in the

execution of the instruction in progress (no interrupt
request will be serviced until the instruction in progress
is completed).

3. The instruction in progress is RETI or any access to

the interrupt priority or interrupt enable registers (no
interrupt will be serviced after RETI or after a read or
write to IP0, IP1, IEN0 or IEN1 until at least one other
instruction has been subsequently executed).

The polling cycle is repeated with each machine cycle, and
the values polled are the values that were present at S5P2
of the previous machine cycle. Note that if an interrupt flag
is active but not being responded to for one of the above
mentioned conditions, if the flag is still inactive when the
blocking condition is removed, the denied interrupt will not
be serviced. In other words, the fact that the interrupt flag
was once active but not serviced is not remembered.
Every polling cycle is new.

Note that if an interrupt of higher priority level becomes
active prior to S5P2 of the machine cycle labelled C3, then
in accordance with the rules it will be vectored to during
C5 and C6, without any instruction of the lower priority
routine having been executed. Thus the processor
acknowledges an interrupt request by executing a
hardware generated LCALL to the appropriate servicing
routine. The hardware generated LCALL pushes the
contents of the Program Counter on to the stack (but does
not save the PSW) and reloads the PC with an address
that depends on the source of the interrupt; see Table 20.

Execution proceeds from that location until the RETI
instruction is encountered. The RETI instruction informs
the processor that the interrupt routine is no longer in
progress, then pops the top two bytes from the stack and
reloads the Program Counter. Execution of the interrupted
program continues from where it left off.

Note that a simple RET instruction would also return
execution to the interrupted program, but it would have left
the interrupt control system thinking an interrupt was still in
progress, making future interrupts impossible.

Table 20 Interrupt vectors

Additional details on the interrupt operation are given in

“Data Handbook IC20, 80C51-Based 8-bit
Microcontrollers”

.

SOURCE VECTOR ADDRESS

INT0 0003H

I

2

C-bus 002BH

Timer 0 000BH

INT1 0013H

BUSY 0063H

Timer 1 001BH

CC 006BH

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Fig.7 The interrupt structure.

handbook, full pagewidth

INTERRUPT

SOURCES

PRIORITY

GLOBAL
ENABLE

PX0

S1

T0

PX1

BUSY

T1

CC

IEN0/1

REGISTERS

IP0/1

REGISTERS

HIGH

LOW

INTERRUPT POLLING SEQUENCE

MGR378

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Philips Semiconductors Product specification

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P8xCx70 family

11.2 Interrupt enable structure

Each interrupt source can be individually enabled or disabled by setting or clearing its associated bit in the Interrupt
Enable Registers (IEN0 and IEN1). All interrupt sources can also be globally disabled by clearing the EA bit in SFR IEN0.
The Interrupt Enable Registers are described in Sections 11.2.1 and 11.2.2.

11.2.1 I

NTERRUPT ENABLE REGISTER 0 (IEN0)

Table 21 Interrupt Enable Register 0 (SFR address A8H)

Table 22 Description of the IEN0 bits

11.2.2 I

NTERRUPT ENABLE REGISTER 1 (IEN1)

Table 23 Interrupt Enable Register 1 (SFR address E8H)

Table 24 Description of the IEN1 bits

76543210

EA − ES1 − ET1 EX1 ET0 EX0

BIT SYMBOL DESCRIPTION

7EAGeneral enable/disable control. When EA = 0, no interrupt is enabled. When EA = 1,

any individually enabled interrupt will be accepted.
6 − This bit is not used; program to a logic 0 for future compatibility reasons.
5 ES1 EnableI2C-bus SIO interrupt.
4 − This bit is not used; program to a logic 0 for future compatibility reasons.
3 ET1 Enable Timer 1 interrupt.
2 EX1 Enable external interrupt1.
1 ET0 Enable Timer 0 interrupt.
0 EX0 Enable external interrupt0.

76543210

−ECC EBUSY −−−−−

BIT SYMBOL DESCRIPTION

7 − This bit is not used; program to a logic 0 for future compatibility reasons.
6 ECC Enable external interrupt 8 (CC data ready).
5 EBUSY Enable external interrupt 7 (

BUSY interrupt).

4to0 − These 5 bits are not used; program to logic 0s for future compatibility reasons.

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11.3 Interrupt priority structure

Each interrupt source can be assigned one of two priority
levels. Interrupt priority levels are defined by the Interrupt
Priority Registers (IP0 and IP1). These registers are
described in Sections 11.3.1 and 11.3.2.

A low priority interrupt may be interrupted by a high priority
interrupt level interrupt. A high priority interrupt routine
cannot be interrupted by any other interrupt source. If two
interrupts of different priority occur simultaneously, the
high priority level request is serviced. If requests of the
same priority are received simultaneously, an internal
polling sequence determines which request is serviced.
Thus, within each priority level, there is a second priority
structure determined by the polling sequence. This second
priority structure is shown in Table 25.

Table 25 Interrupt priority

Note

1. The ‘priority within level’ structure is only used to
resolve simultaneous requests of the same priority
level.

SOURCE PRIORITY WITHIN LEVEL

(1)

INT0 highest

I

2

C-bus ↓

Timer 0 ↓

INT1 ↓

BUSY ↓

Timer 1 ↓

CC lowest

11.3.1 INTERRUPT PRIORITY REGISTER 0 (IP0)

Table 26 Interrupt Priority Register 0 (SFR address B8H)

Table 27 Description of IP0 bits

Note

1. Where: logic 0 = low priority; logic 1 = high priority.

76543210

−−PS1 − PT1 PX1 PT0 PX0

BIT

(1)

SYMBOL DESCRIPTION

7to6 − This bit is not used, program to a logic 0 for future compatibility reasons.

5 PS1 I

2

C-bus SIO interrupt priority level.
4 − This bit is not used, program to a logic 0 for future compatibility reasons.
3 PT1 Timer 1 interrupt priority level.
2 PX1 External interrupt1 priority level.
1 PT0 Timer 0 interrupt priority level.
0 PX0 External interrupt0 priority level.

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11.3.2 INTERRUPT PRIORITY REGISTER 1 (IP1)

Table 28 Interrupt Priority Register 1 (SFR address F8H)

Table 29 Description of the IP1 bits

11.4 Interrupt Request Register 1 (IRQ1)

An interrupt request from the Closed Caption Data Slicer or from the OSD will be flagged by setting the related bit in the
Interrupt Request Register 1 to a logic 1. These bits must be reset to logic 0s by software.

Table 30 Interrupt Request Register 1 (SFR address 98H)

Table 31 Description of IRQ1 bits

76543210

−PCC PBUSY −−−−−

BIT SYMBOL DESCRIPTION

7 − This bit is not used, program to a logic 0 for future compatibility reasons.
6 PCC CC interrupt priority level, fixed to a logic 1.
5 PBUSY

BUSY interrupt 7 priority level, fixed to a logic 1.

4to0 − These 5 bits are not used, program to logic 0s for future compatibility reasons.

76543210

−RCC RBUSY −−−−−

BIT SYMBOL DESCRIPTION

7 − This bit is not used, program to a logic 0 for future compatibility reasons.
6 RCC Request for CC interrupt, active HIGH.
5 RBUSY Request for BUSY interrupt, active HIGH.

4to0 − These 5 bits are not used, program to logic 0s for future compatibility reasons.