INTEGRATED CIRCUITS
83C749/87C749
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
Preliminary specification |
1998 Apr 23 |
Supersedes data of 1998 Jan 06
IC20 Data Handbook
m n r
Philips Semiconductors Preliminary specification
80C51 8-bit microcontroller family |
83C749/87C749 |
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2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count |
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DESCRIPTION
The Philips 83C749/87C749 offers many of the advantages of the 80C51 architecture in a small package and at low cost.
The 8XC749 Microcontroller is fabricated with Philips high-density CMOS technology. Philips epitaxial substrate minimizes CMOS latch-up sensitivity.
The 8XC749 contains a 2k × 8 ROM (83C749) EPROM (87C749), a
64 × 8 RAM, 21 I/O lines, a 16-bit auto-reload counter/timer, a fixed-priority level interrupt structure, an on-chip oscillator, a five channel multiplexed 8-bit A/D converter, and an 8-bit PWM output.
The EPROM version of this device, the 87C749, is available in plastic one-time programmable (OTP) packages. Once the array has been programmed, it is functionally equivalent to the masked ROM 83C749. Thus, unless explicitly stated otherwise, all references made to the 83C749 apply equally to the 87C749.
The 83C749 supports two power reduction modes of operation referred to as the idle mode and the power-down mode.
FEATURES
•Available in erasable quartz lid or One-Time Programmable plastic packages
•80C51 based architecture
•Small package sizes
±28-pin DIP
±28-pin Shrink Small Outline Package (SSOP)
±28-pin PLCC
•Wide oscillator frequency range: 3.5MHz to 16MHz
•Low power consumption:
±Normal operation: less than 11mA @ 5V, 12MHz
±Idle mode
±Power-down mode
•2k × 8 ROM (83C749)
EPROM (87C749)
•64 × 8 RAM
•16-bit auto reloadable counter/timer
•5-channel 8-bit A/D converter
•8-bit PWM output/timer
•10-bit fixed-rate timer
•Boolean processor
•CMOS and TTL compatible
•Well suited for logic replacement, consumer and industrial applications
PART NUMBER SELECTION
ROM |
EPROM1 |
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TEMPERATURE RANGE °C |
FREQUENCY |
DRAWING |
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AND PACKAGE |
NUMBER |
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P83C749EBP N |
P87C749EBP N |
OTP |
0 to +70, 28-pin Plastic Dual In-line Package |
3.5 to 16MHz |
SOT117-2 |
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P83C749EBA A |
P87C749EBA A |
OTP |
0 to +70, 28-pin Plastic Leaded Chip Carrier |
3.5 to 16MHz |
SOT261-3 |
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P83C749EBD DB |
P87C749EBD DB |
OTP |
0 to +70, 28-pin Shrink Small Outline Package |
3.5 to 16MHz |
SOT341-1 |
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NOTE:
1. OTP = One Time Programmable EPROM.
1998 Apr 23 |
2 |
Philips Semiconductors |
Preliminary specification |
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80C51 8-bit microcontroller family
83C749/87C749
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
BLOCK DIAGRAM
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P0.0±P0.4 |
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PORT 0 |
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DRIVERS |
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VCC |
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PWM |
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VSS |
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RAM ADDR |
RAM |
PORT 0 |
PORT 2 |
ROM/ |
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REGISTER |
LATCH |
LATCH |
EPROM |
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B |
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ACC |
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STACK |
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REGISTER |
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POINTER |
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PROGRAM |
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ADDRESS |
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TMP2 |
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TMP1 |
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REGISTER |
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ALU |
PCON |
TCON |
BUFFER |
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IE |
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TH0 |
TL0 |
PC |
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RTH |
RTL |
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PSW |
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INCRE- |
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INTERRUPT AND |
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MENTER |
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TIMER BLOCKS |
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PROGRAM |
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COUNTER |
RST |
TIMING |
INSTRUCTION |
REGISTER |
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DPTR |
AND |
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CONTROL |
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PD |
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PORT 1 |
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PORT 3 |
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LATCH |
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LATCH |
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OSCILLATOR |
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ADC |
PORT 1 |
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PORT 3 |
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DRIVERS |
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DRIVERS |
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X1 |
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X2 |
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AVSS |
AVCC |
P1.0±P1.7 |
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P3.0±P3.7 |
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SU00305 |
1998 Apr 23 |
3 |
Philips Semiconductors |
Preliminary specification |
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80C51 8-bit microcontroller family
83C749/87C749
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
PIN CONFIGURATION
P3.4/A4 |
1 |
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P3.3/A3 |
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2 |
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P3.2/A2/A10 |
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3 |
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P3.1/A1/A9 |
4 |
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P3.0/A0/A8 |
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5 |
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PLASTIC |
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DUAL |
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P0.2/VPP |
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IN-LINE |
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P0.1/OE±PGM |
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PACKAGE |
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7 |
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AND |
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SHRINK |
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P0.0/ASEL |
8 |
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SMALL |
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OUTLINE |
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RST |
9 |
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PACKAGE |
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X2 |
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10 |
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X1 |
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11 |
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VSS |
12 |
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P1.0/ADC0/D0 |
13 |
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P1.1/ADC1/D1 |
14 |
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4 |
1 |
26 |
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5 |
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PLASTIC |
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LEADED |
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CHIP |
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11 |
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CARRIER |
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12 |
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Pin |
Function |
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Pin |
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1 |
P3.4/A4 |
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2 |
P3.3/A3 |
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16 |
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3 |
P3.2/A2/A10 |
17 |
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P3.1/A1/A9 |
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P3.0/A0/A8 |
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P0.2/VPP |
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P0.1/OE-PGM |
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P0.0/ASEL |
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RST |
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10 |
X2 |
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24 |
11 |
X1 |
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25 |
12 |
VSS |
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26 |
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P1.0/ADC0/D0 |
27 |
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P1.1/ADC1/D1 |
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28 VCC
27 P3.5/A5
26 P3.6/A6
25 P3.7/A7
24 P0.4/PWM OUT
23 P0.3
22 P1.7/T0/D7
21 P1.6/INT1/D6
20 P1.5/INT0/D5
19 AVCC
18 AVSS
17 P1.4/ADC4/D4
16 P1.3/ADC3/D3
15 P1.2/ADC2/D2
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Function
P1.2/ADC2/D2
P1.3/ADC3/D3
P1.4/ADC4/D4
AVSS
AVCC
P1.5/INT0/D5
P1.6/INT1/D6
P1.7/T0/D7
P0.3 P0.4/PWM OUT P3.7/A7 P3.6/A6 P3.5/A5
VCC
SU00304
1998 Apr 23 |
4 |
Philips Semiconductors |
Preliminary specification |
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80C51 8-bit microcontroller family
83C749/87C749
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
PIN DESCRIPTION
MNEMONIC |
PIN NO. |
TYPE |
NAME AND FUNCTION |
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VSS |
12 |
I |
Circuit Ground Potential. |
VCC |
28 |
I |
Supply voltage during normal, idle, and power-down operation. |
P0.0±P0.4 |
8±6 |
I/O |
Port 0: Port 0 is a 5-bit bidirectional port. Port 0.0±P0.2 are open drain. Port 0.0±P0.2 pins that have |
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23, 24 |
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1s written to them float, and in that state can be used as high-impedance inputs. P0.3±P0.4 are |
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bidirectional I/O port pins with internal pull-ups. These pins are driven low if the port register bit is |
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written with a 0. The state of the pin can always be read from the port register by the program. Port 0.3 |
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and 0.4 have internal pull-ups that function identically to port 3. Pins that have 1s written to them are |
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pulled high by the internal pull-ups and can be used as inputs. |
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While P0.0 anbd P0.1 differ from ªstandard TTLº characteristics, they are close enough for the pins to |
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still be used as general-purpose I/O. |
6I VPP (P0.2) ± Programming voltage input. (See Note 2.)
7I OE/PGM (P0.1) ± Input which specifies verify mode (output enable) or the program mode.
OE/PGM = 1 output enabled (verify mode).
OE/PGM = 0 program mode.
8I ASEL (P0.0) ± Input which indicates which bits of the EPROM address are applied to port 3. ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
P1.0±P1.7 |
13±17, |
I/O |
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to |
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20±22 |
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them are pulled high by the internal pull-ups and can be used as inputs. P0.3±P0.4 pins are |
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bidirectional I/O port pins with internal pull-ups. As inputs, port 1 pins that are externally pulled low will |
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source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also |
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serves the special function features of the SC80C51 family as listed below: |
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20 |
I |
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(P1.5): External interrupt. |
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INT0 |
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21 |
I |
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(P1.6): External interrupt. |
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INT1 |
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22 |
I |
T0 (P1.7): Timer 0 external input. |
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13±17 |
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ADC0 (P1.0)±ADC4 (P1.4): Port 1 also functions as the inputs to the five channel multiplexed A/D |
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converter. These pins can be used as outputs only if the A/D function has been disabled. These pins |
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can be used as digital inputs while the A/D converter is enabled. |
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Port 1 serves to output the addressed EPROM contents in the verify mode and accepts as inputs the |
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value to program into the selected address during the program mode. |
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P3.0±P3.7 |
5±1, |
I/O |
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to |
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27±25 |
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them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are |
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externally being pulled low will source current because of the pull-ups. (See DC Electrical |
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Characteristics: IIL). Port 3 also functions as the address input for the EPROM memory location to be |
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programmed (or verified). The 11-bit address is multiplexed into this port as specified by P0.0/ASEL. |
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RST |
9 |
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Reset: A high on this pin for two machine cycles while the oscillator is running resets the device. An |
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internal diffused resistor to VSS permits a power-on RESET using only an external capacitor to VCC. |
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After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places the device |
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in the programming state allowing programming address, data and VPP to be applied for programming |
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or verification purposes. The RESET serial sequence must be synchronized with the X1 input. |
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X1 |
11 |
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Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. X1 |
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also serves as the clock to strobe in a serial bit stream into RESET to place the device in the |
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programming state. |
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X2 |
10 |
O |
Crystal 2: Output from the inverting oscillator amplifier. |
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AVCC 1 |
19 |
I |
Analog supply voltage and reference input. |
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AVSS 1 |
18 |
I |
Analog supply and reference ground. |
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NOTE:
1.AVSS (reference ground) must be connected to 0V (ground). AVCC (reference input) cannot differ from VCC by more than ±0.2V, and must be in the range 4.5V to 5.5V.
2.When P0.2 is at or close to 0 volt, it may affect the internal ROM operation. We recommend that P0.2 be tied to VCC via a small pullup (e.g., 2kΩ).
1998 Apr 23 |
5 |
Philips Semiconductors |
Preliminary specification |
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80C51 8-bit microcontroller family
83C749/87C749
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
OSCILLATOR CHARACTERISTICS
X1 and X2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator.
To drive the device from an external clock source, X1 should be driven while X2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.
IDLE MODE
The 8XC749 includes the 80C51 power-down and idle mode features. In idle mode, the CPU puts itself to sleep while all of the on-chip peripherals except the A/D and PWM stay active. The functions that continue to run while in the idle mode are Timer 0,
Timer I, and the interrupts. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode.
The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. Upon powering-up the circuit, or exiting from idle mode, sufficient time must be allowed for stabilization of the internal analog reference voltages before an A/D conversion is started.
Special Function Registers
The special function registers (directly addressable only) contain all of the 8XC751 registers except the program counter and the four register banks. Most of the 21 special function registers are used to control the on-chip peripheral hardware. Other registers include arithmetic registers (ACC, B, PSW), stack pointer (SP) and data pointer registers (DPH, DPL). Nine of the SFRs are bit addressable.
Data Pointer
The data pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). In the 80C51 this register allows the access of external data memory using the MOVX instruction. Since the 83C749 does not support MOVX or external memory accesses, this register is generally used as a 16-bit offset pointer of the accumulator in a MOVC instruction. DPTR may also be manipulated as two independent 8-bit registers.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware reset is the only way to terminate the power-down mode. The control bits for the reduced power modes are in the special function register
PCON.
Table 1. External Pin Status During Idle and
Power-Down Modes
MODE |
Port 0* |
Port 1 |
Port 2 |
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Idle |
Data |
Data |
Data |
Power-down |
Data |
Data |
Data |
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*Except for PWM output (P0.4).
DIFFERENCES BETWEEN THE 8XC749 AND THE 80C51
Program Memory
On the 8XC749, program memory is 2048 bytes long and is not externally expandable, so the 80C51 instructions MOVX, LJMP, and LCALL are not implemented. If these instructions are executed, the appropriate number of instruction cycles will take place along with external fetches; however, no operation will take place. The LJMP may not respond to all program address bits. The only fixed locations in program memory are the addresses at which execution is taken up in response to reset and interrupts, which are as follows:
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Program Memory |
Event |
Address |
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Reset |
000 |
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External |
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003 |
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INT0 |
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Counter/timer 0 |
00B |
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External |
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013 |
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INT1 |
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Timer I |
01B |
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ADC |
02B |
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PWM |
033 |
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Memory Organization
The 8XC749 manipulates operands in three memory address spaces. The first is the program memory space which contains program instructions as well as constants such as look-up tables. The program memory space contains 2k bytes in the 8XC749.
The second memory space is the data memory array which has a logical address space of 128 bytes. However, only the first 64 (0 to
3FH) are implemented in the 8XC749.
The third memory space is the special function register array having a 128-byte address space (80H to FFH). Only selected locations in this memory space are used (see Table 2). Note that the architecture of these memory spaces (internal program memory, internal data memory, and special function registers) is identical to the 80C51, and the 8XC749 varies only in the amount of memory physically implemented.
The 8XC749 does not directly address any external data or program memory spaces. For this reason, the MOVX instructions in the 80C51 instruction set are not implemented in the 83C749, nor are the alternate I/O pin functions RD and WR.
I/O Ports
The I/O pins provided by the 83C749 consist of port 0, port 1, and port 3.
Port 0
Port 0 is a 5-bit bidirectional I/O port and includes alternate functions on some pins of this port. Pins P0.3 and P0.4 are provided with internal pullups while the remaining pins (P0.0, P0.1, and P0.2) have open drain output structures. The alternate function for port P0.4 is PWM output.
If the alternate function PWM is not being used, then this pin may be used as an I/O port.
1998 Apr 23 |
6 |
Philips Semiconductors |
Preliminary specification |
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80C51 8-bit microcontroller family
83C749/87C749
2K/64 OTP/ROM, 5 channel 8-bit A/D, PWM, low pin count
Port 1
Port 1 is an 8-bit bidirectional I/O port whose structure is identical to the 80C51, but also includes alternate input functions on all pins. The alternate pin functions for port 1 are:
P1.0-P1.4 - ADC0-ADC4 - A/D converter analog inputs
P1.5 INT0 - external interrupt 0 input
P1.6 INT1 - external interrupt 1 input
P1.7 - T0 - timer 0 external input
If the alternate functions INT0, INT1, or T0 are not being used, these pins may be used as standard I/O ports. It is necessary to connect
AVCC and AVSS to VCC and VSS, respectively, in order to use P1.5, P1.6, and P1.7 pins as standard I/O pins. When the A/D converter is enabled, the analog channel connected to the A/D may not be used as a digital input; however, the remaining analog inputs may be used as digital inputs. They may not be used as digital outputs. While the
A/D is enabled, the analog inputs are floating.
Port 3
Port 3 is an 8-bit bidirectional I/O port whose structure is identical to the 80C51. Note that the alternate functions associated with port 3 of the 80C51 have been moved to port 1 of the 83C749 (as applicable). See Figure 1 for port bit configurations.
Counter/Timer Subsystem
The 8XC749 has one counter/timer called timer/counter 0. Its operation is similar to mode 2 operation on the 80C51, but is extended to 16 bits with 16 bits of autoload. The controls for this counter are centralized in a single register called TCON.
Timer I Implementation
Timer I is clocked once per machine cycle, which is the oscillator frequency divided by 12. The timer operation is enabled by setting the TIRUN bit (bit 4) in the I2CFG register. Writing a 0 into the TIRUN bit will stop and clear the timer. The timer is 10 bits wide, and when it reaches the terminal count of 1024, it carries out and sets the Timer I interrupt flag. An interrupt will occur if the Timer I interrupt is enabled by bit ETI (bit 4) of the Interrupt Enable (IE) register, and global interrupts are enabled by bit EA (bit 7) of the same IE register.
The vector address for the Timer I interrupt is 1Bhex, and the interrupt service routine must start at this address. As with all 8051 family microcontrollers, only the Program Counter is pushed onto the stack upon interrupt (other registers that are used both by the
READ |
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ALTERNATE |
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OUTPUT |
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LATCH |
FUNCTION |
VDD |
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INTERNAL
PULL-UP
INT. BUS |
D |
Q |
P1.X |
P1.X |
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LATCH |
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PIN |
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WRITE TO |
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CL |
Q |
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LATCH |
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READ
PIN ALTERNATE INPUT
FUNCTION
interrupt service routine and elsewhere must be explicitly saved). The Timer I interrupt flag is cleared by setting the CKRTI bit (bit 5 of the I1CFG register. For more information, see application note AN427.
Interrupt SubsystemÐFixed Priority
The IP register and the 2-level interrupt system of the 80C51 are eliminated. The interrupt structure is a seven-source, one-level interrupt system similar to the 8XC751. Simultaneous interrupt conditions are resolved by a single-level, fixed priority as follows:
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Interrupt Control Registers
The 80C51 interrupt enable register is modified to take into account the different interrupt sources of the 8XC749.
Interrupt Enable Register
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EX1 |
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EX0 |
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IE.7 |
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EAD |
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IE.4 |
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IE.3 |
EPWM |
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EX1 |
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ET0 |
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EX0 |
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External interrupt 0 |
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INT. BUS |
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ALTERNATE INPUT |
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FUNCTION |
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SU00306 |
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Figure 1. Port Bit Latches and I/O Buffers
1998 Apr 23 |
7 |
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