INTEGRATED CIRCUITS
83C748/87C748
80C51 8-bit microcontroller family 2K/64 OTP/ROM, low pin count
Preliminary specification |
1999 Apr 15 |
Supersedes data of 1998 Apr 23
IC20 Data Handbook
m n r
Philips Semiconductors |
Preliminary specification |
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80C51 8-bit microcontroller family
83C748/87C748
2K/64 OTP/ROM, low pin count
DESCRIPTION
The Philips 83C748/87C748 offers the advantages of the 80C51 architecture in a small package and at low cost.
The 8XC748 Microcontroller is fabricated with Philips high-density CMOS technology. Philips epitaxial substrate minimizes CMOS latch-up sensitivity.
The 8XC748 contains a 2k × 8 ROM (83C748) EPROM (87C748), a 64 × 8 RAM, 19 I/O lines, a 16-bit auto-reload counter/timer, a four-source, fixed-priority level interrupt structure, and an on-chip oscillator.
FEATURES
•80C51 based architecture
•Small package sizes
±24-pin DIP (300 mil ªskinny DIPº)
±24-pin Shrink Small Outline Package (SSOP)
±28-pin PLCC
•87C748 available in erasable quartz lid or one-time programmable plastic packages
•Wide oscillator frequency range: ±3.5 to 16MHz
•Low power consumption:
±Normal operation: less than 11mA @ 5V, 12MHz
±Idle mode
±Power-down mode
•2k × 8 ROM (83C748) 2k × 8 EPROM (87C748)
•64 × 8 RAM
•16-bit auto reloadable counter/timer
•10-bit fixed-rate timer
•Boolean processor
•CMOS and TTL compatible
•Well suited for logic replacement, consumer and industrial applications
•LED drive outputs
PIN CONFIGURATIONS
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P3.4/A4 |
1 |
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24 |
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VCC |
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P3.3/A3 |
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2 |
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23 |
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P3.5/A5 |
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P3.2/A2/A10 |
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22 |
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P3.6/A6 |
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P3.1/A1/A9 |
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PLASTIC |
21 |
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P3.7/A7 |
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DUAL |
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P3.0/A0/A8 |
5 |
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20 |
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P1.7/T0/D7 |
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IN-LINE |
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AND |
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P0.2/VPP |
6 |
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SHRINK |
19 |
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P1.6/INT1/D6 |
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SMALL |
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P0.1/OE±PGM |
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OUTLINE |
18 |
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P1.5/INT0/D5 |
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PACKAGE |
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P0.0/ASEL |
8 |
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P1.4/D4 |
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RST |
9 |
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16 |
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P1.3/D3 |
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X2 |
10 |
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15 |
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P1.2/D2 |
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X1 |
11 |
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14 |
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P1.1/D1 |
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VSS |
12 |
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13 |
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P1.0/D0 |
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4 |
1 |
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26 |
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5 |
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PLASTIC |
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25 |
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LEADED |
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CHIP |
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CARRIER |
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11 |
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19 |
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12 |
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18 |
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Pin |
Function |
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Pin |
Function |
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1 |
P3.4/A4 |
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15 |
P1.0/D0 |
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2 |
P3.3/A3 |
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16 |
P1.1/D1 |
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3 |
P3.2/A2/A10 |
17 |
P1.2/D2 |
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4 |
P3.1/A1/A9 |
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18 |
P1.3/D3 |
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5 |
NC* |
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19 |
P1.4/D4 |
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6 |
P3.0/A0/A8 |
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20 |
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P1.5/INT0/D5 |
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7 |
P0.2/VPP |
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21 |
NC* |
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8 |
P0.1/OE-PGM |
22 |
NC* |
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9 |
P0.0/ASEL |
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23 |
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P1.6/INT1/D6 |
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10 |
NC* |
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24 |
P1.7/T0/D7 |
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11 |
RST |
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25 |
P3.7/A7 |
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12 |
X2 |
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26 |
P3.6/A6 |
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13 |
X1 |
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27 |
P3.5/A5 |
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14 |
VSS |
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28 |
VCC |
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* NO INTERNAL CONNECTION |
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SU00295A |
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ORDERING INFORMATION
ROM |
EPROM1 |
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TEMPERATURE RANGE °C |
FREQUENCY |
DRAWING |
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AND PACKAGE |
MHz |
NUMBER |
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P83C748EBP N |
P87C748EBP N |
OTP |
0 to +70, Plastic Dual In-line Package |
3.5 to 16 |
SOT222-1 |
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P83C748EBA A |
P87C748EBA A |
OTP |
0 to +70, Plastic Leaded Chip Carrier |
3.5 to 16 |
SOT261-3 |
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P83C748EBD DB |
P87C748EBD DB |
OTP |
0 to +70, Shrink Small Outline Package |
3.5 to 16 |
SOT340-1 |
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NOTE:
1. OTP = One Time Programmable EPROM.
1999 Apr 15 |
2 |
Philips Semiconductors |
Preliminary specification |
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80C51 8-bit microcontroller family
83C748/87C748
2K/64 OTP/ROM, low pin count
BLOCK DIAGRAM
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P0.0±P0.2 |
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PORT 0 |
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DRIVERS |
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VCC |
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VSS |
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RAM ADDR |
RAM |
PORT 0 |
ROM/ |
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REGISTER |
LATCH |
EPROM |
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B |
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ACC |
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STACK |
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REGISTER |
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POINTER |
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PROGRAM |
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ADDRESS |
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TMP2 |
TMP1 |
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REGISTER |
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ALU |
PCON |
TCON |
BUFFER |
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IE |
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TH0 |
TL0 |
PC |
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RTH |
RTL |
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PSW |
INCRE- |
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INTERRUPT AND |
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MENTER |
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TIMER BLOCKS |
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PROGRAM |
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COUNTER |
RST |
TIMING |
INSTRUCTION |
REGISTER |
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DPTR |
AND |
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CONTROL |
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PD |
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PORT 1 |
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PORT 3 |
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LATCH |
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LATCH |
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OSCILLATOR |
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PORT 1 |
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PORT 3 |
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DRIVERS |
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DRIVERS |
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X1 |
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X2 |
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P1.0±P1.7 |
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P3.0±P3.7 |
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SU00296 |
1999 Apr 15 |
3 |
Philips Semiconductors |
Preliminary specification |
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80C51 8-bit microcontroller family
83C748/87C748
2K/64 OTP/ROM, low pin count
PIN DESCRIPTIONS
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PIN NO. |
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MNEMONIC |
DIP/ |
LCC |
TYPE |
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NAME AND FUNCTION |
SSOP |
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VSS |
12 |
14 |
I |
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Circuit Ground Potential |
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VCC |
24 |
28 |
I |
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Supply voltage during normal, idle, and power-down operation. |
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P0.0±P0.2 |
8±6 |
9±7 |
I/O |
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Port 0: Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float, |
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and in that state can be used as high-impedance inputs. These pins are driven low if the port register |
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bit is written with a 0. The state of the pin can always be read from the port register by the program. |
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P0.0 and P0.1 are open drain bidirectional I/O pins. While these differ from ªstandard TTLº |
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characteristics, they are close enough for the pins to still be used as general-purpose I/O. Port 0 |
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also provides alternate functions for programming the EPROM memory as follows: |
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6 |
7 |
N/A |
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VPP (P0.2) ± Programming voltage input. (See Note 1). |
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7 |
8 |
I |
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OE/PGM (P0.1) ± Input which specifies verify mode (output enable) or the program mode. |
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OE/PGM = 1 output enabled (verify mode). |
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OE/PGM = 0 program mode. |
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8 |
9 |
I |
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ASEL (P0.0) ± Input which indicates which bits of the EPROM address are applied to port 3. |
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ASEL = 0 low address byte available on port 3. |
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ASEL = 1 high address byte available on port 3 (only the three least significant bits are used). |
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P1.0±P1.7 |
13±20 |
15±20, |
I/O |
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Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written |
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23, 24 |
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to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins |
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that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical |
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Characteristics: IIL). Port 1 serves to output the addressed EPROM contents in the verify mode and |
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accepts as inputs the value to program into the selected address during the program mode. Port 1 |
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also serves the special function features of the 80C51 family as listed below: |
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18 |
20 |
I |
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(P1.5): External interrupt. |
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INT0 |
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19 |
23 |
I |
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(P1.6): External interrupt. |
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INT1 |
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20 |
24 |
I |
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T0 (P1.7): Timer 0 external input. |
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P3.0±P3.7 |
5±1, |
6, 4±1, |
I/O |
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Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written |
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23±21 |
27±25 |
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to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins |
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that are externally being pulled low will source current because of the pull-ups. (See DC Electrical |
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Characteristics: IIL). Port 3 also functions as the address input for the EPROM memory location to be |
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programmed (or verified). The 11-bit address is multiplexed into this port as specified by P0.0/ASEL. |
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RST |
9 |
11 |
I |
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Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. |
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An internal diffused resistor to VSS permits a power-on RESET using only an external capacitor to |
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VCC. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places |
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the device in the programming state allowing programming address, data and VPP to be applied for |
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programming or verification purposes. The RESET serial sequence must be synchronized with the |
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X1 input. |
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X1 |
11 |
13 |
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Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. |
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X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the |
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programming state. |
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X2 |
10 |
12 |
O |
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Crystal 2: Output from the inverting oscillator amplifier. |
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NOTE:
1.When P0.2 is at or close to 0 volts, it may affect the internal ROM operation. It is recommended that P0.2 be tied to VCC via a small pull-up (e.g. 2k ).
ABSOLUTE MAXIMUM RATINGS1, 2
PARAMETER |
RATING |
UNIT |
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Storage temperature range |
±65 to +150 |
°C |
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Voltage from VCC to VSS |
±0.5 to +6.5 |
V |
Voltage from any pin to VSS (except VPP) |
±0.5 to VCC + 0.5 |
V |
Power dissipation |
1.0 |
W |
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Voltage on VPP pin to VSS |
0 to +13.0 |
V |
Maximum IOL per I/O pin |
10 |
mA |
NOTES:
1.Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied.
2.This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
1999 Apr 15 |
4 |
Philips Semiconductors |
Preliminary specification |
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|
80C51 8-bit microcontroller family
83C748/87C748
2K/64 OTP/ROM, low pin count
DC ELECTRICAL CHARACTERISTICS
T = 0°C to +70°C, V |
CC |
= 5V ±10%, V |
SS |
= 0V1 |
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amb |
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SYMBOL |
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PARAMETER |
TEST CONDITIONS |
LIMITS |
UNIT |
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MIN |
MAX |
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VIL |
Input low voltage |
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±0.5 |
0.2VDD±0.1 |
V |
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VIH |
Input high voltage, except X1, RST |
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0.2VCC+0.9 |
VCC+0.5 |
V |
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VIH1 |
Input high voltage, X1, RST |
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0.7VCC |
VCC+0.5 |
V |
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P0.2 |
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VIL1 |
Input low voltage |
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±0.5 |
0.3VCC |
V |
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VIH2 |
Input high voltage |
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0.7VCC |
VCC+0.5 |
V |
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V |
OL |
Output low voltage, ports 1 and 3 |
I |
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= 1.6mA2 |
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0.45 |
V |
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OL |
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V |
OL1 |
Output low voltage, port 0.2 |
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I |
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= 3.2mA2 |
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0.45 |
V |
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OL |
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VOH |
Output high voltage, ports 1 and 3 |
IOH = ±60μA |
2.4 |
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V |
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IOH = ±25μA |
0.75VCC |
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V |
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IOH = ±10μA |
0.9VCC |
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V |
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Port 0.0 and 0.1 ± Drivers |
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VOL2 |
Output low voltage |
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IOL = 3mA |
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0.4 |
V |
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Driver, receiver combined: |
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(over VCC range) |
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C |
Capacitance |
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10 |
pF |
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IIL |
Logical 0 input current, ports 1 and 3 |
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VIN = 0.45V |
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±50 |
μA |
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I |
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Logical 1 to 0 transition current, ports 1 and 33 |
V = 2V (0 to 70°C) |
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±650 |
μA |
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TL |
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IN |
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ILI |
Input leakage current, port 0 |
0.45 < VIN < VCC |
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±10 |
μA |
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RRST |
Internal pull-down resistor |
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25 |
175 |
kΩ |
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CIO |
Pin capacitance |
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Test freq = 1MHz, |
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10 |
pF |
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Tamb = 25°C |
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I |
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Power-down current4 |
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V |
= 2 to V |
CC |
max |
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50 |
μA |
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PD |
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CC |
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VPP |
VPP program voltage (for 87C748 only) |
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VSS = 0V |
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VCC = 5V±10% |
12.5 |
13.0 |
V |
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Tamb = 21°C to 27°C |
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IPP |
Program current (for 87C748 only) |
VPP = 13.0V |
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50 |
mA |
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ICC |
Supply current (see Figure 2) |
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NOTES:
1.Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
2.Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: |
10mA |
Maximum IOL per 8-bit port: |
26mA |
Maximum total IOL for all outputs: |
67mA |
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
3.Pins of ports 1 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V.
4.Power-down ICC is measured with all output pins disconnected; port 0 = VCC; X2, X1 n.c.; RST = VSS.
5.Active ICC is measured with all output pins disconnected; X1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC ± 0.5V; X2 n.c.; RST = port 0 = VCC. ICC will be slightly higher if a crystal oscillator is used.
6.Idle ICC is measured with all output pins disconnected; X1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC ± 0.5V; X2 n.c.; port 0 = VCC; RST = VSS.
1999 Apr 15 |
5 |
Philips Semiconductors |
Preliminary specification |
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80C51 8-bit microcontroller family
83C748/87C748
2K/64 OTP/ROM, low pin count
AC ELECTRICAL CHARACTERISTICS
T = 0°C to +70°C, V |
CC |
= 5V ±10%, V |
SS |
= 0V1, 2 |
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amb |
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16MHz CLOCK |
VARIABLE CLOCK |
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SYMBOL |
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PARAMETER |
MIN |
MAX |
MIN |
MAX |
UNIT |
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1/tCLCL |
Oscillator frequency: |
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3.5 |
12 |
MHz |
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3.5 |
16 |
MHz |
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External Clock (Figure 1) |
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tCHCX |
High time |
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20 |
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20 |
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ns |
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tCLCX |
Low time |
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20 |
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20 |
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ns |
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tCLCH |
Rise time |
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20 |
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20 |
ns |
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tCHCL |
Fall time |
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20 |
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20 |
ns |
NOTES:
1.Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
2.Load capacitance for ports = 80pF.
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are:
C ± Clock
D ± Input data
H ± Logic level high
L |
± |
Logic level low |
Q ± |
Output data |
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T ± |
Time |
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V ± |
Valid |
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X |
± |
No longer a valid logic level |
Z |
± |
Float |
VCC ±0.5 |
tCLCX |
0.2VCC + 0.9
0.2VCC ± 0.1
0.45V |
tCHCX |
tCHCL |
tCLCH |
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tCLCL |
SU00297
Figure 1. External Clock Drive
ROM CODE SUBMISSION
When submitting ROM code for the 83C748, the following must be specified: 1. 2k byte user ROM data
ADDRESS |
CONTENT |
BIT(S) |
COMMENT |
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0000H to 07FFH |
DATA |
7:0 |
User ROM Data |
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1999 Apr 15 |
6 |
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