Philips N74F832N, N74F832D, N74F1832N, N74F1832D Datasheet

INTEGRATED CIRCUITS

74F832, 74F1832

Hex 2-input OR drivers

Product specification

1991 Jan 02

IC15 Data Handbook

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Philips Semiconductors	Product specification
Hex 2-input OR drivers	74F832/74F1832

FEATURES

•High capacitive drive capability

•Choice of configuration

Corner VCC and GND ± 74F832

Center VCC and GND ± 74F1832

•Typical propagation delay of 3.5ns

•Superior ground noise characteristics (implemented using output edge rate control)

•Increased source and sink current (64mA)

TYPE	TYPICAL PROP-	TYPICAL SUPPLY
	AGATION DELAY	CURRENT
		( TOTAL)
74F832	3.5ns	26mA
74F1832	3.5ns	26mA

PIN CONFIGURATION

		74F832
D0a	1	20	VCC
D0b	2	19	D5b
Q0	3	18	D5a
D1a	4	17	Q5
D1b	5	16	D4b
Q1	6	15	D4a
D2a	7	14	Q4
D2b	8	13	D3b
Q2	9	12	D3a
GND 10		11	Q3
		SF00511

ORDERING INFORMATION

		ORDER CODE
DESCRIPTION		COMMERCIAL RANGE			PKG DWG #
		VCC = 5V ±10%,
		Tamb = 0°C to +70°C
20±pin plastic Dual		N74F832N, N74F1832N			SOT146-1
In-line Package
20±pin plastic Small		N74F832D, N74F1832D			SOT163-1
Outline Large
INPUT AND OUTPUT LOADING
AND FAN OUT TABLE
PINS	DESCRIPTION		74F (U.L.)	LOAD VALUE
			HIGH/LOW		HIGH/LOW
Dna ± Dnb	Data inputs		1.0/0.033		20μA/20μA
Q0 ± Q5	Data outputs		3200/106.7		64mA/64mA

NOTE: One (1.0) FAST unit load is defined as: 20μA in the high state and 0.6mA in the low state.

LOGIC SYMBOL

										74F832
1			2	4		5		7		8		12		13		15		16			18		19
	D0a D0bD1a D1bD2a D2b D3aD3bD4aD4bD5a D5b
						Q0		Q1		Q2 Q3 Q4 Q5
						3		6		9		11		14 17
VCC = Pin 20
GND = Pin 10																					SF00512
IEC/IEEE SYMBOL
												74F832
			1
												1											3
			2
			4																				6
			5
			7																				9
			8
			12																				11
			13
			15																				14
			16
			18																				17
			19

SF00513

January 2, 1991

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853-1529 01348

Philips Semiconductors	Product specification
Hex 2-input OR drivers	74F832/74F1832

PIN CONFIGURATION					LOGIC DIAGRAM
		74F1832												74F832																		74F1832
D4b	1	20	D4a		D0a								1							3			D0a								6			8
	2	19	Q4										2									QO									7														QO
Q5					D0b																		D0b
D5a	3	18	D3b		D1a								4							6			D1a								9					11
													5									Q1									10														Q1
D5b	4	17	D3a		D1b																		D1b
VCC	5	16	Q3										7							9											12		14
					D2a								8									Q2	D2a								13														Q2
D0a	6	15	GND		D2b																		D2b
D0b	7	14	Q2		D3a								12							11		Q3	D3a								17	16													Q3
	8	13	D2b										13																		18
Q0					D3b																		D3b
													15																		20
D1a	9	12	D2a		D4a															14			D4a									19
																						Q4																							Q4
													16																		1
D1b 10		11	Q1		D4b																		D4b
					D5a								18							17			D5a								3		2
		SF00514											19									Q5									4														Q5
					D5b																		D5b
					VCC = Pin 20																		VCC = Pin 5
					GND = Pin 10																		GND = Pin 15																		SF00517

LOGIC SYMBOL

									74F1832
6		7	9		10		12		13		17		18		20		1	3		4
D0a D0bD1a D1bD2a D2b D3a D3bD4a D4bD5a D5b
					Q0		Q1		Q2 Q3 Q4 Q5
					8		11		14		16		19		2

VCC = Pin 5
GND = Pin 15	SF00515

FUNCTION TABLE

		INPUTS			OUTPUT
		Dna		Dnb	Qn
		H		X	H
		X		H	H
		L		L	L
NOTES:
H	=	High voltage level
L	=	Low voltage level
X	=	Don't care

IEC/IEEE SYMBOL

			74F1832
	6
			1	8
	7
	9			11
	10
	12			14
	13
17				16
18
	20			19
	1
		3		2
4
				SF00516

January 2, 1991

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