Philips N74F786N, N74F786D Datasheet

INTEGRATED CIRCUITS

74F786

4-bit asynchronous bus arbiter

Product specification

1991 Feb 14

IC15 Data Handbook

m n r

Philips Semiconductors	Product specification
4-bit asynchronous bus arbiter	74F786

FEATURES

•Arbitrates between 4 asynchronous inputs

•Separate grant output for each input

•Common output enable

•On board 4 input AND gate

•Metastable±free outputs

•Industrial temperature range available (±40°C to +85°C)

DESCRIPTION

The 74F786 is an asynchronous 4±bit arbiter designed for high speed real±time applications. The priority of arbitration is determined on a first±come first±served basis. Separate bus grant (BGn) outputs are available to indicate which one of the request inputs is served by the arbitration logic. All BGn outputs are enabled by a common enable (EN) pin. In order to generate a bus request signal a separate 4 input AND gate is provided which may also be used as an independent AND gate. Unused bus request (BR) inputs may be disabled by tying them high.

The 74F786 is designed so that contention between two or more request signals will not glitch or display a metastable condition. In

this situation an increase in the BRn to BGn tPHL may be observed. A typical 74F786 has an h = 6.6ns, t = 0.41ns and To = 5μsec.

Where:

h = Typical propagation delay through the device and t and To are device parameters derived from test results and can most nearly be defined as:

t = A function of the rate at which a latch in a metastable state resolves that condition.

To = A function of the measurement of the propensity of a latch to enter a metastable state. To is also a very strong function of the normal propagation delay of the device.

For further information, please refer to the 74F786 application notes.

		TYPICAL	TYPICAL
	TYPE		SUPPLY CURRENT
		PROPAGATION DELAY
			(TOTAL)
	74F786	6.6ns	55mA

ORDERING INFORMATION

		ORDER CODE
	COMMERCIAL RANGE	INDUSTRIAL RANGE
DESCRIPTION	VCC = 5V ±10%,	VCC = 5V ±10%,	PKG DWG #
	Tamb = 0°C to +70°C	Tamb = ±40°C to +85°C
16±pin plastic DIP	N74F786N	I74F786N	SOT 38-4
16±pin plastic SO	N74F786D	I74F786D	SOT109-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

	PINS						DESCRIPTION	74F (U.L.) HIGH/	LOAD VALUE HIGH/
								LOW	LOW
							Bus request inputs (active low)	1.0/3.0	20μA/1.8mA
	BR0 ± BR3
	A, B, C, D						AND gate inputs	1.0/1.0	20μA/0.6mA
							Common bus grant output enable input (active low)	1.0/1.0	20μA/0.6mA
			EN
	YOUT						AND gate output	150/40	3.0mA/24mA
							Bus grant outputs (active low)	150/40	3.0mA/24mA
	BG0 ± BG3

NOTE:

One (1.0) FAST unit load is defined as: 20μA in the high state and 0.6mA in the low state.

LOGIC SYMBOL									IEC/IEEE SYMBOL
										BUS ARBITER
											Φ
	4	5	6	7	15	1	2	3	9	EN	74F786
									4	BR0	BG0	13
	BR0 BR1 BR2 BR3				A	B	C	D	5
										BR1		12
											BG1
									6
6	EN									BR2	BG2	11
									7
												10
										BR3	BG3
		BG0	BG1	BG2		BG3 YOUT			15		&
									1
									2			14
		13	12	11		10	14
									3
VCC = Pin 16
GND = Pin 8							SF00442					SF00443

February 14, 1991

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853±1269 01717

Philips Semiconductors	Product specification
4-bit asynchronous bus arbiter	74F786

FUNCTIONAL DESCRIPTION

The BRn inputs have no inherent priority. The arbiter assigns priority to the incoming requests as they are received, therefore, the first BR asserted will have the highest priority. When a bus request is received its corresponding bus grant becomes active, provided that EN is low. If additional bus requests are made during this time they are queued. When the first request is removed, the arbiter services the bus request with the next highest priority. Removing a request while a previous request is being serviced can cause a grant to be changed when arbitrating between three or four requests. For that reason, the user should not remove ungranted requests when arbitrating between three or four requests. This does not apply to arbitration between two requests.

If two or more BRn inputs are asserted at precisely the same time, one of them will be selected at random, and all BGn outputs will be held in the high state until the selection is made. This guarantees that an erroneous BGn will not be generated even though a metastable condition may occur internal to the device. When the EN is in the high state the BGn outputs are forced high.

PIN CONFIGURATION

	B		1		16	VCC
	C		2		15	A
	D		3		14	YOUT
	BR0		4		13
							BG0
	BR1		5		12
							BG1
	BR2		6		11		BG2
	BR3		7		10		BG3
GND
			8		9		EN
					SF00441

PIN DESCRIPTION

SYMBOL

PINS

TYPE

NAME

FUNCTION

The logic of this device arbitrates between these four inputs.

BR0 ± BR3

4, 5, 6, 7

Input

Bus request inputs (active low)

Unused inputs should be tied high.

A, B, C, D

15, 1, 2, 3

Input

Inputs of the 4±input AND gate

9

Input

Enable input

When low it enables the

EN

BG0 ± BG3 outputs.

These outputs indicate the selected bus request.

BG0 corre-

BG0 ± BG3

13, 12, 11, 10

Output

Bus grant outputs (active low)

sponds to BR0, BG1 to BR1, etc.

YOUT

14

Output

Output of the 4±input AND gate

GND

8

Ground

ground (0V)

VCC

16

Power

Positive supply voltages

February 14, 1991

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Philips Semiconductors	Product specification
4-bit asynchronous bus arbiter	74F786

ARBITER FUNCTION TABLE

INPUTS

OUTPUTS

EN

BR0

BR1

BR2

BR3

BG0

BG1

BG2

BG3

L

1

X

X

X

L

H

H

H

L

X

1

X

X

H

L

H

H

L

X

X

1

X

H

H

L

H

L

X

X

X

1

H

H

H

L

H

X

X

X

X

H

H

H

H

Notes to mode selection function table

H

=

High±voltage level

L

=

Low±voltage level

X

=

Don't care

1

=

First of inputs to go low

ARBITER FUNCTION TABLE

			INPUTS				OUTPUT
	A		B		C	D	YOUT
	L		L		L	L	L
	L		L		L	H	L
	L		L		H	L	L
	L		L		H	H	L
	L		H		L	L	L
	L		H		L	H	L
	L		H		H	L	L
	L		H		H	H	L
	H		L		L	L	L
	H		L		L	H	L
	H		L		H	L	L
	H		L		H	H	L
	H		H		L	L	L
	H		H		L	H	L
	H		H		H	L	L
	H		H		H	H	H
Notes to AND function table
H	=	High±voltage level
L	=	Low±voltage level

February 14, 1991

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