INTEGRATED CIRCUITS
74F776
Pi-bus transceiver
Product specification |
1990 Dec 19 |
IC15 Data Handbook
m n r
Philips Semiconductors |
Product specification |
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Pi±bus transceiver |
74F776 |
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FEATURES
•Octal latched transceiver
•Drives heavily loaded backplanes with equivalent load impedances down to 10 ohms
•High drive (100mA) open collector drivers on B port
•Reduced voltage swing (1 volt) produces less noise and reduces power consumption
•High speed operation enhances performance of backplane buses and facilitates incident wave switching
•Compatible with Pi±bus and IEEE 896 Futurebus standards
•Built±in precision band±gap reference provides accurate receiver thresholds and improved noise immunity
•Controlled output ramp and multiple GND pins minimize ground bounce
•Glitch±free power up/power down operation
•Multiple package options
•Industrial temperature range available (±40°C to +85°C)
DESCRIPTION
The 74F776 is an octal bidirectional latched transceiver and is intended to provide the electrical interface to a high performance wired±OR bus. The B port inverting drivers are low±capacitance open collector with controlled ramp and are designed to sink 100mA from 2 volts. The B port inverting receivers have a 100 mV threshold region and a 4ns glitch filter.
The 74F776 B port interfaces to 'Backplane Transceiver Logic' (BTL). BTL features a reduced (1V to 2V) voltage swing for lower power
consumption and a series diode on the drivers to reduce capacitive loading. Incident wave switching is employed, therefore BTL propagation delays are short. Although the voltage swing is less for BTL, so is its receiver threshold, therefore noise margins are excellent.
BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane.
The 74F776 A port has TTL 3±state drivers and TTL receivers with a latch function. A separate high±level control voltage input (VX) is provided to limit the A side output level to a given voltage level (such as 3.3V). For 5.0V systems, VX is simply tied to VCC.
The 74F776 has a designed feature to control the B output transitions during power sequencing. There are two possible sequencing, They are as follows:
1.When LE = low and OEBn = low then the B outputs are disabled until the LE circuitry takes control. Then the B outputs will follow the A inputs, making a maximum of one transition during power±up (or down).
2. If LE = high or OEBn = high then the B outputs will be disabled during power±up (or down).
TYPE |
TYPICAL PROPAGA- |
TYPICAL SUPPLY |
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TION DELAY |
CURRENT( TOTAL) |
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74F776 |
6.5ns |
80mA |
ORDERING INFORMATION
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ORDER CODE |
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COMMERCIAL RANGE |
INDUSTRIAL RANGE |
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DESCRIPTION |
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VCC = 5V ±10%, Tamb = 0°C to +70°C |
VCC = 5V ±10%, Tamb = ±40°C to +85°C |
PKG DWG # |
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28±pin plastic DIP (600 mil) |
N74F776N |
I74F776N |
SOT117-2 |
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28±pin PLCC |
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N74F776A |
I74F776A |
SOT261-2 |
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INPUT AND OUTPUT LOADING AND FAN OUT TABLE |
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PINS |
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DESCRIPTION |
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74F (U.L.) |
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LOAD VALUE |
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HIGH/LOW |
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HIGH/LOW |
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A0 ± A7 |
PNP latched inputs |
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3.5/0.117 |
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70μA/70μA |
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B0 ± B7 |
Data inputs with threshold circuitry |
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5.0/0.167 |
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100μA/100μA |
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OEA |
A output enable input (active high) |
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1.0/0.033 |
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20μA/20μA |
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B output enable inputs (active low) |
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1.0/0.033 |
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20μA/20μA |
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OEB0, OEB1 |
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Latch enable input (active low) |
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1.0/0.033 |
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20μA/20μA |
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LE |
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A0 ± A7 |
3±state outputs |
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150/40 |
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3mA/24mA |
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B0 ± B7 |
Open collector outputs |
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OC/166.7 |
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OC/100mA |
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Notes to input and output loading and fan out table
One (1.0) FAST unit load is defined as: 20μA in the high state and 0.6mA in the low state.
OC = Open collector.
December 19, 1990 |
2 |
853 1121 01321 |
Philips Semiconductors |
Product specification |
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Pi±bus transceiver |
74F776 |
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PIN CONFIGURATION |
IEC/IEEE SYMBOL |
VCC 1 |
28 |
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LE |
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OEA |
2 |
27 |
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B0 |
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15 |
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16 |
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A0 |
3 |
26 |
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B1 |
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28 |
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GND |
4 |
25 |
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GND |
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2 |
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A1 |
5 |
24 |
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B2 |
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A2 |
6 |
23 |
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B3 |
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3 |
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A3 |
7 |
22 |
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GND |
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GND |
8 |
21 |
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B4 |
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5 |
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A4 |
9 |
20 |
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B5 |
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6 |
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A5 |
10 |
19 |
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B6 |
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7 |
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GND |
11 |
18 |
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GND |
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9 |
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A6 |
12 |
17 |
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B7 |
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10 |
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A7 |
13 |
16 |
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12 |
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OEB1 |
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VX |
14 |
15 |
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13 |
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OEB0 |
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SF00422 |
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EN2 |
EN1 |
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EN3 |
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ID |
27 |
2 |
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3 |
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26 |
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24 |
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23 |
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21 |
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20 |
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19 |
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17 |
SF00424
PIN CONFIGURATION PLCC
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GND A0 OEA VCC |
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B0 |
B1 |
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LE |
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4 |
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3 |
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2 |
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1 |
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28 |
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27 |
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26 |
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A1 |
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25 |
GND |
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A2 |
6 |
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B2 |
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24 |
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A3 |
7 |
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B3 |
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23 |
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PLCC |
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GND |
8 |
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GND |
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22 |
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A4 |
9 |
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21 |
B4 |
A5 |
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20 |
B5 |
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GND |
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11 |
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19 |
B6 |
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12 |
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14 |
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15 |
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17 |
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18 |
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A6 |
A7 VX |
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B7 GND |
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OEB0 |
OEB1 |
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SF00423 |
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LOGIC SYMBOL
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3 |
5 |
6 |
7 |
9 |
10 |
12 |
13 |
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A0 |
A1 |
A2 |
A3 |
A4 |
A5 |
A6 |
A7 |
15 |
OEB0 |
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2 |
OEA |
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28 |
LE |
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16 |
OEB1 |
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B0 |
B1 |
B2 |
B3 |
B4 |
B5 |
B6 |
B7 |
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27 |
26 |
24 |
23 |
21 |
20 |
19 |
17 |
VCC = Pin 1, VX = Pin 14
GND = Pin 4, 8, 11, 18, 22, 25
SF00425
PIN DESCRIPTION
SYMBOL |
PINS |
TYPE |
NAME AND FUNCTION |
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A0 ± A7 |
3, 5, 6, 7, 9, 10, 12, 13 |
I/O |
PNP latched input/3±state output (with VX control option) |
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B0 ± B7 |
27, 26, 24, 23, 21, 20, 19, 17 |
I/O |
Data input with special threshold circuitry to reject noise/ open collector output, high |
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current drive |
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15 |
Input |
Enables the B outputs when both pins are low |
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OEB0 |
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16 |
Input |
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OEB1 |
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OEA |
2 |
Input |
Enables the A outputs when high |
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28 |
Input |
Latched when high (a special feature is built in for proper enabling times) |
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LE |
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VX |
14 |
Input |
Clamping voltage keeping VOH from rising above VX (VX = Vcc for normal use) |
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December 19, 1990 |
3 |
Philips Semiconductors |
Product specification |
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Pi±bus transceiver |
74F776 |
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LOGIC DIAGRAM
VCC = Pin 1, VX = Pin 14, GND = Pin 4, 8, 11, 18, 22, 25
OEB0 |
15 |
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OEB1 |
16 |
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OEA |
2 |
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LE |
28 |
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A0 |
3 |
Data |
Q |
27 |
B0 |
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LE |
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A1 |
5 |
Data |
Q |
26 |
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B1 |
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LE |
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A2 |
6 |
Data |
Q |
24 |
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B2 |
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LE |
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A3 |
7 |
Data |
Q |
23 |
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B3 |
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LE |
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A4 |
9 |
Data |
Q |
21 |
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B4 |
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LE |
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A5 |
10 |
Data |
Q |
20 |
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B5 |
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LE |
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A6 |
12 |
Data |
Q |
19 |
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B6 |
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LE |
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A7 |
13 |
Data |
Q |
17 |
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B7 |
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LE |
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SF00426 |
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December 19, 1990 |
4 |
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