Philips N74F760N, N74F760D, N74F757N, N74F756N, N74F756D Datasheet
74F756
Octal inverter buffer (open-collector)
74F757
Octal buffer (open-collector)
74F760
Octal buffer (open-collector)
Product specification
IC15 Data Handbook
1989 Nov 27
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74F756/74F757/74F760
Buffers
74F756 Octal Inverter Buffer (Open Collector)
74F757 Octal Buffer (Open Collector)
74F760 Octal Buffer (Open Collector)
2
1989 Nov 27 853–0270 98220
FEA TURES
•Octal bus interface
•Open collector versions of 74F240, 74F241 and 74F244
DESCRIPTION
The 74F756, 74F757 and 74F760 are octal buffers that are ideal for
driving bus lines of buffer memory address registers. The 74F756 is
the open collector version of 74F240, 74F757 is the open collector
version of 74F241 and 74760 is the open collector version of
74F244. These devices feature two Output Enables. OE
a and OEb
(or OEb for the 74F757), each controlling four of the outputs.
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL SUPPL Y
CURRENT (TOTAL)
74F756 9.0ns 40mA
74F757 9.0ns 45mA
74F760 9.0ns 45mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
VCC = 5V ±10%, T
amb
= 0°C to +70°C
PKG DWG #
20–pin plastic DIP N74F756N, N74F757AN, N74F760N SOT146-1
20–pin plastic SOL N74F756D, N74F757AD, N74F760D SOT163-1
INPUT AND OUTPUT LOADING AND FAN OUT TABLE
PINS DESCRIPTION
74F (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
Ian, Ibn Data inputs 1.0/1.67 20µA/1.0mA
OEa, OEb Output enable input (active Low) 1.0/1.67 20µA/0.2mA
OEb Output enable input (active High 74F757) 1.0/1.67 20µA/1.0mA
Yan, Ybn Data outputs (74F757, 74F760) OC/106.7 OC/64mA
Yan, Ybn Data outputs (74F756) OC/106.7 OC/64mA
Notes:
One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the Low state.
OC=Open Collector
Philips Semiconductors Product specification
74F756/74F757/74F760Buffers
1989 Nov 27
3
PIN CONFIGURATION for 74F756
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
SF00320
OEa
Ia0
Yb0
Ia1
Y
b1
Ia2
Y
b2
Ia3
Yb3
GND
V
CC
OEb
Y
a0
Ib0
Y
a1
Ib1
Y
a2
Ib2
Ya3
Ib3
LOGIC SYMBOL for 74F756
VCC = Pin 20
GND = Pin 10
SF00321
119OEa
OEb
2 4 6 8 17 15 13 11
181614123579
Ia0 Ia1 Ia2 Ia3 Ib0 Ib1 Ib2 Ib3
Ya0 Ya1 Ya2 Ya3 Yb0 Yb1 Yb2 Yb3
IEC/IEEE SYMBOL for 74F756
2
4
6
8
17
15
13
11
1
19
18
16
14
12
3
5
7
9
EN1
EN2
1
2
SF01246
LOGIC DIAGRAM for 74F756
VCC = Pin 20
GND = Pin 10
SF01247
3
5
7
9
17
15
13
11
19
Y
b0
Y
b1
Y
b2
Y
b3
Y
a0
Y
a1
Y
a2
Y
a3
Ib0
Ib1
Ib2
Ib3
OE
b
18
16
14
12
2
4
6
8
1
Ia0
Ia1
Ia2
Ia3
OEb
FUNCTION TABLE for 74F756
INPUTS OUTPUTS
OEa Ia OEb Ib Ya Yb
L L L L H H
L H L H L L
H X H X H (off) H (off)
H = High voltage level
L = Low voltage level
X = Don’t care
Philips Semiconductors Product specification
74F756/74F757/74F760Buffers
1989 Nov 27
4
PIN CONFIGURATION for 74F757
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20 V
CC
SF01248
OEb
Ya0
Ib0
Ya1
Ib1
Ya2
Ib2
Ya3
Ib3
OE
a
Ia0
Yb0
Ia1
Yb1
Ia2
Yb2
Ia3
Yb3
GND
LOGIC SYMBOL for 74F757
OEa
OEb
1
19
V
CC
= Pin 20
GND = Pin 10
2 4 6 8 17 15 13 11
Ia0 Ia1 Ia2 Ia3 Ib0 Ib1 Ib2 Ib3
18 16 14 12 3 5 7 9
Ya0 Ya1Ya2Ya3Yb0Yb1Yb2Yb3
SF01250
IEC/IEEE SYMBOL for 74F757
1
2
SF01249
9
7
5
3
12
14
16
18
1
19
2
4
6
8
17
15
13
11
EN1
EN2
LOGIC DIAGRAM for 74F757
V
CC
= Pin 20
GND = Pin 10
2
4
6
8
1
18
16
14
12
Ia0
Ia1
Ia2
Ia3
OEa
Ya0
Ya1
Ya2
Ya3
17
15
13
11
19
3
5
7
9
Ib0
Ib1
Ib2
Ib3
OEb
Yb0
Yb1
Yb2
Yb3
SF01251
FUNCTION TABLE for 74F757
INPUTS OUTPUTS
OEa Ia OEb Ib Ya Yb
L L H L L L
L H H H H H
H X L X H (off) H (off)
H = High voltage level
L = Low voltage level
X = Don’t care
Loading...