Philips N74F74N, N74F74D Datasheet

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INTEGRATED CIRCUITS

74F74

Dual D-type flip-flop

Product specification

1996 Mar 12

Supercedes data of 1990 Oct 23

IC15 Data Handbook

m n r

Philips Semiconductors

Product specification

 

 

 

 

 

Dual D-type flip-flop

74F74

 

 

 

 

 

 

FEATURE

Industrial temperature range available (±40°C to +85°C)

DESCRIPTION

The 74F74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input. When set and reset are inactive (high), data at the D input is transferred to the Q and Q outputs on the low-to-high transition of the clock. Data must be stable just one setup time prior to the low-to-high transition of the clock for predictable operation. Clock triggering occurs at a voltage level and is not directly related to the transition time of the positive-going pulse. Following the hold time interval, data at the D input may be changed without affecting the levels of the output.

PIN CONFIGURATION

 

 

 

 

 

 

 

 

 

 

 

 

 

RD0

1

 

14

 

VCC

 

 

D0

 

 

 

 

 

 

 

 

 

2

 

13

 

RD1

 

CP0

 

 

 

 

D1

 

3

 

12

 

 

 

 

 

 

 

 

 

 

CP1

 

SD0

4

 

11

 

 

 

Q0

 

 

 

 

 

 

 

 

 

5

 

10

 

SD1

 

 

 

 

 

 

 

 

 

Q1

 

 

Q0

6

 

9

 

GND

 

 

 

 

 

 

 

7

 

8

 

Q1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SF00045

TYPE

TYPICAL fmax

TYPICAL SUPPLY CURRENT (TOTAL)

74F74

125MHz

11.5mA

 

 

 

ORDERING INFORMATION

 

ORDER CODE

 

 

 

 

 

 

 

DESCRIPTION

COMMERCIAL RANGE

 

INDUSTRIAL RANGE

PKG. DWG. #

VCC = 5V ±10%,

 

VCC = 5V ±10%,

 

 

 

 

Tamb = 0°C to +70°C

 

Tamb = ±40°C to +85°C

 

14-pin plastic DIP

N74F74N

 

I74F74N

SOT27-1

 

 

 

 

 

14-pin plastic SO

N74F74D

 

I74F74D

SOT108-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

 

 

PINS

 

 

 

 

 

 

 

DESCRIPTION

 

 

74F (U.L.) HIGH/LOW

 

LOAD VALUE HIGH/LOW

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D0, D1

 

Data inputs

 

 

1.0/1.0

 

 

 

20μA/0.6mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CP0, CP1

 

Clock inputs (active rising edge)

 

 

1.0/1.0

 

 

 

20μA/0.6mA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Set inputs (active low)

 

 

1.0/3.0

 

 

 

20μA/1.8mA

 

SD0, SD1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset inputs (active low)

 

 

1.0/3.0

 

 

 

20μA/1.8mA

 

RD0, RD1

 

 

 

 

 

Q0, Q1,

 

 

 

 

 

 

Data outputs

 

 

50/33

 

 

 

1.0mA/20mA

Q0, Q1

 

 

 

 

 

NOTE: One (1.0) FAST unit load is defined as: 20μA in the high state and 0.6mA in the low state.

 

 

 

 

 

 

LOGIC SYMBOL

 

 

 

 

 

 

 

 

 

 

IEC/IEEE SYMBOL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

S

&

 

5

 

 

3

 

 

 

CP0

D0

D1

 

 

3

C1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1D

 

 

6

 

 

4

 

 

 

SD0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

1

 

 

 

RD0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

 

CP1

 

 

 

 

 

 

 

10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

S

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

10

 

 

 

SD1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

9

 

 

 

 

 

 

 

 

 

 

 

 

11

 

 

 

13

 

 

 

RD1

 

 

 

 

 

 

 

C2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q0

Q0

Q1 Q1

 

 

2D

 

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

13

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC = Pin 14

5

6

9 8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GND = Pin 7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SF00046

 

 

 

 

 

 

 

SF00047

 

1996 Mar 12

2

853 0335 16554

Philips N74F74N, N74F74D Datasheet

Philips Semiconductors

Product specification

 

 

 

Dual D-type flip-flop

74F74

 

 

 

LOGIC DIAGRAM

SD

4, 10

 

 

 

RD

1, 13

5, 9

 

Q

 

3, 11

6, 8

CP

Q

 

 

D

2, 12

 

 

 

VCC = Pin 14

 

GND = Pin 7

 

 

 

SF00048

FUNCTION TABLE

 

 

 

 

 

INPUTS

 

OUTPUTS

OPERATING

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SD

 

 

RD

 

CP

 

D

Q

Q

MODE

 

 

 

 

 

 

 

L

 

 

H

 

X

 

X

H

 

L

Asynchronous set

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

L

 

X

 

X

L

 

H

Asynchronous reset

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

 

L

 

X

 

X

H

 

H

Undetermined*

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

H

 

 

h

H

 

L

Load º1º

 

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

H

 

 

l

L

 

H

Load º0º

 

 

 

 

 

 

 

 

 

 

 

 

 

H

 

 

H

 

 

X

NC

NC

Hold

NOTES:

 

 

 

 

 

 

 

 

H

=

High voltage level

 

 

 

 

 

 

h

=

High voltage level one setup time prior to low-to-high clock

 

transition

 

 

 

 

 

 

 

 

L

=

Low voltage level

 

 

 

 

 

 

l

=

Low voltage level one setup time prior to low-to-high clock

 

transition

 

 

 

 

 

 

 

 

NC=

No change from the previous setup

 

X

=

Don't care

 

 

 

 

 

 

 

 

= Low-to-high clock transition

= Not low-to-high clock transition

*= This setup is unstable and will change when either set or reset return to the high level.

ABSOLUTE MAXIMUM RATINGS

(Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free air temperature range.)

SYMBOL

PARAMETER

RATING

UNIT

 

 

 

 

 

VCC

Supply voltage

±0.5 to +7.0

V

VIN

Input voltage

±0.5 to +7.0

V

IIN

Input current

±30 to +5

mA

VOUT

Voltage applied to output in high output state

±0.5 to VCC

V

IOUT

Current applied to output in low output state

40

mA

Tamb

Operating free air temperature range

Commercial range

0 to +70

°C

 

 

 

Industrial range

±40 to +85

°C

 

 

 

 

 

 

 

Tstg

Storage temperature range

±65 to +150

°C

RECOMMENDED OPERATING CONDITIONS

SYMBOL

PARAMETER

 

LIMITS

 

UNIT

 

 

 

MIN

NOM

MAX

 

 

 

 

 

 

 

 

 

 

 

VCC

Supply voltage

4.5

5.0

5.5

V

VIH

High-level input voltage

2.0

 

 

V

VIL

Low-level input voltage

 

 

0.8

V

IIk

Input clamp current

 

 

±18

mA

IOH

High-level output current

 

 

±1

mA

IOL

Low-level output current

 

 

20

mA

Tamb

Operating free air temperature range

Commercial range

0

 

+70

°C

 

 

 

 

 

Industrial range

±40

 

+85

°C

 

 

 

1996 Mar 12

3

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