INTEGRATED CIRCUITS
74ALS563A/74ALS564A
Latch flip/flop
Product specification |
1996 Jul 01 |
IC05 Data Handbook |
|
m n r
Philips Semiconductors |
Product specification |
||
|
|
||
|
|
|
|
Latch/flip-flop |
74ALS563A/74ALS564A |
||
|
|
|
|
|
|
|
|
74ALS563A |
Octal transparent latch, inverting (3-State) |
|
|
74ALS564A |
Octal D flip-flop, inverting (3-State) |
|
|
FEATURES
•74ALS563A is broadside pinout and inverting version of 74ALS373
•74ALS564A is broadside pinout and inverting version of 74ALS374
•Inputs and outputs on opposite side of package allow easy interface to microprocessors
•Useful as an input or output port for microprocessors
•3-State outputs for bus interfacing
•Common output enable
•74ALS573A and 74ALS574A are non-inverting version of 74ALS563B and 74ALS564A respectively
|
TYPICAL |
TYPICAL |
|
TYPE |
SUPPLY CURRENT |
||
PROPAGATION DELAY |
|||
|
(TOTAL) |
||
|
|
||
|
|
|
|
74ALS563A |
6.0ns |
12mA |
|
|
|
|
|
74ALS564A |
6.0ns |
15mA |
|
|
|
|
ORDERING INFORMATION
|
ORDER CODE |
|
|
|
|
DRAWING |
|
DESCRIPTION |
COMMERCIAL RANGE |
||
NUMBER |
|||
|
VCC = 5V ±10%, |
||
|
Tamb = 0°C to +70°C |
|
|
20-pin plastic DIP |
74ALS563AN, 74ALS564AN |
SOT146-1 |
|
|
|
|
|
20-pin plastic SOL |
74ALS563AD, 74ALS564AD |
SOT163-1 |
|
|
|
|
DESCRIPTION
The 74ALS563A is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates.
The 74ALS563A is a complementary version of the 74ALS373 and has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors.
The data on the D inputs is transferred to the latch outputs when the enable (E) input is High. The latch remains transparent to the data input while E is High, and stores the inverted data that is present one setup time before the High-to-Low enable transition.
The 74ALS564A is a complementary version of the 74ALS373 and has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors.
It is an 8-bit edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop's Q output.
The active-Low output enable (OE) controls all eight 3-State buffers independent of the latch operation. When OE is Low, latched or transparent data appears at the output.
When OE is High, the outputs are in high impedance ªoffº state, which means they will neither drive nor load the bus.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
|
PINS |
DESCRIPTION |
74ALS (U.L.) |
LOAD VALUE |
|||||
|
HIGH/LOW |
HIGH/LOW |
|||||||
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
D0 ± D7 |
Data inputs |
1.0/2.0 |
20μA/0.2mA |
|||||
|
|
|
|
|
|
|
|
|
|
E (74ALS563A) |
Enable input |
1.0/1.0 |
20μA/0.1mA |
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Output enable input (active-Low) |
1.0/1.0 |
20μA/0.1mA |
|
|
|
OE |
||||||
CP (74ALS564A) |
Clock pulse input (active rising edge) |
1.0/2.0 |
20μA/0.2mA |
||||||
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
Data outputs |
130/240 |
2.6mA/24mA |
|
Q0 ± Q7 |
||||||||
NOTE: One (1.0) ALS unit load is defined as: 20μA in the High state and 0.1mA in the Low state.
1996 Jul 01 |
2 |
853±1306 01670 |
Philips Semiconductors |
Product specification |
|
|
|
|
Latch/flip-flop |
74ALS563A/74ALS564A |
|
|
|
|
PIN CONFIGURATION ± 74ALS563A |
|
PIN CONFIGURATION ± 74ALS564A |
|||||||||||||
|
|
1 |
20 |
VCC |
|
|
|
1 |
20 |
VCC |
|||||
|
OE |
OE |
|||||||||||||
D0 |
2 |
19 |
|
|
|
|
|
D0 |
2 |
19 |
|
|
|
||
Q0 |
Q0 |
||||||||||||||
D1 |
3 |
18 |
|
|
|
|
D1 |
3 |
18 |
|
|
|
|||
|
Q1 |
Q1 |
|||||||||||||
D2 |
4 |
17 |
|
|
|
|
D2 |
4 |
17 |
|
|
|
|||
|
Q2 |
Q2 |
|||||||||||||
D3 |
5 |
16 |
|
|
|
|
D3 |
5 |
16 |
|
|
|
|||
|
Q3 |
Q3 |
|||||||||||||
D4 |
6 |
15 |
|
|
|
|
D4 |
6 |
15 |
|
|
|
|||
|
Q4 |
Q4 |
|||||||||||||
D5 |
7 |
14 |
|
|
|
|
D5 |
7 |
14 |
|
|
|
|||
|
Q5 |
Q5 |
|||||||||||||
D6 |
8 |
13 |
|
|
|
|
D6 |
8 |
13 |
|
|
|
|||
|
Q6 |
Q6 |
|||||||||||||
D7 |
9 |
12 |
|
|
|
|
D7 |
9 |
12 |
|
|
|
|||
|
Q7 |
Q7 |
|||||||||||||
GND |
10 |
11 |
E |
|
GND |
10 |
11 |
CP |
|||||||
|
|
|
|
|
|
|
SC00111 |
|
|
|
|
|
|
|
SF01052 |
LOGIC SYMBOL ± 74ALS563A
|
|
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
|
||||||||
11 |
|
E |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
1 |
|
OE |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
|
||||||||
VCC=Pin 20 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
GND=Pin 10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SC00112 |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
LOGIC SYMBOL ± 74ALS564A
|
|
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
|
||||||||
11 |
|
CP |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
1 |
|
OE |
|
|
|
|
|
|
|
|
|
|
Q6 |
Q7 |
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
|
||||||||
VCC=Pin 20 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
GND=Pin 10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SF01053 |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IEC/IEEE SYMBOL ± 74ALS563A |
|
IEC/IEEE SYMBOL ± 74ALS564A |
|||||||||||||||||||
|
1 |
|
|
|
|
|
|
|
|
|
1 |
|
|
|
|
|
|
|
|
||
EN1 |
|
|
|
|
|
|
EN1 |
|
|
|
|
|
|
||||||||
|
11 |
|
|
|
|
|
|
|
11 |
|
|
|
|
|
|
||||||
EN2 |
|
|
|
|
|
|
|
C2 |
|
|
|
|
|
|
|||||||
|
2 |
|
|
19 |
|
|
|
|
2 |
|
|
|
19 |
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
2D |
1 |
|
|
|
|
2D |
1 |
|
|
|
|
||||||||||
|
3 |
|
18 |
|
|
|
|
3 |
|
18 |
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
||||||||||||||
4 |
|
|
|
|
17 |
|
|
|
4 |
|
|
|
|
17 |
|
|
|
||||
|
|
|
|
|
|
|
|
||||||||||||||
|
|
|
|
|
|
|
16 |
|
|
|
|
|
|
|
|
|
|
16 |
|
|
|
5 |
|
|
|
|
|
|
|
5 |
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
15 |
|
|
|
|
|
|
|
|
|
|
15 |
|
|
|
6 |
|
|
|
|
|
|
|
6 |
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
14 |
|
|
|
|
|
|
|
|
|
|
14 |
|
|
|
7 |
|
|
|
|
|
|
|
7 |
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
13 |
|
|
|
|
|
|
|
|
|
|
13 |
|
|
|
8 |
|
|
|
|
|
|
|
8 |
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
12 |
|
|
|
|
|
|
|
|
|
|
12 |
|
|
|
9 |
|
|
|
|
|
|
|
9 |
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
SC00113 |
|
|
|
|
|
|
|
|
|
|
|
SF01054 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1996 Jul 01 |
3 |
Philips Semiconductors |
Product specification |
|
|
|
|
Latch/flip-flop |
74ALS563A/74ALS564A |
|
|
|
|
LOGIC DIAGRAM ± 74ALS563A
|
D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
|
|
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
|
|
D |
D |
D |
D |
D |
D |
D |
|
D |
|
E Q |
E Q |
E Q |
E Q |
E Q |
E Q |
E Q |
|
E Q |
E |
11 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
OE |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
VCC = Pin 20 |
|
Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
GND = Pin 10 |
|
|
|
|
|
|
|
|
SC00116 |
|
|
|
|
|
|
|
|
|
FUNCTION TABLE ± 74ALS563A
|
|
|
|
|
INPUTS |
|
OUTPUTS |
INTERNAL |
OPERATING MODE |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
OE |
|
E |
|
Dn |
REGISTER |
Q0 ± Q7 |
|
|||||
|
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
L |
|
H |
|
L |
L |
|
|
H |
Enable and read register |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
|
H |
|
H |
H |
|
|
L |
||||
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
L |
|
↓ |
|
l |
L |
|
|
H |
Latch and read register |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
L |
|
↓ |
|
h |
H |
|
|
L |
||||
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
L |
|
L |
|
X |
NC |
|
|
NC |
Hold |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
H |
|
L |
|
X |
NC |
|
|
Z |
Disable outputs |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H |
|
H |
|
Dn |
Dn |
|
|
Z |
||||
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H |
= |
High voltage level |
|
|
|
|
|
|
|
|
||||
h |
= |
High state must be present one setup time before the High-to-Low enable transition |
|
|||||||||||
L |
= |
Low voltage level |
|
|
|
|
|
|
|
|
||||
l |
= |
Low state must be present one setup time before the High-to-Low enable transition |
|
|||||||||||
NC= |
No change |
|
|
|
|
|
|
|
|
|
|
|||
X |
= |
Don't care |
|
|
|
|
|
|
|
|
|
|
||
Z |
= |
High impedance ªoffº state |
|
|
|
|
|
|
|
|
||||
↓ = |
High-to-Low enable transition |
|
|
|
|
|
|
|
|
|||||
1996 Jul 01 |
4 |
Loading...