Philips N74ALS377D, N74ALS377DB, N74ALS377N Datasheet

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74ALS377

Octal D flip–flop with enable

Product specification
IC05 Data Handbook

1991 Feb 08

INTEGRATED CIRCUITS

Philips Semiconductors Product specification

74ALS377Octal D flip-flop with enable

2

1991 Feb 08 853–1399 01670

FEA TURES

•Ideal for addressable register applications

•Enable for address and data synchronization applications

•Eight edge-triggered D-type flip-flops

•Buffered common clock

•See 74ALS273 for master reset version

•See 74ALS373 for transparent latch version

•See 74ALS374 for 3-State version

DESCRIPTION

The 74ALS377 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered clock (CP)
input loads all flip-flops simultaneously when the Enable (E

) is Low.

The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output. The E

input must be stable
one setup time prior to the Low-to-High clock transition for
predictable operation.

TYPE

TYPICAL f

MAX

TYPICAL

SUPPLY CURRENT

(TOTAL)

74ALS377 95MHz 15mA

PIN CONFIGURATION

20
19
18
17
16
15
14
13
12

10 11

9

8

7

6

5

4

3

2

1

V

CC

Q7
D7
D6
Q6
Q5
D5
D4
Q4

CP

Q0

D0

D1
Q1
Q2

D2

D3
Q3

GND

E

SF00350

ORDERING INFORMA TION

ORDER CODE

DESCRIPTION COMMERCIAL RANGE

V

CC

= 5V ±10%,

T

amb

= 0°C to +70°C

DRAWING

NUMBER

20-pin plastic DIP 74ALS377N SOT146-1

20-pin plastic SOL 74ALS377D SOT163-1

20-pin plastic SSOP

Type II

74ALS377DB SOT339-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS DESCRIPTION

74ALS (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

D0 – D7 Data inputs 1.0/2.0 20µA/0.2mA

CP Clock pulse input (active rising edge) 1.0/1.0 20µA/0.1mA

E Latch enable input 1.0/1.0 20µA/0.1mA

Q0 – Q7 Data outputs 130/240 2.6mA/24mA

NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.

LOGIC SYMBOL

SF00351

3 4 7 8 13 14 1817

D0 D1 D2 D3 D4 D5 D6 D7

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

1

11

E

CP

V

CC

= Pin 20

GND = Pin 10

IEC/IEEE SYMBOL

SF00352

1

32
4

5

7

6

8

9

G1

11

1C2

13

12

14

15

17

16

18

19

2D

Philips Semiconductors Product specification

74ALS377Octal D flip-flop with enable

1991 Feb 08

3

LOGIC DIAGRAM

DQ

CP

D

CP

D

CP

DQ

CP

QQ

3478

11

Q0 Q1 Q2 Q3

CP

D0 D1 D2 D3

DQ

CP

D

CP

D

CP

DQ

CP

QQ

13 14 17 18

D4 D5 D6 D7

1

2 5 6 9 12 15 16 19

Q4 Q5 Q6 Q7

E

SF00353

VCC = Pin 20
GND = Pin 10

FUNCTION TABLE

INPUTS OUTPUTS

E CP Dn Qn

OPERATING MODE

l ↑ h H Load “1”

l ↑ l L Load “0”
h ↑ X NC
H X X NC

Hold (do nothing)

H = High-voltage level
h = High state must be present one setup time before the Low-to-High clock transition
L = Low-voltage level
l = Low state must be present one setup time before the Low-to-High clock transition
NC= No change
X = Don’t care
↑ = Low-to-High clock transition