Philips N74ALS373D, N74ALS373DB, N74ALS373N, N74ALS374D, N74ALS374DB Datasheet
...
74ALS373/74ALS374
Latch/flip–flop
Product specification
IC05 Data Handbook
1991 Feb 08
INTEGRATED CIRCUITS
Philips Semiconductors Product specification
74ALS373/74ALS374Latch/flip-flop
74ALS373 Octal transparent latch (3-State)
74ALS374 Octal D flip-flop (3-State)
2
1991 Feb 08 853–1243 01670
FEA TURES
•8-bit transparent latch – 74ALS373
•8-bit positive edge triggered register – 74ALS374
•3-State output buffers
•Common 3-State output register
•Independent register and 3-State buffer operation
TYPE
TYPICAL
PROPAGATION DELAY
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS373 6.0ns 14mA
TYPE
TYPICAL
f
MAX
TYPICAL
SUPPLY CURRENT
(TOTAL)
74ALS374 50MHz 17mA
ORDERING INFORMATION
ORDER CODE
DESCRIPTION COMMERCIAL RANGE
V
CC
= 5V ±10%,
T
amb
= 0°C to +70°C
DRAWING
NUMBER
20-pin plastic DIP 74ALS373N, 74ALS374N SOT146-1
20-pin plastic SOL 74ALS373D, 74ALS374D SOT163-1
20-pin plastic SSOP
Type II
74ALS373DB, 74ALS374DB SOT339-1
DESCRIPTION
The 74ALS373 is an octal transparent latch coupled to eight 3-State
output devices. The two sections of the device are controlled
independently by enable (E) and output enable (OE
) control gates.
The data on the D inputs is transferred to the latch outputs when the
enable (E) input is High. The latch remains transparent to the data
input while E is High, and stores the data that is present one setup
time before the High-to-Low enable transition.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the latch operation. When OE is Low, latched or
transparent data appears at the output.
When OE is High, the outputs are in High impedance “off” state,
which means they will neither drive nor load the bus.
The 74ALS374 is an 8-bit edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by clock (CP) and output enable (OE) control gates.
The register is fully edge triggered. The state of the D input, one
setup time before the Low-to-High clock transition is transferred to
the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-Low output enable (OE) controls all eight 3-State buffers
independent of the register operation. When OE is Low, the data in
the register appears at the outputs. When OE is High, the outputs
are in High impedance “off” state, which means they will neither
drive nor load the bus.
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS DESCRIPTION
74ALS (U.L.)
HIGH/LOW
LOAD VALUE
HIGH/LOW
D0 – D7 Data inputs 1.0/1.0 20µA/0.1mA
E (74ALS373) Enable input (active-High) 1.0/1.0 20µA/0.1mA
OE Output enable inputs (active-Low) 1.0/1.0 20µA/0.1mA
CP (74ALS374) Clock pulse input (active rising edge) 1.0/1.0 20µA/0.1mA
Q0 – Q7 3-State outputs 130/240 2.6mA/24mA
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
Philips Semiconductors Product specification
74ALS373/74ALS374Latch/flip-flop
1991 Feb 08
3
PIN CONFIGURATION – 74ALS373
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
E
SF00250
PIN CONFIGURATION – 74ALS374
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
GND
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
SF00253
LOGIC SYMBOL – 74ALS373
E
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
D0 D1 D2 D3 D4 D5 D6 D7
3 4 7 8 13 14 17 18
2 5 6 9 12 15 16 19
V
CC
= Pin 20
GND = Pin 10
11
1
OE
SF00251
LOGIC SYMBOL – 74ALS374
CP
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
D0 D1 D2 D3 D4 D5 D6 D7
3 4 7 8 13 14 17 18
2 5 6 9 12 15 16 19
V
CC
= Pin 20
11
1
GND = Pin 10
OE
SF00254
IEC/IEEE SYMBOL – 74ALS373
1
EN2
2D
EN1
1
11
3
4
7
8
13
14
17
18
2
5
6
12
9
15
16
19
SF00252
IEC/IEEE SYMBOL – 74ALS374
1
C1
2D
EN1
1
11
3
4
7
8
13
14
17
18
2
5
6
12
9
15
16
19
SC00098
Philips Semiconductors Product specification
74ALS373/74ALS374Latch/flip-flop
1991 Feb 08
4
LOGIC DIAGRAM – 74ALS373
V
CC
= Pin 20
GND = Pin 10
D0
D
E
Q
Q0
3
2
D1
D
E
Q
Q1
4
5
D2
D
E
Q
Q2
7
6
D3
D
E
Q
Q3
8
9
D4
D
E
Q
Q4
13
12
D5
D
E
Q
Q5
14
15
D6
D
E
Q
Q6
17
16
D7
D
E
Q
Q7
18
19
11
1
E
OE
SF00256
FUNCTION T ABLE – 74ALS373
INPUTS
OUTPUTS
OE E Dn
INTERNAL REGISTER
Q0 – Q7
OPERATING MODE
L H L L L
L H H H H
Enable and read register
L ↓ l L L
L ↓ h H H
Latch and read register
L L X NC NC Hold
H L X NC Z
p
H H Dn Dn Z
Disable outputs
H = High-voltage level
h = High state must be present one setup time before the High-to-Low enable transition
L = Low-voltage level
l = Low state must be present one setup time before the High-to-Low enable transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↓ = High-to-Low enable transition
Loading...