INTEGRATED CIRCUITS
74ALS164
8±bit serial±in parallel±out shift register
Product specification |
1991 Feb 08 |
IC05 Data Handbook |
|
m n r
Philips Semiconductors |
Product specification |
|
|
|
|
|
|
|
8-bit serial-in parallel-out shift register |
74ALS164 |
|
|
|
|
|
|
|
FEATURES
•Gated serial data inputs
•Typical shift frequency of 75MHz
•Asynchronous master reset
•Buffered clock and data inputs
•Fully synchronous data transfer
DESCRIPTION
The 74ALS164 is an 8-bit edge-triggered shift register with serial data entry and an output from each of the eight stages. Data is entered serially through one of two inputs (Dsa, Dsb); either input can be used as an active-high enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied High.
Data shifts one place to the right on each Low-to-high transition of the clock (CP) input, and enters into Q0 the logical AND of the two data inputs (Dsa, Dsb) that existed one setup time before the rising edge. A Low level on the Master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs Low.
PIN CONFIGURATION
|
|
|
|
VCC |
||
Dsa |
1 |
|
14 |
|||
Dsb |
|
|
|
Q7 |
||
2 |
|
13 |
||||
Q0 |
|
|
|
Q6 |
||
3 |
|
12 |
||||
Q1 |
|
|
|
Q5 |
||
4 |
|
11 |
||||
Q2 |
|
|
|
Q4 |
||
5 |
|
10 |
||||
Q3 |
|
|
|
|
|
|
6 |
|
9 |
|
MR |
|
|
GND |
|
|
|
CP |
||
7 |
|
8 |
||||
|
|
|
|
|
|
SF00717 |
|
|
|
|
|
|
|
|
TYPICAL |
TYPICAL |
|
TYPE |
SUPPLY CURRENT |
||
fMAX |
|||
|
(TOTAL) |
||
74ALS164 |
75MHz |
10mA |
ORDERING INFORMATION
|
ORDER CODE |
|
|
|
DRAWING |
DESCRIPTION |
COMMERCIAL RANGE |
|
|
VCC = 5V ±10%, |
NUMBER |
|
Tamb = 0°C to +70°C |
|
14-pin plastic DIP |
74ALS164N |
SOT27-1 |
|
|
|
14-pin plastic SO |
74ALS164D |
SOT108-1 |
|
|
|
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DESCRIPTION |
|
|
74ALS (U.L.) |
|
|
|
|
LOAD VALUE |
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
HIGH/LOW |
|
|
|
|
HIGH/LOW |
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Dsa, Dsb |
|
|
|
|
Data inputs |
|
|
|
|
|
|
|
1.0/1.0 |
|
|
|
|
|
|
20μA/0.1mA |
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
CP |
|
|
|
|
Clock Pulse input (active rising edge) |
|
|
1.0/1.0 |
|
|
|
|
|
|
20μA/0.1mA |
||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
Master Reset input (active-Low) |
|
|
1.0/1.0 |
|
|
|
|
|
|
20μA/0.1mA |
||||||||||||||||
|
MR |
|
|
|
|
|
|
|
|
|
|
|||||||||||||||||||||||
Q0 ± Q7 |
|
|
|
|
Data outputs |
|
|
|
|
|
|
|
20/80 |
|
|
|
|
|
|
0.4mA/8mA |
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
NOTE: One (1.0) ALS unit load is defined as: 20μA in the High state and 0.1mA in the Low state. |
|
|
|
|
|
|
|
|
||||||||||||||||||||||||||
LOGIC SYMBOL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IEC/IEEE SYMBOL |
|
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
8 |
|
|
|
SRG8 |
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
C1/→ |
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
1 |
|
|
|
2 |
|
|
|
|
|
|
|
|
9 |
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
R |
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1 |
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
8 |
|
|
|
|
|
|
Dsa |
|
Dsb |
|
|
|
|
|
|
|
2 |
|
& |
|
1D |
|
|
3 |
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||
|
CP |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
4 |
|
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
9 |
|
MR |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
5 |
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
|
|
|
|
Q0 Q1 |
Q3 Q4 Q0 Q1 |
Q3 Q4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
6 |
|
|||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
10 |
|
|
|
|
|
3 |
4 |
5 |
6 |
10 |
11 |
12 |
13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
11 |
|
|||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
12 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC = Pin 14 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
13 |
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
GND = Pin 7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SF00713 |
|
|
|
|
|
|
|
|
|
|
|
|
SF00714 |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1991 Feb 08 |
2 |
853±1510 01670 |
Philips Semiconductors |
Product specification |
|
|
|
|
8-bit serial-in parallel-out shift register |
74ALS164 |
|
|
|
|
LOGIC DIAGRAM
Dsa
Dsb
CP
MR
VCC = Pin 14
GND = Pin 7
1 |
|
|
|
|
|
|
|
|
|
2 |
D Q |
D Q |
D Q |
D Q |
D Q |
D Q |
D Q |
D Q |
|
|
|
|
|
|
|
|
|
|
|
|
CP |
CP |
CP |
CP |
CP |
CP |
CP |
CP |
|
|
RD |
RD |
RD |
RD |
RD |
RD |
RD |
RD |
|
8 |
|
|
|
|
|
|
|
|
|
9 |
|
|
|
|
|
|
|
|
|
|
3 |
4 |
5 |
6 |
10 |
11 |
12 |
13 |
|
|
Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
SF00715 |
|
|
|
|
|
|
|
|
|
MODE SELECT FUNCTION TABLE
|
|
|
|
INPUTS |
|
|
|
|
|
OUTPUTS |
|
|
|
OPERATING MODE |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
MR |
|
|
CP |
Dsa |
Dsb |
|
Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
|
|
L |
|
X |
X |
X |
|
L |
L |
L |
L |
L |
L |
L |
L |
Reset (Clear) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H |
|
↑ |
l |
l |
|
L |
q0 |
q1 |
q2 |
q3 |
q4 |
q5 |
q6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H |
|
↑ |
l |
h |
|
L |
q0 |
q1 |
q2 |
q3 |
q4 |
q5 |
q6 |
Shift |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H |
|
↑ |
h |
l |
|
L |
q0 |
q1 |
q2 |
q3 |
q4 |
q5 |
q6 |
||
|
|
|
|
|||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H |
|
↑ |
h |
h |
|
H |
q0 |
q1 |
q2 |
q3 |
q4 |
q5 |
q6 |
|
|
NOTES: |
|
|
|
|
|
|
|
|
|
|
|
|
||||
H |
= |
|
High voltage level |
|
|
|
|
|
|
|
|
|
|
|
||
h |
= |
|
High voltage level one setup time prior to the Low-to-High clock transition |
|
|
|
||||||||||
L |
= |
|
Low voltage level |
|
|
|
|
|
|
|
|
|
|
|
||
l |
= |
|
Low voltage level one setup time prior to the Low-to-High clock transition |
|
|
|
||||||||||
qn = |
Lower case letter indicate the state of the referenced output one setup time prior to the Low-to-High clock transition. |
|||||||||||||||
X |
= |
|
Don't care |
|
|
|
|
|
|
|
|
|
|
|
|
|
↑ |
= |
|
Low-to-High clock transition |
|
|
|
|
|
|
|
|
|
||||
APPLICATION
The 74ALS164 can be cascaded to form synchronous shift registers of longer length.
Here, two devices are combined to form a 16-bit shift register.
CLEAR
CLOCK
|
|
Dsa |
|
|
CP |
|
|
|
|
MR |
|
|
|
|
|
|
|
Dsa |
|
|
CP |
|
|
|
|
MR |
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
DATA |
|
|
|
|
|
74ALS164 |
|
|
|
|
|
|
|
|
|
|
|
|
74ALS164 |
|
|
|
|
|||||||||||||
|
|
Dsb |
|
|
|
|
|
|
|
|
|
|
Dsb |
|
|
|
|
|
|
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
ENABLE |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
H |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
|
|
|
Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
D7 |
|
|
|
D8 |
D9 |
D10 D11 |
D12 D13 D14 D15 |
||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||||||||
SC00063
1991 Feb 08 |
3 |
Loading...