Philips FTP1.1 Service Manual

Circuit Descriptions, Abbreviation List, and IC Data Sheets

9. Circuit Descriptions, Abbreviation List, and IC Data Sheets

EN 95FTP1.1E 9.

Index of this chapter:

1. Introduction

2. Block diagram

3. Power supply

4. Input/Output (I/O)

5. Video Processing

6. Audio

7. Synchronisation

8. Control

9. Protections

10. PDP Panel

11. Software upgrading

12. Abbreviation list

13. IC Data Sheets

Notes:

• Only new circuits (circuits that are not published recently)

are described.

• For the other "known" circuits, see: – EM5E manual. This manual is available under number

3122 785 12560 (= English).

– EM6E manual. This manual is available under number

3122 785 13070 (= English).

– FM24 manual. This manual is available under number

3122 785 12770 (= English).

• Figures can deviate slightly from the actual situation, due to different set executions.

• For a good understanding of the following circuit descriptions, please use the wiring, block and circuit diagrams. Where necessary, you will find a separate drawing for clarification.

• Where EBILD (Eagle Based Intelligent LCD Driver) is mentioned, please note that the SW for this programmable device is optimised for PDP.

Further features of the SSP are:

• The 3D Comb filter functionality (for USA) is integrated on the SSP.

• The rear I/O connections (like SCART and cinch) are integrated on the SSP, even as the tuner.

• VGA input (for Europe).

• DVI input (only for USA).

On the photographs you can see where all the functional cells are located on the SSP:

9.1 Introduction

The FTP11 is a 42-inch integrated PDP flat screen set, which uses the EM6 small signal panel. The HOP part is replaced by an Erasable Programmable Logic Device (EPLD). This chassis has no PIP, no FDW, and no TXT-DW. Also, features like Dolby, DVD-loader, HDD, and/or radio are not present. In this chapter, the European version is described. In some cases also the US version is described.

9.1.1 Features

This chassis has the following (new) features:

• Next step "Active Control" with: two new bars ("Motion" and "Tint Control" bar), four split demos, etc.

• Small Signal Panel (SSP) that is based on the existing EM6 architecture: a full panel with integrated (shielded) Feature Box as in the former MG-chassis. This approach gives better EMC / crosstalk behaviour and less cables.

• Upgradeable main software (via ComPair).

9.1.2 Small Signal Panel

The SSP is a high tech module (four layer, 2 sides reflow technology, full SMC) with very high component density and partial shielding (FBX, EBILD) for EMC-reasons. Despite this, it is designed in such a way, that repair on component level is possible. To achieve this, attention was paid to:

• Clearance around surface mounted ICs (for replacing).

• Detailed diagnostics and fault finding is possible via

ComPair.

• Software upgrading is possible via ComPair.

EN 96 FTP1.1E9.

Circuit Descriptions, Abbreviation List, and IC Data Sheets

TO PDP PANEL

LVDS

DC/DC CONVERTER

ADC

VGA/RGB

EPLD

VGA

ADC

LVDS

CINCH

(AUDIO)

PIXEL PLUS

FM2

FM3

2V5

FBX (2FH)

OTC HIP

FM5

3V3

CINCH (EXT5)

OTC

MAIN

FBX

SCART

(EXT1/2)

AUDIO PROC.

DPL

MSP

XTL

HIP1

XTL

SCART

(EXT3/4)

DW/PIP

HIP 2

MUPPET

TUNER

I/O

HEADPHONE ANTENNA

SERVICE

CONNECTOR

CL 36532075_049.eps

241103

TUNER

DW/PIP

Figure 9-1 SSP top view

DC/DC CONVERTER

AUDIO PROCESSOR FBX (2FH)

FMI

PICNIC

HIP

COMB

FILTER

I/O

OTC

FLASH

(EPG)

DRAM (TXT)

FALCONIC

PIXEL PLUS

DNM

FM4

EAGLE

VGA/RGB

ANTENNA

SERVICE

CONNECTOR

HEADPHONE CINCH

SCART

(EXT 3/4)

SCART

(EXT 1/2)

(EXT5)

Figure 9-2 SSP bottom view

AUDIO

VGACINCH

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Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.2 Block Diagram

EN 97FTP1.1E 9.

CVBS 1

STATUS

EXT 1

FBL 1

TUN_CVBS

OUT

STATUS 2

Y/CVBS2

R2 C IN

EXT 2

B2 C OUT

FBL 2

Y/CVBS 2 OUT

CVBS 3

EXT 3

STATUS 3

Main Tuner

VIF OUT

Y/Cvbs ext 1/4 main

read_status 1

read_status2

From OTC

P50

CIN

bs ext 3

rgb ext 1 YUV1fH

fbl ext 1

TUN_CVBS OUT

Y/CVBSrecordOut

G D

cvbs

ter

cvbs int

cvbs 1

cvbs 2

y-cvbs 3 c3

y-cvbs 4 c4

FBL 1 in

FBL 2 in

rgb1

rgb2

PIP OUT

YYYCCC

SCART2 OUT

MAIN OUT

yuv 1fh

HIP

MAIN

CVBS pip out

PR OC

CVBS PIP

OUTmain

YUV MAIN

Comb control

CVBS txt out main

set_rgb_main

2FH/3FH

INPUTS

FBX

COMB

CVBS TXT

EBILD

LVDS

transmitter

PDP

A/D

HD3

OTC

Status 3

Status 4

I2C

P50 to scart 2

Keyboard input

RGB OTC

OTC blanking

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Figure 9-3 Block diagram FTP11

The main tuner is a PLL tuner and delivers the IF-signal, via audio and video SAW-filters, to the main HIP (High-end Input Processor). This HIP has the following functions:

• IF modulation.

• Video source select and record select (for 1fH inputs).

• Colour decoder.

• Synchronisation.

The following video input/output connections (with audio connections) are available for Europe:

• Side: interfaces CVBS and Y/C.

• EXT1: interfaces CVBS, RGB-, and YUV-input (1fH)

• EXT2: interfaces CVBS and Y/C (meant for VCR or DVDR

connection).

• EXT3: interfaces CVBS.

• AV5: interfaces YPbPr (2fH/3fH).

• AV6: interfaces VGA (2fH/3fH).

The HIP delivers YUV and H/V-sync signals to the PICNIC (in the Feature Box). This IC takes care of:

• Analogue to Digital conversion and vice versa.

• 100 Hz processing

• Interlaced to progressive scan conversion.

• Panorama mode.

• Noise reduction.

• Dynamic contrast.

After the PICNIC, the YUV-signals are fed to the FALCONIC for "Natural Motion", followed by the Eagle for picture enhancement. The processed YUV signals (from Eagle or PICNIC) are, together with the sync-signals from the PICNIC, then fed to the EBILD (Eagle Based Intelligent LCD Driver). This programmed IC handles the video control. The RGBsignals for TXT/CC/OSD (from the uP) are also inserted via this IC. The video part delivers the RGB signals to the PDP-panel.

The sound part is built around an MSP (Multi-channel Sound Processor) for IF sound detection, sound control and source selection. Amplification is done via a "class D" integrated power amplifier IC, the TDA7490.

The microprocessor, called OTC (OSD, TXT/CC and Control) takes care of the analogue TXT input processing and output processing. The OTC, ROM, and RAM are supplied with 3.3 V. The NVM (Non Volatile Memory) is used to store the settings; the Flash-RAM contains the set software.

9.3 Power Supply

For Service this supply-panel is a black box. When defect (this can be traced via error-codes in the error buffer, or by strange phenomena), a new panel must be ordered, and after receipt, the defective panel must be send for repair. In that case before sending it, check if the supply-output lines match with the values on the PDP-sticker.

EN 98 FTP1.1E9.

Circuit Descriptions, Abbreviation List, and IC Data Sheets

9.3.1 Power Balance

Table 9-1 Total power balance overview

Voltage Value Current

P_max Remarks

(max)

+3V3-DISP 3.3 V 3.6 12 +5V-DISP 5 V 0.8 4 +5V2-DISP 5.2 V 0.3 1.6 Standby voltage +8V-DISP 8.6 V 0.4 3.4 +9V-STBY 9 V +9V-STBY-SW 9 V -

9.3.2 Switch On/Off

Via the ON/OFF knob on the side the set can be switched “on” or “off”, although when “off” not all power is removed. Only by disconnecting the mains power cord from the power socket all power is really gone.

9.3.3 Power States

There are four different power states. Some characteristics of these are summarised in the "Power states" table.

Table 9-2 Power states overview

On/Off

Power state

OUT (mainscord disconnected)

OFF OFF Only standby supply is working OTC not

STAND BY (1) ON Standby supply is working Red LED is "on" (in

SEMI STAND BY ON Standby supply is working

ON ON The set is working Green LED is "on" (in

switch Remarks

XNo power

powered Main supply not working No LED is "on"

Europe and in US)

Main supply is working PDP is not active EPG loading and P50 recording possible (Europe) Time extraction (Europe and US) Red and Green LEDs are "on"

Europe and in US)

Events from OFF to SEMI-STANDBY or ON

(See also figure "Step wise start-up diagram" in chapter "Service Modes, Error Codes, and Fault Finding").

1. The set is in "off" state until the ON/OFF switch is switched to "on". The standby voltage +5V-DISP becomes available, the OTC resets, the I/O pins are initialised, and the watchdog is enabled. The set comes in standby mode.

– The sets leaves the stand by mode if: – A time extraction must be started (after every start up). – A P50 recording has to start. – An EPG loading has to start. – The Standby bit is set to "off"; when a user switches on

the set, the standby bit is also set to "off".

2. The STANDBY line is set to "low", the +5V_SW is "on", the relay closes, and the LCD AUX supply starts up (8V6 is present).

3. The rest of the ICs are initialised. The EBILD is initialised min 400 ms after the standby line is set to "low".

4. If the standby bit was set, the set goes into semi-standby until:

– The time extraction is done. – The P50 recording has finished. – The EPG loading has finished.

5. If the standby bit was not set, the PDP is switched "on". The

PWR-OK-PDP signal from the supply is received at the EBILD to inform the main processor of proper operating PDP supply.

Events in SEMI-STANDBY

1. The set can be in semi-standby during Time extraction, EPG loading, or P50 (Easylink) recording. The semistandby state is ended when:

– Time extraction has finished. – P50 recording has finished. – EPG loading has finished. – A P50 recording starts during EPG loading. – A user event "On" or "Standby". – The set goes into protection.

2. If the standby bit is not set (after user event), the PDP is

switched "on".

3. If a P50 recording or an EPG loading has to start, the set stays in semi-standby. If the P50 recording has to start during EPG loading, the P50 has priority.

4. If there is no P50 recording or EPG loading, the set goes to standby.

Events from ON to SEMI-STANDBY/STANDBY

1. The set can be switched to standby: – Via the RC (to semi-standby). – Via the MENU button on the top control, long press (to

semi stand by).

– Via a protection (to standby).

2. The running instructions are finished.

3. The PDP is switched "off"; this is controlled by the OTC by

means of the STANDBY line.

– Sound is muted – If there was a protection, the STANDBY line is put

"high", and the set goes to standby.

4. If there was no protection, the set goes to semi-standby.

5. After an event in semi-standby, the set goes to standby.

6. Protections are disabled.

7. The OTC sets the STANDBY line "high", this switches "off"

the main power supply, and only the standby supply remains working.

8. The set is in standby.

9.4 Input/Output (I/O)

9.4.1 Introduction

The chassis follows the standard SCART specification:

• The presence of the incoming source is detected via pin 8 of the SCART signal.

• The Aspect Ratio of the incoming source is derived from the voltage level on SCART pin 8. The pin 8 information is handled by the HIP for SCART 1 and 2 and by the OTC for SCART 3.

• The P50 in/out is handled via P1-4 and P3-7 of the OTC.

• RGB sources break in with an additional fast blanking

signal that is detected by the HIP. The HIP then internally chooses other signal processing. RGB sources that only have fast blanking and no pin 8 status do not overrule the main TV source. There is no automatic break in detection for the front input.

• The HIP for further image processing does the detection between Y/C and CVBS automatically.

• When Y/C is detected, the HIP will add Y and C signal to compose CVBS again. This addition should be overruled by software at the moment any Y/C signal is the source and the presence of a P50 Y/C video recorder is detected: only Y signal is directed to record out (C is already hardwired to EXT 2 out). Note: P50: Chroma-out is pin 7, Chroma-in is pin 15. NonP50: both Chroma-out and -in is pin 15 (hardwiring C to pin 7 out; non-P50 not supported).

• The signal on MONITOR_OUT follows the incoming source, except in case the incoming source is EXT2, YPbPr-2fH, or VGA. Then the output signal should be FRONTEND_OUT.

Circuit Descriptions, Abbreviation List, and IC Data Sheets

Note: The SCART input (1fH) path is equal to the one described in the EM6E manual. Therefore, it is not described in much detail here.

9.4.2 Input detection

The RGB or YPbPr input signals (2fH/3fH) are sent to the ADC (AD9883A) together with H and V pulses from DVI (USA) or VGA (EUR), and the Y signal from YPbPr called Sync On Green (green is same line as Y). The AD converter:

• Detects via H and V sync, if RGB is present or not.

• Detects via Sync On Green, if YPbPr is present or not.

• Detects the selected sync.

• Selects the sync switch via I2C.

• Does AD conversion to 848 samples per line, 8 bits in 422

format. This means one bus for Y signal with 8 bits and one bus for UV with 4 U and 4 V bits. Depending on the system detected by EBILD, the sample frequency is changed. Via I2C, the "PLL_DIV" signal is given in 11 bits (2 Bytes).

When a 1fH input is detected, the AD converter is set in tristate.

1fH input flow

START1Fh selection

Mute sound, Blank picture

EN 99FTP1.1E 9.

Put ADC: power down

Put PICNIC: freerun OFF

Set FBX, see lookup table

Set EBILD, see lookup table

Demute sound, Unblank picture

1FH

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Figure 9-4 Flowchart 1fH detection

1. If a 1fH selection is done (except for AV4 in USA), the sound is muted and the picture is blanked.

2. The ADC is powered down.

3. The PICNIC is not in free run.

4. Both FBX and EBILD are set in 1fH (see lookup table).

5. Sound is demuted and picture is unblanked.

EN 100 FTP1.1E9.

2fH/3fH input flow

AV5 or AV6 Eur AV4 or AV5 US

Selection

Circuit Descriptions, Abbreviation List, and IC Data Sheets

START

Put ADC: full power

Mute sound, Blank picture

AV4 on US ?

wait 200 msec

yes

Put picnic: freerun ON

Put ADC on last status from select. input

get Ebild: samples/line, lines/field=STDET1

wait >20 msec

get Ebild: samples/line, lines/field=STDET2

wait >20 msec

get Ebild: samples/line, lines/field=STDET3

STDET1=2=3?

yes

Supp standard ?

yes

same standard as last status?

Set ADC, see tookup table

1Fh detection in HIP?

yes

Put picnic to 1FH

Put picnic: freerun OFF

Unblank, demute

Set ADC to default value

ADC to default value ?

yes

wait >20 msec

get Ebild: samples/line, lines/field=STDET1

wait >20 msec

get Ebild: samples/line, lines/field=STDET2

wait >20 msec

get Ebild: samples/line, lines/field=STDET3

STDET1=2=3?

yes

Supp standard ?

yes

Store standard as last status selected input

Set FBX, see lookup table

Set EBILD, see lookup table

Unblank, demute

yes

set Ebild: blue mute

OSD: Message

wait: 200 msec

Figure 9-5 Flowchart 2fH/3fH detection

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