Philips 74HCT161U, 74HCT161PW, 74HCT161NB, 74HCT161N, 74HCT161D Datasheet

DATA SH EET

Product specification
File under Integrated Circuits, IC06

December 1990

INTEGRATED CIRCUITS

74HC/HCT161

Presettable synchronous 4-bit
binary counter; asynchronous reset

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

December 1990 2

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary
counter; asynchronous reset

74HC/HCT161

FEATURES

• Synchronous counting and loading

• Two count enable inputs for n-bit cascading

• Positive-edge triggered clock

• Asynchronous reset

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT161 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

The 74HC/HCT161 are synchronous presettable binary
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q

0

to Q3) of the counters may be preset to a

HIGH or LOW level. A LOW level at the parallel enable

input (PE) disables the counting action and causes the
data at the data inputs (D0 to D3) to be loaded into the
counter on the positive-going edge of the clock (providing
that the set-up and hold time requirements forPE are met).
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).

A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q0 to Q3) to LOW level regardless
of the levels at CP, PE, CET and CEP inputs (thus
providing an asynchronous clear function).

The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q0. This
pulse can be used to enable the next cascaded stage.

The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:

f

max

=

1

t

P(max)

(CP to TC) t+SU(CEP to CP)

---------------------------------------------------------------------------------------------------

QUICK REFERENCE DATA

GND = 0 V; T

amb

=25°C; tr=tf= 6 ns

SYMBOL PARAMETER CONDITIONS

TYPICAL

UNIT

HC HCT

t

PHL

/ t

PLH

propagation delay

CP to Q

n

CP to TC
MR to Q

n

MR to TC
CET to TC

CL= 15 pF;
VCC=5 V 19

21
20
20
10

20
24
25
26
14

ns
ns
ns
ns
ns

f

max

maximum clock frequency 44 45 MHz

C

I

input capacitance 3.5 3.5 pF

C

PD

power dissipation
capacitance per package

notes 1 and 2 33 35 pF

Notes

1. CPD is used to determine the
dynamic power dissipation
(PD in µW):

PD=CPD× V

CC

2

× fi+

∑ (CL× V

CC

2

× fo)

where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

CC

2

× fo) = sum of

outputs
CL= output load capacitance in

pF
VCC= supply voltage in V

2. For HC the condition is
VI= GND to V

CC

For HCT the condition is

VI= GND to VCC− 1.5 V

December 1990 3

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary
counter; asynchronous reset

74HC/HCT161

ORDERING INFORMATION

See

“74HC/HCT/HCU/HCMOS Logic Package Information”

.

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1

MR asynchronous master reset (active LOW)
2 CP clock input (LOW-to-HIGH, edge-triggered)
3, 4, 5, 6 D

0

to D

3

data inputs
7 CEP count enable input
8 GND ground (0 V)
9

PE parallel enable input (active LOW)
10 CET count enable carry input
14, 13, 12, 11 Q

0

to Q

3

flip-flop outputs
15 TC terminal count output
16 V

CC

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 4

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary
counter; asynchronous reset

74HC/HCT161

FUNCTION TABLE

Note

1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH).
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the

LOW-to-HIGH CP transition
X = don’t care
↑ = LOW-to-HIGH CP transition

OPERATING MODE

INPUTS OUTPUTS

MR CP CEP CET PE D

n

Q

n

TC

reset (clear) L X X X X X L L
parallel load H

H

↑
↑

X
X

X
X

I
I

I
h

L
H

L

(1)

count H ↑ h h h X count

(1)

hold
(do nothing)

H
H

X
X

I
X

X
I

h
h

X
X

q

n

q

n

(1)

L

Fig.4 Functional diagram.